1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * aQuantia Corporation Network Driver 4 * Copyright (C) 2014-2019 aQuantia Corporation. All rights reserved 5 */ 6 7 /* File hw_atl_llh_internal.h: Preprocessor definitions 8 * for Atlantic registers. 9 */ 10 11 #ifndef HW_ATL_LLH_INTERNAL_H 12 #define HW_ATL_LLH_INTERNAL_H 13 14 /* global microprocessor semaphore definitions 15 * base address: 0x000003a0 16 * parameter: semaphore {s} | stride size 0x4 | range [0, 15] 17 */ 18 #define HW_ATL_GLB_CPU_SEM_ADR(semaphore) (0x000003a0u + (semaphore) * 0x4) 19 /* register address for bitfield rx dma good octet counter lsw [1f:0] */ 20 #define HW_ATL_STATS_RX_DMA_GOOD_OCTET_COUNTERLSW 0x00006808 21 /* register address for bitfield rx dma good packet counter lsw [1f:0] */ 22 #define HW_ATL_STATS_RX_DMA_GOOD_PKT_COUNTERLSW 0x00006800 23 /* register address for bitfield tx dma good octet counter lsw [1f:0] */ 24 #define HW_ATL_STATS_TX_DMA_GOOD_OCTET_COUNTERLSW 0x00008808 25 /* register address for bitfield tx dma good packet counter lsw [1f:0] */ 26 #define HW_ATL_STATS_TX_DMA_GOOD_PKT_COUNTERLSW 0x00008800 27 28 /* register address for bitfield rx dma good octet counter msw [3f:20] */ 29 #define HW_ATL_STATS_RX_DMA_GOOD_OCTET_COUNTERMSW 0x0000680c 30 /* register address for bitfield rx dma good packet counter msw [3f:20] */ 31 #define HW_ATL_STATS_RX_DMA_GOOD_PKT_COUNTERMSW 0x00006804 32 /* register address for bitfield tx dma good octet counter msw [3f:20] */ 33 #define HW_ATL_STATS_TX_DMA_GOOD_OCTET_COUNTERMSW 0x0000880c 34 /* register address for bitfield tx dma good packet counter msw [3f:20] */ 35 #define HW_ATL_STATS_TX_DMA_GOOD_PKT_COUNTERMSW 0x00008804 36 37 /* preprocessor definitions for msm rx errors counter register */ 38 #define HW_ATL_MAC_MSM_RX_ERRS_CNT_ADR 0x00000120u 39 40 /* preprocessor definitions for msm rx unicast frames counter register */ 41 #define HW_ATL_MAC_MSM_RX_UCST_FRM_CNT_ADR 0x000000e0u 42 43 /* preprocessor definitions for msm rx multicast frames counter register */ 44 #define HW_ATL_MAC_MSM_RX_MCST_FRM_CNT_ADR 0x000000e8u 45 46 /* preprocessor definitions for msm rx broadcast frames counter register */ 47 #define HW_ATL_MAC_MSM_RX_BCST_FRM_CNT_ADR 0x000000f0u 48 49 /* preprocessor definitions for msm rx broadcast octets counter register 1 */ 50 #define HW_ATL_MAC_MSM_RX_BCST_OCTETS_COUNTER1_ADR 0x000001b0u 51 52 /* preprocessor definitions for msm rx broadcast octets counter register 2 */ 53 #define HW_ATL_MAC_MSM_RX_BCST_OCTETS_COUNTER2_ADR 0x000001b4u 54 55 /* preprocessor definitions for msm rx unicast octets counter register 0 */ 56 #define HW_ATL_MAC_MSM_RX_UCST_OCTETS_COUNTER0_ADR 0x000001b8u 57 58 /* preprocessor definitions for msm tx unicast frames counter register */ 59 #define HW_ATL_MAC_MSM_TX_UCST_FRM_CNT_ADR 0x00000108u 60 61 /* preprocessor definitions for msm tx multicast frames counter register */ 62 #define HW_ATL_MAC_MSM_TX_MCST_FRM_CNT_ADR 0x00000110u 63 64 /* preprocessor definitions for global mif identification */ 65 #define HW_ATL_GLB_MIF_ID_ADR 0x0000001cu 66 67 /* register address for bitfield iamr_lsw[1f:0] */ 68 #define HW_ATL_ITR_IAMRLSW_ADR 0x00002090 69 /* register address for bitfield rx dma drop packet counter [1f:0] */ 70 #define HW_ATL_RPB_RX_DMA_DROP_PKT_CNT_ADR 0x00006818 71 72 /* register address for bitfield imcr_lsw[1f:0] */ 73 #define HW_ATL_ITR_IMCRLSW_ADR 0x00002070 74 /* register address for bitfield imsr_lsw[1f:0] */ 75 #define HW_ATL_ITR_IMSRLSW_ADR 0x00002060 76 /* register address for bitfield itr_reg_res_dsbl */ 77 #define HW_ATL_ITR_REG_RES_DSBL_ADR 0x00002300 78 /* bitmask for bitfield itr_reg_res_dsbl */ 79 #define HW_ATL_ITR_REG_RES_DSBL_MSK 0x20000000 80 /* lower bit position of bitfield itr_reg_res_dsbl */ 81 #define HW_ATL_ITR_REG_RES_DSBL_SHIFT 29 82 /* register address for bitfield iscr_lsw[1f:0] */ 83 #define HW_ATL_ITR_ISCRLSW_ADR 0x00002050 84 /* register address for bitfield isr_lsw[1f:0] */ 85 #define HW_ATL_ITR_ISRLSW_ADR 0x00002000 86 /* register address for bitfield itr_reset */ 87 #define HW_ATL_ITR_RES_ADR 0x00002300 88 /* bitmask for bitfield itr_reset */ 89 #define HW_ATL_ITR_RES_MSK 0x80000000 90 /* lower bit position of bitfield itr_reset */ 91 #define HW_ATL_ITR_RES_SHIFT 31 92 93 /* register address for bitfield rsc_en */ 94 #define HW_ATL_ITR_RSC_EN_ADR 0x00002200 95 96 /* register address for bitfield rsc_delay */ 97 #define HW_ATL_ITR_RSC_DELAY_ADR 0x00002204 98 /* bitmask for bitfield rsc_delay */ 99 #define HW_ATL_ITR_RSC_DELAY_MSK 0x0000000f 100 /* width of bitfield rsc_delay */ 101 #define HW_ATL_ITR_RSC_DELAY_WIDTH 4 102 /* lower bit position of bitfield rsc_delay */ 103 #define HW_ATL_ITR_RSC_DELAY_SHIFT 0 104 105 /* register address for bitfield dca{d}_cpuid[7:0] */ 106 #define HW_ATL_RDM_DCADCPUID_ADR(dca) (0x00006100 + (dca) * 0x4) 107 /* bitmask for bitfield dca{d}_cpuid[7:0] */ 108 #define HW_ATL_RDM_DCADCPUID_MSK 0x000000ff 109 /* lower bit position of bitfield dca{d}_cpuid[7:0] */ 110 #define HW_ATL_RDM_DCADCPUID_SHIFT 0 111 /* register address for bitfield dca_en */ 112 #define HW_ATL_RDM_DCA_EN_ADR 0x00006180 113 114 /* rx dca_en bitfield definitions 115 * preprocessor definitions for the bitfield "dca_en". 116 * port="pif_rdm_dca_en_i" 117 */ 118 119 /* register address for bitfield dca_en */ 120 #define HW_ATL_RDM_DCA_EN_ADR 0x00006180 121 /* bitmask for bitfield dca_en */ 122 #define HW_ATL_RDM_DCA_EN_MSK 0x80000000 123 /* inverted bitmask for bitfield dca_en */ 124 #define HW_ATL_RDM_DCA_EN_MSKN 0x7fffffff 125 /* lower bit position of bitfield dca_en */ 126 #define HW_ATL_RDM_DCA_EN_SHIFT 31 127 /* width of bitfield dca_en */ 128 #define HW_ATL_RDM_DCA_EN_WIDTH 1 129 /* default value of bitfield dca_en */ 130 #define HW_ATL_RDM_DCA_EN_DEFAULT 0x1 131 132 /* rx dca_mode[3:0] bitfield definitions 133 * preprocessor definitions for the bitfield "dca_mode[3:0]". 134 * port="pif_rdm_dca_mode_i[3:0]" 135 */ 136 137 /* register address for bitfield dca_mode[3:0] */ 138 #define HW_ATL_RDM_DCA_MODE_ADR 0x00006180 139 /* bitmask for bitfield dca_mode[3:0] */ 140 #define HW_ATL_RDM_DCA_MODE_MSK 0x0000000f 141 /* inverted bitmask for bitfield dca_mode[3:0] */ 142 #define HW_ATL_RDM_DCA_MODE_MSKN 0xfffffff0 143 /* lower bit position of bitfield dca_mode[3:0] */ 144 #define HW_ATL_RDM_DCA_MODE_SHIFT 0 145 /* width of bitfield dca_mode[3:0] */ 146 #define HW_ATL_RDM_DCA_MODE_WIDTH 4 147 /* default value of bitfield dca_mode[3:0] */ 148 #define HW_ATL_RDM_DCA_MODE_DEFAULT 0x0 149 150 /* rx desc{d}_data_size[4:0] bitfield definitions 151 * preprocessor definitions for the bitfield "desc{d}_data_size[4:0]". 152 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 153 * port="pif_rdm_desc0_data_size_i[4:0]" 154 */ 155 156 /* register address for bitfield desc{d}_data_size[4:0] */ 157 #define HW_ATL_RDM_DESCDDATA_SIZE_ADR(descriptor) \ 158 (0x00005b18 + (descriptor) * 0x20) 159 /* bitmask for bitfield desc{d}_data_size[4:0] */ 160 #define HW_ATL_RDM_DESCDDATA_SIZE_MSK 0x0000001f 161 /* inverted bitmask for bitfield desc{d}_data_size[4:0] */ 162 #define HW_ATL_RDM_DESCDDATA_SIZE_MSKN 0xffffffe0 163 /* lower bit position of bitfield desc{d}_data_size[4:0] */ 164 #define HW_ATL_RDM_DESCDDATA_SIZE_SHIFT 0 165 /* width of bitfield desc{d}_data_size[4:0] */ 166 #define HW_ATL_RDM_DESCDDATA_SIZE_WIDTH 5 167 /* default value of bitfield desc{d}_data_size[4:0] */ 168 #define HW_ATL_RDM_DESCDDATA_SIZE_DEFAULT 0x0 169 170 /* rx dca{d}_desc_en bitfield definitions 171 * preprocessor definitions for the bitfield "dca{d}_desc_en". 172 * parameter: dca {d} | stride size 0x4 | range [0, 31] 173 * port="pif_rdm_dca_desc_en_i[0]" 174 */ 175 176 /* register address for bitfield dca{d}_desc_en */ 177 #define HW_ATL_RDM_DCADDESC_EN_ADR(dca) (0x00006100 + (dca) * 0x4) 178 /* bitmask for bitfield dca{d}_desc_en */ 179 #define HW_ATL_RDM_DCADDESC_EN_MSK 0x80000000 180 /* inverted bitmask for bitfield dca{d}_desc_en */ 181 #define HW_ATL_RDM_DCADDESC_EN_MSKN 0x7fffffff 182 /* lower bit position of bitfield dca{d}_desc_en */ 183 #define HW_ATL_RDM_DCADDESC_EN_SHIFT 31 184 /* width of bitfield dca{d}_desc_en */ 185 #define HW_ATL_RDM_DCADDESC_EN_WIDTH 1 186 /* default value of bitfield dca{d}_desc_en */ 187 #define HW_ATL_RDM_DCADDESC_EN_DEFAULT 0x0 188 189 /* rx desc{d}_en bitfield definitions 190 * preprocessor definitions for the bitfield "desc{d}_en". 191 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 192 * port="pif_rdm_desc_en_i[0]" 193 */ 194 195 /* register address for bitfield desc{d}_en */ 196 #define HW_ATL_RDM_DESCDEN_ADR(descriptor) (0x00005b08 + (descriptor) * 0x20) 197 /* bitmask for bitfield desc{d}_en */ 198 #define HW_ATL_RDM_DESCDEN_MSK 0x80000000 199 /* inverted bitmask for bitfield desc{d}_en */ 200 #define HW_ATL_RDM_DESCDEN_MSKN 0x7fffffff 201 /* lower bit position of bitfield desc{d}_en */ 202 #define HW_ATL_RDM_DESCDEN_SHIFT 31 203 /* width of bitfield desc{d}_en */ 204 #define HW_ATL_RDM_DESCDEN_WIDTH 1 205 /* default value of bitfield desc{d}_en */ 206 #define HW_ATL_RDM_DESCDEN_DEFAULT 0x0 207 208 /* rx desc{d}_hdr_size[4:0] bitfield definitions 209 * preprocessor definitions for the bitfield "desc{d}_hdr_size[4:0]". 210 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 211 * port="pif_rdm_desc0_hdr_size_i[4:0]" 212 */ 213 214 /* register address for bitfield desc{d}_hdr_size[4:0] */ 215 #define HW_ATL_RDM_DESCDHDR_SIZE_ADR(descriptor) \ 216 (0x00005b18 + (descriptor) * 0x20) 217 /* bitmask for bitfield desc{d}_hdr_size[4:0] */ 218 #define HW_ATL_RDM_DESCDHDR_SIZE_MSK 0x00001f00 219 /* inverted bitmask for bitfield desc{d}_hdr_size[4:0] */ 220 #define HW_ATL_RDM_DESCDHDR_SIZE_MSKN 0xffffe0ff 221 /* lower bit position of bitfield desc{d}_hdr_size[4:0] */ 222 #define HW_ATL_RDM_DESCDHDR_SIZE_SHIFT 8 223 /* width of bitfield desc{d}_hdr_size[4:0] */ 224 #define HW_ATL_RDM_DESCDHDR_SIZE_WIDTH 5 225 /* default value of bitfield desc{d}_hdr_size[4:0] */ 226 #define HW_ATL_RDM_DESCDHDR_SIZE_DEFAULT 0x0 227 228 /* rx desc{d}_hdr_split bitfield definitions 229 * preprocessor definitions for the bitfield "desc{d}_hdr_split". 230 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 231 * port="pif_rdm_desc_hdr_split_i[0]" 232 */ 233 234 /* register address for bitfield desc{d}_hdr_split */ 235 #define HW_ATL_RDM_DESCDHDR_SPLIT_ADR(descriptor) \ 236 (0x00005b08 + (descriptor) * 0x20) 237 /* bitmask for bitfield desc{d}_hdr_split */ 238 #define HW_ATL_RDM_DESCDHDR_SPLIT_MSK 0x10000000 239 /* inverted bitmask for bitfield desc{d}_hdr_split */ 240 #define HW_ATL_RDM_DESCDHDR_SPLIT_MSKN 0xefffffff 241 /* lower bit position of bitfield desc{d}_hdr_split */ 242 #define HW_ATL_RDM_DESCDHDR_SPLIT_SHIFT 28 243 /* width of bitfield desc{d}_hdr_split */ 244 #define HW_ATL_RDM_DESCDHDR_SPLIT_WIDTH 1 245 /* default value of bitfield desc{d}_hdr_split */ 246 #define HW_ATL_RDM_DESCDHDR_SPLIT_DEFAULT 0x0 247 248 /* rx desc{d}_hd[c:0] bitfield definitions 249 * preprocessor definitions for the bitfield "desc{d}_hd[c:0]". 250 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 251 * port="rdm_pif_desc0_hd_o[12:0]" 252 */ 253 254 /* register address for bitfield desc{d}_hd[c:0] */ 255 #define HW_ATL_RDM_DESCDHD_ADR(descriptor) (0x00005b0c + (descriptor) * 0x20) 256 /* bitmask for bitfield desc{d}_hd[c:0] */ 257 #define HW_ATL_RDM_DESCDHD_MSK 0x00001fff 258 /* inverted bitmask for bitfield desc{d}_hd[c:0] */ 259 #define HW_ATL_RDM_DESCDHD_MSKN 0xffffe000 260 /* lower bit position of bitfield desc{d}_hd[c:0] */ 261 #define HW_ATL_RDM_DESCDHD_SHIFT 0 262 /* width of bitfield desc{d}_hd[c:0] */ 263 #define HW_ATL_RDM_DESCDHD_WIDTH 13 264 265 /* rx desc{d}_len[9:0] bitfield definitions 266 * preprocessor definitions for the bitfield "desc{d}_len[9:0]". 267 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 268 * port="pif_rdm_desc0_len_i[9:0]" 269 */ 270 271 /* register address for bitfield desc{d}_len[9:0] */ 272 #define HW_ATL_RDM_DESCDLEN_ADR(descriptor) (0x00005b08 + (descriptor) * 0x20) 273 /* bitmask for bitfield desc{d}_len[9:0] */ 274 #define HW_ATL_RDM_DESCDLEN_MSK 0x00001ff8 275 /* inverted bitmask for bitfield desc{d}_len[9:0] */ 276 #define HW_ATL_RDM_DESCDLEN_MSKN 0xffffe007 277 /* lower bit position of bitfield desc{d}_len[9:0] */ 278 #define HW_ATL_RDM_DESCDLEN_SHIFT 3 279 /* width of bitfield desc{d}_len[9:0] */ 280 #define HW_ATL_RDM_DESCDLEN_WIDTH 10 281 /* default value of bitfield desc{d}_len[9:0] */ 282 #define HW_ATL_RDM_DESCDLEN_DEFAULT 0x0 283 284 /* rx desc{d}_reset bitfield definitions 285 * preprocessor definitions for the bitfield "desc{d}_reset". 286 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 287 * port="pif_rdm_q_pf_res_i[0]" 288 */ 289 290 /* register address for bitfield desc{d}_reset */ 291 #define HW_ATL_RDM_DESCDRESET_ADR(descriptor) (0x00005b08 + (descriptor) * 0x20) 292 /* bitmask for bitfield desc{d}_reset */ 293 #define HW_ATL_RDM_DESCDRESET_MSK 0x02000000 294 /* inverted bitmask for bitfield desc{d}_reset */ 295 #define HW_ATL_RDM_DESCDRESET_MSKN 0xfdffffff 296 /* lower bit position of bitfield desc{d}_reset */ 297 #define HW_ATL_RDM_DESCDRESET_SHIFT 25 298 /* width of bitfield desc{d}_reset */ 299 #define HW_ATL_RDM_DESCDRESET_WIDTH 1 300 /* default value of bitfield desc{d}_reset */ 301 #define HW_ATL_RDM_DESCDRESET_DEFAULT 0x0 302 303 /* rdm_desc_init_i bitfield definitions 304 * preprocessor definitions for the bitfield rdm_desc_init_i. 305 * port="pif_rdm_desc_init_i" 306 */ 307 308 /* register address for bitfield rdm_desc_init_i */ 309 #define HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_ADR 0x00005a00 310 /* bitmask for bitfield rdm_desc_init_i */ 311 #define HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_MSK 0xffffffff 312 /* inverted bitmask for bitfield rdm_desc_init_i */ 313 #define HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_MSKN 0x00000000 314 /* lower bit position of bitfield rdm_desc_init_i */ 315 #define HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_SHIFT 0 316 /* width of bitfield rdm_desc_init_i */ 317 #define HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_WIDTH 32 318 /* default value of bitfield rdm_desc_init_i */ 319 #define HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_DEFAULT 0x0 320 321 /* rdm_desc_init_done_i bitfield definitions 322 * preprocessor definitions for the bitfield rdm_desc_init_done_i. 323 * port="pif_rdm_desc_init_done_i" 324 */ 325 326 /* register address for bitfield rdm_desc_init_done_i */ 327 #define RDM_RX_DMA_DESC_CACHE_INIT_DONE_ADR 0x00005a10 328 /* bitmask for bitfield rdm_desc_init_done_i */ 329 #define RDM_RX_DMA_DESC_CACHE_INIT_DONE_MSK 0x00000001U 330 /* inverted bitmask for bitfield rdm_desc_init_done_i */ 331 #define RDM_RX_DMA_DESC_CACHE_INIT_DONE_MSKN 0xfffffffe 332 /* lower bit position of bitfield rdm_desc_init_done_i */ 333 #define RDM_RX_DMA_DESC_CACHE_INIT_DONE_SHIFT 0U 334 /* width of bitfield rdm_desc_init_done_i */ 335 #define RDM_RX_DMA_DESC_CACHE_INIT_DONE_WIDTH 1 336 /* default value of bitfield rdm_desc_init_done_i */ 337 #define RDM_RX_DMA_DESC_CACHE_INIT_DONE_DEFAULT 0x0 338 339 340 /* rx int_desc_wrb_en bitfield definitions 341 * preprocessor definitions for the bitfield "int_desc_wrb_en". 342 * port="pif_rdm_int_desc_wrb_en_i" 343 */ 344 345 /* register address for bitfield int_desc_wrb_en */ 346 #define HW_ATL_RDM_INT_DESC_WRB_EN_ADR 0x00005a30 347 /* bitmask for bitfield int_desc_wrb_en */ 348 #define HW_ATL_RDM_INT_DESC_WRB_EN_MSK 0x00000004 349 /* inverted bitmask for bitfield int_desc_wrb_en */ 350 #define HW_ATL_RDM_INT_DESC_WRB_EN_MSKN 0xfffffffb 351 /* lower bit position of bitfield int_desc_wrb_en */ 352 #define HW_ATL_RDM_INT_DESC_WRB_EN_SHIFT 2 353 /* width of bitfield int_desc_wrb_en */ 354 #define HW_ATL_RDM_INT_DESC_WRB_EN_WIDTH 1 355 /* default value of bitfield int_desc_wrb_en */ 356 #define HW_ATL_RDM_INT_DESC_WRB_EN_DEFAULT 0x0 357 358 /* rx dca{d}_hdr_en bitfield definitions 359 * preprocessor definitions for the bitfield "dca{d}_hdr_en". 360 * parameter: dca {d} | stride size 0x4 | range [0, 31] 361 * port="pif_rdm_dca_hdr_en_i[0]" 362 */ 363 364 /* register address for bitfield dca{d}_hdr_en */ 365 #define HW_ATL_RDM_DCADHDR_EN_ADR(dca) (0x00006100 + (dca) * 0x4) 366 /* bitmask for bitfield dca{d}_hdr_en */ 367 #define HW_ATL_RDM_DCADHDR_EN_MSK 0x40000000 368 /* inverted bitmask for bitfield dca{d}_hdr_en */ 369 #define HW_ATL_RDM_DCADHDR_EN_MSKN 0xbfffffff 370 /* lower bit position of bitfield dca{d}_hdr_en */ 371 #define HW_ATL_RDM_DCADHDR_EN_SHIFT 30 372 /* width of bitfield dca{d}_hdr_en */ 373 #define HW_ATL_RDM_DCADHDR_EN_WIDTH 1 374 /* default value of bitfield dca{d}_hdr_en */ 375 #define HW_ATL_RDM_DCADHDR_EN_DEFAULT 0x0 376 377 /* rx dca{d}_pay_en bitfield definitions 378 * preprocessor definitions for the bitfield "dca{d}_pay_en". 379 * parameter: dca {d} | stride size 0x4 | range [0, 31] 380 * port="pif_rdm_dca_pay_en_i[0]" 381 */ 382 383 /* register address for bitfield dca{d}_pay_en */ 384 #define HW_ATL_RDM_DCADPAY_EN_ADR(dca) (0x00006100 + (dca) * 0x4) 385 /* bitmask for bitfield dca{d}_pay_en */ 386 #define HW_ATL_RDM_DCADPAY_EN_MSK 0x20000000 387 /* inverted bitmask for bitfield dca{d}_pay_en */ 388 #define HW_ATL_RDM_DCADPAY_EN_MSKN 0xdfffffff 389 /* lower bit position of bitfield dca{d}_pay_en */ 390 #define HW_ATL_RDM_DCADPAY_EN_SHIFT 29 391 /* width of bitfield dca{d}_pay_en */ 392 #define HW_ATL_RDM_DCADPAY_EN_WIDTH 1 393 /* default value of bitfield dca{d}_pay_en */ 394 #define HW_ATL_RDM_DCADPAY_EN_DEFAULT 0x0 395 396 /* RX rdm_int_rim_en Bitfield Definitions 397 * Preprocessor definitions for the bitfield "rdm_int_rim_en". 398 * PORT="pif_rdm_int_rim_en_i" 399 */ 400 401 /* Register address for bitfield rdm_int_rim_en */ 402 #define HW_ATL_RDM_INT_RIM_EN_ADR 0x00005A30 403 /* Bitmask for bitfield rdm_int_rim_en */ 404 #define HW_ATL_RDM_INT_RIM_EN_MSK 0x00000008 405 /* Inverted bitmask for bitfield rdm_int_rim_en */ 406 #define HW_ATL_RDM_INT_RIM_EN_MSKN 0xFFFFFFF7 407 /* Lower bit position of bitfield rdm_int_rim_en */ 408 #define HW_ATL_RDM_INT_RIM_EN_SHIFT 3 409 /* Width of bitfield rdm_int_rim_en */ 410 #define HW_ATL_RDM_INT_RIM_EN_WIDTH 1 411 /* Default value of bitfield rdm_int_rim_en */ 412 #define HW_ATL_RDM_INT_RIM_EN_DEFAULT 0x0 413 414 /* general interrupt mapping register definitions 415 * preprocessor definitions for general interrupt mapping register 416 * base address: 0x00002180 417 * parameter: regidx {f} | stride size 0x4 | range [0, 3] 418 */ 419 #define HW_ATL_GEN_INTR_MAP_ADR(regidx) (0x00002180u + (regidx) * 0x4) 420 421 /* general interrupt status register definitions 422 * preprocessor definitions for general interrupt status register 423 * address: 0x000021A0 424 */ 425 426 #define HW_ATL_GEN_INTR_STAT_ADR 0x000021A4U 427 428 /* interrupt global control register definitions 429 * preprocessor definitions for interrupt global control register 430 * address: 0x00002300 431 */ 432 #define HW_ATL_INTR_GLB_CTL_ADR 0x00002300u 433 434 /* interrupt throttle register definitions 435 * preprocessor definitions for interrupt throttle register 436 * base address: 0x00002800 437 * parameter: throttle {t} | stride size 0x4 | range [0, 31] 438 */ 439 #define HW_ATL_INTR_THR_ADR(throttle) (0x00002800u + (throttle) * 0x4) 440 441 /* rx dma descriptor base address lsw definitions 442 * preprocessor definitions for rx dma descriptor base address lsw 443 * base address: 0x00005b00 444 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 445 */ 446 #define HW_ATL_RX_DMA_DESC_BASE_ADDRLSW_ADR(descriptor) \ 447 (0x00005b00u + (descriptor) * 0x20) 448 449 /* rx dma descriptor base address msw definitions 450 * preprocessor definitions for rx dma descriptor base address msw 451 * base address: 0x00005b04 452 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 453 */ 454 #define HW_ATL_RX_DMA_DESC_BASE_ADDRMSW_ADR(descriptor) \ 455 (0x00005b04u + (descriptor) * 0x20) 456 457 /* rx dma descriptor status register definitions 458 * preprocessor definitions for rx dma descriptor status register 459 * base address: 0x00005b14 460 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 461 */ 462 #define HW_ATL_RX_DMA_DESC_STAT_ADR(descriptor) \ 463 (0x00005b14u + (descriptor) * 0x20) 464 465 /* rx dma descriptor tail pointer register definitions 466 * preprocessor definitions for rx dma descriptor tail pointer register 467 * base address: 0x00005b10 468 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 469 */ 470 #define HW_ATL_RX_DMA_DESC_TAIL_PTR_ADR(descriptor) \ 471 (0x00005b10u + (descriptor) * 0x20) 472 473 /* rx interrupt moderation control register definitions 474 * Preprocessor definitions for RX Interrupt Moderation Control Register 475 * Base Address: 0x00005A40 476 * Parameter: RIM {R} | stride size 0x4 | range [0, 31] 477 */ 478 #define HW_ATL_RX_INTR_MODERATION_CTL_ADR(rim) (0x00005A40u + (rim) * 0x4) 479 480 /* rx filter multicast filter mask register definitions 481 * preprocessor definitions for rx filter multicast filter mask register 482 * address: 0x00005270 483 */ 484 #define HW_ATL_RX_FLR_MCST_FLR_MSK_ADR 0x00005270u 485 486 /* rx filter multicast filter register definitions 487 * preprocessor definitions for rx filter multicast filter register 488 * base address: 0x00005250 489 * parameter: filter {f} | stride size 0x4 | range [0, 7] 490 */ 491 #define HW_ATL_RX_FLR_MCST_FLR_ADR(filter) (0x00005250u + (filter) * 0x4) 492 493 /* RX Filter RSS Control Register 1 Definitions 494 * Preprocessor definitions for RX Filter RSS Control Register 1 495 * Address: 0x000054C0 496 */ 497 #define HW_ATL_RX_FLR_RSS_CONTROL1_ADR 0x000054C0u 498 499 /* RX Filter Control Register 2 Definitions 500 * Preprocessor definitions for RX Filter Control Register 2 501 * Address: 0x00005104 502 */ 503 #define HW_ATL_RX_FLR_CONTROL2_ADR 0x00005104u 504 505 /* tx tx dma debug control [1f:0] bitfield definitions 506 * preprocessor definitions for the bitfield "tx dma debug control [1f:0]". 507 * port="pif_tdm_debug_cntl_i[31:0]" 508 */ 509 510 /* register address for bitfield tx dma debug control [1f:0] */ 511 #define HW_ATL_TDM_TX_DMA_DEBUG_CTL_ADR 0x00008920 512 /* bitmask for bitfield tx dma debug control [1f:0] */ 513 #define HW_ATL_TDM_TX_DMA_DEBUG_CTL_MSK 0xffffffff 514 /* inverted bitmask for bitfield tx dma debug control [1f:0] */ 515 #define HW_ATL_TDM_TX_DMA_DEBUG_CTL_MSKN 0x00000000 516 /* lower bit position of bitfield tx dma debug control [1f:0] */ 517 #define HW_ATL_TDM_TX_DMA_DEBUG_CTL_SHIFT 0 518 /* width of bitfield tx dma debug control [1f:0] */ 519 #define HW_ATL_TDM_TX_DMA_DEBUG_CTL_WIDTH 32 520 /* default value of bitfield tx dma debug control [1f:0] */ 521 #define HW_ATL_TDM_TX_DMA_DEBUG_CTL_DEFAULT 0x0 522 523 /* tx dma descriptor base address lsw definitions 524 * preprocessor definitions for tx dma descriptor base address lsw 525 * base address: 0x00007c00 526 * parameter: descriptor {d} | stride size 0x40 | range [0, 31] 527 */ 528 #define HW_ATL_TX_DMA_DESC_BASE_ADDRLSW_ADR(descriptor) \ 529 (0x00007c00u + (descriptor) * 0x40) 530 531 /* tx dma descriptor tail pointer register definitions 532 * preprocessor definitions for tx dma descriptor tail pointer register 533 * base address: 0x00007c10 534 * parameter: descriptor {d} | stride size 0x40 | range [0, 31] 535 */ 536 #define HW_ATL_TX_DMA_DESC_TAIL_PTR_ADR(descriptor) \ 537 (0x00007c10u + (descriptor) * 0x40) 538 539 /* rx dma_sys_loopback bitfield definitions 540 * preprocessor definitions for the bitfield "dma_sys_loopback". 541 * port="pif_rpb_dma_sys_lbk_i" 542 */ 543 544 /* register address for bitfield dma_sys_loopback */ 545 #define HW_ATL_RPB_DMA_SYS_LBK_ADR 0x00005000 546 /* bitmask for bitfield dma_sys_loopback */ 547 #define HW_ATL_RPB_DMA_SYS_LBK_MSK 0x00000040 548 /* inverted bitmask for bitfield dma_sys_loopback */ 549 #define HW_ATL_RPB_DMA_SYS_LBK_MSKN 0xffffffbf 550 /* lower bit position of bitfield dma_sys_loopback */ 551 #define HW_ATL_RPB_DMA_SYS_LBK_SHIFT 6 552 /* width of bitfield dma_sys_loopback */ 553 #define HW_ATL_RPB_DMA_SYS_LBK_WIDTH 1 554 /* default value of bitfield dma_sys_loopback */ 555 #define HW_ATL_RPB_DMA_SYS_LBK_DEFAULT 0x0 556 557 /* rx dma_net_loopback bitfield definitions 558 * preprocessor definitions for the bitfield "dma_net_loopback". 559 * port="pif_rpb_dma_net_lbk_i" 560 */ 561 562 /* register address for bitfield dma_net_loopback */ 563 #define HW_ATL_RPB_DMA_NET_LBK_ADR 0x00005000 564 /* bitmask for bitfield dma_net_loopback */ 565 #define HW_ATL_RPB_DMA_NET_LBK_MSK 0x00000010 566 /* inverted bitmask for bitfield dma_net_loopback */ 567 #define HW_ATL_RPB_DMA_NET_LBK_MSKN 0xffffffef 568 /* lower bit position of bitfield dma_net_loopback */ 569 #define HW_ATL_RPB_DMA_NET_LBK_SHIFT 4 570 /* width of bitfield dma_net_loopback */ 571 #define HW_ATL_RPB_DMA_NET_LBK_WIDTH 1 572 /* default value of bitfield dma_net_loopback */ 573 #define HW_ATL_RPB_DMA_NET_LBK_DEFAULT 0x0 574 575 /* rx rx_tc_mode bitfield definitions 576 * preprocessor definitions for the bitfield "rx_tc_mode". 577 * port="pif_rpb_rx_tc_mode_i,pif_rpf_rx_tc_mode_i" 578 */ 579 580 /* register address for bitfield rx_tc_mode */ 581 #define HW_ATL_RPB_RPF_RX_TC_MODE_ADR 0x00005700 582 /* bitmask for bitfield rx_tc_mode */ 583 #define HW_ATL_RPB_RPF_RX_TC_MODE_MSK 0x00000100 584 /* inverted bitmask for bitfield rx_tc_mode */ 585 #define HW_ATL_RPB_RPF_RX_TC_MODE_MSKN 0xfffffeff 586 /* lower bit position of bitfield rx_tc_mode */ 587 #define HW_ATL_RPB_RPF_RX_TC_MODE_SHIFT 8 588 /* width of bitfield rx_tc_mode */ 589 #define HW_ATL_RPB_RPF_RX_TC_MODE_WIDTH 1 590 /* default value of bitfield rx_tc_mode */ 591 #define HW_ATL_RPB_RPF_RX_TC_MODE_DEFAULT 0x0 592 593 /* rx rx_buf_en bitfield definitions 594 * preprocessor definitions for the bitfield "rx_buf_en". 595 * port="pif_rpb_rx_buf_en_i" 596 */ 597 598 /* register address for bitfield rx_buf_en */ 599 #define HW_ATL_RPB_RX_BUF_EN_ADR 0x00005700 600 /* bitmask for bitfield rx_buf_en */ 601 #define HW_ATL_RPB_RX_BUF_EN_MSK 0x00000001 602 /* inverted bitmask for bitfield rx_buf_en */ 603 #define HW_ATL_RPB_RX_BUF_EN_MSKN 0xfffffffe 604 /* lower bit position of bitfield rx_buf_en */ 605 #define HW_ATL_RPB_RX_BUF_EN_SHIFT 0 606 /* width of bitfield rx_buf_en */ 607 #define HW_ATL_RPB_RX_BUF_EN_WIDTH 1 608 /* default value of bitfield rx_buf_en */ 609 #define HW_ATL_RPB_RX_BUF_EN_DEFAULT 0x0 610 611 /* rx rx{b}_hi_thresh[d:0] bitfield definitions 612 * preprocessor definitions for the bitfield "rx{b}_hi_thresh[d:0]". 613 * parameter: buffer {b} | stride size 0x10 | range [0, 7] 614 * port="pif_rpb_rx0_hi_thresh_i[13:0]" 615 */ 616 617 /* register address for bitfield rx{b}_hi_thresh[d:0] */ 618 #define HW_ATL_RPB_RXBHI_THRESH_ADR(buffer) (0x00005714 + (buffer) * 0x10) 619 /* bitmask for bitfield rx{b}_hi_thresh[d:0] */ 620 #define HW_ATL_RPB_RXBHI_THRESH_MSK 0x3fff0000 621 /* inverted bitmask for bitfield rx{b}_hi_thresh[d:0] */ 622 #define HW_ATL_RPB_RXBHI_THRESH_MSKN 0xc000ffff 623 /* lower bit position of bitfield rx{b}_hi_thresh[d:0] */ 624 #define HW_ATL_RPB_RXBHI_THRESH_SHIFT 16 625 /* width of bitfield rx{b}_hi_thresh[d:0] */ 626 #define HW_ATL_RPB_RXBHI_THRESH_WIDTH 14 627 /* default value of bitfield rx{b}_hi_thresh[d:0] */ 628 #define HW_ATL_RPB_RXBHI_THRESH_DEFAULT 0x0 629 630 /* rx rx{b}_lo_thresh[d:0] bitfield definitions 631 * preprocessor definitions for the bitfield "rx{b}_lo_thresh[d:0]". 632 * parameter: buffer {b} | stride size 0x10 | range [0, 7] 633 * port="pif_rpb_rx0_lo_thresh_i[13:0]" 634 */ 635 636 /* register address for bitfield rx{b}_lo_thresh[d:0] */ 637 #define HW_ATL_RPB_RXBLO_THRESH_ADR(buffer) (0x00005714 + (buffer) * 0x10) 638 /* bitmask for bitfield rx{b}_lo_thresh[d:0] */ 639 #define HW_ATL_RPB_RXBLO_THRESH_MSK 0x00003fff 640 /* inverted bitmask for bitfield rx{b}_lo_thresh[d:0] */ 641 #define HW_ATL_RPB_RXBLO_THRESH_MSKN 0xffffc000 642 /* lower bit position of bitfield rx{b}_lo_thresh[d:0] */ 643 #define HW_ATL_RPB_RXBLO_THRESH_SHIFT 0 644 /* width of bitfield rx{b}_lo_thresh[d:0] */ 645 #define HW_ATL_RPB_RXBLO_THRESH_WIDTH 14 646 /* default value of bitfield rx{b}_lo_thresh[d:0] */ 647 #define HW_ATL_RPB_RXBLO_THRESH_DEFAULT 0x0 648 649 /* rx rx_fc_mode[1:0] bitfield definitions 650 * preprocessor definitions for the bitfield "rx_fc_mode[1:0]". 651 * port="pif_rpb_rx_fc_mode_i[1:0]" 652 */ 653 654 /* register address for bitfield rx_fc_mode[1:0] */ 655 #define HW_ATL_RPB_RX_FC_MODE_ADR 0x00005700 656 /* bitmask for bitfield rx_fc_mode[1:0] */ 657 #define HW_ATL_RPB_RX_FC_MODE_MSK 0x00000030 658 /* inverted bitmask for bitfield rx_fc_mode[1:0] */ 659 #define HW_ATL_RPB_RX_FC_MODE_MSKN 0xffffffcf 660 /* lower bit position of bitfield rx_fc_mode[1:0] */ 661 #define HW_ATL_RPB_RX_FC_MODE_SHIFT 4 662 /* width of bitfield rx_fc_mode[1:0] */ 663 #define HW_ATL_RPB_RX_FC_MODE_WIDTH 2 664 /* default value of bitfield rx_fc_mode[1:0] */ 665 #define HW_ATL_RPB_RX_FC_MODE_DEFAULT 0x0 666 667 /* rx rx{b}_buf_size[8:0] bitfield definitions 668 * preprocessor definitions for the bitfield "rx{b}_buf_size[8:0]". 669 * parameter: buffer {b} | stride size 0x10 | range [0, 7] 670 * port="pif_rpb_rx0_buf_size_i[8:0]" 671 */ 672 673 /* register address for bitfield rx{b}_buf_size[8:0] */ 674 #define HW_ATL_RPB_RXBBUF_SIZE_ADR(buffer) (0x00005710 + (buffer) * 0x10) 675 /* bitmask for bitfield rx{b}_buf_size[8:0] */ 676 #define HW_ATL_RPB_RXBBUF_SIZE_MSK 0x000001ff 677 /* inverted bitmask for bitfield rx{b}_buf_size[8:0] */ 678 #define HW_ATL_RPB_RXBBUF_SIZE_MSKN 0xfffffe00 679 /* lower bit position of bitfield rx{b}_buf_size[8:0] */ 680 #define HW_ATL_RPB_RXBBUF_SIZE_SHIFT 0 681 /* width of bitfield rx{b}_buf_size[8:0] */ 682 #define HW_ATL_RPB_RXBBUF_SIZE_WIDTH 9 683 /* default value of bitfield rx{b}_buf_size[8:0] */ 684 #define HW_ATL_RPB_RXBBUF_SIZE_DEFAULT 0x0 685 686 /* rx rx{b}_xoff_en bitfield definitions 687 * preprocessor definitions for the bitfield "rx{b}_xoff_en". 688 * parameter: buffer {b} | stride size 0x10 | range [0, 7] 689 * port="pif_rpb_rx_xoff_en_i[0]" 690 */ 691 692 /* register address for bitfield rx{b}_xoff_en */ 693 #define HW_ATL_RPB_RXBXOFF_EN_ADR(buffer) (0x00005714 + (buffer) * 0x10) 694 /* bitmask for bitfield rx{b}_xoff_en */ 695 #define HW_ATL_RPB_RXBXOFF_EN_MSK 0x80000000 696 /* inverted bitmask for bitfield rx{b}_xoff_en */ 697 #define HW_ATL_RPB_RXBXOFF_EN_MSKN 0x7fffffff 698 /* lower bit position of bitfield rx{b}_xoff_en */ 699 #define HW_ATL_RPB_RXBXOFF_EN_SHIFT 31 700 /* width of bitfield rx{b}_xoff_en */ 701 #define HW_ATL_RPB_RXBXOFF_EN_WIDTH 1 702 /* default value of bitfield rx{b}_xoff_en */ 703 #define HW_ATL_RPB_RXBXOFF_EN_DEFAULT 0x0 704 705 /* rx l2_bc_thresh[f:0] bitfield definitions 706 * preprocessor definitions for the bitfield "l2_bc_thresh[f:0]". 707 * port="pif_rpf_l2_bc_thresh_i[15:0]" 708 */ 709 710 /* register address for bitfield l2_bc_thresh[f:0] */ 711 #define HW_ATL_RPFL2BC_THRESH_ADR 0x00005100 712 /* bitmask for bitfield l2_bc_thresh[f:0] */ 713 #define HW_ATL_RPFL2BC_THRESH_MSK 0xffff0000 714 /* inverted bitmask for bitfield l2_bc_thresh[f:0] */ 715 #define HW_ATL_RPFL2BC_THRESH_MSKN 0x0000ffff 716 /* lower bit position of bitfield l2_bc_thresh[f:0] */ 717 #define HW_ATL_RPFL2BC_THRESH_SHIFT 16 718 /* width of bitfield l2_bc_thresh[f:0] */ 719 #define HW_ATL_RPFL2BC_THRESH_WIDTH 16 720 /* default value of bitfield l2_bc_thresh[f:0] */ 721 #define HW_ATL_RPFL2BC_THRESH_DEFAULT 0x0 722 723 /* rx l2_bc_en bitfield definitions 724 * preprocessor definitions for the bitfield "l2_bc_en". 725 * port="pif_rpf_l2_bc_en_i" 726 */ 727 728 /* register address for bitfield l2_bc_en */ 729 #define HW_ATL_RPFL2BC_EN_ADR 0x00005100 730 /* bitmask for bitfield l2_bc_en */ 731 #define HW_ATL_RPFL2BC_EN_MSK 0x00000001 732 /* inverted bitmask for bitfield l2_bc_en */ 733 #define HW_ATL_RPFL2BC_EN_MSKN 0xfffffffe 734 /* lower bit position of bitfield l2_bc_en */ 735 #define HW_ATL_RPFL2BC_EN_SHIFT 0 736 /* width of bitfield l2_bc_en */ 737 #define HW_ATL_RPFL2BC_EN_WIDTH 1 738 /* default value of bitfield l2_bc_en */ 739 #define HW_ATL_RPFL2BC_EN_DEFAULT 0x0 740 741 /* rx l2_bc_act[2:0] bitfield definitions 742 * preprocessor definitions for the bitfield "l2_bc_act[2:0]". 743 * port="pif_rpf_l2_bc_act_i[2:0]" 744 */ 745 746 /* register address for bitfield l2_bc_act[2:0] */ 747 #define HW_ATL_RPFL2BC_ACT_ADR 0x00005100 748 /* bitmask for bitfield l2_bc_act[2:0] */ 749 #define HW_ATL_RPFL2BC_ACT_MSK 0x00007000 750 /* inverted bitmask for bitfield l2_bc_act[2:0] */ 751 #define HW_ATL_RPFL2BC_ACT_MSKN 0xffff8fff 752 /* lower bit position of bitfield l2_bc_act[2:0] */ 753 #define HW_ATL_RPFL2BC_ACT_SHIFT 12 754 /* width of bitfield l2_bc_act[2:0] */ 755 #define HW_ATL_RPFL2BC_ACT_WIDTH 3 756 /* default value of bitfield l2_bc_act[2:0] */ 757 #define HW_ATL_RPFL2BC_ACT_DEFAULT 0x0 758 759 /* rx l2_mc_en{f} bitfield definitions 760 * preprocessor definitions for the bitfield "l2_mc_en{f}". 761 * parameter: filter {f} | stride size 0x4 | range [0, 7] 762 * port="pif_rpf_l2_mc_en_i[0]" 763 */ 764 765 /* register address for bitfield l2_mc_en{f} */ 766 #define HW_ATL_RPFL2MC_ENF_ADR(filter) (0x00005250 + (filter) * 0x4) 767 /* bitmask for bitfield l2_mc_en{f} */ 768 #define HW_ATL_RPFL2MC_ENF_MSK 0x80000000 769 /* inverted bitmask for bitfield l2_mc_en{f} */ 770 #define HW_ATL_RPFL2MC_ENF_MSKN 0x7fffffff 771 /* lower bit position of bitfield l2_mc_en{f} */ 772 #define HW_ATL_RPFL2MC_ENF_SHIFT 31 773 /* width of bitfield l2_mc_en{f} */ 774 #define HW_ATL_RPFL2MC_ENF_WIDTH 1 775 /* default value of bitfield l2_mc_en{f} */ 776 #define HW_ATL_RPFL2MC_ENF_DEFAULT 0x0 777 778 /* rx l2_promis_mode bitfield definitions 779 * preprocessor definitions for the bitfield "l2_promis_mode". 780 * port="pif_rpf_l2_promis_mode_i" 781 */ 782 783 /* register address for bitfield l2_promis_mode */ 784 #define HW_ATL_RPFL2PROMIS_MODE_ADR 0x00005100 785 /* bitmask for bitfield l2_promis_mode */ 786 #define HW_ATL_RPFL2PROMIS_MODE_MSK 0x00000008 787 /* inverted bitmask for bitfield l2_promis_mode */ 788 #define HW_ATL_RPFL2PROMIS_MODE_MSKN 0xfffffff7 789 /* lower bit position of bitfield l2_promis_mode */ 790 #define HW_ATL_RPFL2PROMIS_MODE_SHIFT 3 791 /* width of bitfield l2_promis_mode */ 792 #define HW_ATL_RPFL2PROMIS_MODE_WIDTH 1 793 /* default value of bitfield l2_promis_mode */ 794 #define HW_ATL_RPFL2PROMIS_MODE_DEFAULT 0x0 795 796 /* rx l2_uc_act{f}[2:0] bitfield definitions 797 * preprocessor definitions for the bitfield "l2_uc_act{f}[2:0]". 798 * parameter: filter {f} | stride size 0x8 | range [0, 37] 799 * port="pif_rpf_l2_uc_act0_i[2:0]" 800 */ 801 802 /* register address for bitfield l2_uc_act{f}[2:0] */ 803 #define HW_ATL_RPFL2UC_ACTF_ADR(filter) (0x00005114 + (filter) * 0x8) 804 /* bitmask for bitfield l2_uc_act{f}[2:0] */ 805 #define HW_ATL_RPFL2UC_ACTF_MSK 0x00070000 806 /* inverted bitmask for bitfield l2_uc_act{f}[2:0] */ 807 #define HW_ATL_RPFL2UC_ACTF_MSKN 0xfff8ffff 808 /* lower bit position of bitfield l2_uc_act{f}[2:0] */ 809 #define HW_ATL_RPFL2UC_ACTF_SHIFT 16 810 /* width of bitfield l2_uc_act{f}[2:0] */ 811 #define HW_ATL_RPFL2UC_ACTF_WIDTH 3 812 /* default value of bitfield l2_uc_act{f}[2:0] */ 813 #define HW_ATL_RPFL2UC_ACTF_DEFAULT 0x0 814 815 /* rx l2_uc_en{f} bitfield definitions 816 * preprocessor definitions for the bitfield "l2_uc_en{f}". 817 * parameter: filter {f} | stride size 0x8 | range [0, 37] 818 * port="pif_rpf_l2_uc_en_i[0]" 819 */ 820 821 /* register address for bitfield l2_uc_en{f} */ 822 #define HW_ATL_RPFL2UC_ENF_ADR(filter) (0x00005114 + (filter) * 0x8) 823 /* bitmask for bitfield l2_uc_en{f} */ 824 #define HW_ATL_RPFL2UC_ENF_MSK 0x80000000 825 /* inverted bitmask for bitfield l2_uc_en{f} */ 826 #define HW_ATL_RPFL2UC_ENF_MSKN 0x7fffffff 827 /* lower bit position of bitfield l2_uc_en{f} */ 828 #define HW_ATL_RPFL2UC_ENF_SHIFT 31 829 /* width of bitfield l2_uc_en{f} */ 830 #define HW_ATL_RPFL2UC_ENF_WIDTH 1 831 /* default value of bitfield l2_uc_en{f} */ 832 #define HW_ATL_RPFL2UC_ENF_DEFAULT 0x0 833 834 /* register address for bitfield l2_uc_da{f}_lsw[1f:0] */ 835 #define HW_ATL_RPFL2UC_DAFLSW_ADR(filter) (0x00005110 + (filter) * 0x8) 836 /* register address for bitfield l2_uc_da{f}_msw[f:0] */ 837 #define HW_ATL_RPFL2UC_DAFMSW_ADR(filter) (0x00005114 + (filter) * 0x8) 838 /* bitmask for bitfield l2_uc_da{f}_msw[f:0] */ 839 #define HW_ATL_RPFL2UC_DAFMSW_MSK 0x0000ffff 840 /* lower bit position of bitfield l2_uc_da{f}_msw[f:0] */ 841 #define HW_ATL_RPFL2UC_DAFMSW_SHIFT 0 842 843 /* rx l2_mc_accept_all bitfield definitions 844 * Preprocessor definitions for the bitfield "l2_mc_accept_all". 845 * PORT="pif_rpf_l2_mc_all_accept_i" 846 */ 847 848 /* Register address for bitfield l2_mc_accept_all */ 849 #define HW_ATL_RPFL2MC_ACCEPT_ALL_ADR 0x00005270 850 /* Bitmask for bitfield l2_mc_accept_all */ 851 #define HW_ATL_RPFL2MC_ACCEPT_ALL_MSK 0x00004000 852 /* Inverted bitmask for bitfield l2_mc_accept_all */ 853 #define HW_ATL_RPFL2MC_ACCEPT_ALL_MSKN 0xFFFFBFFF 854 /* Lower bit position of bitfield l2_mc_accept_all */ 855 #define HW_ATL_RPFL2MC_ACCEPT_ALL_SHIFT 14 856 /* Width of bitfield l2_mc_accept_all */ 857 #define HW_ATL_RPFL2MC_ACCEPT_ALL_WIDTH 1 858 /* Default value of bitfield l2_mc_accept_all */ 859 #define HW_ATL_RPFL2MC_ACCEPT_ALL_DEFAULT 0x0 860 861 /* width of bitfield rx_tc_up{t}[2:0] */ 862 #define HW_ATL_RPF_RPB_RX_TC_UPT_WIDTH 3 863 /* default value of bitfield rx_tc_up{t}[2:0] */ 864 #define HW_ATL_RPF_RPB_RX_TC_UPT_DEFAULT 0x0 865 866 /* rx rss_key_addr[4:0] bitfield definitions 867 * preprocessor definitions for the bitfield "rss_key_addr[4:0]". 868 * port="pif_rpf_rss_key_addr_i[4:0]" 869 */ 870 871 /* register address for bitfield rss_key_addr[4:0] */ 872 #define HW_ATL_RPF_RSS_KEY_ADDR_ADR 0x000054d0 873 /* bitmask for bitfield rss_key_addr[4:0] */ 874 #define HW_ATL_RPF_RSS_KEY_ADDR_MSK 0x0000001f 875 /* inverted bitmask for bitfield rss_key_addr[4:0] */ 876 #define HW_ATL_RPF_RSS_KEY_ADDR_MSKN 0xffffffe0 877 /* lower bit position of bitfield rss_key_addr[4:0] */ 878 #define HW_ATL_RPF_RSS_KEY_ADDR_SHIFT 0 879 /* width of bitfield rss_key_addr[4:0] */ 880 #define HW_ATL_RPF_RSS_KEY_ADDR_WIDTH 5 881 /* default value of bitfield rss_key_addr[4:0] */ 882 #define HW_ATL_RPF_RSS_KEY_ADDR_DEFAULT 0x0 883 884 /* rx rss_key_wr_data[1f:0] bitfield definitions 885 * preprocessor definitions for the bitfield "rss_key_wr_data[1f:0]". 886 * port="pif_rpf_rss_key_wr_data_i[31:0]" 887 */ 888 889 /* register address for bitfield rss_key_wr_data[1f:0] */ 890 #define HW_ATL_RPF_RSS_KEY_WR_DATA_ADR 0x000054d4 891 /* bitmask for bitfield rss_key_wr_data[1f:0] */ 892 #define HW_ATL_RPF_RSS_KEY_WR_DATA_MSK 0xffffffff 893 /* inverted bitmask for bitfield rss_key_wr_data[1f:0] */ 894 #define HW_ATL_RPF_RSS_KEY_WR_DATA_MSKN 0x00000000 895 /* lower bit position of bitfield rss_key_wr_data[1f:0] */ 896 #define HW_ATL_RPF_RSS_KEY_WR_DATA_SHIFT 0 897 /* width of bitfield rss_key_wr_data[1f:0] */ 898 #define HW_ATL_RPF_RSS_KEY_WR_DATA_WIDTH 32 899 /* default value of bitfield rss_key_wr_data[1f:0] */ 900 #define HW_ATL_RPF_RSS_KEY_WR_DATA_DEFAULT 0x0 901 902 /* rx rss_key_wr_en_i bitfield definitions 903 * preprocessor definitions for the bitfield "rss_key_wr_en_i". 904 * port="pif_rpf_rss_key_wr_en_i" 905 */ 906 907 /* register address for bitfield rss_key_wr_en_i */ 908 #define HW_ATL_RPF_RSS_KEY_WR_ENI_ADR 0x000054d0 909 /* bitmask for bitfield rss_key_wr_en_i */ 910 #define HW_ATL_RPF_RSS_KEY_WR_ENI_MSK 0x00000020 911 /* inverted bitmask for bitfield rss_key_wr_en_i */ 912 #define HW_ATL_RPF_RSS_KEY_WR_ENI_MSKN 0xffffffdf 913 /* lower bit position of bitfield rss_key_wr_en_i */ 914 #define HW_ATL_RPF_RSS_KEY_WR_ENI_SHIFT 5 915 /* width of bitfield rss_key_wr_en_i */ 916 #define HW_ATL_RPF_RSS_KEY_WR_ENI_WIDTH 1 917 /* default value of bitfield rss_key_wr_en_i */ 918 #define HW_ATL_RPF_RSS_KEY_WR_ENI_DEFAULT 0x0 919 920 /* rx rss_redir_addr[3:0] bitfield definitions 921 * preprocessor definitions for the bitfield "rss_redir_addr[3:0]". 922 * port="pif_rpf_rss_redir_addr_i[3:0]" 923 */ 924 925 /* register address for bitfield rss_redir_addr[3:0] */ 926 #define HW_ATL_RPF_RSS_REDIR_ADDR_ADR 0x000054e0 927 /* bitmask for bitfield rss_redir_addr[3:0] */ 928 #define HW_ATL_RPF_RSS_REDIR_ADDR_MSK 0x0000000f 929 /* inverted bitmask for bitfield rss_redir_addr[3:0] */ 930 #define HW_ATL_RPF_RSS_REDIR_ADDR_MSKN 0xfffffff0 931 /* lower bit position of bitfield rss_redir_addr[3:0] */ 932 #define HW_ATL_RPF_RSS_REDIR_ADDR_SHIFT 0 933 /* width of bitfield rss_redir_addr[3:0] */ 934 #define HW_ATL_RPF_RSS_REDIR_ADDR_WIDTH 4 935 /* default value of bitfield rss_redir_addr[3:0] */ 936 #define HW_ATL_RPF_RSS_REDIR_ADDR_DEFAULT 0x0 937 938 /* rx rss_redir_wr_data[f:0] bitfield definitions 939 * preprocessor definitions for the bitfield "rss_redir_wr_data[f:0]". 940 * port="pif_rpf_rss_redir_wr_data_i[15:0]" 941 */ 942 943 /* register address for bitfield rss_redir_wr_data[f:0] */ 944 #define HW_ATL_RPF_RSS_REDIR_WR_DATA_ADR 0x000054e4 945 /* bitmask for bitfield rss_redir_wr_data[f:0] */ 946 #define HW_ATL_RPF_RSS_REDIR_WR_DATA_MSK 0x0000ffff 947 /* inverted bitmask for bitfield rss_redir_wr_data[f:0] */ 948 #define HW_ATL_RPF_RSS_REDIR_WR_DATA_MSKN 0xffff0000 949 /* lower bit position of bitfield rss_redir_wr_data[f:0] */ 950 #define HW_ATL_RPF_RSS_REDIR_WR_DATA_SHIFT 0 951 /* width of bitfield rss_redir_wr_data[f:0] */ 952 #define HW_ATL_RPF_RSS_REDIR_WR_DATA_WIDTH 16 953 /* default value of bitfield rss_redir_wr_data[f:0] */ 954 #define HW_ATL_RPF_RSS_REDIR_WR_DATA_DEFAULT 0x0 955 956 /* rx rss_redir_wr_en_i bitfield definitions 957 * preprocessor definitions for the bitfield "rss_redir_wr_en_i". 958 * port="pif_rpf_rss_redir_wr_en_i" 959 */ 960 961 /* register address for bitfield rss_redir_wr_en_i */ 962 #define HW_ATL_RPF_RSS_REDIR_WR_ENI_ADR 0x000054e0 963 /* bitmask for bitfield rss_redir_wr_en_i */ 964 #define HW_ATL_RPF_RSS_REDIR_WR_ENI_MSK 0x00000010 965 /* inverted bitmask for bitfield rss_redir_wr_en_i */ 966 #define HW_ATL_RPF_RSS_REDIR_WR_ENI_MSKN 0xffffffef 967 /* lower bit position of bitfield rss_redir_wr_en_i */ 968 #define HW_ATL_RPF_RSS_REDIR_WR_ENI_SHIFT 4 969 /* width of bitfield rss_redir_wr_en_i */ 970 #define HW_ATL_RPF_RSS_REDIR_WR_ENI_WIDTH 1 971 /* default value of bitfield rss_redir_wr_en_i */ 972 #define HW_ATL_RPF_RSS_REDIR_WR_ENI_DEFAULT 0x0 973 974 /* rx tpo_rpf_sys_loopback bitfield definitions 975 * preprocessor definitions for the bitfield "tpo_rpf_sys_loopback". 976 * port="pif_rpf_tpo_pkt_sys_lbk_i" 977 */ 978 979 /* register address for bitfield tpo_rpf_sys_loopback */ 980 #define HW_ATL_RPF_TPO_RPF_SYS_LBK_ADR 0x00005000 981 /* bitmask for bitfield tpo_rpf_sys_loopback */ 982 #define HW_ATL_RPF_TPO_RPF_SYS_LBK_MSK 0x00000100 983 /* inverted bitmask for bitfield tpo_rpf_sys_loopback */ 984 #define HW_ATL_RPF_TPO_RPF_SYS_LBK_MSKN 0xfffffeff 985 /* lower bit position of bitfield tpo_rpf_sys_loopback */ 986 #define HW_ATL_RPF_TPO_RPF_SYS_LBK_SHIFT 8 987 /* width of bitfield tpo_rpf_sys_loopback */ 988 #define HW_ATL_RPF_TPO_RPF_SYS_LBK_WIDTH 1 989 /* default value of bitfield tpo_rpf_sys_loopback */ 990 #define HW_ATL_RPF_TPO_RPF_SYS_LBK_DEFAULT 0x0 991 992 /* rx vl_inner_tpid[f:0] bitfield definitions 993 * preprocessor definitions for the bitfield "vl_inner_tpid[f:0]". 994 * port="pif_rpf_vl_inner_tpid_i[15:0]" 995 */ 996 997 /* register address for bitfield vl_inner_tpid[f:0] */ 998 #define HW_ATL_RPF_VL_INNER_TPID_ADR 0x00005284 999 /* bitmask for bitfield vl_inner_tpid[f:0] */ 1000 #define HW_ATL_RPF_VL_INNER_TPID_MSK 0x0000ffff 1001 /* inverted bitmask for bitfield vl_inner_tpid[f:0] */ 1002 #define HW_ATL_RPF_VL_INNER_TPID_MSKN 0xffff0000 1003 /* lower bit position of bitfield vl_inner_tpid[f:0] */ 1004 #define HW_ATL_RPF_VL_INNER_TPID_SHIFT 0 1005 /* width of bitfield vl_inner_tpid[f:0] */ 1006 #define HW_ATL_RPF_VL_INNER_TPID_WIDTH 16 1007 /* default value of bitfield vl_inner_tpid[f:0] */ 1008 #define HW_ATL_RPF_VL_INNER_TPID_DEFAULT 0x8100 1009 1010 /* rx vl_outer_tpid[f:0] bitfield definitions 1011 * preprocessor definitions for the bitfield "vl_outer_tpid[f:0]". 1012 * port="pif_rpf_vl_outer_tpid_i[15:0]" 1013 */ 1014 1015 /* register address for bitfield vl_outer_tpid[f:0] */ 1016 #define HW_ATL_RPF_VL_OUTER_TPID_ADR 0x00005284 1017 /* bitmask for bitfield vl_outer_tpid[f:0] */ 1018 #define HW_ATL_RPF_VL_OUTER_TPID_MSK 0xffff0000 1019 /* inverted bitmask for bitfield vl_outer_tpid[f:0] */ 1020 #define HW_ATL_RPF_VL_OUTER_TPID_MSKN 0x0000ffff 1021 /* lower bit position of bitfield vl_outer_tpid[f:0] */ 1022 #define HW_ATL_RPF_VL_OUTER_TPID_SHIFT 16 1023 /* width of bitfield vl_outer_tpid[f:0] */ 1024 #define HW_ATL_RPF_VL_OUTER_TPID_WIDTH 16 1025 /* default value of bitfield vl_outer_tpid[f:0] */ 1026 #define HW_ATL_RPF_VL_OUTER_TPID_DEFAULT 0x88a8 1027 1028 /* rx vl_promis_mode bitfield definitions 1029 * preprocessor definitions for the bitfield "vl_promis_mode". 1030 * port="pif_rpf_vl_promis_mode_i" 1031 */ 1032 1033 /* register address for bitfield vl_promis_mode */ 1034 #define HW_ATL_RPF_VL_PROMIS_MODE_ADR 0x00005280 1035 /* bitmask for bitfield vl_promis_mode */ 1036 #define HW_ATL_RPF_VL_PROMIS_MODE_MSK 0x00000002 1037 /* inverted bitmask for bitfield vl_promis_mode */ 1038 #define HW_ATL_RPF_VL_PROMIS_MODE_MSKN 0xfffffffd 1039 /* lower bit position of bitfield vl_promis_mode */ 1040 #define HW_ATL_RPF_VL_PROMIS_MODE_SHIFT 1 1041 /* width of bitfield vl_promis_mode */ 1042 #define HW_ATL_RPF_VL_PROMIS_MODE_WIDTH 1 1043 /* default value of bitfield vl_promis_mode */ 1044 #define HW_ATL_RPF_VL_PROMIS_MODE_DEFAULT 0x0 1045 1046 /* RX vl_accept_untagged_mode Bitfield Definitions 1047 * Preprocessor definitions for the bitfield "vl_accept_untagged_mode". 1048 * PORT="pif_rpf_vl_accept_untagged_i" 1049 */ 1050 1051 /* Register address for bitfield vl_accept_untagged_mode */ 1052 #define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_ADR 0x00005280 1053 /* Bitmask for bitfield vl_accept_untagged_mode */ 1054 #define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_MSK 0x00000004 1055 /* Inverted bitmask for bitfield vl_accept_untagged_mode */ 1056 #define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_MSKN 0xFFFFFFFB 1057 /* Lower bit position of bitfield vl_accept_untagged_mode */ 1058 #define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_SHIFT 2 1059 /* Width of bitfield vl_accept_untagged_mode */ 1060 #define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_WIDTH 1 1061 /* Default value of bitfield vl_accept_untagged_mode */ 1062 #define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_DEFAULT 0x0 1063 1064 /* rX vl_untagged_act[2:0] Bitfield Definitions 1065 * Preprocessor definitions for the bitfield "vl_untagged_act[2:0]". 1066 * PORT="pif_rpf_vl_untagged_act_i[2:0]" 1067 */ 1068 1069 /* Register address for bitfield vl_untagged_act[2:0] */ 1070 #define HW_ATL_RPF_VL_UNTAGGED_ACT_ADR 0x00005280 1071 /* Bitmask for bitfield vl_untagged_act[2:0] */ 1072 #define HW_ATL_RPF_VL_UNTAGGED_ACT_MSK 0x00000038 1073 /* Inverted bitmask for bitfield vl_untagged_act[2:0] */ 1074 #define HW_ATL_RPF_VL_UNTAGGED_ACT_MSKN 0xFFFFFFC7 1075 /* Lower bit position of bitfield vl_untagged_act[2:0] */ 1076 #define HW_ATL_RPF_VL_UNTAGGED_ACT_SHIFT 3 1077 /* Width of bitfield vl_untagged_act[2:0] */ 1078 #define HW_ATL_RPF_VL_UNTAGGED_ACT_WIDTH 3 1079 /* Default value of bitfield vl_untagged_act[2:0] */ 1080 #define HW_ATL_RPF_VL_UNTAGGED_ACT_DEFAULT 0x0 1081 1082 /* RX vl_en{F} Bitfield Definitions 1083 * Preprocessor definitions for the bitfield "vl_en{F}". 1084 * Parameter: filter {F} | stride size 0x4 | range [0, 15] 1085 * PORT="pif_rpf_vl_en_i[0]" 1086 */ 1087 1088 /* Register address for bitfield vl_en{F} */ 1089 #define HW_ATL_RPF_VL_EN_F_ADR(filter) (0x00005290 + (filter) * 0x4) 1090 /* Bitmask for bitfield vl_en{F} */ 1091 #define HW_ATL_RPF_VL_EN_F_MSK 0x80000000 1092 /* Inverted bitmask for bitfield vl_en{F} */ 1093 #define HW_ATL_RPF_VL_EN_F_MSKN 0x7FFFFFFF 1094 /* Lower bit position of bitfield vl_en{F} */ 1095 #define HW_ATL_RPF_VL_EN_F_SHIFT 31 1096 /* Width of bitfield vl_en{F} */ 1097 #define HW_ATL_RPF_VL_EN_F_WIDTH 1 1098 /* Default value of bitfield vl_en{F} */ 1099 #define HW_ATL_RPF_VL_EN_F_DEFAULT 0x0 1100 1101 /* RX vl_act{F}[2:0] Bitfield Definitions 1102 * Preprocessor definitions for the bitfield "vl_act{F}[2:0]". 1103 * Parameter: filter {F} | stride size 0x4 | range [0, 15] 1104 * PORT="pif_rpf_vl_act0_i[2:0]" 1105 */ 1106 1107 /* Register address for bitfield vl_act{F}[2:0] */ 1108 #define HW_ATL_RPF_VL_ACT_F_ADR(filter) (0x00005290 + (filter) * 0x4) 1109 /* Bitmask for bitfield vl_act{F}[2:0] */ 1110 #define HW_ATL_RPF_VL_ACT_F_MSK 0x00070000 1111 /* Inverted bitmask for bitfield vl_act{F}[2:0] */ 1112 #define HW_ATL_RPF_VL_ACT_F_MSKN 0xFFF8FFFF 1113 /* Lower bit position of bitfield vl_act{F}[2:0] */ 1114 #define HW_ATL_RPF_VL_ACT_F_SHIFT 16 1115 /* Width of bitfield vl_act{F}[2:0] */ 1116 #define HW_ATL_RPF_VL_ACT_F_WIDTH 3 1117 /* Default value of bitfield vl_act{F}[2:0] */ 1118 #define HW_ATL_RPF_VL_ACT_F_DEFAULT 0x0 1119 1120 /* RX vl_id{F}[B:0] Bitfield Definitions 1121 * Preprocessor definitions for the bitfield "vl_id{F}[B:0]". 1122 * Parameter: filter {F} | stride size 0x4 | range [0, 15] 1123 * PORT="pif_rpf_vl_id0_i[11:0]" 1124 */ 1125 1126 /* Register address for bitfield vl_id{F}[B:0] */ 1127 #define HW_ATL_RPF_VL_ID_F_ADR(filter) (0x00005290 + (filter) * 0x4) 1128 /* Bitmask for bitfield vl_id{F}[B:0] */ 1129 #define HW_ATL_RPF_VL_ID_F_MSK 0x00000FFF 1130 /* Inverted bitmask for bitfield vl_id{F}[B:0] */ 1131 #define HW_ATL_RPF_VL_ID_F_MSKN 0xFFFFF000 1132 /* Lower bit position of bitfield vl_id{F}[B:0] */ 1133 #define HW_ATL_RPF_VL_ID_F_SHIFT 0 1134 /* Width of bitfield vl_id{F}[B:0] */ 1135 #define HW_ATL_RPF_VL_ID_F_WIDTH 12 1136 /* Default value of bitfield vl_id{F}[B:0] */ 1137 #define HW_ATL_RPF_VL_ID_F_DEFAULT 0x0 1138 1139 /* RX vl_rxq_en{F} Bitfield Definitions 1140 * Preprocessor definitions for the bitfield "vl_rxq{F}". 1141 * Parameter: filter {F} | stride size 0x4 | range [0, 15] 1142 * PORT="pif_rpf_vl_rxq_en_i" 1143 */ 1144 1145 /* Register address for bitfield vl_rxq_en{F} */ 1146 #define HW_ATL_RPF_VL_RXQ_EN_F_ADR(filter) (0x00005290 + (filter) * 0x4) 1147 /* Bitmask for bitfield vl_rxq_en{F} */ 1148 #define HW_ATL_RPF_VL_RXQ_EN_F_MSK 0x10000000 1149 /* Inverted bitmask for bitfield vl_rxq_en{F}[ */ 1150 #define HW_ATL_RPF_VL_RXQ_EN_F_MSKN 0xEFFFFFFF 1151 /* Lower bit position of bitfield vl_rxq_en{F} */ 1152 #define HW_ATL_RPF_VL_RXQ_EN_F_SHIFT 28 1153 /* Width of bitfield vl_rxq_en{F} */ 1154 #define HW_ATL_RPF_VL_RXQ_EN_F_WIDTH 1 1155 /* Default value of bitfield vl_rxq_en{F} */ 1156 #define HW_ATL_RPF_VL_RXQ_EN_F_DEFAULT 0x0 1157 1158 /* RX vl_rxq{F}[4:0] Bitfield Definitions 1159 * Preprocessor definitions for the bitfield "vl_rxq{F}[4:0]". 1160 * Parameter: filter {F} | stride size 0x4 | range [0, 15] 1161 * PORT="pif_rpf_vl_rxq0_i[4:0]" 1162 */ 1163 1164 /* Register address for bitfield vl_rxq{F}[4:0] */ 1165 #define HW_ATL_RPF_VL_RXQ_F_ADR(filter) (0x00005290 + (filter) * 0x4) 1166 /* Bitmask for bitfield vl_rxq{F}[4:0] */ 1167 #define HW_ATL_RPF_VL_RXQ_F_MSK 0x01F00000 1168 /* Inverted bitmask for bitfield vl_rxq{F}[4:0] */ 1169 #define HW_ATL_RPF_VL_RXQ_F_MSKN 0xFE0FFFFF 1170 /* Lower bit position of bitfield vl_rxq{F}[4:0] */ 1171 #define HW_ATL_RPF_VL_RXQ_F_SHIFT 20 1172 /* Width of bitfield vl_rxw{F}[4:0] */ 1173 #define HW_ATL_RPF_VL_RXQ_F_WIDTH 5 1174 /* Default value of bitfield vl_rxq{F}[4:0] */ 1175 #define HW_ATL_RPF_VL_RXQ_F_DEFAULT 0x0 1176 1177 /* rx et_en{f} bitfield definitions 1178 * preprocessor definitions for the bitfield "et_en{f}". 1179 * parameter: filter {f} | stride size 0x4 | range [0, 15] 1180 * port="pif_rpf_et_en_i[0]" 1181 */ 1182 1183 /* register address for bitfield et_en{f} */ 1184 #define HW_ATL_RPF_ET_ENF_ADR(filter) (0x00005300 + (filter) * 0x4) 1185 /* bitmask for bitfield et_en{f} */ 1186 #define HW_ATL_RPF_ET_ENF_MSK 0x80000000 1187 /* inverted bitmask for bitfield et_en{f} */ 1188 #define HW_ATL_RPF_ET_ENF_MSKN 0x7fffffff 1189 /* lower bit position of bitfield et_en{f} */ 1190 #define HW_ATL_RPF_ET_ENF_SHIFT 31 1191 /* width of bitfield et_en{f} */ 1192 #define HW_ATL_RPF_ET_ENF_WIDTH 1 1193 /* default value of bitfield et_en{f} */ 1194 #define HW_ATL_RPF_ET_ENF_DEFAULT 0x0 1195 1196 /* rx et_up{f}_en bitfield definitions 1197 * preprocessor definitions for the bitfield "et_up{f}_en". 1198 * parameter: filter {f} | stride size 0x4 | range [0, 15] 1199 * port="pif_rpf_et_up_en_i[0]" 1200 */ 1201 1202 /* register address for bitfield et_up{f}_en */ 1203 #define HW_ATL_RPF_ET_UPFEN_ADR(filter) (0x00005300 + (filter) * 0x4) 1204 /* bitmask for bitfield et_up{f}_en */ 1205 #define HW_ATL_RPF_ET_UPFEN_MSK 0x40000000 1206 /* inverted bitmask for bitfield et_up{f}_en */ 1207 #define HW_ATL_RPF_ET_UPFEN_MSKN 0xbfffffff 1208 /* lower bit position of bitfield et_up{f}_en */ 1209 #define HW_ATL_RPF_ET_UPFEN_SHIFT 30 1210 /* width of bitfield et_up{f}_en */ 1211 #define HW_ATL_RPF_ET_UPFEN_WIDTH 1 1212 /* default value of bitfield et_up{f}_en */ 1213 #define HW_ATL_RPF_ET_UPFEN_DEFAULT 0x0 1214 1215 /* rx et_rxq{f}_en bitfield definitions 1216 * preprocessor definitions for the bitfield "et_rxq{f}_en". 1217 * parameter: filter {f} | stride size 0x4 | range [0, 15] 1218 * port="pif_rpf_et_rxq_en_i[0]" 1219 */ 1220 1221 /* register address for bitfield et_rxq{f}_en */ 1222 #define HW_ATL_RPF_ET_RXQFEN_ADR(filter) (0x00005300 + (filter) * 0x4) 1223 /* bitmask for bitfield et_rxq{f}_en */ 1224 #define HW_ATL_RPF_ET_RXQFEN_MSK 0x20000000 1225 /* inverted bitmask for bitfield et_rxq{f}_en */ 1226 #define HW_ATL_RPF_ET_RXQFEN_MSKN 0xdfffffff 1227 /* lower bit position of bitfield et_rxq{f}_en */ 1228 #define HW_ATL_RPF_ET_RXQFEN_SHIFT 29 1229 /* width of bitfield et_rxq{f}_en */ 1230 #define HW_ATL_RPF_ET_RXQFEN_WIDTH 1 1231 /* default value of bitfield et_rxq{f}_en */ 1232 #define HW_ATL_RPF_ET_RXQFEN_DEFAULT 0x0 1233 1234 /* rx et_up{f}[2:0] bitfield definitions 1235 * preprocessor definitions for the bitfield "et_up{f}[2:0]". 1236 * parameter: filter {f} | stride size 0x4 | range [0, 15] 1237 * port="pif_rpf_et_up0_i[2:0]" 1238 */ 1239 1240 /* register address for bitfield et_up{f}[2:0] */ 1241 #define HW_ATL_RPF_ET_UPF_ADR(filter) (0x00005300 + (filter) * 0x4) 1242 /* bitmask for bitfield et_up{f}[2:0] */ 1243 #define HW_ATL_RPF_ET_UPF_MSK 0x1c000000 1244 /* inverted bitmask for bitfield et_up{f}[2:0] */ 1245 #define HW_ATL_RPF_ET_UPF_MSKN 0xe3ffffff 1246 /* lower bit position of bitfield et_up{f}[2:0] */ 1247 #define HW_ATL_RPF_ET_UPF_SHIFT 26 1248 /* width of bitfield et_up{f}[2:0] */ 1249 #define HW_ATL_RPF_ET_UPF_WIDTH 3 1250 /* default value of bitfield et_up{f}[2:0] */ 1251 #define HW_ATL_RPF_ET_UPF_DEFAULT 0x0 1252 1253 /* rx et_rxq{f}[4:0] bitfield definitions 1254 * preprocessor definitions for the bitfield "et_rxq{f}[4:0]". 1255 * parameter: filter {f} | stride size 0x4 | range [0, 15] 1256 * port="pif_rpf_et_rxq0_i[4:0]" 1257 */ 1258 1259 /* register address for bitfield et_rxq{f}[4:0] */ 1260 #define HW_ATL_RPF_ET_RXQF_ADR(filter) (0x00005300 + (filter) * 0x4) 1261 /* bitmask for bitfield et_rxq{f}[4:0] */ 1262 #define HW_ATL_RPF_ET_RXQF_MSK 0x01f00000 1263 /* inverted bitmask for bitfield et_rxq{f}[4:0] */ 1264 #define HW_ATL_RPF_ET_RXQF_MSKN 0xfe0fffff 1265 /* lower bit position of bitfield et_rxq{f}[4:0] */ 1266 #define HW_ATL_RPF_ET_RXQF_SHIFT 20 1267 /* width of bitfield et_rxq{f}[4:0] */ 1268 #define HW_ATL_RPF_ET_RXQF_WIDTH 5 1269 /* default value of bitfield et_rxq{f}[4:0] */ 1270 #define HW_ATL_RPF_ET_RXQF_DEFAULT 0x0 1271 1272 /* rx et_mng_rxq{f} bitfield definitions 1273 * preprocessor definitions for the bitfield "et_mng_rxq{f}". 1274 * parameter: filter {f} | stride size 0x4 | range [0, 15] 1275 * port="pif_rpf_et_mng_rxq_i[0]" 1276 */ 1277 1278 /* register address for bitfield et_mng_rxq{f} */ 1279 #define HW_ATL_RPF_ET_MNG_RXQF_ADR(filter) (0x00005300 + (filter) * 0x4) 1280 /* bitmask for bitfield et_mng_rxq{f} */ 1281 #define HW_ATL_RPF_ET_MNG_RXQF_MSK 0x00080000 1282 /* inverted bitmask for bitfield et_mng_rxq{f} */ 1283 #define HW_ATL_RPF_ET_MNG_RXQF_MSKN 0xfff7ffff 1284 /* lower bit position of bitfield et_mng_rxq{f} */ 1285 #define HW_ATL_RPF_ET_MNG_RXQF_SHIFT 19 1286 /* width of bitfield et_mng_rxq{f} */ 1287 #define HW_ATL_RPF_ET_MNG_RXQF_WIDTH 1 1288 /* default value of bitfield et_mng_rxq{f} */ 1289 #define HW_ATL_RPF_ET_MNG_RXQF_DEFAULT 0x0 1290 1291 /* rx et_act{f}[2:0] bitfield definitions 1292 * preprocessor definitions for the bitfield "et_act{f}[2:0]". 1293 * parameter: filter {f} | stride size 0x4 | range [0, 15] 1294 * port="pif_rpf_et_act0_i[2:0]" 1295 */ 1296 1297 /* register address for bitfield et_act{f}[2:0] */ 1298 #define HW_ATL_RPF_ET_ACTF_ADR(filter) (0x00005300 + (filter) * 0x4) 1299 /* bitmask for bitfield et_act{f}[2:0] */ 1300 #define HW_ATL_RPF_ET_ACTF_MSK 0x00070000 1301 /* inverted bitmask for bitfield et_act{f}[2:0] */ 1302 #define HW_ATL_RPF_ET_ACTF_MSKN 0xfff8ffff 1303 /* lower bit position of bitfield et_act{f}[2:0] */ 1304 #define HW_ATL_RPF_ET_ACTF_SHIFT 16 1305 /* width of bitfield et_act{f}[2:0] */ 1306 #define HW_ATL_RPF_ET_ACTF_WIDTH 3 1307 /* default value of bitfield et_act{f}[2:0] */ 1308 #define HW_ATL_RPF_ET_ACTF_DEFAULT 0x0 1309 1310 /* rx et_val{f}[f:0] bitfield definitions 1311 * preprocessor definitions for the bitfield "et_val{f}[f:0]". 1312 * parameter: filter {f} | stride size 0x4 | range [0, 15] 1313 * port="pif_rpf_et_val0_i[15:0]" 1314 */ 1315 1316 /* register address for bitfield et_val{f}[f:0] */ 1317 #define HW_ATL_RPF_ET_VALF_ADR(filter) (0x00005300 + (filter) * 0x4) 1318 /* bitmask for bitfield et_val{f}[f:0] */ 1319 #define HW_ATL_RPF_ET_VALF_MSK 0x0000ffff 1320 /* inverted bitmask for bitfield et_val{f}[f:0] */ 1321 #define HW_ATL_RPF_ET_VALF_MSKN 0xffff0000 1322 /* lower bit position of bitfield et_val{f}[f:0] */ 1323 #define HW_ATL_RPF_ET_VALF_SHIFT 0 1324 /* width of bitfield et_val{f}[f:0] */ 1325 #define HW_ATL_RPF_ET_VALF_WIDTH 16 1326 /* default value of bitfield et_val{f}[f:0] */ 1327 #define HW_ATL_RPF_ET_VALF_DEFAULT 0x0 1328 1329 /* RX l3_l4_en{F} Bitfield Definitions 1330 * Preprocessor definitions for the bitfield "l3_l4_en{F}". 1331 * Parameter: filter {F} | stride size 0x4 | range [0, 7] 1332 * PORT="pif_rpf_l3_l4_en_i[0]" 1333 */ 1334 1335 #define HW_ATL_RPF_L3_REG_CTRL_ADR(filter) (0x00005380 + (filter) * 0x4) 1336 1337 /* RX rpf_l3_sa{D}[1F:0] Bitfield Definitions 1338 * Preprocessor definitions for the bitfield "l3_sa{D}[1F:0]". 1339 * Parameter: location {D} | stride size 0x4 | range [0, 7] 1340 * PORT="pif_rpf_l3_sa0_i[31:0]" 1341 */ 1342 1343 /* Register address for bitfield pif_rpf_l3_sa0_i[31:0] */ 1344 #define HW_ATL_RPF_L3_SRCA_ADR(filter) (0x000053B0 + (filter) * 0x4) 1345 /* Bitmask for bitfield l3_sa0[1F:0] */ 1346 #define HW_ATL_RPF_L3_SRCA_MSK 0xFFFFFFFFu 1347 /* Inverted bitmask for bitfield l3_sa0[1F:0] */ 1348 #define HW_ATL_RPF_L3_SRCA_MSKN 0xFFFFFFFFu 1349 /* Lower bit position of bitfield l3_sa0[1F:0] */ 1350 #define HW_ATL_RPF_L3_SRCA_SHIFT 0 1351 /* Width of bitfield l3_sa0[1F:0] */ 1352 #define HW_ATL_RPF_L3_SRCA_WIDTH 32 1353 /* Default value of bitfield l3_sa0[1F:0] */ 1354 #define HW_ATL_RPF_L3_SRCA_DEFAULT 0x0 1355 1356 /* RX rpf_l3_da{D}[1F:0] Bitfield Definitions 1357 * Preprocessor definitions for the bitfield "l3_da{D}[1F:0]". 1358 * Parameter: location {D} | stride size 0x4 | range [0, 7] 1359 * PORT="pif_rpf_l3_da0_i[31:0]" 1360 */ 1361 1362 /* Register address for bitfield pif_rpf_l3_da0_i[31:0] */ 1363 #define HW_ATL_RPF_L3_DSTA_ADR(filter) (0x000053D0 + (filter) * 0x4) 1364 /* Bitmask for bitfield l3_da0[1F:0] */ 1365 #define HW_ATL_RPF_L3_DSTA_MSK 0xFFFFFFFFu 1366 /* Inverted bitmask for bitfield l3_da0[1F:0] */ 1367 #define HW_ATL_RPF_L3_DSTA_MSKN 0xFFFFFFFFu 1368 /* Lower bit position of bitfield l3_da0[1F:0] */ 1369 #define HW_ATL_RPF_L3_DSTA_SHIFT 0 1370 /* Width of bitfield l3_da0[1F:0] */ 1371 #define HW_ATL_RPF_L3_DSTA_WIDTH 32 1372 /* Default value of bitfield l3_da0[1F:0] */ 1373 #define HW_ATL_RPF_L3_DSTA_DEFAULT 0x0 1374 1375 /* RX l4_sp{D}[F:0] Bitfield Definitions 1376 * Preprocessor definitions for the bitfield "l4_sp{D}[F:0]". 1377 * Parameter: srcport {D} | stride size 0x4 | range [0, 7] 1378 * PORT="pif_rpf_l4_sp0_i[15:0]" 1379 */ 1380 1381 /* Register address for bitfield l4_sp{D}[F:0] */ 1382 #define HW_ATL_RPF_L4_SPD_ADR(srcport) (0x00005400u + (srcport) * 0x4) 1383 /* Bitmask for bitfield l4_sp{D}[F:0] */ 1384 #define HW_ATL_RPF_L4_SPD_MSK 0x0000FFFFu 1385 /* Inverted bitmask for bitfield l4_sp{D}[F:0] */ 1386 #define HW_ATL_RPF_L4_SPD_MSKN 0xFFFF0000u 1387 /* Lower bit position of bitfield l4_sp{D}[F:0] */ 1388 #define HW_ATL_RPF_L4_SPD_SHIFT 0 1389 /* Width of bitfield l4_sp{D}[F:0] */ 1390 #define HW_ATL_RPF_L4_SPD_WIDTH 16 1391 /* Default value of bitfield l4_sp{D}[F:0] */ 1392 #define HW_ATL_RPF_L4_SPD_DEFAULT 0x0 1393 1394 /* RX l4_dp{D}[F:0] Bitfield Definitions 1395 * Preprocessor definitions for the bitfield "l4_dp{D}[F:0]". 1396 * Parameter: destport {D} | stride size 0x4 | range [0, 7] 1397 * PORT="pif_rpf_l4_dp0_i[15:0]" 1398 */ 1399 1400 /* Register address for bitfield l4_dp{D}[F:0] */ 1401 #define HW_ATL_RPF_L4_DPD_ADR(destport) (0x00005420u + (destport) * 0x4) 1402 /* Bitmask for bitfield l4_dp{D}[F:0] */ 1403 #define HW_ATL_RPF_L4_DPD_MSK 0x0000FFFFu 1404 /* Inverted bitmask for bitfield l4_dp{D}[F:0] */ 1405 #define HW_ATL_RPF_L4_DPD_MSKN 0xFFFF0000u 1406 /* Lower bit position of bitfield l4_dp{D}[F:0] */ 1407 #define HW_ATL_RPF_L4_DPD_SHIFT 0 1408 /* Width of bitfield l4_dp{D}[F:0] */ 1409 #define HW_ATL_RPF_L4_DPD_WIDTH 16 1410 /* Default value of bitfield l4_dp{D}[F:0] */ 1411 #define HW_ATL_RPF_L4_DPD_DEFAULT 0x0 1412 1413 /* rx ipv4_chk_en bitfield definitions 1414 * preprocessor definitions for the bitfield "ipv4_chk_en". 1415 * port="pif_rpo_ipv4_chk_en_i" 1416 */ 1417 1418 /* register address for bitfield ipv4_chk_en */ 1419 #define HW_ATL_RPO_IPV4CHK_EN_ADR 0x00005580 1420 /* bitmask for bitfield ipv4_chk_en */ 1421 #define HW_ATL_RPO_IPV4CHK_EN_MSK 0x00000002 1422 /* inverted bitmask for bitfield ipv4_chk_en */ 1423 #define HW_ATL_RPO_IPV4CHK_EN_MSKN 0xfffffffd 1424 /* lower bit position of bitfield ipv4_chk_en */ 1425 #define HW_ATL_RPO_IPV4CHK_EN_SHIFT 1 1426 /* width of bitfield ipv4_chk_en */ 1427 #define HW_ATL_RPO_IPV4CHK_EN_WIDTH 1 1428 /* default value of bitfield ipv4_chk_en */ 1429 #define HW_ATL_RPO_IPV4CHK_EN_DEFAULT 0x0 1430 1431 /* rx desc{d}_vl_strip bitfield definitions 1432 * preprocessor definitions for the bitfield "desc{d}_vl_strip". 1433 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 1434 * port="pif_rpo_desc_vl_strip_i[0]" 1435 */ 1436 1437 /* register address for bitfield desc{d}_vl_strip */ 1438 #define HW_ATL_RPO_DESCDVL_STRIP_ADR(descriptor) \ 1439 (0x00005b08 + (descriptor) * 0x20) 1440 /* bitmask for bitfield desc{d}_vl_strip */ 1441 #define HW_ATL_RPO_DESCDVL_STRIP_MSK 0x20000000 1442 /* inverted bitmask for bitfield desc{d}_vl_strip */ 1443 #define HW_ATL_RPO_DESCDVL_STRIP_MSKN 0xdfffffff 1444 /* lower bit position of bitfield desc{d}_vl_strip */ 1445 #define HW_ATL_RPO_DESCDVL_STRIP_SHIFT 29 1446 /* width of bitfield desc{d}_vl_strip */ 1447 #define HW_ATL_RPO_DESCDVL_STRIP_WIDTH 1 1448 /* default value of bitfield desc{d}_vl_strip */ 1449 #define HW_ATL_RPO_DESCDVL_STRIP_DEFAULT 0x0 1450 1451 /* rx l4_chk_en bitfield definitions 1452 * preprocessor definitions for the bitfield "l4_chk_en". 1453 * port="pif_rpo_l4_chk_en_i" 1454 */ 1455 1456 /* register address for bitfield l4_chk_en */ 1457 #define HW_ATL_RPOL4CHK_EN_ADR 0x00005580 1458 /* bitmask for bitfield l4_chk_en */ 1459 #define HW_ATL_RPOL4CHK_EN_MSK 0x00000001 1460 /* inverted bitmask for bitfield l4_chk_en */ 1461 #define HW_ATL_RPOL4CHK_EN_MSKN 0xfffffffe 1462 /* lower bit position of bitfield l4_chk_en */ 1463 #define HW_ATL_RPOL4CHK_EN_SHIFT 0 1464 /* width of bitfield l4_chk_en */ 1465 #define HW_ATL_RPOL4CHK_EN_WIDTH 1 1466 /* default value of bitfield l4_chk_en */ 1467 #define HW_ATL_RPOL4CHK_EN_DEFAULT 0x0 1468 1469 /* RX outer_vl_ins_mode Bitfield Definitions 1470 * Preprocessor definitions for the bitfield "outer_vl_ins_mode". 1471 * PORT="pif_rpo_outer_vl_mode_i" 1472 */ 1473 1474 /* Register address for bitfield outer_vl_ins_mode */ 1475 #define HW_ATL_RPO_OUTER_VL_INS_MODE_ADR 0x00005580 1476 /* Bitmask for bitfield outer_vl_ins_mode */ 1477 #define HW_ATL_RPO_OUTER_VL_INS_MODE_MSK 0x00000004 1478 /* Inverted bitmask for bitfield outer_vl_ins_mode */ 1479 #define HW_ATL_RPO_OUTER_VL_INS_MODE_MSKN 0xFFFFFFFB 1480 /* Lower bit position of bitfield outer_vl_ins_mode */ 1481 #define HW_ATL_RPO_OUTER_VL_INS_MODE_SHIFT 2 1482 /* Width of bitfield outer_vl_ins_mode */ 1483 #define HW_ATL_RPO_OUTER_VL_INS_MODE_WIDTH 1 1484 /* Default value of bitfield outer_vl_ins_mode */ 1485 #define HW_ATL_RPO_OUTER_VL_INS_MODE_DEFAULT 0x0 1486 1487 /* rx reg_res_dsbl bitfield definitions 1488 * preprocessor definitions for the bitfield "reg_res_dsbl". 1489 * port="pif_rx_reg_res_dsbl_i" 1490 */ 1491 1492 /* register address for bitfield reg_res_dsbl */ 1493 #define HW_ATL_RX_REG_RES_DSBL_ADR 0x00005000 1494 /* bitmask for bitfield reg_res_dsbl */ 1495 #define HW_ATL_RX_REG_RES_DSBL_MSK 0x20000000 1496 /* inverted bitmask for bitfield reg_res_dsbl */ 1497 #define HW_ATL_RX_REG_RES_DSBL_MSKN 0xdfffffff 1498 /* lower bit position of bitfield reg_res_dsbl */ 1499 #define HW_ATL_RX_REG_RES_DSBL_SHIFT 29 1500 /* width of bitfield reg_res_dsbl */ 1501 #define HW_ATL_RX_REG_RES_DSBL_WIDTH 1 1502 /* default value of bitfield reg_res_dsbl */ 1503 #define HW_ATL_RX_REG_RES_DSBL_DEFAULT 0x1 1504 1505 /* tx dca{d}_cpuid[7:0] bitfield definitions 1506 * preprocessor definitions for the bitfield "dca{d}_cpuid[7:0]". 1507 * parameter: dca {d} | stride size 0x4 | range [0, 31] 1508 * port="pif_tdm_dca0_cpuid_i[7:0]" 1509 */ 1510 1511 /* register address for bitfield dca{d}_cpuid[7:0] */ 1512 #define HW_ATL_TDM_DCADCPUID_ADR(dca) (0x00008400 + (dca) * 0x4) 1513 /* bitmask for bitfield dca{d}_cpuid[7:0] */ 1514 #define HW_ATL_TDM_DCADCPUID_MSK 0x000000ff 1515 /* inverted bitmask for bitfield dca{d}_cpuid[7:0] */ 1516 #define HW_ATL_TDM_DCADCPUID_MSKN 0xffffff00 1517 /* lower bit position of bitfield dca{d}_cpuid[7:0] */ 1518 #define HW_ATL_TDM_DCADCPUID_SHIFT 0 1519 /* width of bitfield dca{d}_cpuid[7:0] */ 1520 #define HW_ATL_TDM_DCADCPUID_WIDTH 8 1521 /* default value of bitfield dca{d}_cpuid[7:0] */ 1522 #define HW_ATL_TDM_DCADCPUID_DEFAULT 0x0 1523 1524 /* tx lso_en[1f:0] bitfield definitions 1525 * preprocessor definitions for the bitfield "lso_en[1f:0]". 1526 * port="pif_tdm_lso_en_i[31:0]" 1527 */ 1528 1529 /* register address for bitfield lso_en[1f:0] */ 1530 #define HW_ATL_TDM_LSO_EN_ADR 0x00007810 1531 /* bitmask for bitfield lso_en[1f:0] */ 1532 #define HW_ATL_TDM_LSO_EN_MSK 0xffffffff 1533 /* inverted bitmask for bitfield lso_en[1f:0] */ 1534 #define HW_ATL_TDM_LSO_EN_MSKN 0x00000000 1535 /* lower bit position of bitfield lso_en[1f:0] */ 1536 #define HW_ATL_TDM_LSO_EN_SHIFT 0 1537 /* width of bitfield lso_en[1f:0] */ 1538 #define HW_ATL_TDM_LSO_EN_WIDTH 32 1539 /* default value of bitfield lso_en[1f:0] */ 1540 #define HW_ATL_TDM_LSO_EN_DEFAULT 0x0 1541 1542 /* tx dca_en bitfield definitions 1543 * preprocessor definitions for the bitfield "dca_en". 1544 * port="pif_tdm_dca_en_i" 1545 */ 1546 1547 /* register address for bitfield dca_en */ 1548 #define HW_ATL_TDM_DCA_EN_ADR 0x00008480 1549 /* bitmask for bitfield dca_en */ 1550 #define HW_ATL_TDM_DCA_EN_MSK 0x80000000 1551 /* inverted bitmask for bitfield dca_en */ 1552 #define HW_ATL_TDM_DCA_EN_MSKN 0x7fffffff 1553 /* lower bit position of bitfield dca_en */ 1554 #define HW_ATL_TDM_DCA_EN_SHIFT 31 1555 /* width of bitfield dca_en */ 1556 #define HW_ATL_TDM_DCA_EN_WIDTH 1 1557 /* default value of bitfield dca_en */ 1558 #define HW_ATL_TDM_DCA_EN_DEFAULT 0x1 1559 1560 /* tx dca_mode[3:0] bitfield definitions 1561 * preprocessor definitions for the bitfield "dca_mode[3:0]". 1562 * port="pif_tdm_dca_mode_i[3:0]" 1563 */ 1564 1565 /* register address for bitfield dca_mode[3:0] */ 1566 #define HW_ATL_TDM_DCA_MODE_ADR 0x00008480 1567 /* bitmask for bitfield dca_mode[3:0] */ 1568 #define HW_ATL_TDM_DCA_MODE_MSK 0x0000000f 1569 /* inverted bitmask for bitfield dca_mode[3:0] */ 1570 #define HW_ATL_TDM_DCA_MODE_MSKN 0xfffffff0 1571 /* lower bit position of bitfield dca_mode[3:0] */ 1572 #define HW_ATL_TDM_DCA_MODE_SHIFT 0 1573 /* width of bitfield dca_mode[3:0] */ 1574 #define HW_ATL_TDM_DCA_MODE_WIDTH 4 1575 /* default value of bitfield dca_mode[3:0] */ 1576 #define HW_ATL_TDM_DCA_MODE_DEFAULT 0x0 1577 1578 /* tx dca{d}_desc_en bitfield definitions 1579 * preprocessor definitions for the bitfield "dca{d}_desc_en". 1580 * parameter: dca {d} | stride size 0x4 | range [0, 31] 1581 * port="pif_tdm_dca_desc_en_i[0]" 1582 */ 1583 1584 /* register address for bitfield dca{d}_desc_en */ 1585 #define HW_ATL_TDM_DCADDESC_EN_ADR(dca) (0x00008400 + (dca) * 0x4) 1586 /* bitmask for bitfield dca{d}_desc_en */ 1587 #define HW_ATL_TDM_DCADDESC_EN_MSK 0x80000000 1588 /* inverted bitmask for bitfield dca{d}_desc_en */ 1589 #define HW_ATL_TDM_DCADDESC_EN_MSKN 0x7fffffff 1590 /* lower bit position of bitfield dca{d}_desc_en */ 1591 #define HW_ATL_TDM_DCADDESC_EN_SHIFT 31 1592 /* width of bitfield dca{d}_desc_en */ 1593 #define HW_ATL_TDM_DCADDESC_EN_WIDTH 1 1594 /* default value of bitfield dca{d}_desc_en */ 1595 #define HW_ATL_TDM_DCADDESC_EN_DEFAULT 0x0 1596 1597 /* tx desc{d}_en bitfield definitions 1598 * preprocessor definitions for the bitfield "desc{d}_en". 1599 * parameter: descriptor {d} | stride size 0x40 | range [0, 31] 1600 * port="pif_tdm_desc_en_i[0]" 1601 */ 1602 1603 /* register address for bitfield desc{d}_en */ 1604 #define HW_ATL_TDM_DESCDEN_ADR(descriptor) (0x00007c08 + (descriptor) * 0x40) 1605 /* bitmask for bitfield desc{d}_en */ 1606 #define HW_ATL_TDM_DESCDEN_MSK 0x80000000 1607 /* inverted bitmask for bitfield desc{d}_en */ 1608 #define HW_ATL_TDM_DESCDEN_MSKN 0x7fffffff 1609 /* lower bit position of bitfield desc{d}_en */ 1610 #define HW_ATL_TDM_DESCDEN_SHIFT 31 1611 /* width of bitfield desc{d}_en */ 1612 #define HW_ATL_TDM_DESCDEN_WIDTH 1 1613 /* default value of bitfield desc{d}_en */ 1614 #define HW_ATL_TDM_DESCDEN_DEFAULT 0x0 1615 1616 /* tx desc{d}_hd[c:0] bitfield definitions 1617 * preprocessor definitions for the bitfield "desc{d}_hd[c:0]". 1618 * parameter: descriptor {d} | stride size 0x40 | range [0, 31] 1619 * port="tdm_pif_desc0_hd_o[12:0]" 1620 */ 1621 1622 /* register address for bitfield desc{d}_hd[c:0] */ 1623 #define HW_ATL_TDM_DESCDHD_ADR(descriptor) (0x00007c0c + (descriptor) * 0x40) 1624 /* bitmask for bitfield desc{d}_hd[c:0] */ 1625 #define HW_ATL_TDM_DESCDHD_MSK 0x00001fff 1626 /* inverted bitmask for bitfield desc{d}_hd[c:0] */ 1627 #define HW_ATL_TDM_DESCDHD_MSKN 0xffffe000 1628 /* lower bit position of bitfield desc{d}_hd[c:0] */ 1629 #define HW_ATL_TDM_DESCDHD_SHIFT 0 1630 /* width of bitfield desc{d}_hd[c:0] */ 1631 #define HW_ATL_TDM_DESCDHD_WIDTH 13 1632 1633 /* tx desc{d}_len[9:0] bitfield definitions 1634 * preprocessor definitions for the bitfield "desc{d}_len[9:0]". 1635 * parameter: descriptor {d} | stride size 0x40 | range [0, 31] 1636 * port="pif_tdm_desc0_len_i[9:0]" 1637 */ 1638 1639 /* register address for bitfield desc{d}_len[9:0] */ 1640 #define HW_ATL_TDM_DESCDLEN_ADR(descriptor) (0x00007c08 + (descriptor) * 0x40) 1641 /* bitmask for bitfield desc{d}_len[9:0] */ 1642 #define HW_ATL_TDM_DESCDLEN_MSK 0x00001ff8 1643 /* inverted bitmask for bitfield desc{d}_len[9:0] */ 1644 #define HW_ATL_TDM_DESCDLEN_MSKN 0xffffe007 1645 /* lower bit position of bitfield desc{d}_len[9:0] */ 1646 #define HW_ATL_TDM_DESCDLEN_SHIFT 3 1647 /* width of bitfield desc{d}_len[9:0] */ 1648 #define HW_ATL_TDM_DESCDLEN_WIDTH 10 1649 /* default value of bitfield desc{d}_len[9:0] */ 1650 #define HW_ATL_TDM_DESCDLEN_DEFAULT 0x0 1651 1652 /* tx int_desc_wrb_en bitfield definitions 1653 * preprocessor definitions for the bitfield "int_desc_wrb_en". 1654 * port="pif_tdm_int_desc_wrb_en_i" 1655 */ 1656 1657 /* register address for bitfield int_desc_wrb_en */ 1658 #define HW_ATL_TDM_INT_DESC_WRB_EN_ADR 0x00007b40 1659 /* bitmask for bitfield int_desc_wrb_en */ 1660 #define HW_ATL_TDM_INT_DESC_WRB_EN_MSK 0x00000002 1661 /* inverted bitmask for bitfield int_desc_wrb_en */ 1662 #define HW_ATL_TDM_INT_DESC_WRB_EN_MSKN 0xfffffffd 1663 /* lower bit position of bitfield int_desc_wrb_en */ 1664 #define HW_ATL_TDM_INT_DESC_WRB_EN_SHIFT 1 1665 /* width of bitfield int_desc_wrb_en */ 1666 #define HW_ATL_TDM_INT_DESC_WRB_EN_WIDTH 1 1667 /* default value of bitfield int_desc_wrb_en */ 1668 #define HW_ATL_TDM_INT_DESC_WRB_EN_DEFAULT 0x0 1669 1670 /* tx desc{d}_wrb_thresh[6:0] bitfield definitions 1671 * preprocessor definitions for the bitfield "desc{d}_wrb_thresh[6:0]". 1672 * parameter: descriptor {d} | stride size 0x40 | range [0, 31] 1673 * port="pif_tdm_desc0_wrb_thresh_i[6:0]" 1674 */ 1675 1676 /* register address for bitfield desc{d}_wrb_thresh[6:0] */ 1677 #define HW_ATL_TDM_DESCDWRB_THRESH_ADR(descriptor) \ 1678 (0x00007c18 + (descriptor) * 0x40) 1679 /* bitmask for bitfield desc{d}_wrb_thresh[6:0] */ 1680 #define HW_ATL_TDM_DESCDWRB_THRESH_MSK 0x00007f00 1681 /* inverted bitmask for bitfield desc{d}_wrb_thresh[6:0] */ 1682 #define HW_ATL_TDM_DESCDWRB_THRESH_MSKN 0xffff80ff 1683 /* lower bit position of bitfield desc{d}_wrb_thresh[6:0] */ 1684 #define HW_ATL_TDM_DESCDWRB_THRESH_SHIFT 8 1685 /* width of bitfield desc{d}_wrb_thresh[6:0] */ 1686 #define HW_ATL_TDM_DESCDWRB_THRESH_WIDTH 7 1687 /* default value of bitfield desc{d}_wrb_thresh[6:0] */ 1688 #define HW_ATL_TDM_DESCDWRB_THRESH_DEFAULT 0x0 1689 1690 /* tx lso_tcp_flag_first[b:0] bitfield definitions 1691 * preprocessor definitions for the bitfield "lso_tcp_flag_first[b:0]". 1692 * port="pif_thm_lso_tcp_flag_first_i[11:0]" 1693 */ 1694 1695 /* register address for bitfield lso_tcp_flag_first[b:0] */ 1696 #define HW_ATL_THM_LSO_TCP_FLAG_FIRST_ADR 0x00007820 1697 /* bitmask for bitfield lso_tcp_flag_first[b:0] */ 1698 #define HW_ATL_THM_LSO_TCP_FLAG_FIRST_MSK 0x00000fff 1699 /* inverted bitmask for bitfield lso_tcp_flag_first[b:0] */ 1700 #define HW_ATL_THM_LSO_TCP_FLAG_FIRST_MSKN 0xfffff000 1701 /* lower bit position of bitfield lso_tcp_flag_first[b:0] */ 1702 #define HW_ATL_THM_LSO_TCP_FLAG_FIRST_SHIFT 0 1703 /* width of bitfield lso_tcp_flag_first[b:0] */ 1704 #define HW_ATL_THM_LSO_TCP_FLAG_FIRST_WIDTH 12 1705 /* default value of bitfield lso_tcp_flag_first[b:0] */ 1706 #define HW_ATL_THM_LSO_TCP_FLAG_FIRST_DEFAULT 0x0 1707 1708 /* tx lso_tcp_flag_last[b:0] bitfield definitions 1709 * preprocessor definitions for the bitfield "lso_tcp_flag_last[b:0]". 1710 * port="pif_thm_lso_tcp_flag_last_i[11:0]" 1711 */ 1712 1713 /* register address for bitfield lso_tcp_flag_last[b:0] */ 1714 #define HW_ATL_THM_LSO_TCP_FLAG_LAST_ADR 0x00007824 1715 /* bitmask for bitfield lso_tcp_flag_last[b:0] */ 1716 #define HW_ATL_THM_LSO_TCP_FLAG_LAST_MSK 0x00000fff 1717 /* inverted bitmask for bitfield lso_tcp_flag_last[b:0] */ 1718 #define HW_ATL_THM_LSO_TCP_FLAG_LAST_MSKN 0xfffff000 1719 /* lower bit position of bitfield lso_tcp_flag_last[b:0] */ 1720 #define HW_ATL_THM_LSO_TCP_FLAG_LAST_SHIFT 0 1721 /* width of bitfield lso_tcp_flag_last[b:0] */ 1722 #define HW_ATL_THM_LSO_TCP_FLAG_LAST_WIDTH 12 1723 /* default value of bitfield lso_tcp_flag_last[b:0] */ 1724 #define HW_ATL_THM_LSO_TCP_FLAG_LAST_DEFAULT 0x0 1725 1726 /* tx lso_tcp_flag_mid[b:0] bitfield definitions 1727 * preprocessor definitions for the bitfield "lso_tcp_flag_mid[b:0]". 1728 * port="pif_thm_lso_tcp_flag_mid_i[11:0]" 1729 */ 1730 1731 /* Register address for bitfield lro_rsc_max[1F:0] */ 1732 #define HW_ATL_RPO_LRO_RSC_MAX_ADR 0x00005598 1733 /* Bitmask for bitfield lro_rsc_max[1F:0] */ 1734 #define HW_ATL_RPO_LRO_RSC_MAX_MSK 0xFFFFFFFF 1735 /* Inverted bitmask for bitfield lro_rsc_max[1F:0] */ 1736 #define HW_ATL_RPO_LRO_RSC_MAX_MSKN 0x00000000 1737 /* Lower bit position of bitfield lro_rsc_max[1F:0] */ 1738 #define HW_ATL_RPO_LRO_RSC_MAX_SHIFT 0 1739 /* Width of bitfield lro_rsc_max[1F:0] */ 1740 #define HW_ATL_RPO_LRO_RSC_MAX_WIDTH 32 1741 /* Default value of bitfield lro_rsc_max[1F:0] */ 1742 #define HW_ATL_RPO_LRO_RSC_MAX_DEFAULT 0x0 1743 1744 /* RX lro_en[1F:0] Bitfield Definitions 1745 * Preprocessor definitions for the bitfield "lro_en[1F:0]". 1746 * PORT="pif_rpo_lro_en_i[31:0]" 1747 */ 1748 1749 /* Register address for bitfield lro_en[1F:0] */ 1750 #define HW_ATL_RPO_LRO_EN_ADR 0x00005590 1751 /* Bitmask for bitfield lro_en[1F:0] */ 1752 #define HW_ATL_RPO_LRO_EN_MSK 0xFFFFFFFF 1753 /* Inverted bitmask for bitfield lro_en[1F:0] */ 1754 #define HW_ATL_RPO_LRO_EN_MSKN 0x00000000 1755 /* Lower bit position of bitfield lro_en[1F:0] */ 1756 #define HW_ATL_RPO_LRO_EN_SHIFT 0 1757 /* Width of bitfield lro_en[1F:0] */ 1758 #define HW_ATL_RPO_LRO_EN_WIDTH 32 1759 /* Default value of bitfield lro_en[1F:0] */ 1760 #define HW_ATL_RPO_LRO_EN_DEFAULT 0x0 1761 1762 /* RX lro_ptopt_en Bitfield Definitions 1763 * Preprocessor definitions for the bitfield "lro_ptopt_en". 1764 * PORT="pif_rpo_lro_ptopt_en_i" 1765 */ 1766 1767 /* Register address for bitfield lro_ptopt_en */ 1768 #define HW_ATL_RPO_LRO_PTOPT_EN_ADR 0x00005594 1769 /* Bitmask for bitfield lro_ptopt_en */ 1770 #define HW_ATL_RPO_LRO_PTOPT_EN_MSK 0x00008000 1771 /* Inverted bitmask for bitfield lro_ptopt_en */ 1772 #define HW_ATL_RPO_LRO_PTOPT_EN_MSKN 0xFFFF7FFF 1773 /* Lower bit position of bitfield lro_ptopt_en */ 1774 #define HW_ATL_RPO_LRO_PTOPT_EN_SHIFT 15 1775 /* Width of bitfield lro_ptopt_en */ 1776 #define HW_ATL_RPO_LRO_PTOPT_EN_WIDTH 1 1777 /* Default value of bitfield lro_ptopt_en */ 1778 #define HW_ATL_RPO_LRO_PTOPT_EN_DEFALT 0x1 1779 1780 /* RX lro_q_ses_lmt Bitfield Definitions 1781 * Preprocessor definitions for the bitfield "lro_q_ses_lmt". 1782 * PORT="pif_rpo_lro_q_ses_lmt_i[1:0]" 1783 */ 1784 1785 /* Register address for bitfield lro_q_ses_lmt */ 1786 #define HW_ATL_RPO_LRO_QSES_LMT_ADR 0x00005594 1787 /* Bitmask for bitfield lro_q_ses_lmt */ 1788 #define HW_ATL_RPO_LRO_QSES_LMT_MSK 0x00003000 1789 /* Inverted bitmask for bitfield lro_q_ses_lmt */ 1790 #define HW_ATL_RPO_LRO_QSES_LMT_MSKN 0xFFFFCFFF 1791 /* Lower bit position of bitfield lro_q_ses_lmt */ 1792 #define HW_ATL_RPO_LRO_QSES_LMT_SHIFT 12 1793 /* Width of bitfield lro_q_ses_lmt */ 1794 #define HW_ATL_RPO_LRO_QSES_LMT_WIDTH 2 1795 /* Default value of bitfield lro_q_ses_lmt */ 1796 #define HW_ATL_RPO_LRO_QSES_LMT_DEFAULT 0x1 1797 1798 /* RX lro_tot_dsc_lmt[1:0] Bitfield Definitions 1799 * Preprocessor definitions for the bitfield "lro_tot_dsc_lmt[1:0]". 1800 * PORT="pif_rpo_lro_tot_dsc_lmt_i[1:0]" 1801 */ 1802 1803 /* Register address for bitfield lro_tot_dsc_lmt[1:0] */ 1804 #define HW_ATL_RPO_LRO_TOT_DSC_LMT_ADR 0x00005594 1805 /* Bitmask for bitfield lro_tot_dsc_lmt[1:0] */ 1806 #define HW_ATL_RPO_LRO_TOT_DSC_LMT_MSK 0x00000060 1807 /* Inverted bitmask for bitfield lro_tot_dsc_lmt[1:0] */ 1808 #define HW_ATL_RPO_LRO_TOT_DSC_LMT_MSKN 0xFFFFFF9F 1809 /* Lower bit position of bitfield lro_tot_dsc_lmt[1:0] */ 1810 #define HW_ATL_RPO_LRO_TOT_DSC_LMT_SHIFT 5 1811 /* Width of bitfield lro_tot_dsc_lmt[1:0] */ 1812 #define HW_ATL_RPO_LRO_TOT_DSC_LMT_WIDTH 2 1813 /* Default value of bitfield lro_tot_dsc_lmt[1:0] */ 1814 #define HW_ATL_RPO_LRO_TOT_DSC_LMT_DEFALT 0x1 1815 1816 /* RX lro_pkt_min[4:0] Bitfield Definitions 1817 * Preprocessor definitions for the bitfield "lro_pkt_min[4:0]". 1818 * PORT="pif_rpo_lro_pkt_min_i[4:0]" 1819 */ 1820 1821 /* Register address for bitfield lro_pkt_min[4:0] */ 1822 #define HW_ATL_RPO_LRO_PKT_MIN_ADR 0x00005594 1823 /* Bitmask for bitfield lro_pkt_min[4:0] */ 1824 #define HW_ATL_RPO_LRO_PKT_MIN_MSK 0x0000001F 1825 /* Inverted bitmask for bitfield lro_pkt_min[4:0] */ 1826 #define HW_ATL_RPO_LRO_PKT_MIN_MSKN 0xFFFFFFE0 1827 /* Lower bit position of bitfield lro_pkt_min[4:0] */ 1828 #define HW_ATL_RPO_LRO_PKT_MIN_SHIFT 0 1829 /* Width of bitfield lro_pkt_min[4:0] */ 1830 #define HW_ATL_RPO_LRO_PKT_MIN_WIDTH 5 1831 /* Default value of bitfield lro_pkt_min[4:0] */ 1832 #define HW_ATL_RPO_LRO_PKT_MIN_DEFAULT 0x8 1833 1834 /* Width of bitfield lro{L}_des_max[1:0] */ 1835 #define HW_ATL_RPO_LRO_LDES_MAX_WIDTH 2 1836 /* Default value of bitfield lro{L}_des_max[1:0] */ 1837 #define HW_ATL_RPO_LRO_LDES_MAX_DEFAULT 0x0 1838 1839 /* RX lro_tb_div[11:0] Bitfield Definitions 1840 * Preprocessor definitions for the bitfield "lro_tb_div[11:0]". 1841 * PORT="pif_rpo_lro_tb_div_i[11:0]" 1842 */ 1843 1844 /* Register address for bitfield lro_tb_div[11:0] */ 1845 #define HW_ATL_RPO_LRO_TB_DIV_ADR 0x00005620 1846 /* Bitmask for bitfield lro_tb_div[11:0] */ 1847 #define HW_ATL_RPO_LRO_TB_DIV_MSK 0xFFF00000 1848 /* Inverted bitmask for bitfield lro_tb_div[11:0] */ 1849 #define HW_ATL_RPO_LRO_TB_DIV_MSKN 0x000FFFFF 1850 /* Lower bit position of bitfield lro_tb_div[11:0] */ 1851 #define HW_ATL_RPO_LRO_TB_DIV_SHIFT 20 1852 /* Width of bitfield lro_tb_div[11:0] */ 1853 #define HW_ATL_RPO_LRO_TB_DIV_WIDTH 12 1854 /* Default value of bitfield lro_tb_div[11:0] */ 1855 #define HW_ATL_RPO_LRO_TB_DIV_DEFAULT 0xC35 1856 1857 /* RX lro_ina_ival[9:0] Bitfield Definitions 1858 * Preprocessor definitions for the bitfield "lro_ina_ival[9:0]". 1859 * PORT="pif_rpo_lro_ina_ival_i[9:0]" 1860 */ 1861 1862 /* Register address for bitfield lro_ina_ival[9:0] */ 1863 #define HW_ATL_RPO_LRO_INA_IVAL_ADR 0x00005620 1864 /* Bitmask for bitfield lro_ina_ival[9:0] */ 1865 #define HW_ATL_RPO_LRO_INA_IVAL_MSK 0x000FFC00 1866 /* Inverted bitmask for bitfield lro_ina_ival[9:0] */ 1867 #define HW_ATL_RPO_LRO_INA_IVAL_MSKN 0xFFF003FF 1868 /* Lower bit position of bitfield lro_ina_ival[9:0] */ 1869 #define HW_ATL_RPO_LRO_INA_IVAL_SHIFT 10 1870 /* Width of bitfield lro_ina_ival[9:0] */ 1871 #define HW_ATL_RPO_LRO_INA_IVAL_WIDTH 10 1872 /* Default value of bitfield lro_ina_ival[9:0] */ 1873 #define HW_ATL_RPO_LRO_INA_IVAL_DEFAULT 0xA 1874 1875 /* RX lro_max_ival[9:0] Bitfield Definitions 1876 * Preprocessor definitions for the bitfield "lro_max_ival[9:0]". 1877 * PORT="pif_rpo_lro_max_ival_i[9:0]" 1878 */ 1879 1880 /* Register address for bitfield lro_max_ival[9:0] */ 1881 #define HW_ATL_RPO_LRO_MAX_IVAL_ADR 0x00005620 1882 /* Bitmask for bitfield lro_max_ival[9:0] */ 1883 #define HW_ATL_RPO_LRO_MAX_IVAL_MSK 0x000003FF 1884 /* Inverted bitmask for bitfield lro_max_ival[9:0] */ 1885 #define HW_ATL_RPO_LRO_MAX_IVAL_MSKN 0xFFFFFC00 1886 /* Lower bit position of bitfield lro_max_ival[9:0] */ 1887 #define HW_ATL_RPO_LRO_MAX_IVAL_SHIFT 0 1888 /* Width of bitfield lro_max_ival[9:0] */ 1889 #define HW_ATL_RPO_LRO_MAX_IVAL_WIDTH 10 1890 /* Default value of bitfield lro_max_ival[9:0] */ 1891 #define HW_ATL_RPO_LRO_MAX_IVAL_DEFAULT 0x19 1892 1893 /* TX dca{D}_cpuid[7:0] Bitfield Definitions 1894 * Preprocessor definitions for the bitfield "dca{D}_cpuid[7:0]". 1895 * Parameter: DCA {D} | stride size 0x4 | range [0, 31] 1896 * PORT="pif_tdm_dca0_cpuid_i[7:0]" 1897 */ 1898 1899 /* Register address for bitfield dca{D}_cpuid[7:0] */ 1900 #define HW_ATL_TDM_DCA_DCPUID_ADR(dca) (0x00008400 + (dca) * 0x4) 1901 /* Bitmask for bitfield dca{D}_cpuid[7:0] */ 1902 #define HW_ATL_TDM_DCA_DCPUID_MSK 0x000000FF 1903 /* Inverted bitmask for bitfield dca{D}_cpuid[7:0] */ 1904 #define HW_ATL_TDM_DCA_DCPUID_MSKN 0xFFFFFF00 1905 /* Lower bit position of bitfield dca{D}_cpuid[7:0] */ 1906 #define HW_ATL_TDM_DCA_DCPUID_SHIFT 0 1907 /* Width of bitfield dca{D}_cpuid[7:0] */ 1908 #define HW_ATL_TDM_DCA_DCPUID_WIDTH 8 1909 /* Default value of bitfield dca{D}_cpuid[7:0] */ 1910 #define HW_ATL_TDM_DCA_DCPUID_DEFAULT 0x0 1911 1912 /* TX dca{D}_desc_en Bitfield Definitions 1913 * Preprocessor definitions for the bitfield "dca{D}_desc_en". 1914 * Parameter: DCA {D} | stride size 0x4 | range [0, 31] 1915 * PORT="pif_tdm_dca_desc_en_i[0]" 1916 */ 1917 1918 /* Register address for bitfield dca{D}_desc_en */ 1919 #define HW_ATL_TDM_DCA_DDESC_EN_ADR(dca) (0x00008400 + (dca) * 0x4) 1920 /* Bitmask for bitfield dca{D}_desc_en */ 1921 #define HW_ATL_TDM_DCA_DDESC_EN_MSK 0x80000000 1922 /* Inverted bitmask for bitfield dca{D}_desc_en */ 1923 #define HW_ATL_TDM_DCA_DDESC_EN_MSKN 0x7FFFFFFF 1924 /* Lower bit position of bitfield dca{D}_desc_en */ 1925 #define HW_ATL_TDM_DCA_DDESC_EN_SHIFT 31 1926 /* Width of bitfield dca{D}_desc_en */ 1927 #define HW_ATL_TDM_DCA_DDESC_EN_WIDTH 1 1928 /* Default value of bitfield dca{D}_desc_en */ 1929 #define HW_ATL_TDM_DCA_DDESC_EN_DEFAULT 0x0 1930 1931 /* TX desc{D}_en Bitfield Definitions 1932 * Preprocessor definitions for the bitfield "desc{D}_en". 1933 * Parameter: descriptor {D} | stride size 0x40 | range [0, 31] 1934 * PORT="pif_tdm_desc_en_i[0]" 1935 */ 1936 1937 /* Register address for bitfield desc{D}_en */ 1938 #define HW_ATL_TDM_DESC_DEN_ADR(descriptor) (0x00007C08 + (descriptor) * 0x40) 1939 /* Bitmask for bitfield desc{D}_en */ 1940 #define HW_ATL_TDM_DESC_DEN_MSK 0x80000000 1941 /* Inverted bitmask for bitfield desc{D}_en */ 1942 #define HW_ATL_TDM_DESC_DEN_MSKN 0x7FFFFFFF 1943 /* Lower bit position of bitfield desc{D}_en */ 1944 #define HW_ATL_TDM_DESC_DEN_SHIFT 31 1945 /* Width of bitfield desc{D}_en */ 1946 #define HW_ATL_TDM_DESC_DEN_WIDTH 1 1947 /* Default value of bitfield desc{D}_en */ 1948 #define HW_ATL_TDM_DESC_DEN_DEFAULT 0x0 1949 1950 /* TX desc{D}_hd[C:0] Bitfield Definitions 1951 * Preprocessor definitions for the bitfield "desc{D}_hd[C:0]". 1952 * Parameter: descriptor {D} | stride size 0x40 | range [0, 31] 1953 * PORT="tdm_pif_desc0_hd_o[12:0]" 1954 */ 1955 1956 /* Register address for bitfield desc{D}_hd[C:0] */ 1957 #define HW_ATL_TDM_DESC_DHD_ADR(descriptor) (0x00007C0C + (descriptor) * 0x40) 1958 /* Bitmask for bitfield desc{D}_hd[C:0] */ 1959 #define HW_ATL_TDM_DESC_DHD_MSK 0x00001FFF 1960 /* Inverted bitmask for bitfield desc{D}_hd[C:0] */ 1961 #define HW_ATL_TDM_DESC_DHD_MSKN 0xFFFFE000 1962 /* Lower bit position of bitfield desc{D}_hd[C:0] */ 1963 #define HW_ATL_TDM_DESC_DHD_SHIFT 0 1964 /* Width of bitfield desc{D}_hd[C:0] */ 1965 #define HW_ATL_TDM_DESC_DHD_WIDTH 13 1966 1967 /* TX desc{D}_len[9:0] Bitfield Definitions 1968 * Preprocessor definitions for the bitfield "desc{D}_len[9:0]". 1969 * Parameter: descriptor {D} | stride size 0x40 | range [0, 31] 1970 * PORT="pif_tdm_desc0_len_i[9:0]" 1971 */ 1972 1973 /* Register address for bitfield desc{D}_len[9:0] */ 1974 #define HW_ATL_TDM_DESC_DLEN_ADR(descriptor) (0x00007C08 + (descriptor) * 0x40) 1975 /* Bitmask for bitfield desc{D}_len[9:0] */ 1976 #define HW_ATL_TDM_DESC_DLEN_MSK 0x00001FF8 1977 /* Inverted bitmask for bitfield desc{D}_len[9:0] */ 1978 #define HW_ATL_TDM_DESC_DLEN_MSKN 0xFFFFE007 1979 /* Lower bit position of bitfield desc{D}_len[9:0] */ 1980 #define HW_ATL_TDM_DESC_DLEN_SHIFT 3 1981 /* Width of bitfield desc{D}_len[9:0] */ 1982 #define HW_ATL_TDM_DESC_DLEN_WIDTH 10 1983 /* Default value of bitfield desc{D}_len[9:0] */ 1984 #define HW_ATL_TDM_DESC_DLEN_DEFAULT 0x0 1985 1986 /* TX desc{D}_wrb_thresh[6:0] Bitfield Definitions 1987 * Preprocessor definitions for the bitfield "desc{D}_wrb_thresh[6:0]". 1988 * Parameter: descriptor {D} | stride size 0x40 | range [0, 31] 1989 * PORT="pif_tdm_desc0_wrb_thresh_i[6:0]" 1990 */ 1991 1992 /* Register address for bitfield desc{D}_wrb_thresh[6:0] */ 1993 #define HW_ATL_TDM_DESC_DWRB_THRESH_ADR(descriptor) \ 1994 (0x00007C18 + (descriptor) * 0x40) 1995 /* Bitmask for bitfield desc{D}_wrb_thresh[6:0] */ 1996 #define HW_ATL_TDM_DESC_DWRB_THRESH_MSK 0x00007F00 1997 /* Inverted bitmask for bitfield desc{D}_wrb_thresh[6:0] */ 1998 #define HW_ATL_TDM_DESC_DWRB_THRESH_MSKN 0xFFFF80FF 1999 /* Lower bit position of bitfield desc{D}_wrb_thresh[6:0] */ 2000 #define HW_ATL_TDM_DESC_DWRB_THRESH_SHIFT 8 2001 /* Width of bitfield desc{D}_wrb_thresh[6:0] */ 2002 #define HW_ATL_TDM_DESC_DWRB_THRESH_WIDTH 7 2003 /* Default value of bitfield desc{D}_wrb_thresh[6:0] */ 2004 #define HW_ATL_TDM_DESC_DWRB_THRESH_DEFAULT 0x0 2005 2006 /* TX tdm_int_mod_en Bitfield Definitions 2007 * Preprocessor definitions for the bitfield "tdm_int_mod_en". 2008 * PORT="pif_tdm_int_mod_en_i" 2009 */ 2010 2011 /* Register address for bitfield tdm_int_mod_en */ 2012 #define HW_ATL_TDM_INT_MOD_EN_ADR 0x00007B40 2013 /* Bitmask for bitfield tdm_int_mod_en */ 2014 #define HW_ATL_TDM_INT_MOD_EN_MSK 0x00000010 2015 /* Inverted bitmask for bitfield tdm_int_mod_en */ 2016 #define HW_ATL_TDM_INT_MOD_EN_MSKN 0xFFFFFFEF 2017 /* Lower bit position of bitfield tdm_int_mod_en */ 2018 #define HW_ATL_TDM_INT_MOD_EN_SHIFT 4 2019 /* Width of bitfield tdm_int_mod_en */ 2020 #define HW_ATL_TDM_INT_MOD_EN_WIDTH 1 2021 /* Default value of bitfield tdm_int_mod_en */ 2022 #define HW_ATL_TDM_INT_MOD_EN_DEFAULT 0x0 2023 2024 /* TX lso_tcp_flag_mid[B:0] Bitfield Definitions 2025 * Preprocessor definitions for the bitfield "lso_tcp_flag_mid[B:0]". 2026 * PORT="pif_thm_lso_tcp_flag_mid_i[11:0]" 2027 */ 2028 /* register address for bitfield lso_tcp_flag_mid[b:0] */ 2029 #define HW_ATL_THM_LSO_TCP_FLAG_MID_ADR 0x00007820 2030 /* bitmask for bitfield lso_tcp_flag_mid[b:0] */ 2031 #define HW_ATL_THM_LSO_TCP_FLAG_MID_MSK 0x0fff0000 2032 /* inverted bitmask for bitfield lso_tcp_flag_mid[b:0] */ 2033 #define HW_ATL_THM_LSO_TCP_FLAG_MID_MSKN 0xf000ffff 2034 /* lower bit position of bitfield lso_tcp_flag_mid[b:0] */ 2035 #define HW_ATL_THM_LSO_TCP_FLAG_MID_SHIFT 16 2036 /* width of bitfield lso_tcp_flag_mid[b:0] */ 2037 #define HW_ATL_THM_LSO_TCP_FLAG_MID_WIDTH 12 2038 /* default value of bitfield lso_tcp_flag_mid[b:0] */ 2039 #define HW_ATL_THM_LSO_TCP_FLAG_MID_DEFAULT 0x0 2040 2041 /* tx tx_tc_mode bitfield definitions 2042 * preprocessor definitions for the bitfield "tx_tc_mode". 2043 * port="pif_tpb_tx_tc_mode_i,pif_tps_tx_tc_mode_i" 2044 */ 2045 2046 /* register address for bitfield tx_tc_mode */ 2047 #define HW_ATL_TPB_TX_TC_MODE_ADDR 0x00007900 2048 /* bitmask for bitfield tx_tc_mode */ 2049 #define HW_ATL_TPB_TX_TC_MODE_MSK 0x00000100 2050 /* inverted bitmask for bitfield tx_tc_mode */ 2051 #define HW_ATL_TPB_TX_TC_MODE_MSKN 0xFFFFFEFF 2052 /* lower bit position of bitfield tx_tc_mode */ 2053 #define HW_ATL_TPB_TX_TC_MODE_SHIFT 8 2054 /* width of bitfield tx_tc_mode */ 2055 #define HW_ATL_TPB_TX_TC_MODE_WIDTH 1 2056 /* default value of bitfield tx_tc_mode */ 2057 #define HW_ATL_TPB_TX_TC_MODE_DEFAULT 0x0 2058 2059 /* tx tx_desc_rate_mode bitfield definitions 2060 * preprocessor definitions for the bitfield "tx_desc_rate_mode". 2061 * port="pif_tps_desc_rate_mode_i" 2062 */ 2063 2064 /* register address for bitfield tx_desc_rate_mode */ 2065 #define HW_ATL_TPS_TX_DESC_RATE_MODE_ADR 0x00007900 2066 /* bitmask for bitfield tx_desc_rate_mode */ 2067 #define HW_ATL_TPS_TX_DESC_RATE_MODE_MSK 0x00000080 2068 /* inverted bitmask for bitfield tx_desc_rate_mode */ 2069 #define HW_ATL_TPS_TX_DESC_RATE_MODE_MSKN 0xFFFFFF7F 2070 /* lower bit position of bitfield tx_desc_rate_mode */ 2071 #define HW_ATL_TPS_TX_DESC_RATE_MODE_SHIFT 7 2072 /* width of bitfield tx_desc_rate_mode */ 2073 #define HW_ATL_TPS_TX_DESC_RATE_MODE_WIDTH 1 2074 /* default value of bitfield tx_desc_rate_mode */ 2075 #define HW_ATL_TPS_TX_DESC_RATE_MODE_DEFAULT 0x0 2076 2077 /* tx tx_buf_en bitfield definitions 2078 * preprocessor definitions for the bitfield "tx_buf_en". 2079 * port="pif_tpb_tx_buf_en_i" 2080 */ 2081 2082 /* register address for bitfield tx_buf_en */ 2083 #define HW_ATL_TPB_TX_BUF_EN_ADR 0x00007900 2084 /* bitmask for bitfield tx_buf_en */ 2085 #define HW_ATL_TPB_TX_BUF_EN_MSK 0x00000001 2086 /* inverted bitmask for bitfield tx_buf_en */ 2087 #define HW_ATL_TPB_TX_BUF_EN_MSKN 0xfffffffe 2088 /* lower bit position of bitfield tx_buf_en */ 2089 #define HW_ATL_TPB_TX_BUF_EN_SHIFT 0 2090 /* width of bitfield tx_buf_en */ 2091 #define HW_ATL_TPB_TX_BUF_EN_WIDTH 1 2092 /* default value of bitfield tx_buf_en */ 2093 #define HW_ATL_TPB_TX_BUF_EN_DEFAULT 0x0 2094 2095 /* tx tx{b}_hi_thresh[c:0] bitfield definitions 2096 * preprocessor definitions for the bitfield "tx{b}_hi_thresh[c:0]". 2097 * parameter: buffer {b} | stride size 0x10 | range [0, 7] 2098 * port="pif_tpb_tx0_hi_thresh_i[12:0]" 2099 */ 2100 2101 /* register address for bitfield tx{b}_hi_thresh[c:0] */ 2102 #define HW_ATL_TPB_TXBHI_THRESH_ADR(buffer) (0x00007914 + (buffer) * 0x10) 2103 /* bitmask for bitfield tx{b}_hi_thresh[c:0] */ 2104 #define HW_ATL_TPB_TXBHI_THRESH_MSK 0x1fff0000 2105 /* inverted bitmask for bitfield tx{b}_hi_thresh[c:0] */ 2106 #define HW_ATL_TPB_TXBHI_THRESH_MSKN 0xe000ffff 2107 /* lower bit position of bitfield tx{b}_hi_thresh[c:0] */ 2108 #define HW_ATL_TPB_TXBHI_THRESH_SHIFT 16 2109 /* width of bitfield tx{b}_hi_thresh[c:0] */ 2110 #define HW_ATL_TPB_TXBHI_THRESH_WIDTH 13 2111 /* default value of bitfield tx{b}_hi_thresh[c:0] */ 2112 #define HW_ATL_TPB_TXBHI_THRESH_DEFAULT 0x0 2113 2114 /* tx tx{b}_lo_thresh[c:0] bitfield definitions 2115 * preprocessor definitions for the bitfield "tx{b}_lo_thresh[c:0]". 2116 * parameter: buffer {b} | stride size 0x10 | range [0, 7] 2117 * port="pif_tpb_tx0_lo_thresh_i[12:0]" 2118 */ 2119 2120 /* register address for bitfield tx{b}_lo_thresh[c:0] */ 2121 #define HW_ATL_TPB_TXBLO_THRESH_ADR(buffer) (0x00007914 + (buffer) * 0x10) 2122 /* bitmask for bitfield tx{b}_lo_thresh[c:0] */ 2123 #define HW_ATL_TPB_TXBLO_THRESH_MSK 0x00001fff 2124 /* inverted bitmask for bitfield tx{b}_lo_thresh[c:0] */ 2125 #define HW_ATL_TPB_TXBLO_THRESH_MSKN 0xffffe000 2126 /* lower bit position of bitfield tx{b}_lo_thresh[c:0] */ 2127 #define HW_ATL_TPB_TXBLO_THRESH_SHIFT 0 2128 /* width of bitfield tx{b}_lo_thresh[c:0] */ 2129 #define HW_ATL_TPB_TXBLO_THRESH_WIDTH 13 2130 /* default value of bitfield tx{b}_lo_thresh[c:0] */ 2131 #define HW_ATL_TPB_TXBLO_THRESH_DEFAULT 0x0 2132 2133 /* tx dma_sys_loopback bitfield definitions 2134 * preprocessor definitions for the bitfield "dma_sys_loopback". 2135 * port="pif_tpb_dma_sys_lbk_i" 2136 */ 2137 2138 /* register address for bitfield dma_sys_loopback */ 2139 #define HW_ATL_TPB_DMA_SYS_LBK_ADR 0x00007000 2140 /* bitmask for bitfield dma_sys_loopback */ 2141 #define HW_ATL_TPB_DMA_SYS_LBK_MSK 0x00000040 2142 /* inverted bitmask for bitfield dma_sys_loopback */ 2143 #define HW_ATL_TPB_DMA_SYS_LBK_MSKN 0xffffffbf 2144 /* lower bit position of bitfield dma_sys_loopback */ 2145 #define HW_ATL_TPB_DMA_SYS_LBK_SHIFT 6 2146 /* width of bitfield dma_sys_loopback */ 2147 #define HW_ATL_TPB_DMA_SYS_LBK_WIDTH 1 2148 /* default value of bitfield dma_sys_loopback */ 2149 #define HW_ATL_TPB_DMA_SYS_LBK_DEFAULT 0x0 2150 2151 /* tx dma_net_loopback bitfield definitions 2152 * preprocessor definitions for the bitfield "dma_net_loopback". 2153 * port="pif_tpb_dma_net_lbk_i" 2154 */ 2155 2156 /* register address for bitfield dma_net_loopback */ 2157 #define HW_ATL_TPB_DMA_NET_LBK_ADR 0x00007000 2158 /* bitmask for bitfield dma_net_loopback */ 2159 #define HW_ATL_TPB_DMA_NET_LBK_MSK 0x00000010 2160 /* inverted bitmask for bitfield dma_net_loopback */ 2161 #define HW_ATL_TPB_DMA_NET_LBK_MSKN 0xffffffef 2162 /* lower bit position of bitfield dma_net_loopback */ 2163 #define HW_ATL_TPB_DMA_NET_LBK_SHIFT 4 2164 /* width of bitfield dma_net_loopback */ 2165 #define HW_ATL_TPB_DMA_NET_LBK_WIDTH 1 2166 /* default value of bitfield dma_net_loopback */ 2167 #define HW_ATL_TPB_DMA_NET_LBK_DEFAULT 0x0 2168 2169 /* tx tx{b}_buf_size[7:0] bitfield definitions 2170 * preprocessor definitions for the bitfield "tx{b}_buf_size[7:0]". 2171 * parameter: buffer {b} | stride size 0x10 | range [0, 7] 2172 * port="pif_tpb_tx0_buf_size_i[7:0]" 2173 */ 2174 2175 /* register address for bitfield tx{b}_buf_size[7:0] */ 2176 #define HW_ATL_TPB_TXBBUF_SIZE_ADR(buffer) (0x00007910 + (buffer) * 0x10) 2177 /* bitmask for bitfield tx{b}_buf_size[7:0] */ 2178 #define HW_ATL_TPB_TXBBUF_SIZE_MSK 0x000000ff 2179 /* inverted bitmask for bitfield tx{b}_buf_size[7:0] */ 2180 #define HW_ATL_TPB_TXBBUF_SIZE_MSKN 0xffffff00 2181 /* lower bit position of bitfield tx{b}_buf_size[7:0] */ 2182 #define HW_ATL_TPB_TXBBUF_SIZE_SHIFT 0 2183 /* width of bitfield tx{b}_buf_size[7:0] */ 2184 #define HW_ATL_TPB_TXBBUF_SIZE_WIDTH 8 2185 /* default value of bitfield tx{b}_buf_size[7:0] */ 2186 #define HW_ATL_TPB_TXBBUF_SIZE_DEFAULT 0x0 2187 2188 /* tx tx_scp_ins_en bitfield definitions 2189 * preprocessor definitions for the bitfield "tx_scp_ins_en". 2190 * port="pif_tpb_scp_ins_en_i" 2191 */ 2192 2193 /* register address for bitfield tx_scp_ins_en */ 2194 #define HW_ATL_TPB_TX_SCP_INS_EN_ADR 0x00007900 2195 /* bitmask for bitfield tx_scp_ins_en */ 2196 #define HW_ATL_TPB_TX_SCP_INS_EN_MSK 0x00000004 2197 /* inverted bitmask for bitfield tx_scp_ins_en */ 2198 #define HW_ATL_TPB_TX_SCP_INS_EN_MSKN 0xfffffffb 2199 /* lower bit position of bitfield tx_scp_ins_en */ 2200 #define HW_ATL_TPB_TX_SCP_INS_EN_SHIFT 2 2201 /* width of bitfield tx_scp_ins_en */ 2202 #define HW_ATL_TPB_TX_SCP_INS_EN_WIDTH 1 2203 /* default value of bitfield tx_scp_ins_en */ 2204 #define HW_ATL_TPB_TX_SCP_INS_EN_DEFAULT 0x0 2205 2206 /* tx tx_clk_gate_en bitfield definitions 2207 * preprocessor definitions for the bitfield "tx_clk_gate_en". 2208 * port="pif_tpb_clk_gate_en_i" 2209 */ 2210 2211 /* register address for bitfield tx_clk_gate_en */ 2212 #define HW_ATL_TPB_TX_CLK_GATE_EN_ADR 0x00007900 2213 /* bitmask for bitfield tx_clk_gate_en */ 2214 #define HW_ATL_TPB_TX_CLK_GATE_EN_MSK 0x00000010 2215 /* inverted bitmask for bitfield tx_clk_gate_en */ 2216 #define HW_ATL_TPB_TX_CLK_GATE_EN_MSKN 0xffffffef 2217 /* lower bit position of bitfield tx_clk_gate_en */ 2218 #define HW_ATL_TPB_TX_CLK_GATE_EN_SHIFT 4 2219 /* width of bitfield tx_clk_gate_en */ 2220 #define HW_ATL_TPB_TX_CLK_GATE_EN_WIDTH 1 2221 /* default value of bitfield tx_clk_gate_en */ 2222 #define HW_ATL_TPB_TX_CLK_GATE_EN_DEFAULT 0x1 2223 2224 /* tx ipv4_chk_en bitfield definitions 2225 * preprocessor definitions for the bitfield "ipv4_chk_en". 2226 * port="pif_tpo_ipv4_chk_en_i" 2227 */ 2228 2229 /* register address for bitfield ipv4_chk_en */ 2230 #define HW_ATL_TPO_IPV4CHK_EN_ADR 0x00007800 2231 /* bitmask for bitfield ipv4_chk_en */ 2232 #define HW_ATL_TPO_IPV4CHK_EN_MSK 0x00000002 2233 /* inverted bitmask for bitfield ipv4_chk_en */ 2234 #define HW_ATL_TPO_IPV4CHK_EN_MSKN 0xfffffffd 2235 /* lower bit position of bitfield ipv4_chk_en */ 2236 #define HW_ATL_TPO_IPV4CHK_EN_SHIFT 1 2237 /* width of bitfield ipv4_chk_en */ 2238 #define HW_ATL_TPO_IPV4CHK_EN_WIDTH 1 2239 /* default value of bitfield ipv4_chk_en */ 2240 #define HW_ATL_TPO_IPV4CHK_EN_DEFAULT 0x0 2241 2242 /* tx l4_chk_en bitfield definitions 2243 * preprocessor definitions for the bitfield "l4_chk_en". 2244 * port="pif_tpo_l4_chk_en_i" 2245 */ 2246 2247 /* register address for bitfield l4_chk_en */ 2248 #define HW_ATL_TPOL4CHK_EN_ADR 0x00007800 2249 /* bitmask for bitfield l4_chk_en */ 2250 #define HW_ATL_TPOL4CHK_EN_MSK 0x00000001 2251 /* inverted bitmask for bitfield l4_chk_en */ 2252 #define HW_ATL_TPOL4CHK_EN_MSKN 0xfffffffe 2253 /* lower bit position of bitfield l4_chk_en */ 2254 #define HW_ATL_TPOL4CHK_EN_SHIFT 0 2255 /* width of bitfield l4_chk_en */ 2256 #define HW_ATL_TPOL4CHK_EN_WIDTH 1 2257 /* default value of bitfield l4_chk_en */ 2258 #define HW_ATL_TPOL4CHK_EN_DEFAULT 0x0 2259 2260 /* tx pkt_sys_loopback bitfield definitions 2261 * preprocessor definitions for the bitfield "pkt_sys_loopback". 2262 * port="pif_tpo_pkt_sys_lbk_i" 2263 */ 2264 2265 /* register address for bitfield pkt_sys_loopback */ 2266 #define HW_ATL_TPO_PKT_SYS_LBK_ADR 0x00007000 2267 /* bitmask for bitfield pkt_sys_loopback */ 2268 #define HW_ATL_TPO_PKT_SYS_LBK_MSK 0x00000080 2269 /* inverted bitmask for bitfield pkt_sys_loopback */ 2270 #define HW_ATL_TPO_PKT_SYS_LBK_MSKN 0xffffff7f 2271 /* lower bit position of bitfield pkt_sys_loopback */ 2272 #define HW_ATL_TPO_PKT_SYS_LBK_SHIFT 7 2273 /* width of bitfield pkt_sys_loopback */ 2274 #define HW_ATL_TPO_PKT_SYS_LBK_WIDTH 1 2275 /* default value of bitfield pkt_sys_loopback */ 2276 #define HW_ATL_TPO_PKT_SYS_LBK_DEFAULT 0x0 2277 2278 /* tx data_tc_arb_mode bitfield definitions 2279 * preprocessor definitions for the bitfield "data_tc_arb_mode". 2280 * port="pif_tps_data_tc_arb_mode_i" 2281 */ 2282 2283 /* register address for bitfield data_tc_arb_mode */ 2284 #define HW_ATL_TPS_DATA_TC_ARB_MODE_ADR 0x00007100 2285 /* bitmask for bitfield data_tc_arb_mode */ 2286 #define HW_ATL_TPS_DATA_TC_ARB_MODE_MSK 0x00000001 2287 /* inverted bitmask for bitfield data_tc_arb_mode */ 2288 #define HW_ATL_TPS_DATA_TC_ARB_MODE_MSKN 0xfffffffe 2289 /* lower bit position of bitfield data_tc_arb_mode */ 2290 #define HW_ATL_TPS_DATA_TC_ARB_MODE_SHIFT 0 2291 /* width of bitfield data_tc_arb_mode */ 2292 #define HW_ATL_TPS_DATA_TC_ARB_MODE_WIDTH 1 2293 /* default value of bitfield data_tc_arb_mode */ 2294 #define HW_ATL_TPS_DATA_TC_ARB_MODE_DEFAULT 0x0 2295 2296 /* tx desc{r}_rate_en bitfield definitions 2297 * preprocessor definitions for the bitfield "desc{r}_rate_en". 2298 * port="pif_tps_desc_rate_en_i[0]" 2299 */ 2300 2301 /* register address for bitfield desc{r}_rate_en */ 2302 #define HW_ATL_TPS_DESC_RATE_EN_ADR(desc) (0x00007408 + (desc) * 0x10) 2303 /* bitmask for bitfield desc{r}_rate_en */ 2304 #define HW_ATL_TPS_DESC_RATE_EN_MSK 0x80000000 2305 /* inverted bitmask for bitfield desc{r}_rate_en */ 2306 #define HW_ATL_TPS_DESC_RATE_EN_MSKN 0x7FFFFFFF 2307 /* lower bit position of bitfield desc{r}_rate_en */ 2308 #define HW_ATL_TPS_DESC_RATE_EN_SHIFT 31 2309 /* width of bitfield desc{r}_rate_en */ 2310 #define HW_ATL_TPS_DESC_RATE_EN_WIDTH 1 2311 /* default value of bitfield desc{r}_rate_en */ 2312 #define HW_ATL_TPS_DESC_RATE_EN_DEFAULT 0x0 2313 2314 /* tx desc{r}_rate_x bitfield definitions 2315 * preprocessor definitions for the bitfield "desc{r}_rate_x". 2316 * port="pif_tps_desc0_rate_x" 2317 */ 2318 /* register address for bitfield desc{r}_rate_x */ 2319 #define HW_ATL_TPS_DESC_RATE_X_ADR(desc) (0x00007408 + (desc) * 0x10) 2320 /* bitmask for bitfield desc{r}_rate_x */ 2321 #define HW_ATL_TPS_DESC_RATE_X_MSK 0x03FF0000 2322 /* inverted bitmask for bitfield desc{r}_rate_x */ 2323 #define HW_ATL_TPS_DESC_RATE_X_MSKN 0xFC00FFFF 2324 /* lower bit position of bitfield desc{r}_rate_x */ 2325 #define HW_ATL_TPS_DESC_RATE_X_SHIFT 16 2326 /* width of bitfield desc{r}_rate_x */ 2327 #define HW_ATL_TPS_DESC_RATE_X_WIDTH 10 2328 /* default value of bitfield desc{r}_rate_x */ 2329 #define HW_ATL_TPS_DESC_RATE_X_DEFAULT 0x0 2330 2331 /* tx desc{r}_rate_y bitfield definitions 2332 * preprocessor definitions for the bitfield "desc{r}_rate_y". 2333 * port="pif_tps_desc0_rate_y" 2334 */ 2335 /* register address for bitfield desc{r}_rate_y */ 2336 #define HW_ATL_TPS_DESC_RATE_Y_ADR(desc) (0x00007408 + (desc) * 0x10) 2337 /* bitmask for bitfield desc{r}_rate_y */ 2338 #define HW_ATL_TPS_DESC_RATE_Y_MSK 0x00003FFF 2339 /* inverted bitmask for bitfield desc{r}_rate_y */ 2340 #define HW_ATL_TPS_DESC_RATE_Y_MSKN 0xFFFFC000 2341 /* lower bit position of bitfield desc{r}_rate_y */ 2342 #define HW_ATL_TPS_DESC_RATE_Y_SHIFT 0 2343 /* width of bitfield desc{r}_rate_y */ 2344 #define HW_ATL_TPS_DESC_RATE_Y_WIDTH 14 2345 /* default value of bitfield desc{r}_rate_y */ 2346 #define HW_ATL_TPS_DESC_RATE_Y_DEFAULT 0x0 2347 2348 /* tx desc_rate_ta_rst bitfield definitions 2349 * preprocessor definitions for the bitfield "desc_rate_ta_rst". 2350 * port="pif_tps_desc_rate_ta_rst_i" 2351 */ 2352 2353 /* register address for bitfield desc_rate_ta_rst */ 2354 #define HW_ATL_TPS_DESC_RATE_TA_RST_ADR 0x00007310 2355 /* bitmask for bitfield desc_rate_ta_rst */ 2356 #define HW_ATL_TPS_DESC_RATE_TA_RST_MSK 0x80000000 2357 /* inverted bitmask for bitfield desc_rate_ta_rst */ 2358 #define HW_ATL_TPS_DESC_RATE_TA_RST_MSKN 0x7fffffff 2359 /* lower bit position of bitfield desc_rate_ta_rst */ 2360 #define HW_ATL_TPS_DESC_RATE_TA_RST_SHIFT 31 2361 /* width of bitfield desc_rate_ta_rst */ 2362 #define HW_ATL_TPS_DESC_RATE_TA_RST_WIDTH 1 2363 /* default value of bitfield desc_rate_ta_rst */ 2364 #define HW_ATL_TPS_DESC_RATE_TA_RST_DEFAULT 0x0 2365 2366 /* tx desc_rate_limit[a:0] bitfield definitions 2367 * preprocessor definitions for the bitfield "desc_rate_limit[a:0]". 2368 * port="pif_tps_desc_rate_lim_i[10:0]" 2369 */ 2370 2371 /* register address for bitfield desc_rate_limit[a:0] */ 2372 #define HW_ATL_TPS_DESC_RATE_LIM_ADR 0x00007310 2373 /* bitmask for bitfield desc_rate_limit[a:0] */ 2374 #define HW_ATL_TPS_DESC_RATE_LIM_MSK 0x000007ff 2375 /* inverted bitmask for bitfield desc_rate_limit[a:0] */ 2376 #define HW_ATL_TPS_DESC_RATE_LIM_MSKN 0xfffff800 2377 /* lower bit position of bitfield desc_rate_limit[a:0] */ 2378 #define HW_ATL_TPS_DESC_RATE_LIM_SHIFT 0 2379 /* width of bitfield desc_rate_limit[a:0] */ 2380 #define HW_ATL_TPS_DESC_RATE_LIM_WIDTH 11 2381 /* default value of bitfield desc_rate_limit[a:0] */ 2382 #define HW_ATL_TPS_DESC_RATE_LIM_DEFAULT 0x0 2383 2384 /* tx desc_tc_arb_mode[1:0] bitfield definitions 2385 * preprocessor definitions for the bitfield "desc_tc_arb_mode[1:0]". 2386 * port="pif_tps_desc_tc_arb_mode_i[1:0]" 2387 */ 2388 2389 /* register address for bitfield desc_tc_arb_mode[1:0] */ 2390 #define HW_ATL_TPS_DESC_TC_ARB_MODE_ADR 0x00007200 2391 /* bitmask for bitfield desc_tc_arb_mode[1:0] */ 2392 #define HW_ATL_TPS_DESC_TC_ARB_MODE_MSK 0x00000003 2393 /* inverted bitmask for bitfield desc_tc_arb_mode[1:0] */ 2394 #define HW_ATL_TPS_DESC_TC_ARB_MODE_MSKN 0xfffffffc 2395 /* lower bit position of bitfield desc_tc_arb_mode[1:0] */ 2396 #define HW_ATL_TPS_DESC_TC_ARB_MODE_SHIFT 0 2397 /* width of bitfield desc_tc_arb_mode[1:0] */ 2398 #define HW_ATL_TPS_DESC_TC_ARB_MODE_WIDTH 2 2399 /* default value of bitfield desc_tc_arb_mode[1:0] */ 2400 #define HW_ATL_TPS_DESC_TC_ARB_MODE_DEFAULT 0x0 2401 2402 /* tx desc_tc{t}_credit_max[b:0] bitfield definitions 2403 * preprocessor definitions for the bitfield "desc_tc{t}_credit_max[b:0]". 2404 * parameter: tc {t} | stride size 0x4 | range [0, 7] 2405 * port="pif_tps_desc_tc0_credit_max_i[11:0]" 2406 */ 2407 2408 /* register address for bitfield desc_tc{t}_credit_max[b:0] */ 2409 #define HW_ATL_TPS_DESC_TCTCREDIT_MAX_ADR(tc) (0x00007210 + (tc) * 0x4) 2410 /* bitmask for bitfield desc_tc{t}_credit_max[b:0] */ 2411 #define HW_ATL_TPS_DESC_TCTCREDIT_MAX_MSK 0x0fff0000 2412 /* inverted bitmask for bitfield desc_tc{t}_credit_max[b:0] */ 2413 #define HW_ATL_TPS_DESC_TCTCREDIT_MAX_MSKN 0xf000ffff 2414 /* lower bit position of bitfield desc_tc{t}_credit_max[b:0] */ 2415 #define HW_ATL_TPS_DESC_TCTCREDIT_MAX_SHIFT 16 2416 /* width of bitfield desc_tc{t}_credit_max[b:0] */ 2417 #define HW_ATL_TPS_DESC_TCTCREDIT_MAX_WIDTH 12 2418 /* default value of bitfield desc_tc{t}_credit_max[b:0] */ 2419 #define HW_ATL_TPS_DESC_TCTCREDIT_MAX_DEFAULT 0x0 2420 2421 /* tx desc_tc{t}_weight[8:0] bitfield definitions 2422 * preprocessor definitions for the bitfield "desc_tc{t}_weight[8:0]". 2423 * parameter: tc {t} | stride size 0x4 | range [0, 7] 2424 * port="pif_tps_desc_tc0_weight_i[8:0]" 2425 */ 2426 2427 /* register address for bitfield desc_tc{t}_weight[8:0] */ 2428 #define HW_ATL_TPS_DESC_TCTWEIGHT_ADR(tc) (0x00007210 + (tc) * 0x4) 2429 /* bitmask for bitfield desc_tc{t}_weight[8:0] */ 2430 #define HW_ATL_TPS_DESC_TCTWEIGHT_MSK 0x000001ff 2431 /* inverted bitmask for bitfield desc_tc{t}_weight[8:0] */ 2432 #define HW_ATL_TPS_DESC_TCTWEIGHT_MSKN 0xfffffe00 2433 /* lower bit position of bitfield desc_tc{t}_weight[8:0] */ 2434 #define HW_ATL_TPS_DESC_TCTWEIGHT_SHIFT 0 2435 /* width of bitfield desc_tc{t}_weight[8:0] */ 2436 #define HW_ATL_TPS_DESC_TCTWEIGHT_WIDTH 9 2437 /* default value of bitfield desc_tc{t}_weight[8:0] */ 2438 #define HW_ATL_TPS_DESC_TCTWEIGHT_DEFAULT 0x0 2439 2440 /* tx desc_vm_arb_mode bitfield definitions 2441 * preprocessor definitions for the bitfield "desc_vm_arb_mode". 2442 * port="pif_tps_desc_vm_arb_mode_i" 2443 */ 2444 2445 /* register address for bitfield desc_vm_arb_mode */ 2446 #define HW_ATL_TPS_DESC_VM_ARB_MODE_ADR 0x00007300 2447 /* bitmask for bitfield desc_vm_arb_mode */ 2448 #define HW_ATL_TPS_DESC_VM_ARB_MODE_MSK 0x00000001 2449 /* inverted bitmask for bitfield desc_vm_arb_mode */ 2450 #define HW_ATL_TPS_DESC_VM_ARB_MODE_MSKN 0xfffffffe 2451 /* lower bit position of bitfield desc_vm_arb_mode */ 2452 #define HW_ATL_TPS_DESC_VM_ARB_MODE_SHIFT 0 2453 /* width of bitfield desc_vm_arb_mode */ 2454 #define HW_ATL_TPS_DESC_VM_ARB_MODE_WIDTH 1 2455 /* default value of bitfield desc_vm_arb_mode */ 2456 #define HW_ATL_TPS_DESC_VM_ARB_MODE_DEFAULT 0x0 2457 2458 /* tx data_tc{t}_credit_max[b:0] bitfield definitions 2459 * preprocessor definitions for the bitfield "data_tc{t}_credit_max[b:0]". 2460 * parameter: tc {t} | stride size 0x4 | range [0, 7] 2461 * port="pif_tps_data_tc0_credit_max_i[11:0]" 2462 */ 2463 2464 /* register address for bitfield data_tc{t}_credit_max[b:0] */ 2465 #define HW_ATL_TPS_DATA_TCTCREDIT_MAX_ADR(tc) (0x00007110 + (tc) * 0x4) 2466 /* bitmask for bitfield data_tc{t}_credit_max[b:0] */ 2467 #define HW_ATL_TPS_DATA_TCTCREDIT_MAX_MSK 0x0fff0000 2468 /* inverted bitmask for bitfield data_tc{t}_credit_max[b:0] */ 2469 #define HW_ATL_TPS_DATA_TCTCREDIT_MAX_MSKN 0xf000ffff 2470 /* lower bit position of bitfield data_tc{t}_credit_max[b:0] */ 2471 #define HW_ATL_TPS_DATA_TCTCREDIT_MAX_SHIFT 16 2472 /* width of bitfield data_tc{t}_credit_max[b:0] */ 2473 #define HW_ATL_TPS_DATA_TCTCREDIT_MAX_WIDTH 12 2474 /* default value of bitfield data_tc{t}_credit_max[b:0] */ 2475 #define HW_ATL_TPS_DATA_TCTCREDIT_MAX_DEFAULT 0x0 2476 2477 /* tx data_tc{t}_weight[8:0] bitfield definitions 2478 * preprocessor definitions for the bitfield "data_tc{t}_weight[8:0]". 2479 * parameter: tc {t} | stride size 0x4 | range [0, 7] 2480 * port="pif_tps_data_tc0_weight_i[8:0]" 2481 */ 2482 2483 /* register address for bitfield data_tc{t}_weight[8:0] */ 2484 #define HW_ATL_TPS_DATA_TCTWEIGHT_ADR(tc) (0x00007110 + (tc) * 0x4) 2485 /* bitmask for bitfield data_tc{t}_weight[8:0] */ 2486 #define HW_ATL_TPS_DATA_TCTWEIGHT_MSK 0x000001ff 2487 /* inverted bitmask for bitfield data_tc{t}_weight[8:0] */ 2488 #define HW_ATL_TPS_DATA_TCTWEIGHT_MSKN 0xfffffe00 2489 /* lower bit position of bitfield data_tc{t}_weight[8:0] */ 2490 #define HW_ATL_TPS_DATA_TCTWEIGHT_SHIFT 0 2491 /* width of bitfield data_tc{t}_weight[8:0] */ 2492 #define HW_ATL_TPS_DATA_TCTWEIGHT_WIDTH 9 2493 /* default value of bitfield data_tc{t}_weight[8:0] */ 2494 #define HW_ATL_TPS_DATA_TCTWEIGHT_DEFAULT 0x0 2495 2496 /* tx reg_res_dsbl bitfield definitions 2497 * preprocessor definitions for the bitfield "reg_res_dsbl". 2498 * port="pif_tx_reg_res_dsbl_i" 2499 */ 2500 2501 /* register address for bitfield reg_res_dsbl */ 2502 #define HW_ATL_TX_REG_RES_DSBL_ADR 0x00007000 2503 /* bitmask for bitfield reg_res_dsbl */ 2504 #define HW_ATL_TX_REG_RES_DSBL_MSK 0x20000000 2505 /* inverted bitmask for bitfield reg_res_dsbl */ 2506 #define HW_ATL_TX_REG_RES_DSBL_MSKN 0xdfffffff 2507 /* lower bit position of bitfield reg_res_dsbl */ 2508 #define HW_ATL_TX_REG_RES_DSBL_SHIFT 29 2509 /* width of bitfield reg_res_dsbl */ 2510 #define HW_ATL_TX_REG_RES_DSBL_WIDTH 1 2511 /* default value of bitfield reg_res_dsbl */ 2512 #define HW_ATL_TX_REG_RES_DSBL_DEFAULT 0x1 2513 2514 /* mac_phy register access busy bitfield definitions 2515 * preprocessor definitions for the bitfield "register access busy". 2516 * port="msm_pif_reg_busy_o" 2517 */ 2518 2519 /* register address for bitfield register access busy */ 2520 #define HW_ATL_MSM_REG_ACCESS_BUSY_ADR 0x00004400 2521 /* bitmask for bitfield register access busy */ 2522 #define HW_ATL_MSM_REG_ACCESS_BUSY_MSK 0x00001000 2523 /* inverted bitmask for bitfield register access busy */ 2524 #define HW_ATL_MSM_REG_ACCESS_BUSY_MSKN 0xffffefff 2525 /* lower bit position of bitfield register access busy */ 2526 #define HW_ATL_MSM_REG_ACCESS_BUSY_SHIFT 12 2527 /* width of bitfield register access busy */ 2528 #define HW_ATL_MSM_REG_ACCESS_BUSY_WIDTH 1 2529 2530 /* mac_phy msm register address[7:0] bitfield definitions 2531 * preprocessor definitions for the bitfield "msm register address[7:0]". 2532 * port="pif_msm_reg_addr_i[7:0]" 2533 */ 2534 2535 /* register address for bitfield msm register address[7:0] */ 2536 #define HW_ATL_MSM_REG_ADDR_ADR 0x00004400 2537 /* bitmask for bitfield msm register address[7:0] */ 2538 #define HW_ATL_MSM_REG_ADDR_MSK 0x000000ff 2539 /* inverted bitmask for bitfield msm register address[7:0] */ 2540 #define HW_ATL_MSM_REG_ADDR_MSKN 0xffffff00 2541 /* lower bit position of bitfield msm register address[7:0] */ 2542 #define HW_ATL_MSM_REG_ADDR_SHIFT 0 2543 /* width of bitfield msm register address[7:0] */ 2544 #define HW_ATL_MSM_REG_ADDR_WIDTH 8 2545 /* default value of bitfield msm register address[7:0] */ 2546 #define HW_ATL_MSM_REG_ADDR_DEFAULT 0x0 2547 2548 /* mac_phy register read strobe bitfield definitions 2549 * preprocessor definitions for the bitfield "register read strobe". 2550 * port="pif_msm_reg_rden_i" 2551 */ 2552 2553 /* register address for bitfield register read strobe */ 2554 #define HW_ATL_MSM_REG_RD_STROBE_ADR 0x00004400 2555 /* bitmask for bitfield register read strobe */ 2556 #define HW_ATL_MSM_REG_RD_STROBE_MSK 0x00000200 2557 /* inverted bitmask for bitfield register read strobe */ 2558 #define HW_ATL_MSM_REG_RD_STROBE_MSKN 0xfffffdff 2559 /* lower bit position of bitfield register read strobe */ 2560 #define HW_ATL_MSM_REG_RD_STROBE_SHIFT 9 2561 /* width of bitfield register read strobe */ 2562 #define HW_ATL_MSM_REG_RD_STROBE_WIDTH 1 2563 /* default value of bitfield register read strobe */ 2564 #define HW_ATL_MSM_REG_RD_STROBE_DEFAULT 0x0 2565 2566 /* mac_phy msm register read data[31:0] bitfield definitions 2567 * preprocessor definitions for the bitfield "msm register read data[31:0]". 2568 * port="msm_pif_reg_rd_data_o[31:0]" 2569 */ 2570 2571 /* register address for bitfield msm register read data[31:0] */ 2572 #define HW_ATL_MSM_REG_RD_DATA_ADR 0x00004408 2573 /* bitmask for bitfield msm register read data[31:0] */ 2574 #define HW_ATL_MSM_REG_RD_DATA_MSK 0xffffffff 2575 /* inverted bitmask for bitfield msm register read data[31:0] */ 2576 #define HW_ATL_MSM_REG_RD_DATA_MSKN 0x00000000 2577 /* lower bit position of bitfield msm register read data[31:0] */ 2578 #define HW_ATL_MSM_REG_RD_DATA_SHIFT 0 2579 /* width of bitfield msm register read data[31:0] */ 2580 #define HW_ATL_MSM_REG_RD_DATA_WIDTH 32 2581 2582 /* mac_phy msm register write data[31:0] bitfield definitions 2583 * preprocessor definitions for the bitfield "msm register write data[31:0]". 2584 * port="pif_msm_reg_wr_data_i[31:0]" 2585 */ 2586 2587 /* register address for bitfield msm register write data[31:0] */ 2588 #define HW_ATL_MSM_REG_WR_DATA_ADR 0x00004404 2589 /* bitmask for bitfield msm register write data[31:0] */ 2590 #define HW_ATL_MSM_REG_WR_DATA_MSK 0xffffffff 2591 /* inverted bitmask for bitfield msm register write data[31:0] */ 2592 #define HW_ATL_MSM_REG_WR_DATA_MSKN 0x00000000 2593 /* lower bit position of bitfield msm register write data[31:0] */ 2594 #define HW_ATL_MSM_REG_WR_DATA_SHIFT 0 2595 /* width of bitfield msm register write data[31:0] */ 2596 #define HW_ATL_MSM_REG_WR_DATA_WIDTH 32 2597 /* default value of bitfield msm register write data[31:0] */ 2598 #define HW_ATL_MSM_REG_WR_DATA_DEFAULT 0x0 2599 2600 /* mac_phy register write strobe bitfield definitions 2601 * preprocessor definitions for the bitfield "register write strobe". 2602 * port="pif_msm_reg_wren_i" 2603 */ 2604 2605 /* register address for bitfield register write strobe */ 2606 #define HW_ATL_MSM_REG_WR_STROBE_ADR 0x00004400 2607 /* bitmask for bitfield register write strobe */ 2608 #define HW_ATL_MSM_REG_WR_STROBE_MSK 0x00000100 2609 /* inverted bitmask for bitfield register write strobe */ 2610 #define HW_ATL_MSM_REG_WR_STROBE_MSKN 0xfffffeff 2611 /* lower bit position of bitfield register write strobe */ 2612 #define HW_ATL_MSM_REG_WR_STROBE_SHIFT 8 2613 /* width of bitfield register write strobe */ 2614 #define HW_ATL_MSM_REG_WR_STROBE_WIDTH 1 2615 /* default value of bitfield register write strobe */ 2616 #define HW_ATL_MSM_REG_WR_STROBE_DEFAULT 0x0 2617 2618 /* register address for bitfield PTP Digital Clock Read Enable */ 2619 #define HW_ATL_PCS_PTP_CLOCK_READ_ENABLE_ADR 0x00004628 2620 /* bitmask for bitfield PTP Digital Clock Read Enable */ 2621 #define HW_ATL_PCS_PTP_CLOCK_READ_ENABLE_MSK 0x00000010 2622 /* inverted bitmask for bitfield PTP Digital Clock Read Enable */ 2623 #define HW_ATL_PCS_PTP_CLOCK_READ_ENABLE_MSKN 0xFFFFFFEF 2624 /* lower bit position of bitfield PTP Digital Clock Read Enable */ 2625 #define HW_ATL_PCS_PTP_CLOCK_READ_ENABLE_SHIFT 4 2626 /* width of bitfield PTP Digital Clock Read Enable */ 2627 #define HW_ATL_PCS_PTP_CLOCK_READ_ENABLE_WIDTH 1 2628 /* default value of bitfield PTP Digital Clock Read Enable */ 2629 #define HW_ATL_PCS_PTP_CLOCK_READ_ENABLE_DEFAULT 0x0 2630 2631 /* register address for ptp counter reading */ 2632 #define HW_ATL_PCS_PTP_TS_VAL_ADDR(index) (0x00004900 + (index) * 0x4) 2633 2634 /* mif soft reset bitfield definitions 2635 * preprocessor definitions for the bitfield "soft reset". 2636 * port="pif_glb_res_i" 2637 */ 2638 2639 /* register address for bitfield soft reset */ 2640 #define HW_ATL_GLB_SOFT_RES_ADR 0x00000000 2641 /* bitmask for bitfield soft reset */ 2642 #define HW_ATL_GLB_SOFT_RES_MSK 0x00008000 2643 /* inverted bitmask for bitfield soft reset */ 2644 #define HW_ATL_GLB_SOFT_RES_MSKN 0xffff7fff 2645 /* lower bit position of bitfield soft reset */ 2646 #define HW_ATL_GLB_SOFT_RES_SHIFT 15 2647 /* width of bitfield soft reset */ 2648 #define HW_ATL_GLB_SOFT_RES_WIDTH 1 2649 /* default value of bitfield soft reset */ 2650 #define HW_ATL_GLB_SOFT_RES_DEFAULT 0x0 2651 2652 /* mif register reset disable bitfield definitions 2653 * preprocessor definitions for the bitfield "register reset disable". 2654 * port="pif_glb_reg_res_dsbl_i" 2655 */ 2656 2657 /* register address for bitfield register reset disable */ 2658 #define HW_ATL_GLB_REG_RES_DIS_ADR 0x00000000 2659 /* bitmask for bitfield register reset disable */ 2660 #define HW_ATL_GLB_REG_RES_DIS_MSK 0x00004000 2661 /* inverted bitmask for bitfield register reset disable */ 2662 #define HW_ATL_GLB_REG_RES_DIS_MSKN 0xffffbfff 2663 /* lower bit position of bitfield register reset disable */ 2664 #define HW_ATL_GLB_REG_RES_DIS_SHIFT 14 2665 /* width of bitfield register reset disable */ 2666 #define HW_ATL_GLB_REG_RES_DIS_WIDTH 1 2667 /* default value of bitfield register reset disable */ 2668 #define HW_ATL_GLB_REG_RES_DIS_DEFAULT 0x1 2669 2670 /* tx dma debug control definitions */ 2671 #define HW_ATL_TX_DMA_DEBUG_CTL_ADR 0x00008920u 2672 2673 /* tx dma descriptor base address msw definitions */ 2674 #define HW_ATL_TX_DMA_DESC_BASE_ADDRMSW_ADR(descriptor) \ 2675 (0x00007c04u + (descriptor) * 0x40) 2676 2677 /* tx dma total request limit */ 2678 #define HW_ATL_TX_DMA_TOTAL_REQ_LIMIT_ADR 0x00007b20u 2679 2680 /* tx interrupt moderation control register definitions 2681 * Preprocessor definitions for TX Interrupt Moderation Control Register 2682 * Base Address: 0x00008980 2683 * Parameter: queue {Q} | stride size 0x4 | range [0, 31] 2684 */ 2685 2686 #define HW_ATL_TX_INTR_MODERATION_CTL_ADR(queue) (0x00008980u + (queue) * 0x4) 2687 2688 /* pcie reg_res_dsbl bitfield definitions 2689 * preprocessor definitions for the bitfield "reg_res_dsbl". 2690 * port="pif_pci_reg_res_dsbl_i" 2691 */ 2692 2693 /* register address for bitfield reg_res_dsbl */ 2694 #define HW_ATL_PCI_REG_RES_DSBL_ADR 0x00001000 2695 /* bitmask for bitfield reg_res_dsbl */ 2696 #define HW_ATL_PCI_REG_RES_DSBL_MSK 0x20000000 2697 /* inverted bitmask for bitfield reg_res_dsbl */ 2698 #define HW_ATL_PCI_REG_RES_DSBL_MSKN 0xdfffffff 2699 /* lower bit position of bitfield reg_res_dsbl */ 2700 #define HW_ATL_PCI_REG_RES_DSBL_SHIFT 29 2701 /* width of bitfield reg_res_dsbl */ 2702 #define HW_ATL_PCI_REG_RES_DSBL_WIDTH 1 2703 /* default value of bitfield reg_res_dsbl */ 2704 #define HW_ATL_PCI_REG_RES_DSBL_DEFAULT 0x1 2705 2706 /* PCI core control register */ 2707 #define HW_ATL_PCI_REG_CONTROL6_ADR 0x1014u 2708 2709 /* global microprocessor scratch pad definitions */ 2710 #define HW_ATL_GLB_CPU_SCRATCH_SCP_ADR(scratch_scp) \ 2711 (0x00000300u + (scratch_scp) * 0x4) 2712 2713 /* register address for bitfield uP Force Interrupt */ 2714 #define HW_ATL_MCP_UP_FORCE_INTERRUPT_ADR 0x00000404 2715 /* bitmask for bitfield uP Force Interrupt */ 2716 #define HW_ATL_MCP_UP_FORCE_INTERRUPT_MSK 0x00000002 2717 /* inverted bitmask for bitfield uP Force Interrupt */ 2718 #define HW_ATL_MCP_UP_FORCE_INTERRUPT_MSKN 0xFFFFFFFD 2719 /* lower bit position of bitfield uP Force Interrupt */ 2720 #define HW_ATL_MCP_UP_FORCE_INTERRUPT_SHIFT 1 2721 /* width of bitfield uP Force Interrupt */ 2722 #define HW_ATL_MCP_UP_FORCE_INTERRUPT_WIDTH 1 2723 /* default value of bitfield uP Force Interrupt */ 2724 #define HW_ATL_MCP_UP_FORCE_INTERRUPT_DEFAULT 0x0 2725 2726 /* Preprocessor definitions for Global MDIO Interfaces 2727 * Address: 0x00000280 + 0x4 * Number of interface 2728 */ 2729 #define HW_ATL_GLB_MDIO_IFACE_ADDR_BEGIN 0x00000280u 2730 2731 #define HW_ATL_GLB_MDIO_IFACE_N_ADR(number) \ 2732 (HW_ATL_GLB_MDIO_IFACE_ADDR_BEGIN + (((number) - 1) * 0x4)) 2733 2734 /* MIF MDIO Busy Bitfield Definitions 2735 * Preprocessor definitions for the bitfield "MDIO Busy". 2736 * PORT="mdio_pif_busy_o" 2737 */ 2738 2739 /* Register address for bitfield MDIO Busy */ 2740 #define HW_ATL_MDIO_BUSY_ADR 0x00000284 2741 /* Bitmask for bitfield MDIO Busy */ 2742 #define HW_ATL_MDIO_BUSY_MSK 0x80000000 2743 /* Inverted bitmask for bitfield MDIO Busy */ 2744 #define HW_ATL_MDIO_BUSY_MSKN 0x7FFFFFFF 2745 /* Lower bit position of bitfield MDIO Busy */ 2746 #define HW_ATL_MDIO_BUSY_SHIFT 31 2747 /* Width of bitfield MDIO Busy */ 2748 #define HW_ATL_MDIO_BUSY_WIDTH 1 2749 2750 /* MIF MDIO Execute Operation Bitfield Definitions 2751 * Preprocessor definitions for the bitfield "MDIO Execute Operation". 2752 * PORT="pif_mdio_op_start_i" 2753 */ 2754 2755 /* Register address for bitfield MDIO Execute Operation */ 2756 #define HW_ATL_MDIO_EXECUTE_OPERATION_ADR 0x00000284 2757 /* Bitmask for bitfield MDIO Execute Operation */ 2758 #define HW_ATL_MDIO_EXECUTE_OPERATION_MSK 0x00008000 2759 /* Inverted bitmask for bitfield MDIO Execute Operation */ 2760 #define HW_ATL_MDIO_EXECUTE_OPERATION_MSKN 0xFFFF7FFF 2761 /* Lower bit position of bitfield MDIO Execute Operation */ 2762 #define HW_ATL_MDIO_EXECUTE_OPERATION_SHIFT 15 2763 /* Width of bitfield MDIO Execute Operation */ 2764 #define HW_ATL_MDIO_EXECUTE_OPERATION_WIDTH 1 2765 /* Default value of bitfield MDIO Execute Operation */ 2766 #define HW_ATL_MDIO_EXECUTE_OPERATION_DEFAULT 0x0 2767 2768 /* MIF Op Mode [1:0] Bitfield Definitions 2769 * Preprocessor definitions for the bitfield "Op Mode [1:0]". 2770 * PORT="pif_mdio_mode_i[1:0]" 2771 */ 2772 2773 /* Register address for bitfield Op Mode [1:0] */ 2774 #define HW_ATL_MDIO_OP_MODE_ADR 0x00000284 2775 /* Bitmask for bitfield Op Mode [1:0] */ 2776 #define HW_ATL_MDIO_OP_MODE_MSK 0x00003000 2777 /* Inverted bitmask for bitfield Op Mode [1:0] */ 2778 #define HW_ATL_MDIO_OP_MODE_MSKN 0xFFFFCFFF 2779 /* Lower bit position of bitfield Op Mode [1:0] */ 2780 #define HW_ATL_MDIO_OP_MODE_SHIFT 12 2781 /* Width of bitfield Op Mode [1:0] */ 2782 #define HW_ATL_MDIO_OP_MODE_WIDTH 2 2783 /* Default value of bitfield Op Mode [1:0] */ 2784 #define HW_ATL_MDIO_OP_MODE_DEFAULT 0x0 2785 2786 /* MIF PHY address Bitfield Definitions 2787 * Preprocessor definitions for the bitfield "PHY address". 2788 * PORT="pif_mdio_phy_addr_i[9:0]" 2789 */ 2790 2791 /* Register address for bitfield PHY address */ 2792 #define HW_ATL_MDIO_PHY_ADDRESS_ADR 0x00000284 2793 /* Bitmask for bitfield PHY address */ 2794 #define HW_ATL_MDIO_PHY_ADDRESS_MSK 0x000003FF 2795 /* Inverted bitmask for bitfield PHY address */ 2796 #define HW_ATL_MDIO_PHY_ADDRESS_MSKN 0xFFFFFC00 2797 /* Lower bit position of bitfield PHY address */ 2798 #define HW_ATL_MDIO_PHY_ADDRESS_SHIFT 0 2799 /* Width of bitfield PHY address */ 2800 #define HW_ATL_MDIO_PHY_ADDRESS_WIDTH 10 2801 /* Default value of bitfield PHY address */ 2802 #define HW_ATL_MDIO_PHY_ADDRESS_DEFAULT 0x0 2803 2804 /* MIF MDIO WriteData [F:0] Bitfield Definitions 2805 * Preprocessor definitions for the bitfield "MDIO WriteData [F:0]". 2806 * PORT="pif_mdio_wdata_i[15:0]" 2807 */ 2808 2809 /* Register address for bitfield MDIO WriteData [F:0] */ 2810 #define HW_ATL_MDIO_WRITE_DATA_ADR 0x00000288 2811 /* Bitmask for bitfield MDIO WriteData [F:0] */ 2812 #define HW_ATL_MDIO_WRITE_DATA_MSK 0x0000FFFF 2813 /* Inverted bitmask for bitfield MDIO WriteData [F:0] */ 2814 #define HW_ATL_MDIO_WRITE_DATA_MSKN 0xFFFF0000 2815 /* Lower bit position of bitfield MDIO WriteData [F:0] */ 2816 #define HW_ATL_MDIO_WRITE_DATA_SHIFT 0 2817 /* Width of bitfield MDIO WriteData [F:0] */ 2818 #define HW_ATL_MDIO_WRITE_DATA_WIDTH 16 2819 /* Default value of bitfield MDIO WriteData [F:0] */ 2820 #define HW_ATL_MDIO_WRITE_DATA_DEFAULT 0x0 2821 2822 /* MIF MDIO Address [F:0] Bitfield Definitions 2823 * Preprocessor definitions for the bitfield "MDIO Address [F:0]". 2824 * PORT="pif_mdio_addr_i[15:0]" 2825 */ 2826 2827 /* Register address for bitfield MDIO Address [F:0] */ 2828 #define HW_ATL_MDIO_ADDRESS_ADR 0x0000028C 2829 /* Bitmask for bitfield MDIO Address [F:0] */ 2830 #define HW_ATL_MDIO_ADDRESS_MSK 0x0000FFFF 2831 /* Inverted bitmask for bitfield MDIO Address [F:0] */ 2832 #define HW_ATL_MDIO_ADDRESS_MSKN 0xFFFF0000 2833 /* Lower bit position of bitfield MDIO Address [F:0] */ 2834 #define HW_ATL_MDIO_ADDRESS_SHIFT 0 2835 /* Width of bitfield MDIO Address [F:0] */ 2836 #define HW_ATL_MDIO_ADDRESS_WIDTH 16 2837 /* Default value of bitfield MDIO Address [F:0] */ 2838 #define HW_ATL_MDIO_ADDRESS_DEFAULT 0x0 2839 2840 #define HW_ATL_FW_SM_MDIO 0x0U 2841 #define HW_ATL_FW_SM_RAM 0x2U 2842 2843 #endif /* HW_ATL_LLH_INTERNAL_H */ 2844