1 /* 2 * aQuantia Corporation Network Driver 3 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 */ 9 10 /* File hw_atl_llh_internal.h: Preprocessor definitions 11 * for Atlantic registers. 12 */ 13 14 #ifndef HW_ATL_LLH_INTERNAL_H 15 #define HW_ATL_LLH_INTERNAL_H 16 17 /* global microprocessor semaphore definitions 18 * base address: 0x000003a0 19 * parameter: semaphore {s} | stride size 0x4 | range [0, 15] 20 */ 21 #define glb_cpu_sem_adr(semaphore) (0x000003a0u + (semaphore) * 0x4) 22 /* register address for bitfield rx dma good octet counter lsw [1f:0] */ 23 #define stats_rx_dma_good_octet_counterlsw__adr 0x00006808 24 /* register address for bitfield rx dma good packet counter lsw [1f:0] */ 25 #define stats_rx_dma_good_pkt_counterlsw__adr 0x00006800 26 /* register address for bitfield tx dma good octet counter lsw [1f:0] */ 27 #define stats_tx_dma_good_octet_counterlsw__adr 0x00008808 28 /* register address for bitfield tx dma good packet counter lsw [1f:0] */ 29 #define stats_tx_dma_good_pkt_counterlsw__adr 0x00008800 30 31 /* register address for bitfield rx dma good octet counter msw [3f:20] */ 32 #define stats_rx_dma_good_octet_countermsw__adr 0x0000680c 33 /* register address for bitfield rx dma good packet counter msw [3f:20] */ 34 #define stats_rx_dma_good_pkt_countermsw__adr 0x00006804 35 /* register address for bitfield tx dma good octet counter msw [3f:20] */ 36 #define stats_tx_dma_good_octet_countermsw__adr 0x0000880c 37 /* register address for bitfield tx dma good packet counter msw [3f:20] */ 38 #define stats_tx_dma_good_pkt_countermsw__adr 0x00008804 39 40 /* preprocessor definitions for msm rx errors counter register */ 41 #define mac_msm_rx_errs_cnt_adr 0x00000120u 42 43 /* preprocessor definitions for msm rx unicast frames counter register */ 44 #define mac_msm_rx_ucst_frm_cnt_adr 0x000000e0u 45 46 /* preprocessor definitions for msm rx multicast frames counter register */ 47 #define mac_msm_rx_mcst_frm_cnt_adr 0x000000e8u 48 49 /* preprocessor definitions for msm rx broadcast frames counter register */ 50 #define mac_msm_rx_bcst_frm_cnt_adr 0x000000f0u 51 52 /* preprocessor definitions for msm rx broadcast octets counter register 1 */ 53 #define mac_msm_rx_bcst_octets_counter1_adr 0x000001b0u 54 55 /* preprocessor definitions for msm rx broadcast octets counter register 2 */ 56 #define mac_msm_rx_bcst_octets_counter2_adr 0x000001b4u 57 58 /* preprocessor definitions for msm rx unicast octets counter register 0 */ 59 #define mac_msm_rx_ucst_octets_counter0_adr 0x000001b8u 60 61 /* preprocessor definitions for rx dma statistics counter 7 */ 62 #define rx_dma_stat_counter7_adr 0x00006818u 63 64 /* preprocessor definitions for msm tx unicast frames counter register */ 65 #define mac_msm_tx_ucst_frm_cnt_adr 0x00000108u 66 67 /* preprocessor definitions for msm tx multicast frames counter register */ 68 #define mac_msm_tx_mcst_frm_cnt_adr 0x00000110u 69 70 /* preprocessor definitions for global mif identification */ 71 #define glb_mif_id_adr 0x0000001cu 72 73 /* register address for bitfield iamr_lsw[1f:0] */ 74 #define itr_iamrlsw_adr 0x00002090 75 /* register address for bitfield rx dma drop packet counter [1f:0] */ 76 #define rpb_rx_dma_drop_pkt_cnt_adr 0x00006818 77 78 /* register address for bitfield imcr_lsw[1f:0] */ 79 #define itr_imcrlsw_adr 0x00002070 80 /* register address for bitfield imsr_lsw[1f:0] */ 81 #define itr_imsrlsw_adr 0x00002060 82 /* register address for bitfield itr_reg_res_dsbl */ 83 #define itr_reg_res_dsbl_adr 0x00002300 84 /* bitmask for bitfield itr_reg_res_dsbl */ 85 #define itr_reg_res_dsbl_msk 0x20000000 86 /* lower bit position of bitfield itr_reg_res_dsbl */ 87 #define itr_reg_res_dsbl_shift 29 88 /* register address for bitfield iscr_lsw[1f:0] */ 89 #define itr_iscrlsw_adr 0x00002050 90 /* register address for bitfield isr_lsw[1f:0] */ 91 #define itr_isrlsw_adr 0x00002000 92 /* register address for bitfield itr_reset */ 93 #define itr_res_adr 0x00002300 94 /* bitmask for bitfield itr_reset */ 95 #define itr_res_msk 0x80000000 96 /* lower bit position of bitfield itr_reset */ 97 #define itr_res_shift 31 98 /* register address for bitfield dca{d}_cpuid[7:0] */ 99 #define rdm_dcadcpuid_adr(dca) (0x00006100 + (dca) * 0x4) 100 /* bitmask for bitfield dca{d}_cpuid[7:0] */ 101 #define rdm_dcadcpuid_msk 0x000000ff 102 /* lower bit position of bitfield dca{d}_cpuid[7:0] */ 103 #define rdm_dcadcpuid_shift 0 104 /* register address for bitfield dca_en */ 105 #define rdm_dca_en_adr 0x00006180 106 107 /* rx dca_en bitfield definitions 108 * preprocessor definitions for the bitfield "dca_en". 109 * port="pif_rdm_dca_en_i" 110 */ 111 112 /* register address for bitfield dca_en */ 113 #define rdm_dca_en_adr 0x00006180 114 /* bitmask for bitfield dca_en */ 115 #define rdm_dca_en_msk 0x80000000 116 /* inverted bitmask for bitfield dca_en */ 117 #define rdm_dca_en_mskn 0x7fffffff 118 /* lower bit position of bitfield dca_en */ 119 #define rdm_dca_en_shift 31 120 /* width of bitfield dca_en */ 121 #define rdm_dca_en_width 1 122 /* default value of bitfield dca_en */ 123 #define rdm_dca_en_default 0x1 124 125 /* rx dca_mode[3:0] bitfield definitions 126 * preprocessor definitions for the bitfield "dca_mode[3:0]". 127 * port="pif_rdm_dca_mode_i[3:0]" 128 */ 129 130 /* register address for bitfield dca_mode[3:0] */ 131 #define rdm_dca_mode_adr 0x00006180 132 /* bitmask for bitfield dca_mode[3:0] */ 133 #define rdm_dca_mode_msk 0x0000000f 134 /* inverted bitmask for bitfield dca_mode[3:0] */ 135 #define rdm_dca_mode_mskn 0xfffffff0 136 /* lower bit position of bitfield dca_mode[3:0] */ 137 #define rdm_dca_mode_shift 0 138 /* width of bitfield dca_mode[3:0] */ 139 #define rdm_dca_mode_width 4 140 /* default value of bitfield dca_mode[3:0] */ 141 #define rdm_dca_mode_default 0x0 142 143 /* rx desc{d}_data_size[4:0] bitfield definitions 144 * preprocessor definitions for the bitfield "desc{d}_data_size[4:0]". 145 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 146 * port="pif_rdm_desc0_data_size_i[4:0]" 147 */ 148 149 /* register address for bitfield desc{d}_data_size[4:0] */ 150 #define rdm_descddata_size_adr(descriptor) (0x00005b18 + (descriptor) * 0x20) 151 /* bitmask for bitfield desc{d}_data_size[4:0] */ 152 #define rdm_descddata_size_msk 0x0000001f 153 /* inverted bitmask for bitfield desc{d}_data_size[4:0] */ 154 #define rdm_descddata_size_mskn 0xffffffe0 155 /* lower bit position of bitfield desc{d}_data_size[4:0] */ 156 #define rdm_descddata_size_shift 0 157 /* width of bitfield desc{d}_data_size[4:0] */ 158 #define rdm_descddata_size_width 5 159 /* default value of bitfield desc{d}_data_size[4:0] */ 160 #define rdm_descddata_size_default 0x0 161 162 /* rx dca{d}_desc_en bitfield definitions 163 * preprocessor definitions for the bitfield "dca{d}_desc_en". 164 * parameter: dca {d} | stride size 0x4 | range [0, 31] 165 * port="pif_rdm_dca_desc_en_i[0]" 166 */ 167 168 /* register address for bitfield dca{d}_desc_en */ 169 #define rdm_dcaddesc_en_adr(dca) (0x00006100 + (dca) * 0x4) 170 /* bitmask for bitfield dca{d}_desc_en */ 171 #define rdm_dcaddesc_en_msk 0x80000000 172 /* inverted bitmask for bitfield dca{d}_desc_en */ 173 #define rdm_dcaddesc_en_mskn 0x7fffffff 174 /* lower bit position of bitfield dca{d}_desc_en */ 175 #define rdm_dcaddesc_en_shift 31 176 /* width of bitfield dca{d}_desc_en */ 177 #define rdm_dcaddesc_en_width 1 178 /* default value of bitfield dca{d}_desc_en */ 179 #define rdm_dcaddesc_en_default 0x0 180 181 /* rx desc{d}_en bitfield definitions 182 * preprocessor definitions for the bitfield "desc{d}_en". 183 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 184 * port="pif_rdm_desc_en_i[0]" 185 */ 186 187 /* register address for bitfield desc{d}_en */ 188 #define rdm_descden_adr(descriptor) (0x00005b08 + (descriptor) * 0x20) 189 /* bitmask for bitfield desc{d}_en */ 190 #define rdm_descden_msk 0x80000000 191 /* inverted bitmask for bitfield desc{d}_en */ 192 #define rdm_descden_mskn 0x7fffffff 193 /* lower bit position of bitfield desc{d}_en */ 194 #define rdm_descden_shift 31 195 /* width of bitfield desc{d}_en */ 196 #define rdm_descden_width 1 197 /* default value of bitfield desc{d}_en */ 198 #define rdm_descden_default 0x0 199 200 /* rx desc{d}_hdr_size[4:0] bitfield definitions 201 * preprocessor definitions for the bitfield "desc{d}_hdr_size[4:0]". 202 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 203 * port="pif_rdm_desc0_hdr_size_i[4:0]" 204 */ 205 206 /* register address for bitfield desc{d}_hdr_size[4:0] */ 207 #define rdm_descdhdr_size_adr(descriptor) (0x00005b18 + (descriptor) * 0x20) 208 /* bitmask for bitfield desc{d}_hdr_size[4:0] */ 209 #define rdm_descdhdr_size_msk 0x00001f00 210 /* inverted bitmask for bitfield desc{d}_hdr_size[4:0] */ 211 #define rdm_descdhdr_size_mskn 0xffffe0ff 212 /* lower bit position of bitfield desc{d}_hdr_size[4:0] */ 213 #define rdm_descdhdr_size_shift 8 214 /* width of bitfield desc{d}_hdr_size[4:0] */ 215 #define rdm_descdhdr_size_width 5 216 /* default value of bitfield desc{d}_hdr_size[4:0] */ 217 #define rdm_descdhdr_size_default 0x0 218 219 /* rx desc{d}_hdr_split bitfield definitions 220 * preprocessor definitions for the bitfield "desc{d}_hdr_split". 221 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 222 * port="pif_rdm_desc_hdr_split_i[0]" 223 */ 224 225 /* register address for bitfield desc{d}_hdr_split */ 226 #define rdm_descdhdr_split_adr(descriptor) (0x00005b08 + (descriptor) * 0x20) 227 /* bitmask for bitfield desc{d}_hdr_split */ 228 #define rdm_descdhdr_split_msk 0x10000000 229 /* inverted bitmask for bitfield desc{d}_hdr_split */ 230 #define rdm_descdhdr_split_mskn 0xefffffff 231 /* lower bit position of bitfield desc{d}_hdr_split */ 232 #define rdm_descdhdr_split_shift 28 233 /* width of bitfield desc{d}_hdr_split */ 234 #define rdm_descdhdr_split_width 1 235 /* default value of bitfield desc{d}_hdr_split */ 236 #define rdm_descdhdr_split_default 0x0 237 238 /* rx desc{d}_hd[c:0] bitfield definitions 239 * preprocessor definitions for the bitfield "desc{d}_hd[c:0]". 240 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 241 * port="rdm_pif_desc0_hd_o[12:0]" 242 */ 243 244 /* register address for bitfield desc{d}_hd[c:0] */ 245 #define rdm_descdhd_adr(descriptor) (0x00005b0c + (descriptor) * 0x20) 246 /* bitmask for bitfield desc{d}_hd[c:0] */ 247 #define rdm_descdhd_msk 0x00001fff 248 /* inverted bitmask for bitfield desc{d}_hd[c:0] */ 249 #define rdm_descdhd_mskn 0xffffe000 250 /* lower bit position of bitfield desc{d}_hd[c:0] */ 251 #define rdm_descdhd_shift 0 252 /* width of bitfield desc{d}_hd[c:0] */ 253 #define rdm_descdhd_width 13 254 255 /* rx desc{d}_len[9:0] bitfield definitions 256 * preprocessor definitions for the bitfield "desc{d}_len[9:0]". 257 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 258 * port="pif_rdm_desc0_len_i[9:0]" 259 */ 260 261 /* register address for bitfield desc{d}_len[9:0] */ 262 #define rdm_descdlen_adr(descriptor) (0x00005b08 + (descriptor) * 0x20) 263 /* bitmask for bitfield desc{d}_len[9:0] */ 264 #define rdm_descdlen_msk 0x00001ff8 265 /* inverted bitmask for bitfield desc{d}_len[9:0] */ 266 #define rdm_descdlen_mskn 0xffffe007 267 /* lower bit position of bitfield desc{d}_len[9:0] */ 268 #define rdm_descdlen_shift 3 269 /* width of bitfield desc{d}_len[9:0] */ 270 #define rdm_descdlen_width 10 271 /* default value of bitfield desc{d}_len[9:0] */ 272 #define rdm_descdlen_default 0x0 273 274 /* rx desc{d}_reset bitfield definitions 275 * preprocessor definitions for the bitfield "desc{d}_reset". 276 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 277 * port="pif_rdm_q_pf_res_i[0]" 278 */ 279 280 /* register address for bitfield desc{d}_reset */ 281 #define rdm_descdreset_adr(descriptor) (0x00005b08 + (descriptor) * 0x20) 282 /* bitmask for bitfield desc{d}_reset */ 283 #define rdm_descdreset_msk 0x02000000 284 /* inverted bitmask for bitfield desc{d}_reset */ 285 #define rdm_descdreset_mskn 0xfdffffff 286 /* lower bit position of bitfield desc{d}_reset */ 287 #define rdm_descdreset_shift 25 288 /* width of bitfield desc{d}_reset */ 289 #define rdm_descdreset_width 1 290 /* default value of bitfield desc{d}_reset */ 291 #define rdm_descdreset_default 0x0 292 293 /* rx int_desc_wrb_en bitfield definitions 294 * preprocessor definitions for the bitfield "int_desc_wrb_en". 295 * port="pif_rdm_int_desc_wrb_en_i" 296 */ 297 298 /* register address for bitfield int_desc_wrb_en */ 299 #define rdm_int_desc_wrb_en_adr 0x00005a30 300 /* bitmask for bitfield int_desc_wrb_en */ 301 #define rdm_int_desc_wrb_en_msk 0x00000004 302 /* inverted bitmask for bitfield int_desc_wrb_en */ 303 #define rdm_int_desc_wrb_en_mskn 0xfffffffb 304 /* lower bit position of bitfield int_desc_wrb_en */ 305 #define rdm_int_desc_wrb_en_shift 2 306 /* width of bitfield int_desc_wrb_en */ 307 #define rdm_int_desc_wrb_en_width 1 308 /* default value of bitfield int_desc_wrb_en */ 309 #define rdm_int_desc_wrb_en_default 0x0 310 311 /* rx dca{d}_hdr_en bitfield definitions 312 * preprocessor definitions for the bitfield "dca{d}_hdr_en". 313 * parameter: dca {d} | stride size 0x4 | range [0, 31] 314 * port="pif_rdm_dca_hdr_en_i[0]" 315 */ 316 317 /* register address for bitfield dca{d}_hdr_en */ 318 #define rdm_dcadhdr_en_adr(dca) (0x00006100 + (dca) * 0x4) 319 /* bitmask for bitfield dca{d}_hdr_en */ 320 #define rdm_dcadhdr_en_msk 0x40000000 321 /* inverted bitmask for bitfield dca{d}_hdr_en */ 322 #define rdm_dcadhdr_en_mskn 0xbfffffff 323 /* lower bit position of bitfield dca{d}_hdr_en */ 324 #define rdm_dcadhdr_en_shift 30 325 /* width of bitfield dca{d}_hdr_en */ 326 #define rdm_dcadhdr_en_width 1 327 /* default value of bitfield dca{d}_hdr_en */ 328 #define rdm_dcadhdr_en_default 0x0 329 330 /* rx dca{d}_pay_en bitfield definitions 331 * preprocessor definitions for the bitfield "dca{d}_pay_en". 332 * parameter: dca {d} | stride size 0x4 | range [0, 31] 333 * port="pif_rdm_dca_pay_en_i[0]" 334 */ 335 336 /* register address for bitfield dca{d}_pay_en */ 337 #define rdm_dcadpay_en_adr(dca) (0x00006100 + (dca) * 0x4) 338 /* bitmask for bitfield dca{d}_pay_en */ 339 #define rdm_dcadpay_en_msk 0x20000000 340 /* inverted bitmask for bitfield dca{d}_pay_en */ 341 #define rdm_dcadpay_en_mskn 0xdfffffff 342 /* lower bit position of bitfield dca{d}_pay_en */ 343 #define rdm_dcadpay_en_shift 29 344 /* width of bitfield dca{d}_pay_en */ 345 #define rdm_dcadpay_en_width 1 346 /* default value of bitfield dca{d}_pay_en */ 347 #define rdm_dcadpay_en_default 0x0 348 349 /* RX rdm_int_rim_en Bitfield Definitions 350 * Preprocessor definitions for the bitfield "rdm_int_rim_en". 351 * PORT="pif_rdm_int_rim_en_i" 352 */ 353 354 /* Register address for bitfield rdm_int_rim_en */ 355 #define rdm_int_rim_en_adr 0x00005A30 356 /* Bitmask for bitfield rdm_int_rim_en */ 357 #define rdm_int_rim_en_msk 0x00000008 358 /* Inverted bitmask for bitfield rdm_int_rim_en */ 359 #define rdm_int_rim_en_mskn 0xFFFFFFF7 360 /* Lower bit position of bitfield rdm_int_rim_en */ 361 #define rdm_int_rim_en_shift 3 362 /* Width of bitfield rdm_int_rim_en */ 363 #define rdm_int_rim_en_width 1 364 /* Default value of bitfield rdm_int_rim_en */ 365 #define rdm_int_rim_en_default 0x0 366 367 /* general interrupt mapping register definitions 368 * preprocessor definitions for general interrupt mapping register 369 * base address: 0x00002180 370 * parameter: regidx {f} | stride size 0x4 | range [0, 3] 371 */ 372 #define gen_intr_map_adr(regidx) (0x00002180u + (regidx) * 0x4) 373 374 /* general interrupt status register definitions 375 * preprocessor definitions for general interrupt status register 376 * address: 0x000021A0 377 */ 378 379 #define gen_intr_stat_adr 0x000021A4U 380 381 /* interrupt global control register definitions 382 * preprocessor definitions for interrupt global control register 383 * address: 0x00002300 384 */ 385 #define intr_glb_ctl_adr 0x00002300u 386 387 /* interrupt throttle register definitions 388 * preprocessor definitions for interrupt throttle register 389 * base address: 0x00002800 390 * parameter: throttle {t} | stride size 0x4 | range [0, 31] 391 */ 392 #define intr_thr_adr(throttle) (0x00002800u + (throttle) * 0x4) 393 394 /* rx dma descriptor base address lsw definitions 395 * preprocessor definitions for rx dma descriptor base address lsw 396 * base address: 0x00005b00 397 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 398 */ 399 #define rx_dma_desc_base_addrlsw_adr(descriptor) \ 400 (0x00005b00u + (descriptor) * 0x20) 401 402 /* rx dma descriptor base address msw definitions 403 * preprocessor definitions for rx dma descriptor base address msw 404 * base address: 0x00005b04 405 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 406 */ 407 #define rx_dma_desc_base_addrmsw_adr(descriptor) \ 408 (0x00005b04u + (descriptor) * 0x20) 409 410 /* rx dma descriptor status register definitions 411 * preprocessor definitions for rx dma descriptor status register 412 * base address: 0x00005b14 413 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 414 */ 415 #define rx_dma_desc_stat_adr(descriptor) (0x00005b14u + (descriptor) * 0x20) 416 417 /* rx dma descriptor tail pointer register definitions 418 * preprocessor definitions for rx dma descriptor tail pointer register 419 * base address: 0x00005b10 420 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 421 */ 422 #define rx_dma_desc_tail_ptr_adr(descriptor) (0x00005b10u + (descriptor) * 0x20) 423 424 /* rx interrupt moderation control register definitions 425 * Preprocessor definitions for RX Interrupt Moderation Control Register 426 * Base Address: 0x00005A40 427 * Parameter: RIM {R} | stride size 0x4 | range [0, 31] 428 */ 429 #define rx_intr_moderation_ctl_adr(rim) (0x00005A40u + (rim) * 0x4) 430 431 /* rx filter multicast filter mask register definitions 432 * preprocessor definitions for rx filter multicast filter mask register 433 * address: 0x00005270 434 */ 435 #define rx_flr_mcst_flr_msk_adr 0x00005270u 436 437 /* rx filter multicast filter register definitions 438 * preprocessor definitions for rx filter multicast filter register 439 * base address: 0x00005250 440 * parameter: filter {f} | stride size 0x4 | range [0, 7] 441 */ 442 #define rx_flr_mcst_flr_adr(filter) (0x00005250u + (filter) * 0x4) 443 444 /* RX Filter RSS Control Register 1 Definitions 445 * Preprocessor definitions for RX Filter RSS Control Register 1 446 * Address: 0x000054C0 447 */ 448 #define rx_flr_rss_control1_adr 0x000054C0u 449 450 /* RX Filter Control Register 2 Definitions 451 * Preprocessor definitions for RX Filter Control Register 2 452 * Address: 0x00005104 453 */ 454 #define rx_flr_control2_adr 0x00005104u 455 456 /* tx tx dma debug control [1f:0] bitfield definitions 457 * preprocessor definitions for the bitfield "tx dma debug control [1f:0]". 458 * port="pif_tdm_debug_cntl_i[31:0]" 459 */ 460 461 /* register address for bitfield tx dma debug control [1f:0] */ 462 #define tdm_tx_dma_debug_ctl_adr 0x00008920 463 /* bitmask for bitfield tx dma debug control [1f:0] */ 464 #define tdm_tx_dma_debug_ctl_msk 0xffffffff 465 /* inverted bitmask for bitfield tx dma debug control [1f:0] */ 466 #define tdm_tx_dma_debug_ctl_mskn 0x00000000 467 /* lower bit position of bitfield tx dma debug control [1f:0] */ 468 #define tdm_tx_dma_debug_ctl_shift 0 469 /* width of bitfield tx dma debug control [1f:0] */ 470 #define tdm_tx_dma_debug_ctl_width 32 471 /* default value of bitfield tx dma debug control [1f:0] */ 472 #define tdm_tx_dma_debug_ctl_default 0x0 473 474 /* tx dma descriptor base address lsw definitions 475 * preprocessor definitions for tx dma descriptor base address lsw 476 * base address: 0x00007c00 477 * parameter: descriptor {d} | stride size 0x40 | range [0, 31] 478 */ 479 #define tx_dma_desc_base_addrlsw_adr(descriptor) \ 480 (0x00007c00u + (descriptor) * 0x40) 481 482 /* tx dma descriptor tail pointer register definitions 483 * preprocessor definitions for tx dma descriptor tail pointer register 484 * base address: 0x00007c10 485 * parameter: descriptor {d} | stride size 0x40 | range [0, 31] 486 */ 487 #define tx_dma_desc_tail_ptr_adr(descriptor) (0x00007c10u + (descriptor) * 0x40) 488 489 /* rx dma_sys_loopback bitfield definitions 490 * preprocessor definitions for the bitfield "dma_sys_loopback". 491 * port="pif_rpb_dma_sys_lbk_i" 492 */ 493 494 /* register address for bitfield dma_sys_loopback */ 495 #define rpb_dma_sys_lbk_adr 0x00005000 496 /* bitmask for bitfield dma_sys_loopback */ 497 #define rpb_dma_sys_lbk_msk 0x00000040 498 /* inverted bitmask for bitfield dma_sys_loopback */ 499 #define rpb_dma_sys_lbk_mskn 0xffffffbf 500 /* lower bit position of bitfield dma_sys_loopback */ 501 #define rpb_dma_sys_lbk_shift 6 502 /* width of bitfield dma_sys_loopback */ 503 #define rpb_dma_sys_lbk_width 1 504 /* default value of bitfield dma_sys_loopback */ 505 #define rpb_dma_sys_lbk_default 0x0 506 507 /* rx rx_tc_mode bitfield definitions 508 * preprocessor definitions for the bitfield "rx_tc_mode". 509 * port="pif_rpb_rx_tc_mode_i,pif_rpf_rx_tc_mode_i" 510 */ 511 512 /* register address for bitfield rx_tc_mode */ 513 #define rpb_rpf_rx_tc_mode_adr 0x00005700 514 /* bitmask for bitfield rx_tc_mode */ 515 #define rpb_rpf_rx_tc_mode_msk 0x00000100 516 /* inverted bitmask for bitfield rx_tc_mode */ 517 #define rpb_rpf_rx_tc_mode_mskn 0xfffffeff 518 /* lower bit position of bitfield rx_tc_mode */ 519 #define rpb_rpf_rx_tc_mode_shift 8 520 /* width of bitfield rx_tc_mode */ 521 #define rpb_rpf_rx_tc_mode_width 1 522 /* default value of bitfield rx_tc_mode */ 523 #define rpb_rpf_rx_tc_mode_default 0x0 524 525 /* rx rx_buf_en bitfield definitions 526 * preprocessor definitions for the bitfield "rx_buf_en". 527 * port="pif_rpb_rx_buf_en_i" 528 */ 529 530 /* register address for bitfield rx_buf_en */ 531 #define rpb_rx_buf_en_adr 0x00005700 532 /* bitmask for bitfield rx_buf_en */ 533 #define rpb_rx_buf_en_msk 0x00000001 534 /* inverted bitmask for bitfield rx_buf_en */ 535 #define rpb_rx_buf_en_mskn 0xfffffffe 536 /* lower bit position of bitfield rx_buf_en */ 537 #define rpb_rx_buf_en_shift 0 538 /* width of bitfield rx_buf_en */ 539 #define rpb_rx_buf_en_width 1 540 /* default value of bitfield rx_buf_en */ 541 #define rpb_rx_buf_en_default 0x0 542 543 /* rx rx{b}_hi_thresh[d:0] bitfield definitions 544 * preprocessor definitions for the bitfield "rx{b}_hi_thresh[d:0]". 545 * parameter: buffer {b} | stride size 0x10 | range [0, 7] 546 * port="pif_rpb_rx0_hi_thresh_i[13:0]" 547 */ 548 549 /* register address for bitfield rx{b}_hi_thresh[d:0] */ 550 #define rpb_rxbhi_thresh_adr(buffer) (0x00005714 + (buffer) * 0x10) 551 /* bitmask for bitfield rx{b}_hi_thresh[d:0] */ 552 #define rpb_rxbhi_thresh_msk 0x3fff0000 553 /* inverted bitmask for bitfield rx{b}_hi_thresh[d:0] */ 554 #define rpb_rxbhi_thresh_mskn 0xc000ffff 555 /* lower bit position of bitfield rx{b}_hi_thresh[d:0] */ 556 #define rpb_rxbhi_thresh_shift 16 557 /* width of bitfield rx{b}_hi_thresh[d:0] */ 558 #define rpb_rxbhi_thresh_width 14 559 /* default value of bitfield rx{b}_hi_thresh[d:0] */ 560 #define rpb_rxbhi_thresh_default 0x0 561 562 /* rx rx{b}_lo_thresh[d:0] bitfield definitions 563 * preprocessor definitions for the bitfield "rx{b}_lo_thresh[d:0]". 564 * parameter: buffer {b} | stride size 0x10 | range [0, 7] 565 * port="pif_rpb_rx0_lo_thresh_i[13:0]" 566 */ 567 568 /* register address for bitfield rx{b}_lo_thresh[d:0] */ 569 #define rpb_rxblo_thresh_adr(buffer) (0x00005714 + (buffer) * 0x10) 570 /* bitmask for bitfield rx{b}_lo_thresh[d:0] */ 571 #define rpb_rxblo_thresh_msk 0x00003fff 572 /* inverted bitmask for bitfield rx{b}_lo_thresh[d:0] */ 573 #define rpb_rxblo_thresh_mskn 0xffffc000 574 /* lower bit position of bitfield rx{b}_lo_thresh[d:0] */ 575 #define rpb_rxblo_thresh_shift 0 576 /* width of bitfield rx{b}_lo_thresh[d:0] */ 577 #define rpb_rxblo_thresh_width 14 578 /* default value of bitfield rx{b}_lo_thresh[d:0] */ 579 #define rpb_rxblo_thresh_default 0x0 580 581 /* rx rx_fc_mode[1:0] bitfield definitions 582 * preprocessor definitions for the bitfield "rx_fc_mode[1:0]". 583 * port="pif_rpb_rx_fc_mode_i[1:0]" 584 */ 585 586 /* register address for bitfield rx_fc_mode[1:0] */ 587 #define rpb_rx_fc_mode_adr 0x00005700 588 /* bitmask for bitfield rx_fc_mode[1:0] */ 589 #define rpb_rx_fc_mode_msk 0x00000030 590 /* inverted bitmask for bitfield rx_fc_mode[1:0] */ 591 #define rpb_rx_fc_mode_mskn 0xffffffcf 592 /* lower bit position of bitfield rx_fc_mode[1:0] */ 593 #define rpb_rx_fc_mode_shift 4 594 /* width of bitfield rx_fc_mode[1:0] */ 595 #define rpb_rx_fc_mode_width 2 596 /* default value of bitfield rx_fc_mode[1:0] */ 597 #define rpb_rx_fc_mode_default 0x0 598 599 /* rx rx{b}_buf_size[8:0] bitfield definitions 600 * preprocessor definitions for the bitfield "rx{b}_buf_size[8:0]". 601 * parameter: buffer {b} | stride size 0x10 | range [0, 7] 602 * port="pif_rpb_rx0_buf_size_i[8:0]" 603 */ 604 605 /* register address for bitfield rx{b}_buf_size[8:0] */ 606 #define rpb_rxbbuf_size_adr(buffer) (0x00005710 + (buffer) * 0x10) 607 /* bitmask for bitfield rx{b}_buf_size[8:0] */ 608 #define rpb_rxbbuf_size_msk 0x000001ff 609 /* inverted bitmask for bitfield rx{b}_buf_size[8:0] */ 610 #define rpb_rxbbuf_size_mskn 0xfffffe00 611 /* lower bit position of bitfield rx{b}_buf_size[8:0] */ 612 #define rpb_rxbbuf_size_shift 0 613 /* width of bitfield rx{b}_buf_size[8:0] */ 614 #define rpb_rxbbuf_size_width 9 615 /* default value of bitfield rx{b}_buf_size[8:0] */ 616 #define rpb_rxbbuf_size_default 0x0 617 618 /* rx rx{b}_xoff_en bitfield definitions 619 * preprocessor definitions for the bitfield "rx{b}_xoff_en". 620 * parameter: buffer {b} | stride size 0x10 | range [0, 7] 621 * port="pif_rpb_rx_xoff_en_i[0]" 622 */ 623 624 /* register address for bitfield rx{b}_xoff_en */ 625 #define rpb_rxbxoff_en_adr(buffer) (0x00005714 + (buffer) * 0x10) 626 /* bitmask for bitfield rx{b}_xoff_en */ 627 #define rpb_rxbxoff_en_msk 0x80000000 628 /* inverted bitmask for bitfield rx{b}_xoff_en */ 629 #define rpb_rxbxoff_en_mskn 0x7fffffff 630 /* lower bit position of bitfield rx{b}_xoff_en */ 631 #define rpb_rxbxoff_en_shift 31 632 /* width of bitfield rx{b}_xoff_en */ 633 #define rpb_rxbxoff_en_width 1 634 /* default value of bitfield rx{b}_xoff_en */ 635 #define rpb_rxbxoff_en_default 0x0 636 637 /* rx l2_bc_thresh[f:0] bitfield definitions 638 * preprocessor definitions for the bitfield "l2_bc_thresh[f:0]". 639 * port="pif_rpf_l2_bc_thresh_i[15:0]" 640 */ 641 642 /* register address for bitfield l2_bc_thresh[f:0] */ 643 #define rpfl2bc_thresh_adr 0x00005100 644 /* bitmask for bitfield l2_bc_thresh[f:0] */ 645 #define rpfl2bc_thresh_msk 0xffff0000 646 /* inverted bitmask for bitfield l2_bc_thresh[f:0] */ 647 #define rpfl2bc_thresh_mskn 0x0000ffff 648 /* lower bit position of bitfield l2_bc_thresh[f:0] */ 649 #define rpfl2bc_thresh_shift 16 650 /* width of bitfield l2_bc_thresh[f:0] */ 651 #define rpfl2bc_thresh_width 16 652 /* default value of bitfield l2_bc_thresh[f:0] */ 653 #define rpfl2bc_thresh_default 0x0 654 655 /* rx l2_bc_en bitfield definitions 656 * preprocessor definitions for the bitfield "l2_bc_en". 657 * port="pif_rpf_l2_bc_en_i" 658 */ 659 660 /* register address for bitfield l2_bc_en */ 661 #define rpfl2bc_en_adr 0x00005100 662 /* bitmask for bitfield l2_bc_en */ 663 #define rpfl2bc_en_msk 0x00000001 664 /* inverted bitmask for bitfield l2_bc_en */ 665 #define rpfl2bc_en_mskn 0xfffffffe 666 /* lower bit position of bitfield l2_bc_en */ 667 #define rpfl2bc_en_shift 0 668 /* width of bitfield l2_bc_en */ 669 #define rpfl2bc_en_width 1 670 /* default value of bitfield l2_bc_en */ 671 #define rpfl2bc_en_default 0x0 672 673 /* rx l2_bc_act[2:0] bitfield definitions 674 * preprocessor definitions for the bitfield "l2_bc_act[2:0]". 675 * port="pif_rpf_l2_bc_act_i[2:0]" 676 */ 677 678 /* register address for bitfield l2_bc_act[2:0] */ 679 #define rpfl2bc_act_adr 0x00005100 680 /* bitmask for bitfield l2_bc_act[2:0] */ 681 #define rpfl2bc_act_msk 0x00007000 682 /* inverted bitmask for bitfield l2_bc_act[2:0] */ 683 #define rpfl2bc_act_mskn 0xffff8fff 684 /* lower bit position of bitfield l2_bc_act[2:0] */ 685 #define rpfl2bc_act_shift 12 686 /* width of bitfield l2_bc_act[2:0] */ 687 #define rpfl2bc_act_width 3 688 /* default value of bitfield l2_bc_act[2:0] */ 689 #define rpfl2bc_act_default 0x0 690 691 /* rx l2_mc_en{f} bitfield definitions 692 * preprocessor definitions for the bitfield "l2_mc_en{f}". 693 * parameter: filter {f} | stride size 0x4 | range [0, 7] 694 * port="pif_rpf_l2_mc_en_i[0]" 695 */ 696 697 /* register address for bitfield l2_mc_en{f} */ 698 #define rpfl2mc_enf_adr(filter) (0x00005250 + (filter) * 0x4) 699 /* bitmask for bitfield l2_mc_en{f} */ 700 #define rpfl2mc_enf_msk 0x80000000 701 /* inverted bitmask for bitfield l2_mc_en{f} */ 702 #define rpfl2mc_enf_mskn 0x7fffffff 703 /* lower bit position of bitfield l2_mc_en{f} */ 704 #define rpfl2mc_enf_shift 31 705 /* width of bitfield l2_mc_en{f} */ 706 #define rpfl2mc_enf_width 1 707 /* default value of bitfield l2_mc_en{f} */ 708 #define rpfl2mc_enf_default 0x0 709 710 /* rx l2_promis_mode bitfield definitions 711 * preprocessor definitions for the bitfield "l2_promis_mode". 712 * port="pif_rpf_l2_promis_mode_i" 713 */ 714 715 /* register address for bitfield l2_promis_mode */ 716 #define rpfl2promis_mode_adr 0x00005100 717 /* bitmask for bitfield l2_promis_mode */ 718 #define rpfl2promis_mode_msk 0x00000008 719 /* inverted bitmask for bitfield l2_promis_mode */ 720 #define rpfl2promis_mode_mskn 0xfffffff7 721 /* lower bit position of bitfield l2_promis_mode */ 722 #define rpfl2promis_mode_shift 3 723 /* width of bitfield l2_promis_mode */ 724 #define rpfl2promis_mode_width 1 725 /* default value of bitfield l2_promis_mode */ 726 #define rpfl2promis_mode_default 0x0 727 728 /* rx l2_uc_act{f}[2:0] bitfield definitions 729 * preprocessor definitions for the bitfield "l2_uc_act{f}[2:0]". 730 * parameter: filter {f} | stride size 0x8 | range [0, 37] 731 * port="pif_rpf_l2_uc_act0_i[2:0]" 732 */ 733 734 /* register address for bitfield l2_uc_act{f}[2:0] */ 735 #define rpfl2uc_actf_adr(filter) (0x00005114 + (filter) * 0x8) 736 /* bitmask for bitfield l2_uc_act{f}[2:0] */ 737 #define rpfl2uc_actf_msk 0x00070000 738 /* inverted bitmask for bitfield l2_uc_act{f}[2:0] */ 739 #define rpfl2uc_actf_mskn 0xfff8ffff 740 /* lower bit position of bitfield l2_uc_act{f}[2:0] */ 741 #define rpfl2uc_actf_shift 16 742 /* width of bitfield l2_uc_act{f}[2:0] */ 743 #define rpfl2uc_actf_width 3 744 /* default value of bitfield l2_uc_act{f}[2:0] */ 745 #define rpfl2uc_actf_default 0x0 746 747 /* rx l2_uc_en{f} bitfield definitions 748 * preprocessor definitions for the bitfield "l2_uc_en{f}". 749 * parameter: filter {f} | stride size 0x8 | range [0, 37] 750 * port="pif_rpf_l2_uc_en_i[0]" 751 */ 752 753 /* register address for bitfield l2_uc_en{f} */ 754 #define rpfl2uc_enf_adr(filter) (0x00005114 + (filter) * 0x8) 755 /* bitmask for bitfield l2_uc_en{f} */ 756 #define rpfl2uc_enf_msk 0x80000000 757 /* inverted bitmask for bitfield l2_uc_en{f} */ 758 #define rpfl2uc_enf_mskn 0x7fffffff 759 /* lower bit position of bitfield l2_uc_en{f} */ 760 #define rpfl2uc_enf_shift 31 761 /* width of bitfield l2_uc_en{f} */ 762 #define rpfl2uc_enf_width 1 763 /* default value of bitfield l2_uc_en{f} */ 764 #define rpfl2uc_enf_default 0x0 765 766 /* register address for bitfield l2_uc_da{f}_lsw[1f:0] */ 767 #define rpfl2uc_daflsw_adr(filter) (0x00005110 + (filter) * 0x8) 768 /* register address for bitfield l2_uc_da{f}_msw[f:0] */ 769 #define rpfl2uc_dafmsw_adr(filter) (0x00005114 + (filter) * 0x8) 770 /* bitmask for bitfield l2_uc_da{f}_msw[f:0] */ 771 #define rpfl2uc_dafmsw_msk 0x0000ffff 772 /* lower bit position of bitfield l2_uc_da{f}_msw[f:0] */ 773 #define rpfl2uc_dafmsw_shift 0 774 775 /* rx l2_mc_accept_all bitfield definitions 776 * Preprocessor definitions for the bitfield "l2_mc_accept_all". 777 * PORT="pif_rpf_l2_mc_all_accept_i" 778 */ 779 780 /* Register address for bitfield l2_mc_accept_all */ 781 #define rpfl2mc_accept_all_adr 0x00005270 782 /* Bitmask for bitfield l2_mc_accept_all */ 783 #define rpfl2mc_accept_all_msk 0x00004000 784 /* Inverted bitmask for bitfield l2_mc_accept_all */ 785 #define rpfl2mc_accept_all_mskn 0xFFFFBFFF 786 /* Lower bit position of bitfield l2_mc_accept_all */ 787 #define rpfl2mc_accept_all_shift 14 788 /* Width of bitfield l2_mc_accept_all */ 789 #define rpfl2mc_accept_all_width 1 790 /* Default value of bitfield l2_mc_accept_all */ 791 #define rpfl2mc_accept_all_default 0x0 792 793 /* width of bitfield rx_tc_up{t}[2:0] */ 794 #define rpf_rpb_rx_tc_upt_width 3 795 /* default value of bitfield rx_tc_up{t}[2:0] */ 796 #define rpf_rpb_rx_tc_upt_default 0x0 797 798 /* rx rss_key_addr[4:0] bitfield definitions 799 * preprocessor definitions for the bitfield "rss_key_addr[4:0]". 800 * port="pif_rpf_rss_key_addr_i[4:0]" 801 */ 802 803 /* register address for bitfield rss_key_addr[4:0] */ 804 #define rpf_rss_key_addr_adr 0x000054d0 805 /* bitmask for bitfield rss_key_addr[4:0] */ 806 #define rpf_rss_key_addr_msk 0x0000001f 807 /* inverted bitmask for bitfield rss_key_addr[4:0] */ 808 #define rpf_rss_key_addr_mskn 0xffffffe0 809 /* lower bit position of bitfield rss_key_addr[4:0] */ 810 #define rpf_rss_key_addr_shift 0 811 /* width of bitfield rss_key_addr[4:0] */ 812 #define rpf_rss_key_addr_width 5 813 /* default value of bitfield rss_key_addr[4:0] */ 814 #define rpf_rss_key_addr_default 0x0 815 816 /* rx rss_key_wr_data[1f:0] bitfield definitions 817 * preprocessor definitions for the bitfield "rss_key_wr_data[1f:0]". 818 * port="pif_rpf_rss_key_wr_data_i[31:0]" 819 */ 820 821 /* register address for bitfield rss_key_wr_data[1f:0] */ 822 #define rpf_rss_key_wr_data_adr 0x000054d4 823 /* bitmask for bitfield rss_key_wr_data[1f:0] */ 824 #define rpf_rss_key_wr_data_msk 0xffffffff 825 /* inverted bitmask for bitfield rss_key_wr_data[1f:0] */ 826 #define rpf_rss_key_wr_data_mskn 0x00000000 827 /* lower bit position of bitfield rss_key_wr_data[1f:0] */ 828 #define rpf_rss_key_wr_data_shift 0 829 /* width of bitfield rss_key_wr_data[1f:0] */ 830 #define rpf_rss_key_wr_data_width 32 831 /* default value of bitfield rss_key_wr_data[1f:0] */ 832 #define rpf_rss_key_wr_data_default 0x0 833 834 /* rx rss_key_wr_en_i bitfield definitions 835 * preprocessor definitions for the bitfield "rss_key_wr_en_i". 836 * port="pif_rpf_rss_key_wr_en_i" 837 */ 838 839 /* register address for bitfield rss_key_wr_en_i */ 840 #define rpf_rss_key_wr_eni_adr 0x000054d0 841 /* bitmask for bitfield rss_key_wr_en_i */ 842 #define rpf_rss_key_wr_eni_msk 0x00000020 843 /* inverted bitmask for bitfield rss_key_wr_en_i */ 844 #define rpf_rss_key_wr_eni_mskn 0xffffffdf 845 /* lower bit position of bitfield rss_key_wr_en_i */ 846 #define rpf_rss_key_wr_eni_shift 5 847 /* width of bitfield rss_key_wr_en_i */ 848 #define rpf_rss_key_wr_eni_width 1 849 /* default value of bitfield rss_key_wr_en_i */ 850 #define rpf_rss_key_wr_eni_default 0x0 851 852 /* rx rss_redir_addr[3:0] bitfield definitions 853 * preprocessor definitions for the bitfield "rss_redir_addr[3:0]". 854 * port="pif_rpf_rss_redir_addr_i[3:0]" 855 */ 856 857 /* register address for bitfield rss_redir_addr[3:0] */ 858 #define rpf_rss_redir_addr_adr 0x000054e0 859 /* bitmask for bitfield rss_redir_addr[3:0] */ 860 #define rpf_rss_redir_addr_msk 0x0000000f 861 /* inverted bitmask for bitfield rss_redir_addr[3:0] */ 862 #define rpf_rss_redir_addr_mskn 0xfffffff0 863 /* lower bit position of bitfield rss_redir_addr[3:0] */ 864 #define rpf_rss_redir_addr_shift 0 865 /* width of bitfield rss_redir_addr[3:0] */ 866 #define rpf_rss_redir_addr_width 4 867 /* default value of bitfield rss_redir_addr[3:0] */ 868 #define rpf_rss_redir_addr_default 0x0 869 870 /* rx rss_redir_wr_data[f:0] bitfield definitions 871 * preprocessor definitions for the bitfield "rss_redir_wr_data[f:0]". 872 * port="pif_rpf_rss_redir_wr_data_i[15:0]" 873 */ 874 875 /* register address for bitfield rss_redir_wr_data[f:0] */ 876 #define rpf_rss_redir_wr_data_adr 0x000054e4 877 /* bitmask for bitfield rss_redir_wr_data[f:0] */ 878 #define rpf_rss_redir_wr_data_msk 0x0000ffff 879 /* inverted bitmask for bitfield rss_redir_wr_data[f:0] */ 880 #define rpf_rss_redir_wr_data_mskn 0xffff0000 881 /* lower bit position of bitfield rss_redir_wr_data[f:0] */ 882 #define rpf_rss_redir_wr_data_shift 0 883 /* width of bitfield rss_redir_wr_data[f:0] */ 884 #define rpf_rss_redir_wr_data_width 16 885 /* default value of bitfield rss_redir_wr_data[f:0] */ 886 #define rpf_rss_redir_wr_data_default 0x0 887 888 /* rx rss_redir_wr_en_i bitfield definitions 889 * preprocessor definitions for the bitfield "rss_redir_wr_en_i". 890 * port="pif_rpf_rss_redir_wr_en_i" 891 */ 892 893 /* register address for bitfield rss_redir_wr_en_i */ 894 #define rpf_rss_redir_wr_eni_adr 0x000054e0 895 /* bitmask for bitfield rss_redir_wr_en_i */ 896 #define rpf_rss_redir_wr_eni_msk 0x00000010 897 /* inverted bitmask for bitfield rss_redir_wr_en_i */ 898 #define rpf_rss_redir_wr_eni_mskn 0xffffffef 899 /* lower bit position of bitfield rss_redir_wr_en_i */ 900 #define rpf_rss_redir_wr_eni_shift 4 901 /* width of bitfield rss_redir_wr_en_i */ 902 #define rpf_rss_redir_wr_eni_width 1 903 /* default value of bitfield rss_redir_wr_en_i */ 904 #define rpf_rss_redir_wr_eni_default 0x0 905 906 /* rx tpo_rpf_sys_loopback bitfield definitions 907 * preprocessor definitions for the bitfield "tpo_rpf_sys_loopback". 908 * port="pif_rpf_tpo_pkt_sys_lbk_i" 909 */ 910 911 /* register address for bitfield tpo_rpf_sys_loopback */ 912 #define rpf_tpo_rpf_sys_lbk_adr 0x00005000 913 /* bitmask for bitfield tpo_rpf_sys_loopback */ 914 #define rpf_tpo_rpf_sys_lbk_msk 0x00000100 915 /* inverted bitmask for bitfield tpo_rpf_sys_loopback */ 916 #define rpf_tpo_rpf_sys_lbk_mskn 0xfffffeff 917 /* lower bit position of bitfield tpo_rpf_sys_loopback */ 918 #define rpf_tpo_rpf_sys_lbk_shift 8 919 /* width of bitfield tpo_rpf_sys_loopback */ 920 #define rpf_tpo_rpf_sys_lbk_width 1 921 /* default value of bitfield tpo_rpf_sys_loopback */ 922 #define rpf_tpo_rpf_sys_lbk_default 0x0 923 924 /* rx vl_inner_tpid[f:0] bitfield definitions 925 * preprocessor definitions for the bitfield "vl_inner_tpid[f:0]". 926 * port="pif_rpf_vl_inner_tpid_i[15:0]" 927 */ 928 929 /* register address for bitfield vl_inner_tpid[f:0] */ 930 #define rpf_vl_inner_tpid_adr 0x00005284 931 /* bitmask for bitfield vl_inner_tpid[f:0] */ 932 #define rpf_vl_inner_tpid_msk 0x0000ffff 933 /* inverted bitmask for bitfield vl_inner_tpid[f:0] */ 934 #define rpf_vl_inner_tpid_mskn 0xffff0000 935 /* lower bit position of bitfield vl_inner_tpid[f:0] */ 936 #define rpf_vl_inner_tpid_shift 0 937 /* width of bitfield vl_inner_tpid[f:0] */ 938 #define rpf_vl_inner_tpid_width 16 939 /* default value of bitfield vl_inner_tpid[f:0] */ 940 #define rpf_vl_inner_tpid_default 0x8100 941 942 /* rx vl_outer_tpid[f:0] bitfield definitions 943 * preprocessor definitions for the bitfield "vl_outer_tpid[f:0]". 944 * port="pif_rpf_vl_outer_tpid_i[15:0]" 945 */ 946 947 /* register address for bitfield vl_outer_tpid[f:0] */ 948 #define rpf_vl_outer_tpid_adr 0x00005284 949 /* bitmask for bitfield vl_outer_tpid[f:0] */ 950 #define rpf_vl_outer_tpid_msk 0xffff0000 951 /* inverted bitmask for bitfield vl_outer_tpid[f:0] */ 952 #define rpf_vl_outer_tpid_mskn 0x0000ffff 953 /* lower bit position of bitfield vl_outer_tpid[f:0] */ 954 #define rpf_vl_outer_tpid_shift 16 955 /* width of bitfield vl_outer_tpid[f:0] */ 956 #define rpf_vl_outer_tpid_width 16 957 /* default value of bitfield vl_outer_tpid[f:0] */ 958 #define rpf_vl_outer_tpid_default 0x88a8 959 960 /* rx vl_promis_mode bitfield definitions 961 * preprocessor definitions for the bitfield "vl_promis_mode". 962 * port="pif_rpf_vl_promis_mode_i" 963 */ 964 965 /* register address for bitfield vl_promis_mode */ 966 #define rpf_vl_promis_mode_adr 0x00005280 967 /* bitmask for bitfield vl_promis_mode */ 968 #define rpf_vl_promis_mode_msk 0x00000002 969 /* inverted bitmask for bitfield vl_promis_mode */ 970 #define rpf_vl_promis_mode_mskn 0xfffffffd 971 /* lower bit position of bitfield vl_promis_mode */ 972 #define rpf_vl_promis_mode_shift 1 973 /* width of bitfield vl_promis_mode */ 974 #define rpf_vl_promis_mode_width 1 975 /* default value of bitfield vl_promis_mode */ 976 #define rpf_vl_promis_mode_default 0x0 977 978 /* RX vl_accept_untagged_mode Bitfield Definitions 979 * Preprocessor definitions for the bitfield "vl_accept_untagged_mode". 980 * PORT="pif_rpf_vl_accept_untagged_i" 981 */ 982 983 /* Register address for bitfield vl_accept_untagged_mode */ 984 #define rpf_vl_accept_untagged_mode_adr 0x00005280 985 /* Bitmask for bitfield vl_accept_untagged_mode */ 986 #define rpf_vl_accept_untagged_mode_msk 0x00000004 987 /* Inverted bitmask for bitfield vl_accept_untagged_mode */ 988 #define rpf_vl_accept_untagged_mode_mskn 0xFFFFFFFB 989 /* Lower bit position of bitfield vl_accept_untagged_mode */ 990 #define rpf_vl_accept_untagged_mode_shift 2 991 /* Width of bitfield vl_accept_untagged_mode */ 992 #define rpf_vl_accept_untagged_mode_width 1 993 /* Default value of bitfield vl_accept_untagged_mode */ 994 #define rpf_vl_accept_untagged_mode_default 0x0 995 996 /* rX vl_untagged_act[2:0] Bitfield Definitions 997 * Preprocessor definitions for the bitfield "vl_untagged_act[2:0]". 998 * PORT="pif_rpf_vl_untagged_act_i[2:0]" 999 */ 1000 1001 /* Register address for bitfield vl_untagged_act[2:0] */ 1002 #define rpf_vl_untagged_act_adr 0x00005280 1003 /* Bitmask for bitfield vl_untagged_act[2:0] */ 1004 #define rpf_vl_untagged_act_msk 0x00000038 1005 /* Inverted bitmask for bitfield vl_untagged_act[2:0] */ 1006 #define rpf_vl_untagged_act_mskn 0xFFFFFFC7 1007 /* Lower bit position of bitfield vl_untagged_act[2:0] */ 1008 #define rpf_vl_untagged_act_shift 3 1009 /* Width of bitfield vl_untagged_act[2:0] */ 1010 #define rpf_vl_untagged_act_width 3 1011 /* Default value of bitfield vl_untagged_act[2:0] */ 1012 #define rpf_vl_untagged_act_default 0x0 1013 1014 /* RX vl_en{F} Bitfield Definitions 1015 * Preprocessor definitions for the bitfield "vl_en{F}". 1016 * Parameter: filter {F} | stride size 0x4 | range [0, 15] 1017 * PORT="pif_rpf_vl_en_i[0]" 1018 */ 1019 1020 /* Register address for bitfield vl_en{F} */ 1021 #define rpf_vl_en_f_adr(filter) (0x00005290 + (filter) * 0x4) 1022 /* Bitmask for bitfield vl_en{F} */ 1023 #define rpf_vl_en_f_msk 0x80000000 1024 /* Inverted bitmask for bitfield vl_en{F} */ 1025 #define rpf_vl_en_f_mskn 0x7FFFFFFF 1026 /* Lower bit position of bitfield vl_en{F} */ 1027 #define rpf_vl_en_f_shift 31 1028 /* Width of bitfield vl_en{F} */ 1029 #define rpf_vl_en_f_width 1 1030 /* Default value of bitfield vl_en{F} */ 1031 #define rpf_vl_en_f_default 0x0 1032 1033 /* RX vl_act{F}[2:0] Bitfield Definitions 1034 * Preprocessor definitions for the bitfield "vl_act{F}[2:0]". 1035 * Parameter: filter {F} | stride size 0x4 | range [0, 15] 1036 * PORT="pif_rpf_vl_act0_i[2:0]" 1037 */ 1038 1039 /* Register address for bitfield vl_act{F}[2:0] */ 1040 #define rpf_vl_act_f_adr(filter) (0x00005290 + (filter) * 0x4) 1041 /* Bitmask for bitfield vl_act{F}[2:0] */ 1042 #define rpf_vl_act_f_msk 0x00070000 1043 /* Inverted bitmask for bitfield vl_act{F}[2:0] */ 1044 #define rpf_vl_act_f_mskn 0xFFF8FFFF 1045 /* Lower bit position of bitfield vl_act{F}[2:0] */ 1046 #define rpf_vl_act_f_shift 16 1047 /* Width of bitfield vl_act{F}[2:0] */ 1048 #define rpf_vl_act_f_width 3 1049 /* Default value of bitfield vl_act{F}[2:0] */ 1050 #define rpf_vl_act_f_default 0x0 1051 1052 /* RX vl_id{F}[B:0] Bitfield Definitions 1053 * Preprocessor definitions for the bitfield "vl_id{F}[B:0]". 1054 * Parameter: filter {F} | stride size 0x4 | range [0, 15] 1055 * PORT="pif_rpf_vl_id0_i[11:0]" 1056 */ 1057 1058 /* Register address for bitfield vl_id{F}[B:0] */ 1059 #define rpf_vl_id_f_adr(filter) (0x00005290 + (filter) * 0x4) 1060 /* Bitmask for bitfield vl_id{F}[B:0] */ 1061 #define rpf_vl_id_f_msk 0x00000FFF 1062 /* Inverted bitmask for bitfield vl_id{F}[B:0] */ 1063 #define rpf_vl_id_f_mskn 0xFFFFF000 1064 /* Lower bit position of bitfield vl_id{F}[B:0] */ 1065 #define rpf_vl_id_f_shift 0 1066 /* Width of bitfield vl_id{F}[B:0] */ 1067 #define rpf_vl_id_f_width 12 1068 /* Default value of bitfield vl_id{F}[B:0] */ 1069 #define rpf_vl_id_f_default 0x0 1070 1071 /* RX et_en{F} Bitfield Definitions 1072 * Preprocessor definitions for the bitfield "et_en{F}". 1073 * Parameter: filter {F} | stride size 0x4 | range [0, 15] 1074 * PORT="pif_rpf_et_en_i[0]" 1075 */ 1076 1077 /* Register address for bitfield et_en{F} */ 1078 #define rpf_et_en_f_adr(filter) (0x00005300 + (filter) * 0x4) 1079 /* Bitmask for bitfield et_en{F} */ 1080 #define rpf_et_en_f_msk 0x80000000 1081 /* Inverted bitmask for bitfield et_en{F} */ 1082 #define rpf_et_en_f_mskn 0x7FFFFFFF 1083 /* Lower bit position of bitfield et_en{F} */ 1084 #define rpf_et_en_f_shift 31 1085 /* Width of bitfield et_en{F} */ 1086 #define rpf_et_en_f_width 1 1087 /* Default value of bitfield et_en{F} */ 1088 #define rpf_et_en_f_default 0x0 1089 1090 /* rx et_en{f} bitfield definitions 1091 * preprocessor definitions for the bitfield "et_en{f}". 1092 * parameter: filter {f} | stride size 0x4 | range [0, 15] 1093 * port="pif_rpf_et_en_i[0]" 1094 */ 1095 1096 /* register address for bitfield et_en{f} */ 1097 #define rpf_et_enf_adr(filter) (0x00005300 + (filter) * 0x4) 1098 /* bitmask for bitfield et_en{f} */ 1099 #define rpf_et_enf_msk 0x80000000 1100 /* inverted bitmask for bitfield et_en{f} */ 1101 #define rpf_et_enf_mskn 0x7fffffff 1102 /* lower bit position of bitfield et_en{f} */ 1103 #define rpf_et_enf_shift 31 1104 /* width of bitfield et_en{f} */ 1105 #define rpf_et_enf_width 1 1106 /* default value of bitfield et_en{f} */ 1107 #define rpf_et_enf_default 0x0 1108 1109 /* rx et_up{f}_en bitfield definitions 1110 * preprocessor definitions for the bitfield "et_up{f}_en". 1111 * parameter: filter {f} | stride size 0x4 | range [0, 15] 1112 * port="pif_rpf_et_up_en_i[0]" 1113 */ 1114 1115 /* register address for bitfield et_up{f}_en */ 1116 #define rpf_et_upfen_adr(filter) (0x00005300 + (filter) * 0x4) 1117 /* bitmask for bitfield et_up{f}_en */ 1118 #define rpf_et_upfen_msk 0x40000000 1119 /* inverted bitmask for bitfield et_up{f}_en */ 1120 #define rpf_et_upfen_mskn 0xbfffffff 1121 /* lower bit position of bitfield et_up{f}_en */ 1122 #define rpf_et_upfen_shift 30 1123 /* width of bitfield et_up{f}_en */ 1124 #define rpf_et_upfen_width 1 1125 /* default value of bitfield et_up{f}_en */ 1126 #define rpf_et_upfen_default 0x0 1127 1128 /* rx et_rxq{f}_en bitfield definitions 1129 * preprocessor definitions for the bitfield "et_rxq{f}_en". 1130 * parameter: filter {f} | stride size 0x4 | range [0, 15] 1131 * port="pif_rpf_et_rxq_en_i[0]" 1132 */ 1133 1134 /* register address for bitfield et_rxq{f}_en */ 1135 #define rpf_et_rxqfen_adr(filter) (0x00005300 + (filter) * 0x4) 1136 /* bitmask for bitfield et_rxq{f}_en */ 1137 #define rpf_et_rxqfen_msk 0x20000000 1138 /* inverted bitmask for bitfield et_rxq{f}_en */ 1139 #define rpf_et_rxqfen_mskn 0xdfffffff 1140 /* lower bit position of bitfield et_rxq{f}_en */ 1141 #define rpf_et_rxqfen_shift 29 1142 /* width of bitfield et_rxq{f}_en */ 1143 #define rpf_et_rxqfen_width 1 1144 /* default value of bitfield et_rxq{f}_en */ 1145 #define rpf_et_rxqfen_default 0x0 1146 1147 /* rx et_up{f}[2:0] bitfield definitions 1148 * preprocessor definitions for the bitfield "et_up{f}[2:0]". 1149 * parameter: filter {f} | stride size 0x4 | range [0, 15] 1150 * port="pif_rpf_et_up0_i[2:0]" 1151 */ 1152 1153 /* register address for bitfield et_up{f}[2:0] */ 1154 #define rpf_et_upf_adr(filter) (0x00005300 + (filter) * 0x4) 1155 /* bitmask for bitfield et_up{f}[2:0] */ 1156 #define rpf_et_upf_msk 0x1c000000 1157 /* inverted bitmask for bitfield et_up{f}[2:0] */ 1158 #define rpf_et_upf_mskn 0xe3ffffff 1159 /* lower bit position of bitfield et_up{f}[2:0] */ 1160 #define rpf_et_upf_shift 26 1161 /* width of bitfield et_up{f}[2:0] */ 1162 #define rpf_et_upf_width 3 1163 /* default value of bitfield et_up{f}[2:0] */ 1164 #define rpf_et_upf_default 0x0 1165 1166 /* rx et_rxq{f}[4:0] bitfield definitions 1167 * preprocessor definitions for the bitfield "et_rxq{f}[4:0]". 1168 * parameter: filter {f} | stride size 0x4 | range [0, 15] 1169 * port="pif_rpf_et_rxq0_i[4:0]" 1170 */ 1171 1172 /* register address for bitfield et_rxq{f}[4:0] */ 1173 #define rpf_et_rxqf_adr(filter) (0x00005300 + (filter) * 0x4) 1174 /* bitmask for bitfield et_rxq{f}[4:0] */ 1175 #define rpf_et_rxqf_msk 0x01f00000 1176 /* inverted bitmask for bitfield et_rxq{f}[4:0] */ 1177 #define rpf_et_rxqf_mskn 0xfe0fffff 1178 /* lower bit position of bitfield et_rxq{f}[4:0] */ 1179 #define rpf_et_rxqf_shift 20 1180 /* width of bitfield et_rxq{f}[4:0] */ 1181 #define rpf_et_rxqf_width 5 1182 /* default value of bitfield et_rxq{f}[4:0] */ 1183 #define rpf_et_rxqf_default 0x0 1184 1185 /* rx et_mng_rxq{f} bitfield definitions 1186 * preprocessor definitions for the bitfield "et_mng_rxq{f}". 1187 * parameter: filter {f} | stride size 0x4 | range [0, 15] 1188 * port="pif_rpf_et_mng_rxq_i[0]" 1189 */ 1190 1191 /* register address for bitfield et_mng_rxq{f} */ 1192 #define rpf_et_mng_rxqf_adr(filter) (0x00005300 + (filter) * 0x4) 1193 /* bitmask for bitfield et_mng_rxq{f} */ 1194 #define rpf_et_mng_rxqf_msk 0x00080000 1195 /* inverted bitmask for bitfield et_mng_rxq{f} */ 1196 #define rpf_et_mng_rxqf_mskn 0xfff7ffff 1197 /* lower bit position of bitfield et_mng_rxq{f} */ 1198 #define rpf_et_mng_rxqf_shift 19 1199 /* width of bitfield et_mng_rxq{f} */ 1200 #define rpf_et_mng_rxqf_width 1 1201 /* default value of bitfield et_mng_rxq{f} */ 1202 #define rpf_et_mng_rxqf_default 0x0 1203 1204 /* rx et_act{f}[2:0] bitfield definitions 1205 * preprocessor definitions for the bitfield "et_act{f}[2:0]". 1206 * parameter: filter {f} | stride size 0x4 | range [0, 15] 1207 * port="pif_rpf_et_act0_i[2:0]" 1208 */ 1209 1210 /* register address for bitfield et_act{f}[2:0] */ 1211 #define rpf_et_actf_adr(filter) (0x00005300 + (filter) * 0x4) 1212 /* bitmask for bitfield et_act{f}[2:0] */ 1213 #define rpf_et_actf_msk 0x00070000 1214 /* inverted bitmask for bitfield et_act{f}[2:0] */ 1215 #define rpf_et_actf_mskn 0xfff8ffff 1216 /* lower bit position of bitfield et_act{f}[2:0] */ 1217 #define rpf_et_actf_shift 16 1218 /* width of bitfield et_act{f}[2:0] */ 1219 #define rpf_et_actf_width 3 1220 /* default value of bitfield et_act{f}[2:0] */ 1221 #define rpf_et_actf_default 0x0 1222 1223 /* rx et_val{f}[f:0] bitfield definitions 1224 * preprocessor definitions for the bitfield "et_val{f}[f:0]". 1225 * parameter: filter {f} | stride size 0x4 | range [0, 15] 1226 * port="pif_rpf_et_val0_i[15:0]" 1227 */ 1228 1229 /* register address for bitfield et_val{f}[f:0] */ 1230 #define rpf_et_valf_adr(filter) (0x00005300 + (filter) * 0x4) 1231 /* bitmask for bitfield et_val{f}[f:0] */ 1232 #define rpf_et_valf_msk 0x0000ffff 1233 /* inverted bitmask for bitfield et_val{f}[f:0] */ 1234 #define rpf_et_valf_mskn 0xffff0000 1235 /* lower bit position of bitfield et_val{f}[f:0] */ 1236 #define rpf_et_valf_shift 0 1237 /* width of bitfield et_val{f}[f:0] */ 1238 #define rpf_et_valf_width 16 1239 /* default value of bitfield et_val{f}[f:0] */ 1240 #define rpf_et_valf_default 0x0 1241 1242 /* rx ipv4_chk_en bitfield definitions 1243 * preprocessor definitions for the bitfield "ipv4_chk_en". 1244 * port="pif_rpo_ipv4_chk_en_i" 1245 */ 1246 1247 /* register address for bitfield ipv4_chk_en */ 1248 #define rpo_ipv4chk_en_adr 0x00005580 1249 /* bitmask for bitfield ipv4_chk_en */ 1250 #define rpo_ipv4chk_en_msk 0x00000002 1251 /* inverted bitmask for bitfield ipv4_chk_en */ 1252 #define rpo_ipv4chk_en_mskn 0xfffffffd 1253 /* lower bit position of bitfield ipv4_chk_en */ 1254 #define rpo_ipv4chk_en_shift 1 1255 /* width of bitfield ipv4_chk_en */ 1256 #define rpo_ipv4chk_en_width 1 1257 /* default value of bitfield ipv4_chk_en */ 1258 #define rpo_ipv4chk_en_default 0x0 1259 1260 /* rx desc{d}_vl_strip bitfield definitions 1261 * preprocessor definitions for the bitfield "desc{d}_vl_strip". 1262 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 1263 * port="pif_rpo_desc_vl_strip_i[0]" 1264 */ 1265 1266 /* register address for bitfield desc{d}_vl_strip */ 1267 #define rpo_descdvl_strip_adr(descriptor) (0x00005b08 + (descriptor) * 0x20) 1268 /* bitmask for bitfield desc{d}_vl_strip */ 1269 #define rpo_descdvl_strip_msk 0x20000000 1270 /* inverted bitmask for bitfield desc{d}_vl_strip */ 1271 #define rpo_descdvl_strip_mskn 0xdfffffff 1272 /* lower bit position of bitfield desc{d}_vl_strip */ 1273 #define rpo_descdvl_strip_shift 29 1274 /* width of bitfield desc{d}_vl_strip */ 1275 #define rpo_descdvl_strip_width 1 1276 /* default value of bitfield desc{d}_vl_strip */ 1277 #define rpo_descdvl_strip_default 0x0 1278 1279 /* rx l4_chk_en bitfield definitions 1280 * preprocessor definitions for the bitfield "l4_chk_en". 1281 * port="pif_rpo_l4_chk_en_i" 1282 */ 1283 1284 /* register address for bitfield l4_chk_en */ 1285 #define rpol4chk_en_adr 0x00005580 1286 /* bitmask for bitfield l4_chk_en */ 1287 #define rpol4chk_en_msk 0x00000001 1288 /* inverted bitmask for bitfield l4_chk_en */ 1289 #define rpol4chk_en_mskn 0xfffffffe 1290 /* lower bit position of bitfield l4_chk_en */ 1291 #define rpol4chk_en_shift 0 1292 /* width of bitfield l4_chk_en */ 1293 #define rpol4chk_en_width 1 1294 /* default value of bitfield l4_chk_en */ 1295 #define rpol4chk_en_default 0x0 1296 1297 /* rx reg_res_dsbl bitfield definitions 1298 * preprocessor definitions for the bitfield "reg_res_dsbl". 1299 * port="pif_rx_reg_res_dsbl_i" 1300 */ 1301 1302 /* register address for bitfield reg_res_dsbl */ 1303 #define rx_reg_res_dsbl_adr 0x00005000 1304 /* bitmask for bitfield reg_res_dsbl */ 1305 #define rx_reg_res_dsbl_msk 0x20000000 1306 /* inverted bitmask for bitfield reg_res_dsbl */ 1307 #define rx_reg_res_dsbl_mskn 0xdfffffff 1308 /* lower bit position of bitfield reg_res_dsbl */ 1309 #define rx_reg_res_dsbl_shift 29 1310 /* width of bitfield reg_res_dsbl */ 1311 #define rx_reg_res_dsbl_width 1 1312 /* default value of bitfield reg_res_dsbl */ 1313 #define rx_reg_res_dsbl_default 0x1 1314 1315 /* tx dca{d}_cpuid[7:0] bitfield definitions 1316 * preprocessor definitions for the bitfield "dca{d}_cpuid[7:0]". 1317 * parameter: dca {d} | stride size 0x4 | range [0, 31] 1318 * port="pif_tdm_dca0_cpuid_i[7:0]" 1319 */ 1320 1321 /* register address for bitfield dca{d}_cpuid[7:0] */ 1322 #define tdm_dcadcpuid_adr(dca) (0x00008400 + (dca) * 0x4) 1323 /* bitmask for bitfield dca{d}_cpuid[7:0] */ 1324 #define tdm_dcadcpuid_msk 0x000000ff 1325 /* inverted bitmask for bitfield dca{d}_cpuid[7:0] */ 1326 #define tdm_dcadcpuid_mskn 0xffffff00 1327 /* lower bit position of bitfield dca{d}_cpuid[7:0] */ 1328 #define tdm_dcadcpuid_shift 0 1329 /* width of bitfield dca{d}_cpuid[7:0] */ 1330 #define tdm_dcadcpuid_width 8 1331 /* default value of bitfield dca{d}_cpuid[7:0] */ 1332 #define tdm_dcadcpuid_default 0x0 1333 1334 /* tx lso_en[1f:0] bitfield definitions 1335 * preprocessor definitions for the bitfield "lso_en[1f:0]". 1336 * port="pif_tdm_lso_en_i[31:0]" 1337 */ 1338 1339 /* register address for bitfield lso_en[1f:0] */ 1340 #define tdm_lso_en_adr 0x00007810 1341 /* bitmask for bitfield lso_en[1f:0] */ 1342 #define tdm_lso_en_msk 0xffffffff 1343 /* inverted bitmask for bitfield lso_en[1f:0] */ 1344 #define tdm_lso_en_mskn 0x00000000 1345 /* lower bit position of bitfield lso_en[1f:0] */ 1346 #define tdm_lso_en_shift 0 1347 /* width of bitfield lso_en[1f:0] */ 1348 #define tdm_lso_en_width 32 1349 /* default value of bitfield lso_en[1f:0] */ 1350 #define tdm_lso_en_default 0x0 1351 1352 /* tx dca_en bitfield definitions 1353 * preprocessor definitions for the bitfield "dca_en". 1354 * port="pif_tdm_dca_en_i" 1355 */ 1356 1357 /* register address for bitfield dca_en */ 1358 #define tdm_dca_en_adr 0x00008480 1359 /* bitmask for bitfield dca_en */ 1360 #define tdm_dca_en_msk 0x80000000 1361 /* inverted bitmask for bitfield dca_en */ 1362 #define tdm_dca_en_mskn 0x7fffffff 1363 /* lower bit position of bitfield dca_en */ 1364 #define tdm_dca_en_shift 31 1365 /* width of bitfield dca_en */ 1366 #define tdm_dca_en_width 1 1367 /* default value of bitfield dca_en */ 1368 #define tdm_dca_en_default 0x1 1369 1370 /* tx dca_mode[3:0] bitfield definitions 1371 * preprocessor definitions for the bitfield "dca_mode[3:0]". 1372 * port="pif_tdm_dca_mode_i[3:0]" 1373 */ 1374 1375 /* register address for bitfield dca_mode[3:0] */ 1376 #define tdm_dca_mode_adr 0x00008480 1377 /* bitmask for bitfield dca_mode[3:0] */ 1378 #define tdm_dca_mode_msk 0x0000000f 1379 /* inverted bitmask for bitfield dca_mode[3:0] */ 1380 #define tdm_dca_mode_mskn 0xfffffff0 1381 /* lower bit position of bitfield dca_mode[3:0] */ 1382 #define tdm_dca_mode_shift 0 1383 /* width of bitfield dca_mode[3:0] */ 1384 #define tdm_dca_mode_width 4 1385 /* default value of bitfield dca_mode[3:0] */ 1386 #define tdm_dca_mode_default 0x0 1387 1388 /* tx dca{d}_desc_en bitfield definitions 1389 * preprocessor definitions for the bitfield "dca{d}_desc_en". 1390 * parameter: dca {d} | stride size 0x4 | range [0, 31] 1391 * port="pif_tdm_dca_desc_en_i[0]" 1392 */ 1393 1394 /* register address for bitfield dca{d}_desc_en */ 1395 #define tdm_dcaddesc_en_adr(dca) (0x00008400 + (dca) * 0x4) 1396 /* bitmask for bitfield dca{d}_desc_en */ 1397 #define tdm_dcaddesc_en_msk 0x80000000 1398 /* inverted bitmask for bitfield dca{d}_desc_en */ 1399 #define tdm_dcaddesc_en_mskn 0x7fffffff 1400 /* lower bit position of bitfield dca{d}_desc_en */ 1401 #define tdm_dcaddesc_en_shift 31 1402 /* width of bitfield dca{d}_desc_en */ 1403 #define tdm_dcaddesc_en_width 1 1404 /* default value of bitfield dca{d}_desc_en */ 1405 #define tdm_dcaddesc_en_default 0x0 1406 1407 /* tx desc{d}_en bitfield definitions 1408 * preprocessor definitions for the bitfield "desc{d}_en". 1409 * parameter: descriptor {d} | stride size 0x40 | range [0, 31] 1410 * port="pif_tdm_desc_en_i[0]" 1411 */ 1412 1413 /* register address for bitfield desc{d}_en */ 1414 #define tdm_descden_adr(descriptor) (0x00007c08 + (descriptor) * 0x40) 1415 /* bitmask for bitfield desc{d}_en */ 1416 #define tdm_descden_msk 0x80000000 1417 /* inverted bitmask for bitfield desc{d}_en */ 1418 #define tdm_descden_mskn 0x7fffffff 1419 /* lower bit position of bitfield desc{d}_en */ 1420 #define tdm_descden_shift 31 1421 /* width of bitfield desc{d}_en */ 1422 #define tdm_descden_width 1 1423 /* default value of bitfield desc{d}_en */ 1424 #define tdm_descden_default 0x0 1425 1426 /* tx desc{d}_hd[c:0] bitfield definitions 1427 * preprocessor definitions for the bitfield "desc{d}_hd[c:0]". 1428 * parameter: descriptor {d} | stride size 0x40 | range [0, 31] 1429 * port="tdm_pif_desc0_hd_o[12:0]" 1430 */ 1431 1432 /* register address for bitfield desc{d}_hd[c:0] */ 1433 #define tdm_descdhd_adr(descriptor) (0x00007c0c + (descriptor) * 0x40) 1434 /* bitmask for bitfield desc{d}_hd[c:0] */ 1435 #define tdm_descdhd_msk 0x00001fff 1436 /* inverted bitmask for bitfield desc{d}_hd[c:0] */ 1437 #define tdm_descdhd_mskn 0xffffe000 1438 /* lower bit position of bitfield desc{d}_hd[c:0] */ 1439 #define tdm_descdhd_shift 0 1440 /* width of bitfield desc{d}_hd[c:0] */ 1441 #define tdm_descdhd_width 13 1442 1443 /* tx desc{d}_len[9:0] bitfield definitions 1444 * preprocessor definitions for the bitfield "desc{d}_len[9:0]". 1445 * parameter: descriptor {d} | stride size 0x40 | range [0, 31] 1446 * port="pif_tdm_desc0_len_i[9:0]" 1447 */ 1448 1449 /* register address for bitfield desc{d}_len[9:0] */ 1450 #define tdm_descdlen_adr(descriptor) (0x00007c08 + (descriptor) * 0x40) 1451 /* bitmask for bitfield desc{d}_len[9:0] */ 1452 #define tdm_descdlen_msk 0x00001ff8 1453 /* inverted bitmask for bitfield desc{d}_len[9:0] */ 1454 #define tdm_descdlen_mskn 0xffffe007 1455 /* lower bit position of bitfield desc{d}_len[9:0] */ 1456 #define tdm_descdlen_shift 3 1457 /* width of bitfield desc{d}_len[9:0] */ 1458 #define tdm_descdlen_width 10 1459 /* default value of bitfield desc{d}_len[9:0] */ 1460 #define tdm_descdlen_default 0x0 1461 1462 /* tx int_desc_wrb_en bitfield definitions 1463 * preprocessor definitions for the bitfield "int_desc_wrb_en". 1464 * port="pif_tdm_int_desc_wrb_en_i" 1465 */ 1466 1467 /* register address for bitfield int_desc_wrb_en */ 1468 #define tdm_int_desc_wrb_en_adr 0x00007b40 1469 /* bitmask for bitfield int_desc_wrb_en */ 1470 #define tdm_int_desc_wrb_en_msk 0x00000002 1471 /* inverted bitmask for bitfield int_desc_wrb_en */ 1472 #define tdm_int_desc_wrb_en_mskn 0xfffffffd 1473 /* lower bit position of bitfield int_desc_wrb_en */ 1474 #define tdm_int_desc_wrb_en_shift 1 1475 /* width of bitfield int_desc_wrb_en */ 1476 #define tdm_int_desc_wrb_en_width 1 1477 /* default value of bitfield int_desc_wrb_en */ 1478 #define tdm_int_desc_wrb_en_default 0x0 1479 1480 /* tx desc{d}_wrb_thresh[6:0] bitfield definitions 1481 * preprocessor definitions for the bitfield "desc{d}_wrb_thresh[6:0]". 1482 * parameter: descriptor {d} | stride size 0x40 | range [0, 31] 1483 * port="pif_tdm_desc0_wrb_thresh_i[6:0]" 1484 */ 1485 1486 /* register address for bitfield desc{d}_wrb_thresh[6:0] */ 1487 #define tdm_descdwrb_thresh_adr(descriptor) (0x00007c18 + (descriptor) * 0x40) 1488 /* bitmask for bitfield desc{d}_wrb_thresh[6:0] */ 1489 #define tdm_descdwrb_thresh_msk 0x00007f00 1490 /* inverted bitmask for bitfield desc{d}_wrb_thresh[6:0] */ 1491 #define tdm_descdwrb_thresh_mskn 0xffff80ff 1492 /* lower bit position of bitfield desc{d}_wrb_thresh[6:0] */ 1493 #define tdm_descdwrb_thresh_shift 8 1494 /* width of bitfield desc{d}_wrb_thresh[6:0] */ 1495 #define tdm_descdwrb_thresh_width 7 1496 /* default value of bitfield desc{d}_wrb_thresh[6:0] */ 1497 #define tdm_descdwrb_thresh_default 0x0 1498 1499 /* tx lso_tcp_flag_first[b:0] bitfield definitions 1500 * preprocessor definitions for the bitfield "lso_tcp_flag_first[b:0]". 1501 * port="pif_thm_lso_tcp_flag_first_i[11:0]" 1502 */ 1503 1504 /* register address for bitfield lso_tcp_flag_first[b:0] */ 1505 #define thm_lso_tcp_flag_first_adr 0x00007820 1506 /* bitmask for bitfield lso_tcp_flag_first[b:0] */ 1507 #define thm_lso_tcp_flag_first_msk 0x00000fff 1508 /* inverted bitmask for bitfield lso_tcp_flag_first[b:0] */ 1509 #define thm_lso_tcp_flag_first_mskn 0xfffff000 1510 /* lower bit position of bitfield lso_tcp_flag_first[b:0] */ 1511 #define thm_lso_tcp_flag_first_shift 0 1512 /* width of bitfield lso_tcp_flag_first[b:0] */ 1513 #define thm_lso_tcp_flag_first_width 12 1514 /* default value of bitfield lso_tcp_flag_first[b:0] */ 1515 #define thm_lso_tcp_flag_first_default 0x0 1516 1517 /* tx lso_tcp_flag_last[b:0] bitfield definitions 1518 * preprocessor definitions for the bitfield "lso_tcp_flag_last[b:0]". 1519 * port="pif_thm_lso_tcp_flag_last_i[11:0]" 1520 */ 1521 1522 /* register address for bitfield lso_tcp_flag_last[b:0] */ 1523 #define thm_lso_tcp_flag_last_adr 0x00007824 1524 /* bitmask for bitfield lso_tcp_flag_last[b:0] */ 1525 #define thm_lso_tcp_flag_last_msk 0x00000fff 1526 /* inverted bitmask for bitfield lso_tcp_flag_last[b:0] */ 1527 #define thm_lso_tcp_flag_last_mskn 0xfffff000 1528 /* lower bit position of bitfield lso_tcp_flag_last[b:0] */ 1529 #define thm_lso_tcp_flag_last_shift 0 1530 /* width of bitfield lso_tcp_flag_last[b:0] */ 1531 #define thm_lso_tcp_flag_last_width 12 1532 /* default value of bitfield lso_tcp_flag_last[b:0] */ 1533 #define thm_lso_tcp_flag_last_default 0x0 1534 1535 /* tx lso_tcp_flag_mid[b:0] bitfield definitions 1536 * preprocessor definitions for the bitfield "lso_tcp_flag_mid[b:0]". 1537 * port="pif_thm_lso_tcp_flag_mid_i[11:0]" 1538 */ 1539 1540 /* Register address for bitfield lro_rsc_max[1F:0] */ 1541 #define rpo_lro_rsc_max_adr 0x00005598 1542 /* Bitmask for bitfield lro_rsc_max[1F:0] */ 1543 #define rpo_lro_rsc_max_msk 0xFFFFFFFF 1544 /* Inverted bitmask for bitfield lro_rsc_max[1F:0] */ 1545 #define rpo_lro_rsc_max_mskn 0x00000000 1546 /* Lower bit position of bitfield lro_rsc_max[1F:0] */ 1547 #define rpo_lro_rsc_max_shift 0 1548 /* Width of bitfield lro_rsc_max[1F:0] */ 1549 #define rpo_lro_rsc_max_width 32 1550 /* Default value of bitfield lro_rsc_max[1F:0] */ 1551 #define rpo_lro_rsc_max_default 0x0 1552 1553 /* RX lro_en[1F:0] Bitfield Definitions 1554 * Preprocessor definitions for the bitfield "lro_en[1F:0]". 1555 * PORT="pif_rpo_lro_en_i[31:0]" 1556 */ 1557 1558 /* Register address for bitfield lro_en[1F:0] */ 1559 #define rpo_lro_en_adr 0x00005590 1560 /* Bitmask for bitfield lro_en[1F:0] */ 1561 #define rpo_lro_en_msk 0xFFFFFFFF 1562 /* Inverted bitmask for bitfield lro_en[1F:0] */ 1563 #define rpo_lro_en_mskn 0x00000000 1564 /* Lower bit position of bitfield lro_en[1F:0] */ 1565 #define rpo_lro_en_shift 0 1566 /* Width of bitfield lro_en[1F:0] */ 1567 #define rpo_lro_en_width 32 1568 /* Default value of bitfield lro_en[1F:0] */ 1569 #define rpo_lro_en_default 0x0 1570 1571 /* RX lro_ptopt_en Bitfield Definitions 1572 * Preprocessor definitions for the bitfield "lro_ptopt_en". 1573 * PORT="pif_rpo_lro_ptopt_en_i" 1574 */ 1575 1576 /* Register address for bitfield lro_ptopt_en */ 1577 #define rpo_lro_ptopt_en_adr 0x00005594 1578 /* Bitmask for bitfield lro_ptopt_en */ 1579 #define rpo_lro_ptopt_en_msk 0x00008000 1580 /* Inverted bitmask for bitfield lro_ptopt_en */ 1581 #define rpo_lro_ptopt_en_mskn 0xFFFF7FFF 1582 /* Lower bit position of bitfield lro_ptopt_en */ 1583 #define rpo_lro_ptopt_en_shift 15 1584 /* Width of bitfield lro_ptopt_en */ 1585 #define rpo_lro_ptopt_en_width 1 1586 /* Default value of bitfield lro_ptopt_en */ 1587 #define rpo_lro_ptopt_en_defalt 0x1 1588 1589 /* RX lro_q_ses_lmt Bitfield Definitions 1590 * Preprocessor definitions for the bitfield "lro_q_ses_lmt". 1591 * PORT="pif_rpo_lro_q_ses_lmt_i[1:0]" 1592 */ 1593 1594 /* Register address for bitfield lro_q_ses_lmt */ 1595 #define rpo_lro_qses_lmt_adr 0x00005594 1596 /* Bitmask for bitfield lro_q_ses_lmt */ 1597 #define rpo_lro_qses_lmt_msk 0x00003000 1598 /* Inverted bitmask for bitfield lro_q_ses_lmt */ 1599 #define rpo_lro_qses_lmt_mskn 0xFFFFCFFF 1600 /* Lower bit position of bitfield lro_q_ses_lmt */ 1601 #define rpo_lro_qses_lmt_shift 12 1602 /* Width of bitfield lro_q_ses_lmt */ 1603 #define rpo_lro_qses_lmt_width 2 1604 /* Default value of bitfield lro_q_ses_lmt */ 1605 #define rpo_lro_qses_lmt_default 0x1 1606 1607 /* RX lro_tot_dsc_lmt[1:0] Bitfield Definitions 1608 * Preprocessor definitions for the bitfield "lro_tot_dsc_lmt[1:0]". 1609 * PORT="pif_rpo_lro_tot_dsc_lmt_i[1:0]" 1610 */ 1611 1612 /* Register address for bitfield lro_tot_dsc_lmt[1:0] */ 1613 #define rpo_lro_tot_dsc_lmt_adr 0x00005594 1614 /* Bitmask for bitfield lro_tot_dsc_lmt[1:0] */ 1615 #define rpo_lro_tot_dsc_lmt_msk 0x00000060 1616 /* Inverted bitmask for bitfield lro_tot_dsc_lmt[1:0] */ 1617 #define rpo_lro_tot_dsc_lmt_mskn 0xFFFFFF9F 1618 /* Lower bit position of bitfield lro_tot_dsc_lmt[1:0] */ 1619 #define rpo_lro_tot_dsc_lmt_shift 5 1620 /* Width of bitfield lro_tot_dsc_lmt[1:0] */ 1621 #define rpo_lro_tot_dsc_lmt_width 2 1622 /* Default value of bitfield lro_tot_dsc_lmt[1:0] */ 1623 #define rpo_lro_tot_dsc_lmt_defalt 0x1 1624 1625 /* RX lro_pkt_min[4:0] Bitfield Definitions 1626 * Preprocessor definitions for the bitfield "lro_pkt_min[4:0]". 1627 * PORT="pif_rpo_lro_pkt_min_i[4:0]" 1628 */ 1629 1630 /* Register address for bitfield lro_pkt_min[4:0] */ 1631 #define rpo_lro_pkt_min_adr 0x00005594 1632 /* Bitmask for bitfield lro_pkt_min[4:0] */ 1633 #define rpo_lro_pkt_min_msk 0x0000001F 1634 /* Inverted bitmask for bitfield lro_pkt_min[4:0] */ 1635 #define rpo_lro_pkt_min_mskn 0xFFFFFFE0 1636 /* Lower bit position of bitfield lro_pkt_min[4:0] */ 1637 #define rpo_lro_pkt_min_shift 0 1638 /* Width of bitfield lro_pkt_min[4:0] */ 1639 #define rpo_lro_pkt_min_width 5 1640 /* Default value of bitfield lro_pkt_min[4:0] */ 1641 #define rpo_lro_pkt_min_default 0x8 1642 1643 /* Width of bitfield lro{L}_des_max[1:0] */ 1644 #define rpo_lro_ldes_max_width 2 1645 /* Default value of bitfield lro{L}_des_max[1:0] */ 1646 #define rpo_lro_ldes_max_default 0x0 1647 1648 /* RX lro_tb_div[11:0] Bitfield Definitions 1649 * Preprocessor definitions for the bitfield "lro_tb_div[11:0]". 1650 * PORT="pif_rpo_lro_tb_div_i[11:0]" 1651 */ 1652 1653 /* Register address for bitfield lro_tb_div[11:0] */ 1654 #define rpo_lro_tb_div_adr 0x00005620 1655 /* Bitmask for bitfield lro_tb_div[11:0] */ 1656 #define rpo_lro_tb_div_msk 0xFFF00000 1657 /* Inverted bitmask for bitfield lro_tb_div[11:0] */ 1658 #define rpo_lro_tb_div_mskn 0x000FFFFF 1659 /* Lower bit position of bitfield lro_tb_div[11:0] */ 1660 #define rpo_lro_tb_div_shift 20 1661 /* Width of bitfield lro_tb_div[11:0] */ 1662 #define rpo_lro_tb_div_width 12 1663 /* Default value of bitfield lro_tb_div[11:0] */ 1664 #define rpo_lro_tb_div_default 0xC35 1665 1666 /* RX lro_ina_ival[9:0] Bitfield Definitions 1667 * Preprocessor definitions for the bitfield "lro_ina_ival[9:0]". 1668 * PORT="pif_rpo_lro_ina_ival_i[9:0]" 1669 */ 1670 1671 /* Register address for bitfield lro_ina_ival[9:0] */ 1672 #define rpo_lro_ina_ival_adr 0x00005620 1673 /* Bitmask for bitfield lro_ina_ival[9:0] */ 1674 #define rpo_lro_ina_ival_msk 0x000FFC00 1675 /* Inverted bitmask for bitfield lro_ina_ival[9:0] */ 1676 #define rpo_lro_ina_ival_mskn 0xFFF003FF 1677 /* Lower bit position of bitfield lro_ina_ival[9:0] */ 1678 #define rpo_lro_ina_ival_shift 10 1679 /* Width of bitfield lro_ina_ival[9:0] */ 1680 #define rpo_lro_ina_ival_width 10 1681 /* Default value of bitfield lro_ina_ival[9:0] */ 1682 #define rpo_lro_ina_ival_default 0xA 1683 1684 /* RX lro_max_ival[9:0] Bitfield Definitions 1685 * Preprocessor definitions for the bitfield "lro_max_ival[9:0]". 1686 * PORT="pif_rpo_lro_max_ival_i[9:0]" 1687 */ 1688 1689 /* Register address for bitfield lro_max_ival[9:0] */ 1690 #define rpo_lro_max_ival_adr 0x00005620 1691 /* Bitmask for bitfield lro_max_ival[9:0] */ 1692 #define rpo_lro_max_ival_msk 0x000003FF 1693 /* Inverted bitmask for bitfield lro_max_ival[9:0] */ 1694 #define rpo_lro_max_ival_mskn 0xFFFFFC00 1695 /* Lower bit position of bitfield lro_max_ival[9:0] */ 1696 #define rpo_lro_max_ival_shift 0 1697 /* Width of bitfield lro_max_ival[9:0] */ 1698 #define rpo_lro_max_ival_width 10 1699 /* Default value of bitfield lro_max_ival[9:0] */ 1700 #define rpo_lro_max_ival_default 0x19 1701 1702 /* TX dca{D}_cpuid[7:0] Bitfield Definitions 1703 * Preprocessor definitions for the bitfield "dca{D}_cpuid[7:0]". 1704 * Parameter: DCA {D} | stride size 0x4 | range [0, 31] 1705 * PORT="pif_tdm_dca0_cpuid_i[7:0]" 1706 */ 1707 1708 /* Register address for bitfield dca{D}_cpuid[7:0] */ 1709 #define tdm_dca_dcpuid_adr(dca) (0x00008400 + (dca) * 0x4) 1710 /* Bitmask for bitfield dca{D}_cpuid[7:0] */ 1711 #define tdm_dca_dcpuid_msk 0x000000FF 1712 /* Inverted bitmask for bitfield dca{D}_cpuid[7:0] */ 1713 #define tdm_dca_dcpuid_mskn 0xFFFFFF00 1714 /* Lower bit position of bitfield dca{D}_cpuid[7:0] */ 1715 #define tdm_dca_dcpuid_shift 0 1716 /* Width of bitfield dca{D}_cpuid[7:0] */ 1717 #define tdm_dca_dcpuid_width 8 1718 /* Default value of bitfield dca{D}_cpuid[7:0] */ 1719 #define tdm_dca_dcpuid_default 0x0 1720 1721 /* TX dca{D}_desc_en Bitfield Definitions 1722 * Preprocessor definitions for the bitfield "dca{D}_desc_en". 1723 * Parameter: DCA {D} | stride size 0x4 | range [0, 31] 1724 * PORT="pif_tdm_dca_desc_en_i[0]" 1725 */ 1726 1727 /* Register address for bitfield dca{D}_desc_en */ 1728 #define tdm_dca_ddesc_en_adr(dca) (0x00008400 + (dca) * 0x4) 1729 /* Bitmask for bitfield dca{D}_desc_en */ 1730 #define tdm_dca_ddesc_en_msk 0x80000000 1731 /* Inverted bitmask for bitfield dca{D}_desc_en */ 1732 #define tdm_dca_ddesc_en_mskn 0x7FFFFFFF 1733 /* Lower bit position of bitfield dca{D}_desc_en */ 1734 #define tdm_dca_ddesc_en_shift 31 1735 /* Width of bitfield dca{D}_desc_en */ 1736 #define tdm_dca_ddesc_en_width 1 1737 /* Default value of bitfield dca{D}_desc_en */ 1738 #define tdm_dca_ddesc_en_default 0x0 1739 1740 /* TX desc{D}_en Bitfield Definitions 1741 * Preprocessor definitions for the bitfield "desc{D}_en". 1742 * Parameter: descriptor {D} | stride size 0x40 | range [0, 31] 1743 * PORT="pif_tdm_desc_en_i[0]" 1744 */ 1745 1746 /* Register address for bitfield desc{D}_en */ 1747 #define tdm_desc_den_adr(descriptor) (0x00007C08 + (descriptor) * 0x40) 1748 /* Bitmask for bitfield desc{D}_en */ 1749 #define tdm_desc_den_msk 0x80000000 1750 /* Inverted bitmask for bitfield desc{D}_en */ 1751 #define tdm_desc_den_mskn 0x7FFFFFFF 1752 /* Lower bit position of bitfield desc{D}_en */ 1753 #define tdm_desc_den_shift 31 1754 /* Width of bitfield desc{D}_en */ 1755 #define tdm_desc_den_width 1 1756 /* Default value of bitfield desc{D}_en */ 1757 #define tdm_desc_den_default 0x0 1758 1759 /* TX desc{D}_hd[C:0] Bitfield Definitions 1760 * Preprocessor definitions for the bitfield "desc{D}_hd[C:0]". 1761 * Parameter: descriptor {D} | stride size 0x40 | range [0, 31] 1762 * PORT="tdm_pif_desc0_hd_o[12:0]" 1763 */ 1764 1765 /* Register address for bitfield desc{D}_hd[C:0] */ 1766 #define tdm_desc_dhd_adr(descriptor) (0x00007C0C + (descriptor) * 0x40) 1767 /* Bitmask for bitfield desc{D}_hd[C:0] */ 1768 #define tdm_desc_dhd_msk 0x00001FFF 1769 /* Inverted bitmask for bitfield desc{D}_hd[C:0] */ 1770 #define tdm_desc_dhd_mskn 0xFFFFE000 1771 /* Lower bit position of bitfield desc{D}_hd[C:0] */ 1772 #define tdm_desc_dhd_shift 0 1773 /* Width of bitfield desc{D}_hd[C:0] */ 1774 #define tdm_desc_dhd_width 13 1775 1776 /* TX desc{D}_len[9:0] Bitfield Definitions 1777 * Preprocessor definitions for the bitfield "desc{D}_len[9:0]". 1778 * Parameter: descriptor {D} | stride size 0x40 | range [0, 31] 1779 * PORT="pif_tdm_desc0_len_i[9:0]" 1780 */ 1781 1782 /* Register address for bitfield desc{D}_len[9:0] */ 1783 #define tdm_desc_dlen_adr(descriptor) (0x00007C08 + (descriptor) * 0x40) 1784 /* Bitmask for bitfield desc{D}_len[9:0] */ 1785 #define tdm_desc_dlen_msk 0x00001FF8 1786 /* Inverted bitmask for bitfield desc{D}_len[9:0] */ 1787 #define tdm_desc_dlen_mskn 0xFFFFE007 1788 /* Lower bit position of bitfield desc{D}_len[9:0] */ 1789 #define tdm_desc_dlen_shift 3 1790 /* Width of bitfield desc{D}_len[9:0] */ 1791 #define tdm_desc_dlen_width 10 1792 /* Default value of bitfield desc{D}_len[9:0] */ 1793 #define tdm_desc_dlen_default 0x0 1794 1795 /* TX desc{D}_wrb_thresh[6:0] Bitfield Definitions 1796 * Preprocessor definitions for the bitfield "desc{D}_wrb_thresh[6:0]". 1797 * Parameter: descriptor {D} | stride size 0x40 | range [0, 31] 1798 * PORT="pif_tdm_desc0_wrb_thresh_i[6:0]" 1799 */ 1800 1801 /* Register address for bitfield desc{D}_wrb_thresh[6:0] */ 1802 #define tdm_desc_dwrb_thresh_adr(descriptor) \ 1803 (0x00007C18 + (descriptor) * 0x40) 1804 /* Bitmask for bitfield desc{D}_wrb_thresh[6:0] */ 1805 #define tdm_desc_dwrb_thresh_msk 0x00007F00 1806 /* Inverted bitmask for bitfield desc{D}_wrb_thresh[6:0] */ 1807 #define tdm_desc_dwrb_thresh_mskn 0xFFFF80FF 1808 /* Lower bit position of bitfield desc{D}_wrb_thresh[6:0] */ 1809 #define tdm_desc_dwrb_thresh_shift 8 1810 /* Width of bitfield desc{D}_wrb_thresh[6:0] */ 1811 #define tdm_desc_dwrb_thresh_width 7 1812 /* Default value of bitfield desc{D}_wrb_thresh[6:0] */ 1813 #define tdm_desc_dwrb_thresh_default 0x0 1814 1815 /* TX tdm_int_mod_en Bitfield Definitions 1816 * Preprocessor definitions for the bitfield "tdm_int_mod_en". 1817 * PORT="pif_tdm_int_mod_en_i" 1818 */ 1819 1820 /* Register address for bitfield tdm_int_mod_en */ 1821 #define tdm_int_mod_en_adr 0x00007B40 1822 /* Bitmask for bitfield tdm_int_mod_en */ 1823 #define tdm_int_mod_en_msk 0x00000010 1824 /* Inverted bitmask for bitfield tdm_int_mod_en */ 1825 #define tdm_int_mod_en_mskn 0xFFFFFFEF 1826 /* Lower bit position of bitfield tdm_int_mod_en */ 1827 #define tdm_int_mod_en_shift 4 1828 /* Width of bitfield tdm_int_mod_en */ 1829 #define tdm_int_mod_en_width 1 1830 /* Default value of bitfield tdm_int_mod_en */ 1831 #define tdm_int_mod_en_default 0x0 1832 1833 /* TX lso_tcp_flag_mid[B:0] Bitfield Definitions 1834 * Preprocessor definitions for the bitfield "lso_tcp_flag_mid[B:0]". 1835 * PORT="pif_thm_lso_tcp_flag_mid_i[11:0]" 1836 */ 1837 /* register address for bitfield lso_tcp_flag_mid[b:0] */ 1838 #define thm_lso_tcp_flag_mid_adr 0x00007820 1839 /* bitmask for bitfield lso_tcp_flag_mid[b:0] */ 1840 #define thm_lso_tcp_flag_mid_msk 0x0fff0000 1841 /* inverted bitmask for bitfield lso_tcp_flag_mid[b:0] */ 1842 #define thm_lso_tcp_flag_mid_mskn 0xf000ffff 1843 /* lower bit position of bitfield lso_tcp_flag_mid[b:0] */ 1844 #define thm_lso_tcp_flag_mid_shift 16 1845 /* width of bitfield lso_tcp_flag_mid[b:0] */ 1846 #define thm_lso_tcp_flag_mid_width 12 1847 /* default value of bitfield lso_tcp_flag_mid[b:0] */ 1848 #define thm_lso_tcp_flag_mid_default 0x0 1849 1850 /* tx tx_buf_en bitfield definitions 1851 * preprocessor definitions for the bitfield "tx_buf_en". 1852 * port="pif_tpb_tx_buf_en_i" 1853 */ 1854 1855 /* register address for bitfield tx_buf_en */ 1856 #define tpb_tx_buf_en_adr 0x00007900 1857 /* bitmask for bitfield tx_buf_en */ 1858 #define tpb_tx_buf_en_msk 0x00000001 1859 /* inverted bitmask for bitfield tx_buf_en */ 1860 #define tpb_tx_buf_en_mskn 0xfffffffe 1861 /* lower bit position of bitfield tx_buf_en */ 1862 #define tpb_tx_buf_en_shift 0 1863 /* width of bitfield tx_buf_en */ 1864 #define tpb_tx_buf_en_width 1 1865 /* default value of bitfield tx_buf_en */ 1866 #define tpb_tx_buf_en_default 0x0 1867 1868 /* tx tx{b}_hi_thresh[c:0] bitfield definitions 1869 * preprocessor definitions for the bitfield "tx{b}_hi_thresh[c:0]". 1870 * parameter: buffer {b} | stride size 0x10 | range [0, 7] 1871 * port="pif_tpb_tx0_hi_thresh_i[12:0]" 1872 */ 1873 1874 /* register address for bitfield tx{b}_hi_thresh[c:0] */ 1875 #define tpb_txbhi_thresh_adr(buffer) (0x00007914 + (buffer) * 0x10) 1876 /* bitmask for bitfield tx{b}_hi_thresh[c:0] */ 1877 #define tpb_txbhi_thresh_msk 0x1fff0000 1878 /* inverted bitmask for bitfield tx{b}_hi_thresh[c:0] */ 1879 #define tpb_txbhi_thresh_mskn 0xe000ffff 1880 /* lower bit position of bitfield tx{b}_hi_thresh[c:0] */ 1881 #define tpb_txbhi_thresh_shift 16 1882 /* width of bitfield tx{b}_hi_thresh[c:0] */ 1883 #define tpb_txbhi_thresh_width 13 1884 /* default value of bitfield tx{b}_hi_thresh[c:0] */ 1885 #define tpb_txbhi_thresh_default 0x0 1886 1887 /* tx tx{b}_lo_thresh[c:0] bitfield definitions 1888 * preprocessor definitions for the bitfield "tx{b}_lo_thresh[c:0]". 1889 * parameter: buffer {b} | stride size 0x10 | range [0, 7] 1890 * port="pif_tpb_tx0_lo_thresh_i[12:0]" 1891 */ 1892 1893 /* register address for bitfield tx{b}_lo_thresh[c:0] */ 1894 #define tpb_txblo_thresh_adr(buffer) (0x00007914 + (buffer) * 0x10) 1895 /* bitmask for bitfield tx{b}_lo_thresh[c:0] */ 1896 #define tpb_txblo_thresh_msk 0x00001fff 1897 /* inverted bitmask for bitfield tx{b}_lo_thresh[c:0] */ 1898 #define tpb_txblo_thresh_mskn 0xffffe000 1899 /* lower bit position of bitfield tx{b}_lo_thresh[c:0] */ 1900 #define tpb_txblo_thresh_shift 0 1901 /* width of bitfield tx{b}_lo_thresh[c:0] */ 1902 #define tpb_txblo_thresh_width 13 1903 /* default value of bitfield tx{b}_lo_thresh[c:0] */ 1904 #define tpb_txblo_thresh_default 0x0 1905 1906 /* tx dma_sys_loopback bitfield definitions 1907 * preprocessor definitions for the bitfield "dma_sys_loopback". 1908 * port="pif_tpb_dma_sys_lbk_i" 1909 */ 1910 1911 /* register address for bitfield dma_sys_loopback */ 1912 #define tpb_dma_sys_lbk_adr 0x00007000 1913 /* bitmask for bitfield dma_sys_loopback */ 1914 #define tpb_dma_sys_lbk_msk 0x00000040 1915 /* inverted bitmask for bitfield dma_sys_loopback */ 1916 #define tpb_dma_sys_lbk_mskn 0xffffffbf 1917 /* lower bit position of bitfield dma_sys_loopback */ 1918 #define tpb_dma_sys_lbk_shift 6 1919 /* width of bitfield dma_sys_loopback */ 1920 #define tpb_dma_sys_lbk_width 1 1921 /* default value of bitfield dma_sys_loopback */ 1922 #define tpb_dma_sys_lbk_default 0x0 1923 1924 /* tx tx{b}_buf_size[7:0] bitfield definitions 1925 * preprocessor definitions for the bitfield "tx{b}_buf_size[7:0]". 1926 * parameter: buffer {b} | stride size 0x10 | range [0, 7] 1927 * port="pif_tpb_tx0_buf_size_i[7:0]" 1928 */ 1929 1930 /* register address for bitfield tx{b}_buf_size[7:0] */ 1931 #define tpb_txbbuf_size_adr(buffer) (0x00007910 + (buffer) * 0x10) 1932 /* bitmask for bitfield tx{b}_buf_size[7:0] */ 1933 #define tpb_txbbuf_size_msk 0x000000ff 1934 /* inverted bitmask for bitfield tx{b}_buf_size[7:0] */ 1935 #define tpb_txbbuf_size_mskn 0xffffff00 1936 /* lower bit position of bitfield tx{b}_buf_size[7:0] */ 1937 #define tpb_txbbuf_size_shift 0 1938 /* width of bitfield tx{b}_buf_size[7:0] */ 1939 #define tpb_txbbuf_size_width 8 1940 /* default value of bitfield tx{b}_buf_size[7:0] */ 1941 #define tpb_txbbuf_size_default 0x0 1942 1943 /* tx tx_scp_ins_en bitfield definitions 1944 * preprocessor definitions for the bitfield "tx_scp_ins_en". 1945 * port="pif_tpb_scp_ins_en_i" 1946 */ 1947 1948 /* register address for bitfield tx_scp_ins_en */ 1949 #define tpb_tx_scp_ins_en_adr 0x00007900 1950 /* bitmask for bitfield tx_scp_ins_en */ 1951 #define tpb_tx_scp_ins_en_msk 0x00000004 1952 /* inverted bitmask for bitfield tx_scp_ins_en */ 1953 #define tpb_tx_scp_ins_en_mskn 0xfffffffb 1954 /* lower bit position of bitfield tx_scp_ins_en */ 1955 #define tpb_tx_scp_ins_en_shift 2 1956 /* width of bitfield tx_scp_ins_en */ 1957 #define tpb_tx_scp_ins_en_width 1 1958 /* default value of bitfield tx_scp_ins_en */ 1959 #define tpb_tx_scp_ins_en_default 0x0 1960 1961 /* tx ipv4_chk_en bitfield definitions 1962 * preprocessor definitions for the bitfield "ipv4_chk_en". 1963 * port="pif_tpo_ipv4_chk_en_i" 1964 */ 1965 1966 /* register address for bitfield ipv4_chk_en */ 1967 #define tpo_ipv4chk_en_adr 0x00007800 1968 /* bitmask for bitfield ipv4_chk_en */ 1969 #define tpo_ipv4chk_en_msk 0x00000002 1970 /* inverted bitmask for bitfield ipv4_chk_en */ 1971 #define tpo_ipv4chk_en_mskn 0xfffffffd 1972 /* lower bit position of bitfield ipv4_chk_en */ 1973 #define tpo_ipv4chk_en_shift 1 1974 /* width of bitfield ipv4_chk_en */ 1975 #define tpo_ipv4chk_en_width 1 1976 /* default value of bitfield ipv4_chk_en */ 1977 #define tpo_ipv4chk_en_default 0x0 1978 1979 /* tx l4_chk_en bitfield definitions 1980 * preprocessor definitions for the bitfield "l4_chk_en". 1981 * port="pif_tpo_l4_chk_en_i" 1982 */ 1983 1984 /* register address for bitfield l4_chk_en */ 1985 #define tpol4chk_en_adr 0x00007800 1986 /* bitmask for bitfield l4_chk_en */ 1987 #define tpol4chk_en_msk 0x00000001 1988 /* inverted bitmask for bitfield l4_chk_en */ 1989 #define tpol4chk_en_mskn 0xfffffffe 1990 /* lower bit position of bitfield l4_chk_en */ 1991 #define tpol4chk_en_shift 0 1992 /* width of bitfield l4_chk_en */ 1993 #define tpol4chk_en_width 1 1994 /* default value of bitfield l4_chk_en */ 1995 #define tpol4chk_en_default 0x0 1996 1997 /* tx pkt_sys_loopback bitfield definitions 1998 * preprocessor definitions for the bitfield "pkt_sys_loopback". 1999 * port="pif_tpo_pkt_sys_lbk_i" 2000 */ 2001 2002 /* register address for bitfield pkt_sys_loopback */ 2003 #define tpo_pkt_sys_lbk_adr 0x00007000 2004 /* bitmask for bitfield pkt_sys_loopback */ 2005 #define tpo_pkt_sys_lbk_msk 0x00000080 2006 /* inverted bitmask for bitfield pkt_sys_loopback */ 2007 #define tpo_pkt_sys_lbk_mskn 0xffffff7f 2008 /* lower bit position of bitfield pkt_sys_loopback */ 2009 #define tpo_pkt_sys_lbk_shift 7 2010 /* width of bitfield pkt_sys_loopback */ 2011 #define tpo_pkt_sys_lbk_width 1 2012 /* default value of bitfield pkt_sys_loopback */ 2013 #define tpo_pkt_sys_lbk_default 0x0 2014 2015 /* tx data_tc_arb_mode bitfield definitions 2016 * preprocessor definitions for the bitfield "data_tc_arb_mode". 2017 * port="pif_tps_data_tc_arb_mode_i" 2018 */ 2019 2020 /* register address for bitfield data_tc_arb_mode */ 2021 #define tps_data_tc_arb_mode_adr 0x00007100 2022 /* bitmask for bitfield data_tc_arb_mode */ 2023 #define tps_data_tc_arb_mode_msk 0x00000001 2024 /* inverted bitmask for bitfield data_tc_arb_mode */ 2025 #define tps_data_tc_arb_mode_mskn 0xfffffffe 2026 /* lower bit position of bitfield data_tc_arb_mode */ 2027 #define tps_data_tc_arb_mode_shift 0 2028 /* width of bitfield data_tc_arb_mode */ 2029 #define tps_data_tc_arb_mode_width 1 2030 /* default value of bitfield data_tc_arb_mode */ 2031 #define tps_data_tc_arb_mode_default 0x0 2032 2033 /* tx desc_rate_ta_rst bitfield definitions 2034 * preprocessor definitions for the bitfield "desc_rate_ta_rst". 2035 * port="pif_tps_desc_rate_ta_rst_i" 2036 */ 2037 2038 /* register address for bitfield desc_rate_ta_rst */ 2039 #define tps_desc_rate_ta_rst_adr 0x00007310 2040 /* bitmask for bitfield desc_rate_ta_rst */ 2041 #define tps_desc_rate_ta_rst_msk 0x80000000 2042 /* inverted bitmask for bitfield desc_rate_ta_rst */ 2043 #define tps_desc_rate_ta_rst_mskn 0x7fffffff 2044 /* lower bit position of bitfield desc_rate_ta_rst */ 2045 #define tps_desc_rate_ta_rst_shift 31 2046 /* width of bitfield desc_rate_ta_rst */ 2047 #define tps_desc_rate_ta_rst_width 1 2048 /* default value of bitfield desc_rate_ta_rst */ 2049 #define tps_desc_rate_ta_rst_default 0x0 2050 2051 /* tx desc_rate_limit[a:0] bitfield definitions 2052 * preprocessor definitions for the bitfield "desc_rate_limit[a:0]". 2053 * port="pif_tps_desc_rate_lim_i[10:0]" 2054 */ 2055 2056 /* register address for bitfield desc_rate_limit[a:0] */ 2057 #define tps_desc_rate_lim_adr 0x00007310 2058 /* bitmask for bitfield desc_rate_limit[a:0] */ 2059 #define tps_desc_rate_lim_msk 0x000007ff 2060 /* inverted bitmask for bitfield desc_rate_limit[a:0] */ 2061 #define tps_desc_rate_lim_mskn 0xfffff800 2062 /* lower bit position of bitfield desc_rate_limit[a:0] */ 2063 #define tps_desc_rate_lim_shift 0 2064 /* width of bitfield desc_rate_limit[a:0] */ 2065 #define tps_desc_rate_lim_width 11 2066 /* default value of bitfield desc_rate_limit[a:0] */ 2067 #define tps_desc_rate_lim_default 0x0 2068 2069 /* tx desc_tc_arb_mode[1:0] bitfield definitions 2070 * preprocessor definitions for the bitfield "desc_tc_arb_mode[1:0]". 2071 * port="pif_tps_desc_tc_arb_mode_i[1:0]" 2072 */ 2073 2074 /* register address for bitfield desc_tc_arb_mode[1:0] */ 2075 #define tps_desc_tc_arb_mode_adr 0x00007200 2076 /* bitmask for bitfield desc_tc_arb_mode[1:0] */ 2077 #define tps_desc_tc_arb_mode_msk 0x00000003 2078 /* inverted bitmask for bitfield desc_tc_arb_mode[1:0] */ 2079 #define tps_desc_tc_arb_mode_mskn 0xfffffffc 2080 /* lower bit position of bitfield desc_tc_arb_mode[1:0] */ 2081 #define tps_desc_tc_arb_mode_shift 0 2082 /* width of bitfield desc_tc_arb_mode[1:0] */ 2083 #define tps_desc_tc_arb_mode_width 2 2084 /* default value of bitfield desc_tc_arb_mode[1:0] */ 2085 #define tps_desc_tc_arb_mode_default 0x0 2086 2087 /* tx desc_tc{t}_credit_max[b:0] bitfield definitions 2088 * preprocessor definitions for the bitfield "desc_tc{t}_credit_max[b:0]". 2089 * parameter: tc {t} | stride size 0x4 | range [0, 7] 2090 * port="pif_tps_desc_tc0_credit_max_i[11:0]" 2091 */ 2092 2093 /* register address for bitfield desc_tc{t}_credit_max[b:0] */ 2094 #define tps_desc_tctcredit_max_adr(tc) (0x00007210 + (tc) * 0x4) 2095 /* bitmask for bitfield desc_tc{t}_credit_max[b:0] */ 2096 #define tps_desc_tctcredit_max_msk 0x0fff0000 2097 /* inverted bitmask for bitfield desc_tc{t}_credit_max[b:0] */ 2098 #define tps_desc_tctcredit_max_mskn 0xf000ffff 2099 /* lower bit position of bitfield desc_tc{t}_credit_max[b:0] */ 2100 #define tps_desc_tctcredit_max_shift 16 2101 /* width of bitfield desc_tc{t}_credit_max[b:0] */ 2102 #define tps_desc_tctcredit_max_width 12 2103 /* default value of bitfield desc_tc{t}_credit_max[b:0] */ 2104 #define tps_desc_tctcredit_max_default 0x0 2105 2106 /* tx desc_tc{t}_weight[8:0] bitfield definitions 2107 * preprocessor definitions for the bitfield "desc_tc{t}_weight[8:0]". 2108 * parameter: tc {t} | stride size 0x4 | range [0, 7] 2109 * port="pif_tps_desc_tc0_weight_i[8:0]" 2110 */ 2111 2112 /* register address for bitfield desc_tc{t}_weight[8:0] */ 2113 #define tps_desc_tctweight_adr(tc) (0x00007210 + (tc) * 0x4) 2114 /* bitmask for bitfield desc_tc{t}_weight[8:0] */ 2115 #define tps_desc_tctweight_msk 0x000001ff 2116 /* inverted bitmask for bitfield desc_tc{t}_weight[8:0] */ 2117 #define tps_desc_tctweight_mskn 0xfffffe00 2118 /* lower bit position of bitfield desc_tc{t}_weight[8:0] */ 2119 #define tps_desc_tctweight_shift 0 2120 /* width of bitfield desc_tc{t}_weight[8:0] */ 2121 #define tps_desc_tctweight_width 9 2122 /* default value of bitfield desc_tc{t}_weight[8:0] */ 2123 #define tps_desc_tctweight_default 0x0 2124 2125 /* tx desc_vm_arb_mode bitfield definitions 2126 * preprocessor definitions for the bitfield "desc_vm_arb_mode". 2127 * port="pif_tps_desc_vm_arb_mode_i" 2128 */ 2129 2130 /* register address for bitfield desc_vm_arb_mode */ 2131 #define tps_desc_vm_arb_mode_adr 0x00007300 2132 /* bitmask for bitfield desc_vm_arb_mode */ 2133 #define tps_desc_vm_arb_mode_msk 0x00000001 2134 /* inverted bitmask for bitfield desc_vm_arb_mode */ 2135 #define tps_desc_vm_arb_mode_mskn 0xfffffffe 2136 /* lower bit position of bitfield desc_vm_arb_mode */ 2137 #define tps_desc_vm_arb_mode_shift 0 2138 /* width of bitfield desc_vm_arb_mode */ 2139 #define tps_desc_vm_arb_mode_width 1 2140 /* default value of bitfield desc_vm_arb_mode */ 2141 #define tps_desc_vm_arb_mode_default 0x0 2142 2143 /* tx data_tc{t}_credit_max[b:0] bitfield definitions 2144 * preprocessor definitions for the bitfield "data_tc{t}_credit_max[b:0]". 2145 * parameter: tc {t} | stride size 0x4 | range [0, 7] 2146 * port="pif_tps_data_tc0_credit_max_i[11:0]" 2147 */ 2148 2149 /* register address for bitfield data_tc{t}_credit_max[b:0] */ 2150 #define tps_data_tctcredit_max_adr(tc) (0x00007110 + (tc) * 0x4) 2151 /* bitmask for bitfield data_tc{t}_credit_max[b:0] */ 2152 #define tps_data_tctcredit_max_msk 0x0fff0000 2153 /* inverted bitmask for bitfield data_tc{t}_credit_max[b:0] */ 2154 #define tps_data_tctcredit_max_mskn 0xf000ffff 2155 /* lower bit position of bitfield data_tc{t}_credit_max[b:0] */ 2156 #define tps_data_tctcredit_max_shift 16 2157 /* width of bitfield data_tc{t}_credit_max[b:0] */ 2158 #define tps_data_tctcredit_max_width 12 2159 /* default value of bitfield data_tc{t}_credit_max[b:0] */ 2160 #define tps_data_tctcredit_max_default 0x0 2161 2162 /* tx data_tc{t}_weight[8:0] bitfield definitions 2163 * preprocessor definitions for the bitfield "data_tc{t}_weight[8:0]". 2164 * parameter: tc {t} | stride size 0x4 | range [0, 7] 2165 * port="pif_tps_data_tc0_weight_i[8:0]" 2166 */ 2167 2168 /* register address for bitfield data_tc{t}_weight[8:0] */ 2169 #define tps_data_tctweight_adr(tc) (0x00007110 + (tc) * 0x4) 2170 /* bitmask for bitfield data_tc{t}_weight[8:0] */ 2171 #define tps_data_tctweight_msk 0x000001ff 2172 /* inverted bitmask for bitfield data_tc{t}_weight[8:0] */ 2173 #define tps_data_tctweight_mskn 0xfffffe00 2174 /* lower bit position of bitfield data_tc{t}_weight[8:0] */ 2175 #define tps_data_tctweight_shift 0 2176 /* width of bitfield data_tc{t}_weight[8:0] */ 2177 #define tps_data_tctweight_width 9 2178 /* default value of bitfield data_tc{t}_weight[8:0] */ 2179 #define tps_data_tctweight_default 0x0 2180 2181 /* tx reg_res_dsbl bitfield definitions 2182 * preprocessor definitions for the bitfield "reg_res_dsbl". 2183 * port="pif_tx_reg_res_dsbl_i" 2184 */ 2185 2186 /* register address for bitfield reg_res_dsbl */ 2187 #define tx_reg_res_dsbl_adr 0x00007000 2188 /* bitmask for bitfield reg_res_dsbl */ 2189 #define tx_reg_res_dsbl_msk 0x20000000 2190 /* inverted bitmask for bitfield reg_res_dsbl */ 2191 #define tx_reg_res_dsbl_mskn 0xdfffffff 2192 /* lower bit position of bitfield reg_res_dsbl */ 2193 #define tx_reg_res_dsbl_shift 29 2194 /* width of bitfield reg_res_dsbl */ 2195 #define tx_reg_res_dsbl_width 1 2196 /* default value of bitfield reg_res_dsbl */ 2197 #define tx_reg_res_dsbl_default 0x1 2198 2199 /* mac_phy register access busy bitfield definitions 2200 * preprocessor definitions for the bitfield "register access busy". 2201 * port="msm_pif_reg_busy_o" 2202 */ 2203 2204 /* register address for bitfield register access busy */ 2205 #define msm_reg_access_busy_adr 0x00004400 2206 /* bitmask for bitfield register access busy */ 2207 #define msm_reg_access_busy_msk 0x00001000 2208 /* inverted bitmask for bitfield register access busy */ 2209 #define msm_reg_access_busy_mskn 0xffffefff 2210 /* lower bit position of bitfield register access busy */ 2211 #define msm_reg_access_busy_shift 12 2212 /* width of bitfield register access busy */ 2213 #define msm_reg_access_busy_width 1 2214 2215 /* mac_phy msm register address[7:0] bitfield definitions 2216 * preprocessor definitions for the bitfield "msm register address[7:0]". 2217 * port="pif_msm_reg_addr_i[7:0]" 2218 */ 2219 2220 /* register address for bitfield msm register address[7:0] */ 2221 #define msm_reg_addr_adr 0x00004400 2222 /* bitmask for bitfield msm register address[7:0] */ 2223 #define msm_reg_addr_msk 0x000000ff 2224 /* inverted bitmask for bitfield msm register address[7:0] */ 2225 #define msm_reg_addr_mskn 0xffffff00 2226 /* lower bit position of bitfield msm register address[7:0] */ 2227 #define msm_reg_addr_shift 0 2228 /* width of bitfield msm register address[7:0] */ 2229 #define msm_reg_addr_width 8 2230 /* default value of bitfield msm register address[7:0] */ 2231 #define msm_reg_addr_default 0x0 2232 2233 /* mac_phy register read strobe bitfield definitions 2234 * preprocessor definitions for the bitfield "register read strobe". 2235 * port="pif_msm_reg_rden_i" 2236 */ 2237 2238 /* register address for bitfield register read strobe */ 2239 #define msm_reg_rd_strobe_adr 0x00004400 2240 /* bitmask for bitfield register read strobe */ 2241 #define msm_reg_rd_strobe_msk 0x00000200 2242 /* inverted bitmask for bitfield register read strobe */ 2243 #define msm_reg_rd_strobe_mskn 0xfffffdff 2244 /* lower bit position of bitfield register read strobe */ 2245 #define msm_reg_rd_strobe_shift 9 2246 /* width of bitfield register read strobe */ 2247 #define msm_reg_rd_strobe_width 1 2248 /* default value of bitfield register read strobe */ 2249 #define msm_reg_rd_strobe_default 0x0 2250 2251 /* mac_phy msm register read data[31:0] bitfield definitions 2252 * preprocessor definitions for the bitfield "msm register read data[31:0]". 2253 * port="msm_pif_reg_rd_data_o[31:0]" 2254 */ 2255 2256 /* register address for bitfield msm register read data[31:0] */ 2257 #define msm_reg_rd_data_adr 0x00004408 2258 /* bitmask for bitfield msm register read data[31:0] */ 2259 #define msm_reg_rd_data_msk 0xffffffff 2260 /* inverted bitmask for bitfield msm register read data[31:0] */ 2261 #define msm_reg_rd_data_mskn 0x00000000 2262 /* lower bit position of bitfield msm register read data[31:0] */ 2263 #define msm_reg_rd_data_shift 0 2264 /* width of bitfield msm register read data[31:0] */ 2265 #define msm_reg_rd_data_width 32 2266 2267 /* mac_phy msm register write data[31:0] bitfield definitions 2268 * preprocessor definitions for the bitfield "msm register write data[31:0]". 2269 * port="pif_msm_reg_wr_data_i[31:0]" 2270 */ 2271 2272 /* register address for bitfield msm register write data[31:0] */ 2273 #define msm_reg_wr_data_adr 0x00004404 2274 /* bitmask for bitfield msm register write data[31:0] */ 2275 #define msm_reg_wr_data_msk 0xffffffff 2276 /* inverted bitmask for bitfield msm register write data[31:0] */ 2277 #define msm_reg_wr_data_mskn 0x00000000 2278 /* lower bit position of bitfield msm register write data[31:0] */ 2279 #define msm_reg_wr_data_shift 0 2280 /* width of bitfield msm register write data[31:0] */ 2281 #define msm_reg_wr_data_width 32 2282 /* default value of bitfield msm register write data[31:0] */ 2283 #define msm_reg_wr_data_default 0x0 2284 2285 /* mac_phy register write strobe bitfield definitions 2286 * preprocessor definitions for the bitfield "register write strobe". 2287 * port="pif_msm_reg_wren_i" 2288 */ 2289 2290 /* register address for bitfield register write strobe */ 2291 #define msm_reg_wr_strobe_adr 0x00004400 2292 /* bitmask for bitfield register write strobe */ 2293 #define msm_reg_wr_strobe_msk 0x00000100 2294 /* inverted bitmask for bitfield register write strobe */ 2295 #define msm_reg_wr_strobe_mskn 0xfffffeff 2296 /* lower bit position of bitfield register write strobe */ 2297 #define msm_reg_wr_strobe_shift 8 2298 /* width of bitfield register write strobe */ 2299 #define msm_reg_wr_strobe_width 1 2300 /* default value of bitfield register write strobe */ 2301 #define msm_reg_wr_strobe_default 0x0 2302 2303 /* mif soft reset bitfield definitions 2304 * preprocessor definitions for the bitfield "soft reset". 2305 * port="pif_glb_res_i" 2306 */ 2307 2308 /* register address for bitfield soft reset */ 2309 #define glb_soft_res_adr 0x00000000 2310 /* bitmask for bitfield soft reset */ 2311 #define glb_soft_res_msk 0x00008000 2312 /* inverted bitmask for bitfield soft reset */ 2313 #define glb_soft_res_mskn 0xffff7fff 2314 /* lower bit position of bitfield soft reset */ 2315 #define glb_soft_res_shift 15 2316 /* width of bitfield soft reset */ 2317 #define glb_soft_res_width 1 2318 /* default value of bitfield soft reset */ 2319 #define glb_soft_res_default 0x0 2320 2321 /* mif register reset disable bitfield definitions 2322 * preprocessor definitions for the bitfield "register reset disable". 2323 * port="pif_glb_reg_res_dsbl_i" 2324 */ 2325 2326 /* register address for bitfield register reset disable */ 2327 #define glb_reg_res_dis_adr 0x00000000 2328 /* bitmask for bitfield register reset disable */ 2329 #define glb_reg_res_dis_msk 0x00004000 2330 /* inverted bitmask for bitfield register reset disable */ 2331 #define glb_reg_res_dis_mskn 0xffffbfff 2332 /* lower bit position of bitfield register reset disable */ 2333 #define glb_reg_res_dis_shift 14 2334 /* width of bitfield register reset disable */ 2335 #define glb_reg_res_dis_width 1 2336 /* default value of bitfield register reset disable */ 2337 #define glb_reg_res_dis_default 0x1 2338 2339 /* tx dma debug control definitions */ 2340 #define tx_dma_debug_ctl_adr 0x00008920u 2341 2342 /* tx dma descriptor base address msw definitions */ 2343 #define tx_dma_desc_base_addrmsw_adr(descriptor) \ 2344 (0x00007c04u + (descriptor) * 0x40) 2345 2346 /* tx interrupt moderation control register definitions 2347 * Preprocessor definitions for TX Interrupt Moderation Control Register 2348 * Base Address: 0x00008980 2349 * Parameter: queue {Q} | stride size 0x4 | range [0, 31] 2350 */ 2351 2352 #define tx_intr_moderation_ctl_adr(queue) (0x00008980u + (queue) * 0x4) 2353 2354 /* pcie reg_res_dsbl bitfield definitions 2355 * preprocessor definitions for the bitfield "reg_res_dsbl". 2356 * port="pif_pci_reg_res_dsbl_i" 2357 */ 2358 2359 /* register address for bitfield reg_res_dsbl */ 2360 #define pci_reg_res_dsbl_adr 0x00001000 2361 /* bitmask for bitfield reg_res_dsbl */ 2362 #define pci_reg_res_dsbl_msk 0x20000000 2363 /* inverted bitmask for bitfield reg_res_dsbl */ 2364 #define pci_reg_res_dsbl_mskn 0xdfffffff 2365 /* lower bit position of bitfield reg_res_dsbl */ 2366 #define pci_reg_res_dsbl_shift 29 2367 /* width of bitfield reg_res_dsbl */ 2368 #define pci_reg_res_dsbl_width 1 2369 /* default value of bitfield reg_res_dsbl */ 2370 #define pci_reg_res_dsbl_default 0x1 2371 2372 /* global microprocessor scratch pad definitions */ 2373 #define glb_cpu_scratch_scp_adr(scratch_scp) (0x00000300u + (scratch_scp) * 0x4) 2374 2375 #endif /* HW_ATL_LLH_INTERNAL_H */ 2376