1bab6de8fSDavid VomLehn /* 2bab6de8fSDavid VomLehn * aQuantia Corporation Network Driver 3bab6de8fSDavid VomLehn * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved 4bab6de8fSDavid VomLehn * 5bab6de8fSDavid VomLehn * This program is free software; you can redistribute it and/or modify it 6bab6de8fSDavid VomLehn * under the terms and conditions of the GNU General Public License, 7bab6de8fSDavid VomLehn * version 2, as published by the Free Software Foundation. 8bab6de8fSDavid VomLehn */ 9bab6de8fSDavid VomLehn 10bab6de8fSDavid VomLehn /* File hw_atl_b0_internal.h: Definition of Atlantic B0 chip specific 11bab6de8fSDavid VomLehn * constants. 12bab6de8fSDavid VomLehn */ 13bab6de8fSDavid VomLehn 14bab6de8fSDavid VomLehn #ifndef HW_ATL_B0_INTERNAL_H 15bab6de8fSDavid VomLehn #define HW_ATL_B0_INTERNAL_H 16bab6de8fSDavid VomLehn 17bab6de8fSDavid VomLehn #include "../aq_common.h" 18bab6de8fSDavid VomLehn 19d85fc17bSIgor Russkikh #define HW_ATL_B0_MTU_JUMBO 16352U 20bab6de8fSDavid VomLehn #define HW_ATL_B0_MTU 1514U 21bab6de8fSDavid VomLehn 22bab6de8fSDavid VomLehn #define HW_ATL_B0_TX_RINGS 4U 23bab6de8fSDavid VomLehn #define HW_ATL_B0_RX_RINGS 4U 24bab6de8fSDavid VomLehn 25bab6de8fSDavid VomLehn #define HW_ATL_B0_RINGS_MAX 32U 26bab6de8fSDavid VomLehn #define HW_ATL_B0_TXD_SIZE (16U) 27bab6de8fSDavid VomLehn #define HW_ATL_B0_RXD_SIZE (16U) 28bab6de8fSDavid VomLehn 29bab6de8fSDavid VomLehn #define HW_ATL_B0_MAC 0U 30bab6de8fSDavid VomLehn #define HW_ATL_B0_MAC_MIN 1U 31bab6de8fSDavid VomLehn #define HW_ATL_B0_MAC_MAX 33U 32bab6de8fSDavid VomLehn 33bab6de8fSDavid VomLehn /* UCAST/MCAST filters */ 34bab6de8fSDavid VomLehn #define HW_ATL_B0_UCAST_FILTERS_MAX 38 35bab6de8fSDavid VomLehn #define HW_ATL_B0_MCAST_FILTERS_MAX 8 36bab6de8fSDavid VomLehn 37bab6de8fSDavid VomLehn /* interrupts */ 38bab6de8fSDavid VomLehn #define HW_ATL_B0_ERR_INT 8U 39bab6de8fSDavid VomLehn #define HW_ATL_B0_INT_MASK (0xFFFFFFFFU) 40bab6de8fSDavid VomLehn 41bab6de8fSDavid VomLehn #define HW_ATL_B0_TXD_CTL2_LEN (0xFFFFC000) 42bab6de8fSDavid VomLehn #define HW_ATL_B0_TXD_CTL2_CTX_EN (0x00002000) 43bab6de8fSDavid VomLehn #define HW_ATL_B0_TXD_CTL2_CTX_IDX (0x00001000) 44bab6de8fSDavid VomLehn 45bab6de8fSDavid VomLehn #define HW_ATL_B0_TXD_CTL_DESC_TYPE_TXD (0x00000001) 46bab6de8fSDavid VomLehn #define HW_ATL_B0_TXD_CTL_DESC_TYPE_TXC (0x00000002) 47bab6de8fSDavid VomLehn #define HW_ATL_B0_TXD_CTL_BLEN (0x000FFFF0) 48bab6de8fSDavid VomLehn #define HW_ATL_B0_TXD_CTL_DD (0x00100000) 49bab6de8fSDavid VomLehn #define HW_ATL_B0_TXD_CTL_EOP (0x00200000) 50bab6de8fSDavid VomLehn 51bab6de8fSDavid VomLehn #define HW_ATL_B0_TXD_CTL_CMD_X (0x3FC00000) 52bab6de8fSDavid VomLehn 53bab6de8fSDavid VomLehn #define HW_ATL_B0_TXD_CTL_CMD_VLAN BIT(22) 54bab6de8fSDavid VomLehn #define HW_ATL_B0_TXD_CTL_CMD_FCS BIT(23) 55bab6de8fSDavid VomLehn #define HW_ATL_B0_TXD_CTL_CMD_IPCSO BIT(24) 56bab6de8fSDavid VomLehn #define HW_ATL_B0_TXD_CTL_CMD_TUCSO BIT(25) 57bab6de8fSDavid VomLehn #define HW_ATL_B0_TXD_CTL_CMD_LSO BIT(26) 58bab6de8fSDavid VomLehn #define HW_ATL_B0_TXD_CTL_CMD_WB BIT(27) 59bab6de8fSDavid VomLehn #define HW_ATL_B0_TXD_CTL_CMD_VXLAN BIT(28) 60bab6de8fSDavid VomLehn 61bab6de8fSDavid VomLehn #define HW_ATL_B0_TXD_CTL_CMD_IPV6 BIT(21) 62bab6de8fSDavid VomLehn #define HW_ATL_B0_TXD_CTL_CMD_TCP BIT(22) 63bab6de8fSDavid VomLehn 64bab6de8fSDavid VomLehn #define HW_ATL_B0_MPI_CONTROL_ADR 0x0368U 65bab6de8fSDavid VomLehn #define HW_ATL_B0_MPI_STATE_ADR 0x036CU 66bab6de8fSDavid VomLehn 67bab6de8fSDavid VomLehn #define HW_ATL_B0_MPI_SPEED_MSK 0xFFFFU 68bab6de8fSDavid VomLehn #define HW_ATL_B0_MPI_SPEED_SHIFT 16U 69bab6de8fSDavid VomLehn 70bab6de8fSDavid VomLehn #define HW_ATL_B0_RATE_10G BIT(0) 71bab6de8fSDavid VomLehn #define HW_ATL_B0_RATE_5G BIT(1) 72bab6de8fSDavid VomLehn #define HW_ATL_B0_RATE_2G5 BIT(3) 73bab6de8fSDavid VomLehn #define HW_ATL_B0_RATE_1G BIT(4) 74bab6de8fSDavid VomLehn #define HW_ATL_B0_RATE_100M BIT(5) 75bab6de8fSDavid VomLehn 76bab6de8fSDavid VomLehn #define HW_ATL_B0_TXBUF_MAX 160U 77bab6de8fSDavid VomLehn #define HW_ATL_B0_RXBUF_MAX 320U 78bab6de8fSDavid VomLehn 79bab6de8fSDavid VomLehn #define HW_ATL_B0_RSS_REDIRECTION_MAX 64U 80bab6de8fSDavid VomLehn #define HW_ATL_B0_RSS_REDIRECTION_BITS 3U 81bab6de8fSDavid VomLehn #define HW_ATL_B0_RSS_HASHKEY_BITS 320U 82bab6de8fSDavid VomLehn 83bab6de8fSDavid VomLehn #define HW_ATL_B0_TCRSS_4_8 1 84bab6de8fSDavid VomLehn #define HW_ATL_B0_TC_MAX 1U 85bab6de8fSDavid VomLehn #define HW_ATL_B0_RSS_MAX 8U 86bab6de8fSDavid VomLehn 87bab6de8fSDavid VomLehn #define HW_ATL_B0_LRO_RXD_MAX 2U 88bab6de8fSDavid VomLehn #define HW_ATL_B0_RS_SLIP_ENABLED 0U 89bab6de8fSDavid VomLehn 90bab6de8fSDavid VomLehn /* (256k -1(max pay_len) - 54(header)) */ 91bab6de8fSDavid VomLehn #define HAL_ATL_B0_LSO_MAX_SEGMENT_SIZE 262089U 92bab6de8fSDavid VomLehn 93bab6de8fSDavid VomLehn /* (256k -1(max pay_len) - 74(header)) */ 94bab6de8fSDavid VomLehn #define HAL_ATL_B0_LSO_IPV6_MAX_SEGMENT_SIZE 262069U 95bab6de8fSDavid VomLehn 96bab6de8fSDavid VomLehn #define HW_ATL_B0_CHIP_REVISION_B0 0xA0U 97bab6de8fSDavid VomLehn #define HW_ATL_B0_CHIP_REVISION_UNKNOWN 0xFFU 98bab6de8fSDavid VomLehn 99bab6de8fSDavid VomLehn #define HW_ATL_B0_FW_SEMA_RAM 0x2U 100bab6de8fSDavid VomLehn 101bab6de8fSDavid VomLehn #define HW_ATL_B0_TXC_LEN_TUNLEN (0x0000FF00) 102bab6de8fSDavid VomLehn #define HW_ATL_B0_TXC_LEN_OUTLEN (0xFFFF0000) 103bab6de8fSDavid VomLehn 104bab6de8fSDavid VomLehn #define HW_ATL_B0_TXC_CTL_DESC_TYPE (0x00000007) 105bab6de8fSDavid VomLehn #define HW_ATL_B0_TXC_CTL_CTX_ID (0x00000008) 106bab6de8fSDavid VomLehn #define HW_ATL_B0_TXC_CTL_VLAN (0x000FFFF0) 107bab6de8fSDavid VomLehn #define HW_ATL_B0_TXC_CTL_CMD (0x00F00000) 108bab6de8fSDavid VomLehn #define HW_ATL_B0_TXC_CTL_L2LEN (0x7F000000) 109bab6de8fSDavid VomLehn 110bab6de8fSDavid VomLehn #define HW_ATL_B0_TXC_CTL_L3LEN (0x80000000) /* L3LEN lsb */ 111bab6de8fSDavid VomLehn #define HW_ATL_B0_TXC_LEN2_L3LEN (0x000000FF) /* L3LE upper bits */ 112bab6de8fSDavid VomLehn #define HW_ATL_B0_TXC_LEN2_L4LEN (0x0000FF00) 113bab6de8fSDavid VomLehn #define HW_ATL_B0_TXC_LEN2_MSSLEN (0xFFFF0000) 114bab6de8fSDavid VomLehn 115bab6de8fSDavid VomLehn #define HW_ATL_B0_RXD_DD (0x1) 116bab6de8fSDavid VomLehn #define HW_ATL_B0_RXD_NCEA0 (0x1) 117bab6de8fSDavid VomLehn 118bab6de8fSDavid VomLehn #define HW_ATL_B0_RXD_WB_STAT_RSSTYPE (0x0000000F) 119bab6de8fSDavid VomLehn #define HW_ATL_B0_RXD_WB_STAT_PKTTYPE (0x00000FF0) 120bab6de8fSDavid VomLehn #define HW_ATL_B0_RXD_WB_STAT_RXCTRL (0x00180000) 121bab6de8fSDavid VomLehn #define HW_ATL_B0_RXD_WB_STAT_SPLHDR (0x00200000) 122bab6de8fSDavid VomLehn #define HW_ATL_B0_RXD_WB_STAT_HDRLEN (0xFFC00000) 123bab6de8fSDavid VomLehn 124bab6de8fSDavid VomLehn #define HW_ATL_B0_RXD_WB_STAT2_DD (0x0001) 125bab6de8fSDavid VomLehn #define HW_ATL_B0_RXD_WB_STAT2_EOP (0x0002) 126bab6de8fSDavid VomLehn #define HW_ATL_B0_RXD_WB_STAT2_RXSTAT (0x003C) 127bab6de8fSDavid VomLehn #define HW_ATL_B0_RXD_WB_STAT2_MACERR (0x0004) 128bab6de8fSDavid VomLehn #define HW_ATL_B0_RXD_WB_STAT2_IP4ERR (0x0008) 129bab6de8fSDavid VomLehn #define HW_ATL_B0_RXD_WB_STAT2_TCPUPDERR (0x0010) 130bab6de8fSDavid VomLehn #define HW_ATL_B0_RXD_WB_STAT2_RXESTAT (0x0FC0) 131bab6de8fSDavid VomLehn #define HW_ATL_B0_RXD_WB_STAT2_RSCCNT (0xF000) 132bab6de8fSDavid VomLehn 133bab6de8fSDavid VomLehn #define L2_FILTER_ACTION_DISCARD (0x0) 134bab6de8fSDavid VomLehn #define L2_FILTER_ACTION_HOST (0x1) 135bab6de8fSDavid VomLehn 136bab6de8fSDavid VomLehn #define HW_ATL_B0_UCP_0X370_REG (0x370) 137bab6de8fSDavid VomLehn 138bab6de8fSDavid VomLehn #define HW_ATL_B0_FLUSH() AQ_HW_READ_REG(self, 0x10) 139bab6de8fSDavid VomLehn 140bab6de8fSDavid VomLehn #define HW_ATL_B0_FW_VER_EXPECTED 0x01050006U 141bab6de8fSDavid VomLehn 142bab6de8fSDavid VomLehn /* Hardware tx descriptor */ 143bab6de8fSDavid VomLehn struct __packed hw_atl_txd_s { 144bab6de8fSDavid VomLehn u64 buf_addr; 145bab6de8fSDavid VomLehn u32 ctl; 146bab6de8fSDavid VomLehn u32 ctl2; /* 63..46 - payload length, 45 - ctx enable, 44 - ctx index */ 147bab6de8fSDavid VomLehn }; 148bab6de8fSDavid VomLehn 149bab6de8fSDavid VomLehn /* Hardware tx context descriptor */ 150bab6de8fSDavid VomLehn struct __packed hw_atl_txc_s { 151bab6de8fSDavid VomLehn u32 rsvd; 152bab6de8fSDavid VomLehn u32 len; 153bab6de8fSDavid VomLehn u32 ctl; 154bab6de8fSDavid VomLehn u32 len2; 155bab6de8fSDavid VomLehn }; 156bab6de8fSDavid VomLehn 157bab6de8fSDavid VomLehn /* Hardware rx descriptor */ 158bab6de8fSDavid VomLehn struct __packed hw_atl_rxd_s { 159bab6de8fSDavid VomLehn u64 buf_addr; 160bab6de8fSDavid VomLehn u64 hdr_addr; 161bab6de8fSDavid VomLehn }; 162bab6de8fSDavid VomLehn 163bab6de8fSDavid VomLehn /* Hardware rx descriptor writeback */ 164bab6de8fSDavid VomLehn struct __packed hw_atl_rxd_wb_s { 165bab6de8fSDavid VomLehn u32 type; 166bab6de8fSDavid VomLehn u32 rss_hash; 167bab6de8fSDavid VomLehn u16 status; 168bab6de8fSDavid VomLehn u16 pkt_len; 169bab6de8fSDavid VomLehn u16 next_desc_ptr; 170bab6de8fSDavid VomLehn u16 vlan; 171bab6de8fSDavid VomLehn }; 172bab6de8fSDavid VomLehn 173bab6de8fSDavid VomLehn /* HW layer capabilities */ 174bab6de8fSDavid VomLehn static struct aq_hw_caps_s hw_atl_b0_hw_caps_ = { 175bab6de8fSDavid VomLehn .ports = 1U, 176bab6de8fSDavid VomLehn .is_64_dma = true, 177bab6de8fSDavid VomLehn .msix_irqs = 4U, 178bab6de8fSDavid VomLehn .irq_mask = ~0U, 179bab6de8fSDavid VomLehn .vecs = HW_ATL_B0_RSS_MAX, 180bab6de8fSDavid VomLehn .tcs = HW_ATL_B0_TC_MAX, 181bab6de8fSDavid VomLehn .rxd_alignment = 1U, 182bab6de8fSDavid VomLehn .rxd_size = HW_ATL_B0_RXD_SIZE, 183bab6de8fSDavid VomLehn .rxds = 8U * 1024U, 184bab6de8fSDavid VomLehn .txd_alignment = 1U, 185bab6de8fSDavid VomLehn .txd_size = HW_ATL_B0_TXD_SIZE, 186bab6de8fSDavid VomLehn .txds = 8U * 1024U, 187bab6de8fSDavid VomLehn .txhwb_alignment = 4096U, 188bab6de8fSDavid VomLehn .tx_rings = HW_ATL_B0_TX_RINGS, 189bab6de8fSDavid VomLehn .rx_rings = HW_ATL_B0_RX_RINGS, 190bab6de8fSDavid VomLehn .hw_features = NETIF_F_HW_CSUM | 19168c38659SPavel Belous NETIF_F_RXCSUM | 192bab6de8fSDavid VomLehn NETIF_F_RXHASH | 193bab6de8fSDavid VomLehn NETIF_F_SG | 194bab6de8fSDavid VomLehn NETIF_F_TSO | 195bab6de8fSDavid VomLehn NETIF_F_LRO, 196bab6de8fSDavid VomLehn .hw_priv_flags = IFF_UNICAST_FLT, 197bab6de8fSDavid VomLehn .link_speed_msk = (HW_ATL_B0_RATE_10G | 198bab6de8fSDavid VomLehn HW_ATL_B0_RATE_5G | 199bab6de8fSDavid VomLehn HW_ATL_B0_RATE_2G5 | 200bab6de8fSDavid VomLehn HW_ATL_B0_RATE_1G | 201bab6de8fSDavid VomLehn HW_ATL_B0_RATE_100M), 202bab6de8fSDavid VomLehn .flow_control = true, 203bab6de8fSDavid VomLehn .mtu = HW_ATL_B0_MTU_JUMBO, 204bab6de8fSDavid VomLehn .mac_regs_count = 88, 205bab6de8fSDavid VomLehn .fw_ver_expected = HW_ATL_B0_FW_VER_EXPECTED, 206bab6de8fSDavid VomLehn }; 207bab6de8fSDavid VomLehn 208bab6de8fSDavid VomLehn #endif /* HW_ATL_B0_INTERNAL_H */ 209