1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Atlantic Network Driver 3 * 4 * Copyright (C) 2014-2019 aQuantia Corporation 5 * Copyright (C) 2019-2020 Marvell International Ltd. 6 */ 7 8 /* File hw_atl_b0.c: Definition of Atlantic hardware specific functions. */ 9 10 #include "../aq_hw.h" 11 #include "../aq_hw_utils.h" 12 #include "../aq_ring.h" 13 #include "../aq_nic.h" 14 #include "../aq_phy.h" 15 #include "hw_atl_b0.h" 16 #include "hw_atl_utils.h" 17 #include "hw_atl_llh.h" 18 #include "hw_atl_b0_internal.h" 19 #include "hw_atl_llh_internal.h" 20 21 #define DEFAULT_B0_BOARD_BASIC_CAPABILITIES \ 22 .is_64_dma = true, \ 23 .msix_irqs = 8U, \ 24 .irq_mask = ~0U, \ 25 .vecs = HW_ATL_B0_RSS_MAX, \ 26 .tcs_max = HW_ATL_B0_TC_MAX, \ 27 .rxd_alignment = 1U, \ 28 .rxd_size = HW_ATL_B0_RXD_SIZE, \ 29 .rxds_max = HW_ATL_B0_MAX_RXD, \ 30 .rxds_min = HW_ATL_B0_MIN_RXD, \ 31 .txd_alignment = 1U, \ 32 .txd_size = HW_ATL_B0_TXD_SIZE, \ 33 .txds_max = HW_ATL_B0_MAX_TXD, \ 34 .txds_min = HW_ATL_B0_MIN_TXD, \ 35 .txhwb_alignment = 4096U, \ 36 .tx_rings = HW_ATL_B0_TX_RINGS, \ 37 .rx_rings = HW_ATL_B0_RX_RINGS, \ 38 .hw_features = NETIF_F_HW_CSUM | \ 39 NETIF_F_RXCSUM | \ 40 NETIF_F_RXHASH | \ 41 NETIF_F_SG | \ 42 NETIF_F_TSO | \ 43 NETIF_F_LRO | \ 44 NETIF_F_NTUPLE | \ 45 NETIF_F_HW_VLAN_CTAG_FILTER | \ 46 NETIF_F_HW_VLAN_CTAG_RX | \ 47 NETIF_F_HW_VLAN_CTAG_TX | \ 48 NETIF_F_GSO_UDP_L4 | \ 49 NETIF_F_GSO_PARTIAL | \ 50 NETIF_F_HW_TC, \ 51 .hw_priv_flags = IFF_UNICAST_FLT, \ 52 .flow_control = true, \ 53 .mtu = HW_ATL_B0_MTU_JUMBO, \ 54 .mac_regs_count = 88, \ 55 .hw_alive_check_addr = 0x10U 56 57 #define FRAC_PER_NS 0x100000000LL 58 59 const struct aq_hw_caps_s hw_atl_b0_caps_aqc100 = { 60 DEFAULT_B0_BOARD_BASIC_CAPABILITIES, 61 .media_type = AQ_HW_MEDIA_TYPE_FIBRE, 62 .link_speed_msk = AQ_NIC_RATE_10G | 63 AQ_NIC_RATE_5G | 64 AQ_NIC_RATE_2G5 | 65 AQ_NIC_RATE_1G | 66 AQ_NIC_RATE_100M, 67 }; 68 69 const struct aq_hw_caps_s hw_atl_b0_caps_aqc107 = { 70 DEFAULT_B0_BOARD_BASIC_CAPABILITIES, 71 .media_type = AQ_HW_MEDIA_TYPE_TP, 72 .link_speed_msk = AQ_NIC_RATE_10G | 73 AQ_NIC_RATE_5G | 74 AQ_NIC_RATE_2G5 | 75 AQ_NIC_RATE_1G | 76 AQ_NIC_RATE_100M, 77 }; 78 79 const struct aq_hw_caps_s hw_atl_b0_caps_aqc108 = { 80 DEFAULT_B0_BOARD_BASIC_CAPABILITIES, 81 .media_type = AQ_HW_MEDIA_TYPE_TP, 82 .link_speed_msk = AQ_NIC_RATE_5G | 83 AQ_NIC_RATE_2G5 | 84 AQ_NIC_RATE_1G | 85 AQ_NIC_RATE_100M, 86 }; 87 88 const struct aq_hw_caps_s hw_atl_b0_caps_aqc109 = { 89 DEFAULT_B0_BOARD_BASIC_CAPABILITIES, 90 .media_type = AQ_HW_MEDIA_TYPE_TP, 91 .link_speed_msk = AQ_NIC_RATE_2G5 | 92 AQ_NIC_RATE_1G | 93 AQ_NIC_RATE_100M, 94 }; 95 96 static int hw_atl_b0_hw_reset(struct aq_hw_s *self) 97 { 98 int err = 0; 99 100 err = hw_atl_utils_soft_reset(self); 101 if (err) 102 return err; 103 104 self->aq_fw_ops->set_state(self, MPI_RESET); 105 106 err = aq_hw_err_from_flags(self); 107 108 return err; 109 } 110 111 static int hw_atl_b0_set_fc(struct aq_hw_s *self, u32 fc, u32 tc) 112 { 113 hw_atl_rpb_rx_xoff_en_per_tc_set(self, !!(fc & AQ_NIC_FC_RX), tc); 114 115 return 0; 116 } 117 118 static int hw_atl_b0_tc_ptp_set(struct aq_hw_s *self) 119 { 120 /* Init TC2 for PTP_TX */ 121 hw_atl_tpb_tx_pkt_buff_size_per_tc_set(self, HW_ATL_B0_PTP_TXBUF_SIZE, 122 AQ_HW_PTP_TC); 123 124 /* Init TC2 for PTP_RX */ 125 hw_atl_rpb_rx_pkt_buff_size_per_tc_set(self, HW_ATL_B0_PTP_RXBUF_SIZE, 126 AQ_HW_PTP_TC); 127 /* No flow control for PTP */ 128 hw_atl_rpb_rx_xoff_en_per_tc_set(self, 0U, AQ_HW_PTP_TC); 129 130 return aq_hw_err_from_flags(self); 131 } 132 133 static int hw_atl_b0_hw_qos_set(struct aq_hw_s *self) 134 { 135 struct aq_nic_cfg_s *cfg = self->aq_nic_cfg; 136 u32 tx_buff_size = HW_ATL_B0_TXBUF_MAX; 137 u32 rx_buff_size = HW_ATL_B0_RXBUF_MAX; 138 unsigned int prio = 0U; 139 u32 tc = 0U; 140 141 if (cfg->is_ptp) { 142 tx_buff_size -= HW_ATL_B0_PTP_TXBUF_SIZE; 143 rx_buff_size -= HW_ATL_B0_PTP_RXBUF_SIZE; 144 } 145 146 /* TPS Descriptor rate init */ 147 hw_atl_tps_tx_pkt_shed_desc_rate_curr_time_res_set(self, 0x0U); 148 hw_atl_tps_tx_pkt_shed_desc_rate_lim_set(self, 0xA); 149 150 /* TPS VM init */ 151 hw_atl_tps_tx_pkt_shed_desc_vm_arb_mode_set(self, 0U); 152 153 tx_buff_size /= cfg->tcs; 154 rx_buff_size /= cfg->tcs; 155 for (tc = 0; tc < cfg->tcs; tc++) { 156 u32 threshold = 0U; 157 158 /* Tx buf size TC0 */ 159 hw_atl_tpb_tx_pkt_buff_size_per_tc_set(self, tx_buff_size, tc); 160 161 threshold = (tx_buff_size * (1024 / 32U) * 66U) / 100U; 162 hw_atl_tpb_tx_buff_hi_threshold_per_tc_set(self, threshold, tc); 163 164 threshold = (tx_buff_size * (1024 / 32U) * 50U) / 100U; 165 hw_atl_tpb_tx_buff_lo_threshold_per_tc_set(self, threshold, tc); 166 167 /* QoS Rx buf size per TC */ 168 hw_atl_rpb_rx_pkt_buff_size_per_tc_set(self, rx_buff_size, tc); 169 170 threshold = (rx_buff_size * (1024U / 32U) * 66U) / 100U; 171 hw_atl_rpb_rx_buff_hi_threshold_per_tc_set(self, threshold, tc); 172 173 threshold = (rx_buff_size * (1024U / 32U) * 50U) / 100U; 174 hw_atl_rpb_rx_buff_lo_threshold_per_tc_set(self, threshold, tc); 175 176 hw_atl_b0_set_fc(self, self->aq_nic_cfg->fc.req, tc); 177 } 178 179 if (cfg->is_ptp) 180 hw_atl_b0_tc_ptp_set(self); 181 182 /* QoS 802.1p priority -> TC mapping */ 183 for (prio = 0; prio < 8; ++prio) 184 hw_atl_rpf_rpb_user_priority_tc_map_set(self, prio, 185 cfg->prio_tc_map[prio]); 186 187 return aq_hw_err_from_flags(self); 188 } 189 190 int hw_atl_b0_hw_rss_hash_set(struct aq_hw_s *self, 191 struct aq_rss_parameters *rss_params) 192 { 193 struct aq_nic_cfg_s *cfg = self->aq_nic_cfg; 194 unsigned int addr = 0U; 195 unsigned int i = 0U; 196 int err = 0; 197 u32 val; 198 199 for (i = 10, addr = 0U; i--; ++addr) { 200 u32 key_data = cfg->is_rss ? 201 __swab32(rss_params->hash_secret_key[i]) : 0U; 202 hw_atl_rpf_rss_key_wr_data_set(self, key_data); 203 hw_atl_rpf_rss_key_addr_set(self, addr); 204 hw_atl_rpf_rss_key_wr_en_set(self, 1U); 205 err = readx_poll_timeout_atomic(hw_atl_rpf_rss_key_wr_en_get, 206 self, val, val == 0, 207 1000U, 10000U); 208 if (err < 0) 209 goto err_exit; 210 } 211 212 err = aq_hw_err_from_flags(self); 213 214 err_exit: 215 return err; 216 } 217 218 static int hw_atl_b0_hw_rss_set(struct aq_hw_s *self, 219 struct aq_rss_parameters *rss_params) 220 { 221 u32 num_rss_queues = max(1U, self->aq_nic_cfg->num_rss_queues); 222 u8 *indirection_table = rss_params->indirection_table; 223 u16 bitary[1 + (HW_ATL_B0_RSS_REDIRECTION_MAX * 224 HW_ATL_B0_RSS_REDIRECTION_BITS / 16U)]; 225 int err = 0; 226 u32 i = 0U; 227 u32 val; 228 229 memset(bitary, 0, sizeof(bitary)); 230 231 for (i = HW_ATL_B0_RSS_REDIRECTION_MAX; i--;) { 232 (*(u32 *)(bitary + ((i * 3U) / 16U))) |= 233 ((indirection_table[i] % num_rss_queues) << 234 ((i * 3U) & 0xFU)); 235 } 236 237 for (i = ARRAY_SIZE(bitary); i--;) { 238 hw_atl_rpf_rss_redir_tbl_wr_data_set(self, bitary[i]); 239 hw_atl_rpf_rss_redir_tbl_addr_set(self, i); 240 hw_atl_rpf_rss_redir_wr_en_set(self, 1U); 241 err = readx_poll_timeout_atomic(hw_atl_rpf_rss_redir_wr_en_get, 242 self, val, val == 0, 243 1000U, 10000U); 244 if (err < 0) 245 goto err_exit; 246 } 247 248 err = aq_hw_err_from_flags(self); 249 250 err_exit: 251 return err; 252 } 253 254 int hw_atl_b0_hw_offload_set(struct aq_hw_s *self, 255 struct aq_nic_cfg_s *aq_nic_cfg) 256 { 257 u64 rxcsum = !!(aq_nic_cfg->features & NETIF_F_RXCSUM); 258 unsigned int i; 259 260 /* TX checksums offloads*/ 261 hw_atl_tpo_ipv4header_crc_offload_en_set(self, 1); 262 hw_atl_tpo_tcp_udp_crc_offload_en_set(self, 1); 263 264 /* RX checksums offloads*/ 265 hw_atl_rpo_ipv4header_crc_offload_en_set(self, rxcsum); 266 hw_atl_rpo_tcp_udp_crc_offload_en_set(self, rxcsum); 267 268 /* LSO offloads*/ 269 hw_atl_tdm_large_send_offload_en_set(self, 0xFFFFFFFFU); 270 271 /* Outer VLAN tag offload */ 272 hw_atl_rpo_outer_vlan_tag_mode_set(self, 1U); 273 274 /* LRO offloads */ 275 { 276 unsigned int val = (8U < HW_ATL_B0_LRO_RXD_MAX) ? 0x3U : 277 ((4U < HW_ATL_B0_LRO_RXD_MAX) ? 0x2U : 278 ((2U < HW_ATL_B0_LRO_RXD_MAX) ? 0x1U : 0x0)); 279 280 for (i = 0; i < HW_ATL_B0_RINGS_MAX; i++) 281 hw_atl_rpo_lro_max_num_of_descriptors_set(self, val, i); 282 283 hw_atl_rpo_lro_time_base_divider_set(self, 0x61AU); 284 hw_atl_rpo_lro_inactive_interval_set(self, 0); 285 /* the LRO timebase divider is 5 uS (0x61a), 286 * which is multiplied by 50(0x32) 287 * to get a maximum coalescing interval of 250 uS, 288 * which is the default value 289 */ 290 hw_atl_rpo_lro_max_coalescing_interval_set(self, 50); 291 292 hw_atl_rpo_lro_qsessions_lim_set(self, 1U); 293 294 hw_atl_rpo_lro_total_desc_lim_set(self, 2U); 295 296 hw_atl_rpo_lro_patch_optimization_en_set(self, 1U); 297 298 hw_atl_rpo_lro_min_pay_of_first_pkt_set(self, 10U); 299 300 hw_atl_rpo_lro_pkt_lim_set(self, 1U); 301 302 hw_atl_rpo_lro_en_set(self, 303 aq_nic_cfg->is_lro ? 0xFFFFFFFFU : 0U); 304 hw_atl_itr_rsc_en_set(self, 305 aq_nic_cfg->is_lro ? 0xFFFFFFFFU : 0U); 306 307 hw_atl_itr_rsc_delay_set(self, 1U); 308 } 309 310 return aq_hw_err_from_flags(self); 311 } 312 313 static int hw_atl_b0_hw_init_tx_tc_rate_limit(struct aq_hw_s *self) 314 { 315 static const u32 max_weight = BIT(HW_ATL_TPS_DATA_TCTWEIGHT_WIDTH) - 1; 316 /* Scale factor is based on the number of bits in fractional portion */ 317 static const u32 scale = BIT(HW_ATL_TPS_DESC_RATE_Y_WIDTH); 318 static const u32 frac_msk = HW_ATL_TPS_DESC_RATE_Y_MSK >> 319 HW_ATL_TPS_DESC_RATE_Y_SHIFT; 320 const u32 link_speed = self->aq_link_status.mbps; 321 struct aq_nic_cfg_s *nic_cfg = self->aq_nic_cfg; 322 unsigned long num_min_rated_tcs = 0; 323 u32 tc_weight[AQ_CFG_TCS_MAX]; 324 u32 fixed_max_credit; 325 u8 min_rate_msk = 0; 326 u32 sum_weight = 0; 327 int tc; 328 329 /* By default max_credit is based upon MTU (in unit of 64b) */ 330 fixed_max_credit = nic_cfg->aq_hw_caps->mtu / 64; 331 332 if (link_speed) { 333 min_rate_msk = nic_cfg->tc_min_rate_msk & 334 (BIT(nic_cfg->tcs) - 1); 335 num_min_rated_tcs = hweight8(min_rate_msk); 336 } 337 338 /* First, calculate weights where min_rate is specified */ 339 if (num_min_rated_tcs) { 340 for (tc = 0; tc != nic_cfg->tcs; tc++) { 341 if (!nic_cfg->tc_min_rate[tc]) { 342 tc_weight[tc] = 0; 343 continue; 344 } 345 346 tc_weight[tc] = (-1L + link_speed + 347 nic_cfg->tc_min_rate[tc] * 348 max_weight) / 349 link_speed; 350 tc_weight[tc] = min(tc_weight[tc], max_weight); 351 sum_weight += tc_weight[tc]; 352 } 353 } 354 355 /* WSP, if min_rate is set for at least one TC. 356 * RR otherwise. 357 */ 358 hw_atl_tps_tx_pkt_shed_data_arb_mode_set(self, min_rate_msk ? 1U : 0U); 359 /* Data TC Arbiter takes precedence over Descriptor TC Arbiter, 360 * leave Descriptor TC Arbiter as RR. 361 */ 362 hw_atl_tps_tx_pkt_shed_desc_tc_arb_mode_set(self, 0U); 363 364 hw_atl_tps_tx_desc_rate_mode_set(self, nic_cfg->is_qos ? 1U : 0U); 365 366 for (tc = 0; tc != nic_cfg->tcs; tc++) { 367 const u32 en = (nic_cfg->tc_max_rate[tc] != 0) ? 1U : 0U; 368 const u32 desc = AQ_NIC_CFG_TCVEC2RING(nic_cfg, tc, 0); 369 u32 weight, max_credit; 370 371 hw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(self, tc, 372 fixed_max_credit); 373 hw_atl_tps_tx_pkt_shed_desc_tc_weight_set(self, tc, 0x1E); 374 375 if (num_min_rated_tcs) { 376 weight = tc_weight[tc]; 377 378 if (!weight && sum_weight < max_weight) 379 weight = (max_weight - sum_weight) / 380 (nic_cfg->tcs - num_min_rated_tcs); 381 else if (!weight) 382 weight = 0x64; 383 384 max_credit = max(8 * weight, fixed_max_credit); 385 } else { 386 weight = 0x64; 387 max_credit = 0xFFF; 388 } 389 390 hw_atl_tps_tx_pkt_shed_tc_data_weight_set(self, tc, weight); 391 hw_atl_tps_tx_pkt_shed_tc_data_max_credit_set(self, tc, 392 max_credit); 393 394 hw_atl_tps_tx_desc_rate_en_set(self, desc, en); 395 396 if (en) { 397 /* Nominal rate is always 10G */ 398 const u32 rate = 10000U * scale / 399 nic_cfg->tc_max_rate[tc]; 400 const u32 rate_int = rate >> 401 HW_ATL_TPS_DESC_RATE_Y_WIDTH; 402 const u32 rate_frac = rate & frac_msk; 403 404 hw_atl_tps_tx_desc_rate_x_set(self, desc, rate_int); 405 hw_atl_tps_tx_desc_rate_y_set(self, desc, rate_frac); 406 } else { 407 /* A value of 1 indicates the queue is not 408 * rate controlled. 409 */ 410 hw_atl_tps_tx_desc_rate_x_set(self, desc, 1U); 411 hw_atl_tps_tx_desc_rate_y_set(self, desc, 0U); 412 } 413 } 414 for (tc = nic_cfg->tcs; tc != AQ_CFG_TCS_MAX; tc++) { 415 const u32 desc = AQ_NIC_CFG_TCVEC2RING(nic_cfg, tc, 0); 416 417 hw_atl_tps_tx_desc_rate_en_set(self, desc, 0U); 418 hw_atl_tps_tx_desc_rate_x_set(self, desc, 1U); 419 hw_atl_tps_tx_desc_rate_y_set(self, desc, 0U); 420 } 421 422 return aq_hw_err_from_flags(self); 423 } 424 425 static int hw_atl_b0_hw_init_tx_path(struct aq_hw_s *self) 426 { 427 struct aq_nic_cfg_s *nic_cfg = self->aq_nic_cfg; 428 429 /* Tx TC/Queue number config */ 430 hw_atl_tpb_tps_tx_tc_mode_set(self, nic_cfg->tc_mode); 431 432 hw_atl_thm_lso_tcp_flag_of_first_pkt_set(self, 0x0FF6U); 433 hw_atl_thm_lso_tcp_flag_of_middle_pkt_set(self, 0x0FF6U); 434 hw_atl_thm_lso_tcp_flag_of_last_pkt_set(self, 0x0F7FU); 435 436 /* Tx interrupts */ 437 hw_atl_tdm_tx_desc_wr_wb_irq_en_set(self, 1U); 438 439 /* misc */ 440 aq_hw_write_reg(self, 0x00007040U, ATL_HW_IS_CHIP_FEATURE(self, TPO2) ? 441 0x00010000U : 0x00000000U); 442 hw_atl_tdm_tx_dca_en_set(self, 0U); 443 hw_atl_tdm_tx_dca_mode_set(self, 0U); 444 445 hw_atl_tpb_tx_path_scp_ins_en_set(self, 1U); 446 447 return aq_hw_err_from_flags(self); 448 } 449 450 void hw_atl_b0_hw_init_rx_rss_ctrl1(struct aq_hw_s *self) 451 { 452 struct aq_nic_cfg_s *cfg = self->aq_nic_cfg; 453 u32 rss_ctrl1 = HW_ATL_RSS_DISABLED; 454 455 if (cfg->is_rss) 456 rss_ctrl1 = (cfg->tc_mode == AQ_TC_MODE_8TCS) ? 457 HW_ATL_RSS_ENABLED_8TCS_2INDEX_BITS : 458 HW_ATL_RSS_ENABLED_4TCS_3INDEX_BITS; 459 460 hw_atl_reg_rx_flr_rss_control1set(self, rss_ctrl1); 461 } 462 463 static int hw_atl_b0_hw_init_rx_path(struct aq_hw_s *self) 464 { 465 struct aq_nic_cfg_s *cfg = self->aq_nic_cfg; 466 int i; 467 468 /* Rx TC/RSS number config */ 469 hw_atl_rpb_rpf_rx_traf_class_mode_set(self, cfg->tc_mode); 470 471 /* Rx flow control */ 472 hw_atl_rpb_rx_flow_ctl_mode_set(self, 1U); 473 474 /* RSS Ring selection */ 475 hw_atl_b0_hw_init_rx_rss_ctrl1(self); 476 477 /* Multicast filters */ 478 for (i = HW_ATL_B0_MAC_MAX; i--;) { 479 hw_atl_rpfl2_uc_flr_en_set(self, (i == 0U) ? 1U : 0U, i); 480 hw_atl_rpfl2unicast_flr_act_set(self, 1U, i); 481 } 482 483 hw_atl_reg_rx_flr_mcst_flr_msk_set(self, 0x00000000U); 484 hw_atl_reg_rx_flr_mcst_flr_set(self, 0x00010FFFU, 0U); 485 486 /* Vlan filters */ 487 hw_atl_rpf_vlan_outer_etht_set(self, 0x88A8U); 488 hw_atl_rpf_vlan_inner_etht_set(self, 0x8100U); 489 490 hw_atl_rpf_vlan_prom_mode_en_set(self, 1); 491 492 // Always accept untagged packets 493 hw_atl_rpf_vlan_accept_untagged_packets_set(self, 1U); 494 hw_atl_rpf_vlan_untagged_act_set(self, 1U); 495 496 /* Rx Interrupts */ 497 hw_atl_rdm_rx_desc_wr_wb_irq_en_set(self, 1U); 498 499 /* misc */ 500 aq_hw_write_reg(self, 0x00005040U, ATL_HW_IS_CHIP_FEATURE(self, RPF2) ? 501 0x000F0000U : 0x00000000U); 502 503 hw_atl_rpfl2broadcast_flr_act_set(self, 1U); 504 hw_atl_rpfl2broadcast_count_threshold_set(self, 0xFFFFU & (~0U / 256U)); 505 506 hw_atl_rdm_rx_dca_en_set(self, 0U); 507 hw_atl_rdm_rx_dca_mode_set(self, 0U); 508 509 return aq_hw_err_from_flags(self); 510 } 511 512 int hw_atl_b0_hw_mac_addr_set(struct aq_hw_s *self, u8 *mac_addr) 513 { 514 unsigned int h = 0U; 515 unsigned int l = 0U; 516 int err = 0; 517 518 if (!mac_addr) { 519 err = -EINVAL; 520 goto err_exit; 521 } 522 h = (mac_addr[0] << 8) | (mac_addr[1]); 523 l = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 524 (mac_addr[4] << 8) | mac_addr[5]; 525 526 hw_atl_rpfl2_uc_flr_en_set(self, 0U, HW_ATL_B0_MAC); 527 hw_atl_rpfl2unicast_dest_addresslsw_set(self, l, HW_ATL_B0_MAC); 528 hw_atl_rpfl2unicast_dest_addressmsw_set(self, h, HW_ATL_B0_MAC); 529 hw_atl_rpfl2_uc_flr_en_set(self, 1U, HW_ATL_B0_MAC); 530 531 err = aq_hw_err_from_flags(self); 532 533 err_exit: 534 return err; 535 } 536 537 static int hw_atl_b0_hw_init(struct aq_hw_s *self, u8 *mac_addr) 538 { 539 static u32 aq_hw_atl_igcr_table_[4][2] = { 540 [AQ_HW_IRQ_INVALID] = { 0x20000000U, 0x20000000U }, 541 [AQ_HW_IRQ_LEGACY] = { 0x20000080U, 0x20000080U }, 542 [AQ_HW_IRQ_MSI] = { 0x20000021U, 0x20000025U }, 543 [AQ_HW_IRQ_MSIX] = { 0x20000022U, 0x20000026U }, 544 }; 545 struct aq_nic_cfg_s *aq_nic_cfg = self->aq_nic_cfg; 546 int err = 0; 547 u32 val; 548 549 550 hw_atl_b0_hw_init_tx_path(self); 551 hw_atl_b0_hw_init_rx_path(self); 552 553 hw_atl_b0_hw_mac_addr_set(self, mac_addr); 554 555 self->aq_fw_ops->set_link_speed(self, aq_nic_cfg->link_speed_msk); 556 self->aq_fw_ops->set_state(self, MPI_INIT); 557 558 hw_atl_b0_hw_qos_set(self); 559 hw_atl_b0_hw_rss_set(self, &aq_nic_cfg->aq_rss); 560 hw_atl_b0_hw_rss_hash_set(self, &aq_nic_cfg->aq_rss); 561 562 /* Force limit MRRS on RDM/TDM to 2K */ 563 val = aq_hw_read_reg(self, HW_ATL_PCI_REG_CONTROL6_ADR); 564 aq_hw_write_reg(self, HW_ATL_PCI_REG_CONTROL6_ADR, 565 (val & ~0x707) | 0x404); 566 567 /* TX DMA total request limit. B0 hardware is not capable to 568 * handle more than (8K-MRRS) incoming DMA data. 569 * Value 24 in 256byte units 570 */ 571 aq_hw_write_reg(self, HW_ATL_TX_DMA_TOTAL_REQ_LIMIT_ADR, 24); 572 573 /* Reset link status and read out initial hardware counters */ 574 self->aq_link_status.mbps = 0; 575 self->aq_fw_ops->update_stats(self); 576 577 err = aq_hw_err_from_flags(self); 578 if (err < 0) 579 goto err_exit; 580 581 /* Interrupts */ 582 hw_atl_reg_irq_glb_ctl_set(self, 583 aq_hw_atl_igcr_table_[aq_nic_cfg->irq_type] 584 [(aq_nic_cfg->vecs > 1U) ? 585 1 : 0]); 586 587 hw_atl_itr_irq_auto_masklsw_set(self, aq_nic_cfg->aq_hw_caps->irq_mask); 588 589 /* Interrupts */ 590 hw_atl_reg_gen_irq_map_set(self, 591 ((HW_ATL_B0_ERR_INT << 0x18) | 592 (1U << 0x1F)) | 593 ((HW_ATL_B0_ERR_INT << 0x10) | 594 (1U << 0x17)), 0U); 595 596 /* Enable link interrupt */ 597 if (aq_nic_cfg->link_irq_vec) 598 hw_atl_reg_gen_irq_map_set(self, BIT(7) | 599 aq_nic_cfg->link_irq_vec, 3U); 600 601 hw_atl_b0_hw_offload_set(self, aq_nic_cfg); 602 603 err_exit: 604 return err; 605 } 606 607 int hw_atl_b0_hw_ring_tx_start(struct aq_hw_s *self, struct aq_ring_s *ring) 608 { 609 hw_atl_tdm_tx_desc_en_set(self, 1, ring->idx); 610 611 return aq_hw_err_from_flags(self); 612 } 613 614 int hw_atl_b0_hw_ring_rx_start(struct aq_hw_s *self, struct aq_ring_s *ring) 615 { 616 hw_atl_rdm_rx_desc_en_set(self, 1, ring->idx); 617 618 return aq_hw_err_from_flags(self); 619 } 620 621 int hw_atl_b0_hw_start(struct aq_hw_s *self) 622 { 623 hw_atl_tpb_tx_buff_en_set(self, 1); 624 hw_atl_rpb_rx_buff_en_set(self, 1); 625 626 return aq_hw_err_from_flags(self); 627 } 628 629 static int hw_atl_b0_hw_tx_ring_tail_update(struct aq_hw_s *self, 630 struct aq_ring_s *ring) 631 { 632 hw_atl_reg_tx_dma_desc_tail_ptr_set(self, ring->sw_tail, ring->idx); 633 634 return 0; 635 } 636 637 int hw_atl_b0_hw_ring_tx_xmit(struct aq_hw_s *self, struct aq_ring_s *ring, 638 unsigned int frags) 639 { 640 struct aq_ring_buff_s *buff = NULL; 641 struct hw_atl_txd_s *txd = NULL; 642 unsigned int buff_pa_len = 0U; 643 unsigned int frag_count = 0U; 644 unsigned int pkt_len = 0U; 645 bool is_vlan = false; 646 bool is_gso = false; 647 648 buff = &ring->buff_ring[ring->sw_tail]; 649 pkt_len = (buff->is_eop && buff->is_sop) ? buff->len : buff->len_pkt; 650 651 for (frag_count = 0; frag_count < frags; frag_count++) { 652 txd = (struct hw_atl_txd_s *)&ring->dx_ring[ring->sw_tail * 653 HW_ATL_B0_TXD_SIZE]; 654 txd->ctl = 0; 655 txd->ctl2 = 0; 656 txd->buf_addr = 0; 657 658 buff = &ring->buff_ring[ring->sw_tail]; 659 660 if (buff->is_gso_tcp || buff->is_gso_udp) { 661 if (buff->is_gso_tcp) 662 txd->ctl |= HW_ATL_B0_TXD_CTL_CMD_TCP; 663 txd->ctl |= HW_ATL_B0_TXD_CTL_DESC_TYPE_TXC; 664 txd->ctl |= (buff->len_l3 << 31) | 665 (buff->len_l2 << 24); 666 txd->ctl2 |= (buff->mss << 16); 667 is_gso = true; 668 669 pkt_len -= (buff->len_l4 + 670 buff->len_l3 + 671 buff->len_l2); 672 if (buff->is_ipv6) 673 txd->ctl |= HW_ATL_B0_TXD_CTL_CMD_IPV6; 674 txd->ctl2 |= (buff->len_l4 << 8) | 675 (buff->len_l3 >> 1); 676 } 677 if (buff->is_vlan) { 678 txd->ctl |= HW_ATL_B0_TXD_CTL_DESC_TYPE_TXC; 679 txd->ctl |= buff->vlan_tx_tag << 4; 680 is_vlan = true; 681 } 682 if (!buff->is_gso_tcp && !buff->is_gso_udp && !buff->is_vlan) { 683 buff_pa_len = buff->len; 684 685 txd->buf_addr = buff->pa; 686 txd->ctl |= (HW_ATL_B0_TXD_CTL_BLEN & 687 ((u32)buff_pa_len << 4)); 688 txd->ctl |= HW_ATL_B0_TXD_CTL_DESC_TYPE_TXD; 689 690 /* PAY_LEN */ 691 txd->ctl2 |= HW_ATL_B0_TXD_CTL2_LEN & (pkt_len << 14); 692 693 if (is_gso || is_vlan) { 694 /* enable tx context */ 695 txd->ctl2 |= HW_ATL_B0_TXD_CTL2_CTX_EN; 696 } 697 if (is_gso) 698 txd->ctl |= HW_ATL_B0_TXD_CTL_CMD_LSO; 699 700 /* Tx checksum offloads */ 701 if (buff->is_ip_cso) 702 txd->ctl |= HW_ATL_B0_TXD_CTL_CMD_IPCSO; 703 704 if (buff->is_udp_cso || buff->is_tcp_cso) 705 txd->ctl |= HW_ATL_B0_TXD_CTL_CMD_TUCSO; 706 707 if (is_vlan) 708 txd->ctl |= HW_ATL_B0_TXD_CTL_CMD_VLAN; 709 710 if (unlikely(buff->is_eop)) { 711 txd->ctl |= HW_ATL_B0_TXD_CTL_EOP; 712 txd->ctl |= HW_ATL_B0_TXD_CTL_CMD_WB; 713 is_gso = false; 714 is_vlan = false; 715 } 716 } 717 ring->sw_tail = aq_ring_next_dx(ring, ring->sw_tail); 718 } 719 720 hw_atl_b0_hw_tx_ring_tail_update(self, ring); 721 722 return aq_hw_err_from_flags(self); 723 } 724 725 int hw_atl_b0_hw_ring_rx_init(struct aq_hw_s *self, struct aq_ring_s *aq_ring, 726 struct aq_ring_param_s *aq_ring_param) 727 { 728 u32 dma_desc_addr_msw = (u32)(((u64)aq_ring->dx_ring_pa) >> 32); 729 u32 vlan_rx_stripping = self->aq_nic_cfg->is_vlan_rx_strip; 730 u32 dma_desc_addr_lsw = (u32)aq_ring->dx_ring_pa; 731 732 hw_atl_rdm_rx_desc_en_set(self, false, aq_ring->idx); 733 734 hw_atl_rdm_rx_desc_head_splitting_set(self, 0U, aq_ring->idx); 735 736 hw_atl_reg_rx_dma_desc_base_addresslswset(self, dma_desc_addr_lsw, 737 aq_ring->idx); 738 739 hw_atl_reg_rx_dma_desc_base_addressmswset(self, 740 dma_desc_addr_msw, aq_ring->idx); 741 742 hw_atl_rdm_rx_desc_len_set(self, aq_ring->size / 8U, aq_ring->idx); 743 744 hw_atl_rdm_rx_desc_data_buff_size_set(self, 745 AQ_CFG_RX_FRAME_MAX / 1024U, 746 aq_ring->idx); 747 748 hw_atl_rdm_rx_desc_head_buff_size_set(self, 0U, aq_ring->idx); 749 hw_atl_rdm_rx_desc_head_splitting_set(self, 0U, aq_ring->idx); 750 hw_atl_rpo_rx_desc_vlan_stripping_set(self, !!vlan_rx_stripping, 751 aq_ring->idx); 752 753 /* Rx ring set mode */ 754 755 /* Mapping interrupt vector */ 756 hw_atl_itr_irq_map_rx_set(self, aq_ring_param->vec_idx, aq_ring->idx); 757 hw_atl_itr_irq_map_en_rx_set(self, true, aq_ring->idx); 758 759 hw_atl_rdm_cpu_id_set(self, aq_ring_param->cpu, aq_ring->idx); 760 hw_atl_rdm_rx_desc_dca_en_set(self, 0U, aq_ring->idx); 761 hw_atl_rdm_rx_head_dca_en_set(self, 0U, aq_ring->idx); 762 hw_atl_rdm_rx_pld_dca_en_set(self, 0U, aq_ring->idx); 763 764 return aq_hw_err_from_flags(self); 765 } 766 767 int hw_atl_b0_hw_ring_tx_init(struct aq_hw_s *self, struct aq_ring_s *aq_ring, 768 struct aq_ring_param_s *aq_ring_param) 769 { 770 u32 dma_desc_msw_addr = (u32)(((u64)aq_ring->dx_ring_pa) >> 32); 771 u32 dma_desc_lsw_addr = (u32)aq_ring->dx_ring_pa; 772 773 hw_atl_reg_tx_dma_desc_base_addresslswset(self, dma_desc_lsw_addr, 774 aq_ring->idx); 775 776 hw_atl_reg_tx_dma_desc_base_addressmswset(self, dma_desc_msw_addr, 777 aq_ring->idx); 778 779 hw_atl_tdm_tx_desc_len_set(self, aq_ring->size / 8U, aq_ring->idx); 780 781 hw_atl_b0_hw_tx_ring_tail_update(self, aq_ring); 782 783 /* Set Tx threshold */ 784 hw_atl_tdm_tx_desc_wr_wb_threshold_set(self, 0U, aq_ring->idx); 785 786 /* Mapping interrupt vector */ 787 hw_atl_itr_irq_map_tx_set(self, aq_ring_param->vec_idx, aq_ring->idx); 788 hw_atl_itr_irq_map_en_tx_set(self, true, aq_ring->idx); 789 790 hw_atl_tdm_cpu_id_set(self, aq_ring_param->cpu, aq_ring->idx); 791 hw_atl_tdm_tx_desc_dca_en_set(self, 0U, aq_ring->idx); 792 793 return aq_hw_err_from_flags(self); 794 } 795 796 int hw_atl_b0_hw_ring_rx_fill(struct aq_hw_s *self, struct aq_ring_s *ring, 797 unsigned int sw_tail_old) 798 { 799 for (; sw_tail_old != ring->sw_tail; 800 sw_tail_old = aq_ring_next_dx(ring, sw_tail_old)) { 801 struct hw_atl_rxd_s *rxd = 802 (struct hw_atl_rxd_s *)&ring->dx_ring[sw_tail_old * 803 HW_ATL_B0_RXD_SIZE]; 804 805 struct aq_ring_buff_s *buff = &ring->buff_ring[sw_tail_old]; 806 807 rxd->buf_addr = buff->pa; 808 rxd->hdr_addr = 0U; 809 } 810 811 hw_atl_reg_rx_dma_desc_tail_ptr_set(self, sw_tail_old, ring->idx); 812 813 return aq_hw_err_from_flags(self); 814 } 815 816 static int hw_atl_b0_hw_ring_hwts_rx_fill(struct aq_hw_s *self, 817 struct aq_ring_s *ring) 818 { 819 unsigned int i; 820 821 for (i = aq_ring_avail_dx(ring); i--; 822 ring->sw_tail = aq_ring_next_dx(ring, ring->sw_tail)) { 823 struct hw_atl_rxd_s *rxd = 824 (struct hw_atl_rxd_s *) 825 &ring->dx_ring[ring->sw_tail * HW_ATL_B0_RXD_SIZE]; 826 827 rxd->buf_addr = ring->dx_ring_pa + ring->size * ring->dx_size; 828 rxd->hdr_addr = 0U; 829 } 830 /* Make sure descriptors are updated before bump tail*/ 831 wmb(); 832 833 hw_atl_reg_rx_dma_desc_tail_ptr_set(self, ring->sw_tail, ring->idx); 834 835 return aq_hw_err_from_flags(self); 836 } 837 838 static int hw_atl_b0_hw_ring_hwts_rx_receive(struct aq_hw_s *self, 839 struct aq_ring_s *ring) 840 { 841 while (ring->hw_head != ring->sw_tail) { 842 struct hw_atl_rxd_hwts_wb_s *hwts_wb = 843 (struct hw_atl_rxd_hwts_wb_s *) 844 (ring->dx_ring + (ring->hw_head * HW_ATL_B0_RXD_SIZE)); 845 846 /* RxD is not done */ 847 if (!(hwts_wb->sec_lw0 & 0x1U)) 848 break; 849 850 ring->hw_head = aq_ring_next_dx(ring, ring->hw_head); 851 } 852 853 return aq_hw_err_from_flags(self); 854 } 855 856 int hw_atl_b0_hw_ring_tx_head_update(struct aq_hw_s *self, 857 struct aq_ring_s *ring) 858 { 859 unsigned int hw_head_; 860 int err = 0; 861 862 hw_head_ = hw_atl_tdm_tx_desc_head_ptr_get(self, ring->idx); 863 864 if (aq_utils_obj_test(&self->flags, AQ_HW_FLAG_ERR_UNPLUG)) { 865 err = -ENXIO; 866 goto err_exit; 867 } 868 ring->hw_head = hw_head_; 869 err = aq_hw_err_from_flags(self); 870 871 err_exit: 872 return err; 873 } 874 875 int hw_atl_b0_hw_ring_rx_receive(struct aq_hw_s *self, struct aq_ring_s *ring) 876 { 877 for (; ring->hw_head != ring->sw_tail; 878 ring->hw_head = aq_ring_next_dx(ring, ring->hw_head)) { 879 struct aq_ring_buff_s *buff = NULL; 880 struct hw_atl_rxd_wb_s *rxd_wb = (struct hw_atl_rxd_wb_s *) 881 &ring->dx_ring[ring->hw_head * HW_ATL_B0_RXD_SIZE]; 882 883 unsigned int is_rx_check_sum_enabled = 0U; 884 unsigned int pkt_type = 0U; 885 u8 rx_stat = 0U; 886 887 if (!(rxd_wb->status & 0x1U)) { /* RxD is not done */ 888 break; 889 } 890 891 buff = &ring->buff_ring[ring->hw_head]; 892 893 buff->flags = 0U; 894 buff->is_hash_l4 = 0U; 895 896 rx_stat = (0x0000003CU & rxd_wb->status) >> 2; 897 898 is_rx_check_sum_enabled = (rxd_wb->type >> 19) & 0x3U; 899 900 pkt_type = (rxd_wb->type & HW_ATL_B0_RXD_WB_STAT_PKTTYPE) >> 901 HW_ATL_B0_RXD_WB_STAT_PKTTYPE_SHIFT; 902 903 if (is_rx_check_sum_enabled & BIT(0) && 904 (0x0U == (pkt_type & 0x3U))) 905 buff->is_ip_cso = (rx_stat & BIT(1)) ? 0U : 1U; 906 907 if (is_rx_check_sum_enabled & BIT(1)) { 908 if (0x4U == (pkt_type & 0x1CU)) 909 buff->is_udp_cso = (rx_stat & BIT(2)) ? 0U : 910 !!(rx_stat & BIT(3)); 911 else if (0x0U == (pkt_type & 0x1CU)) 912 buff->is_tcp_cso = (rx_stat & BIT(2)) ? 0U : 913 !!(rx_stat & BIT(3)); 914 } 915 buff->is_cso_err = !!(rx_stat & 0x6); 916 /* Checksum offload workaround for small packets */ 917 if (unlikely(rxd_wb->pkt_len <= 60)) { 918 buff->is_ip_cso = 0U; 919 buff->is_cso_err = 0U; 920 } 921 922 if (self->aq_nic_cfg->is_vlan_rx_strip && 923 ((pkt_type & HW_ATL_B0_RXD_WB_PKTTYPE_VLAN) || 924 (pkt_type & HW_ATL_B0_RXD_WB_PKTTYPE_VLAN_DOUBLE))) { 925 buff->is_vlan = 1; 926 buff->vlan_rx_tag = le16_to_cpu(rxd_wb->vlan); 927 } 928 929 if ((rx_stat & BIT(0)) || rxd_wb->type & 0x1000U) { 930 /* MAC error or DMA error */ 931 buff->is_error = 1U; 932 } 933 if (self->aq_nic_cfg->is_rss) { 934 /* last 4 byte */ 935 u16 rss_type = rxd_wb->type & 0xFU; 936 937 if (rss_type && rss_type < 0x8U) { 938 buff->is_hash_l4 = (rss_type == 0x4 || 939 rss_type == 0x5); 940 buff->rss_hash = rxd_wb->rss_hash; 941 } 942 } 943 944 buff->is_lro = !!(HW_ATL_B0_RXD_WB_STAT2_RSCCNT & 945 rxd_wb->status); 946 if (HW_ATL_B0_RXD_WB_STAT2_EOP & rxd_wb->status) { 947 buff->len = rxd_wb->pkt_len % 948 AQ_CFG_RX_FRAME_MAX; 949 buff->len = buff->len ? 950 buff->len : AQ_CFG_RX_FRAME_MAX; 951 buff->next = 0U; 952 buff->is_eop = 1U; 953 } else { 954 buff->len = 955 rxd_wb->pkt_len > AQ_CFG_RX_FRAME_MAX ? 956 AQ_CFG_RX_FRAME_MAX : rxd_wb->pkt_len; 957 958 if (buff->is_lro) { 959 /* LRO */ 960 buff->next = rxd_wb->next_desc_ptr; 961 ++ring->stats.rx.lro_packets; 962 } else { 963 /* jumbo */ 964 buff->next = 965 aq_ring_next_dx(ring, 966 ring->hw_head); 967 ++ring->stats.rx.jumbo_packets; 968 } 969 } 970 } 971 972 return aq_hw_err_from_flags(self); 973 } 974 975 int hw_atl_b0_hw_irq_enable(struct aq_hw_s *self, u64 mask) 976 { 977 hw_atl_itr_irq_msk_setlsw_set(self, LODWORD(mask)); 978 979 return aq_hw_err_from_flags(self); 980 } 981 982 int hw_atl_b0_hw_irq_disable(struct aq_hw_s *self, u64 mask) 983 { 984 hw_atl_itr_irq_msk_clearlsw_set(self, LODWORD(mask)); 985 hw_atl_itr_irq_status_clearlsw_set(self, LODWORD(mask)); 986 987 atomic_inc(&self->dpc); 988 989 return aq_hw_err_from_flags(self); 990 } 991 992 int hw_atl_b0_hw_irq_read(struct aq_hw_s *self, u64 *mask) 993 { 994 *mask = hw_atl_itr_irq_statuslsw_get(self); 995 996 return aq_hw_err_from_flags(self); 997 } 998 999 #define IS_FILTER_ENABLED(_F_) ((packet_filter & (_F_)) ? 1U : 0U) 1000 1001 int hw_atl_b0_hw_packet_filter_set(struct aq_hw_s *self, 1002 unsigned int packet_filter) 1003 { 1004 struct aq_nic_cfg_s *cfg = self->aq_nic_cfg; 1005 unsigned int i = 0U; 1006 u32 vlan_promisc; 1007 u32 l2_promisc; 1008 1009 l2_promisc = IS_FILTER_ENABLED(IFF_PROMISC) || 1010 !!(cfg->priv_flags & BIT(AQ_HW_LOOPBACK_DMA_NET)); 1011 vlan_promisc = l2_promisc || cfg->is_vlan_force_promisc; 1012 1013 hw_atl_rpfl2promiscuous_mode_en_set(self, l2_promisc); 1014 1015 hw_atl_rpf_vlan_prom_mode_en_set(self, vlan_promisc); 1016 1017 hw_atl_rpfl2multicast_flr_en_set(self, 1018 IS_FILTER_ENABLED(IFF_ALLMULTI) && 1019 IS_FILTER_ENABLED(IFF_MULTICAST), 0); 1020 1021 hw_atl_rpfl2_accept_all_mc_packets_set(self, 1022 IS_FILTER_ENABLED(IFF_ALLMULTI) && 1023 IS_FILTER_ENABLED(IFF_MULTICAST)); 1024 1025 hw_atl_rpfl2broadcast_en_set(self, IS_FILTER_ENABLED(IFF_BROADCAST)); 1026 1027 1028 for (i = HW_ATL_B0_MAC_MIN; i < HW_ATL_B0_MAC_MAX; ++i) 1029 hw_atl_rpfl2_uc_flr_en_set(self, 1030 (cfg->is_mc_list_enabled && 1031 (i <= cfg->mc_list_count)) ? 1032 1U : 0U, i); 1033 1034 return aq_hw_err_from_flags(self); 1035 } 1036 1037 #undef IS_FILTER_ENABLED 1038 1039 static int hw_atl_b0_hw_multicast_list_set(struct aq_hw_s *self, 1040 u8 ar_mac 1041 [AQ_HW_MULTICAST_ADDRESS_MAX] 1042 [ETH_ALEN], 1043 u32 count) 1044 { 1045 int err = 0; 1046 struct aq_nic_cfg_s *cfg = self->aq_nic_cfg; 1047 1048 if (count > (HW_ATL_B0_MAC_MAX - HW_ATL_B0_MAC_MIN)) { 1049 err = -EBADRQC; 1050 goto err_exit; 1051 } 1052 for (cfg->mc_list_count = 0U; 1053 cfg->mc_list_count < count; 1054 ++cfg->mc_list_count) { 1055 u32 i = cfg->mc_list_count; 1056 u32 h = (ar_mac[i][0] << 8) | (ar_mac[i][1]); 1057 u32 l = (ar_mac[i][2] << 24) | (ar_mac[i][3] << 16) | 1058 (ar_mac[i][4] << 8) | ar_mac[i][5]; 1059 1060 hw_atl_rpfl2_uc_flr_en_set(self, 0U, HW_ATL_B0_MAC_MIN + i); 1061 1062 hw_atl_rpfl2unicast_dest_addresslsw_set(self, l, 1063 HW_ATL_B0_MAC_MIN + i); 1064 1065 hw_atl_rpfl2unicast_dest_addressmsw_set(self, h, 1066 HW_ATL_B0_MAC_MIN + i); 1067 1068 hw_atl_rpfl2_uc_flr_en_set(self, 1069 (cfg->is_mc_list_enabled), 1070 HW_ATL_B0_MAC_MIN + i); 1071 } 1072 1073 err = aq_hw_err_from_flags(self); 1074 1075 err_exit: 1076 return err; 1077 } 1078 1079 static int hw_atl_b0_hw_interrupt_moderation_set(struct aq_hw_s *self) 1080 { 1081 unsigned int i = 0U; 1082 u32 itr_tx = 2U; 1083 u32 itr_rx = 2U; 1084 1085 switch (self->aq_nic_cfg->itr) { 1086 case AQ_CFG_INTERRUPT_MODERATION_ON: 1087 case AQ_CFG_INTERRUPT_MODERATION_AUTO: 1088 hw_atl_tdm_tx_desc_wr_wb_irq_en_set(self, 0U); 1089 hw_atl_tdm_tdm_intr_moder_en_set(self, 1U); 1090 hw_atl_rdm_rx_desc_wr_wb_irq_en_set(self, 0U); 1091 hw_atl_rdm_rdm_intr_moder_en_set(self, 1U); 1092 1093 if (self->aq_nic_cfg->itr == AQ_CFG_INTERRUPT_MODERATION_ON) { 1094 /* HW timers are in 2us units */ 1095 int tx_max_timer = self->aq_nic_cfg->tx_itr / 2; 1096 int tx_min_timer = tx_max_timer / 2; 1097 1098 int rx_max_timer = self->aq_nic_cfg->rx_itr / 2; 1099 int rx_min_timer = rx_max_timer / 2; 1100 1101 tx_max_timer = min(HW_ATL_INTR_MODER_MAX, tx_max_timer); 1102 tx_min_timer = min(HW_ATL_INTR_MODER_MIN, tx_min_timer); 1103 rx_max_timer = min(HW_ATL_INTR_MODER_MAX, rx_max_timer); 1104 rx_min_timer = min(HW_ATL_INTR_MODER_MIN, rx_min_timer); 1105 1106 itr_tx |= tx_min_timer << 0x8U; 1107 itr_tx |= tx_max_timer << 0x10U; 1108 itr_rx |= rx_min_timer << 0x8U; 1109 itr_rx |= rx_max_timer << 0x10U; 1110 } else { 1111 static unsigned int hw_atl_b0_timers_table_tx_[][2] = { 1112 {0xfU, 0xffU}, /* 10Gbit */ 1113 {0xfU, 0x1ffU}, /* 5Gbit */ 1114 {0xfU, 0x1ffU}, /* 5Gbit 5GS */ 1115 {0xfU, 0x1ffU}, /* 2.5Gbit */ 1116 {0xfU, 0x1ffU}, /* 1Gbit */ 1117 {0xfU, 0x1ffU}, /* 100Mbit */ 1118 }; 1119 1120 static unsigned int hw_atl_b0_timers_table_rx_[][2] = { 1121 {0x6U, 0x38U},/* 10Gbit */ 1122 {0xCU, 0x70U},/* 5Gbit */ 1123 {0xCU, 0x70U},/* 5Gbit 5GS */ 1124 {0x18U, 0xE0U},/* 2.5Gbit */ 1125 {0x30U, 0x80U},/* 1Gbit */ 1126 {0x4U, 0x50U},/* 100Mbit */ 1127 }; 1128 1129 unsigned int speed_index = 1130 hw_atl_utils_mbps_2_speed_index( 1131 self->aq_link_status.mbps); 1132 1133 /* Update user visible ITR settings */ 1134 self->aq_nic_cfg->tx_itr = hw_atl_b0_timers_table_tx_ 1135 [speed_index][1] * 2; 1136 self->aq_nic_cfg->rx_itr = hw_atl_b0_timers_table_rx_ 1137 [speed_index][1] * 2; 1138 1139 itr_tx |= hw_atl_b0_timers_table_tx_ 1140 [speed_index][0] << 0x8U; 1141 itr_tx |= hw_atl_b0_timers_table_tx_ 1142 [speed_index][1] << 0x10U; 1143 1144 itr_rx |= hw_atl_b0_timers_table_rx_ 1145 [speed_index][0] << 0x8U; 1146 itr_rx |= hw_atl_b0_timers_table_rx_ 1147 [speed_index][1] << 0x10U; 1148 } 1149 break; 1150 case AQ_CFG_INTERRUPT_MODERATION_OFF: 1151 hw_atl_tdm_tx_desc_wr_wb_irq_en_set(self, 1U); 1152 hw_atl_tdm_tdm_intr_moder_en_set(self, 0U); 1153 hw_atl_rdm_rx_desc_wr_wb_irq_en_set(self, 1U); 1154 hw_atl_rdm_rdm_intr_moder_en_set(self, 0U); 1155 itr_tx = 0U; 1156 itr_rx = 0U; 1157 break; 1158 } 1159 1160 for (i = HW_ATL_B0_RINGS_MAX; i--;) { 1161 hw_atl_reg_tx_intr_moder_ctrl_set(self, itr_tx, i); 1162 hw_atl_reg_rx_intr_moder_ctrl_set(self, itr_rx, i); 1163 } 1164 1165 return aq_hw_err_from_flags(self); 1166 } 1167 1168 static int hw_atl_b0_hw_stop(struct aq_hw_s *self) 1169 { 1170 int err; 1171 u32 val; 1172 1173 hw_atl_b0_hw_irq_disable(self, HW_ATL_B0_INT_MASK); 1174 1175 /* Invalidate Descriptor Cache to prevent writing to the cached 1176 * descriptors and to the data pointer of those descriptors 1177 */ 1178 hw_atl_rdm_rx_dma_desc_cache_init_tgl(self); 1179 1180 err = aq_hw_err_from_flags(self); 1181 1182 if (err) 1183 goto err_exit; 1184 1185 readx_poll_timeout_atomic(hw_atl_rdm_rx_dma_desc_cache_init_done_get, 1186 self, val, val == 1, 1000U, 10000U); 1187 1188 err_exit: 1189 return err; 1190 } 1191 1192 int hw_atl_b0_hw_ring_tx_stop(struct aq_hw_s *self, struct aq_ring_s *ring) 1193 { 1194 hw_atl_tdm_tx_desc_en_set(self, 0U, ring->idx); 1195 1196 return aq_hw_err_from_flags(self); 1197 } 1198 1199 int hw_atl_b0_hw_ring_rx_stop(struct aq_hw_s *self, struct aq_ring_s *ring) 1200 { 1201 hw_atl_rdm_rx_desc_en_set(self, 0U, ring->idx); 1202 1203 return aq_hw_err_from_flags(self); 1204 } 1205 1206 #define get_ptp_ts_val_u64(self, indx) \ 1207 ((u64)(hw_atl_pcs_ptp_clock_get(self, indx) & 0xffff)) 1208 1209 static void hw_atl_b0_get_ptp_ts(struct aq_hw_s *self, u64 *stamp) 1210 { 1211 u64 ns; 1212 1213 hw_atl_pcs_ptp_clock_read_enable(self, 1); 1214 hw_atl_pcs_ptp_clock_read_enable(self, 0); 1215 ns = (get_ptp_ts_val_u64(self, 0) + 1216 (get_ptp_ts_val_u64(self, 1) << 16)) * NSEC_PER_SEC + 1217 (get_ptp_ts_val_u64(self, 3) + 1218 (get_ptp_ts_val_u64(self, 4) << 16)); 1219 1220 *stamp = ns + self->ptp_clk_offset; 1221 } 1222 1223 static void hw_atl_b0_adj_params_get(u64 freq, s64 adj, u32 *ns, u32 *fns) 1224 { 1225 /* For accuracy, the digit is extended */ 1226 s64 base_ns = ((adj + NSEC_PER_SEC) * NSEC_PER_SEC); 1227 u64 nsi_frac = 0; 1228 u64 nsi; 1229 1230 base_ns = div64_s64(base_ns, freq); 1231 nsi = div64_u64(base_ns, NSEC_PER_SEC); 1232 1233 if (base_ns != nsi * NSEC_PER_SEC) { 1234 s64 divisor = div64_s64((s64)NSEC_PER_SEC * NSEC_PER_SEC, 1235 base_ns - nsi * NSEC_PER_SEC); 1236 nsi_frac = div64_s64(FRAC_PER_NS * NSEC_PER_SEC, divisor); 1237 } 1238 1239 *ns = (u32)nsi; 1240 *fns = (u32)nsi_frac; 1241 } 1242 1243 static void 1244 hw_atl_b0_mac_adj_param_calc(struct hw_fw_request_ptp_adj_freq *ptp_adj_freq, 1245 u64 phyfreq, u64 macfreq) 1246 { 1247 s64 adj_fns_val; 1248 s64 fns_in_sec_phy = phyfreq * (ptp_adj_freq->fns_phy + 1249 FRAC_PER_NS * ptp_adj_freq->ns_phy); 1250 s64 fns_in_sec_mac = macfreq * (ptp_adj_freq->fns_mac + 1251 FRAC_PER_NS * ptp_adj_freq->ns_mac); 1252 s64 fault_in_sec_phy = FRAC_PER_NS * NSEC_PER_SEC - fns_in_sec_phy; 1253 s64 fault_in_sec_mac = FRAC_PER_NS * NSEC_PER_SEC - fns_in_sec_mac; 1254 /* MAC MCP counter freq is macfreq / 4 */ 1255 s64 diff_in_mcp_overflow = (fault_in_sec_mac - fault_in_sec_phy) * 1256 4 * FRAC_PER_NS; 1257 1258 diff_in_mcp_overflow = div64_s64(diff_in_mcp_overflow, 1259 AQ_HW_MAC_COUNTER_HZ); 1260 adj_fns_val = (ptp_adj_freq->fns_mac + FRAC_PER_NS * 1261 ptp_adj_freq->ns_mac) + diff_in_mcp_overflow; 1262 1263 ptp_adj_freq->mac_ns_adj = div64_s64(adj_fns_val, FRAC_PER_NS); 1264 ptp_adj_freq->mac_fns_adj = adj_fns_val - ptp_adj_freq->mac_ns_adj * 1265 FRAC_PER_NS; 1266 } 1267 1268 static int hw_atl_b0_adj_sys_clock(struct aq_hw_s *self, s64 delta) 1269 { 1270 self->ptp_clk_offset += delta; 1271 1272 self->aq_fw_ops->adjust_ptp(self, self->ptp_clk_offset); 1273 1274 return 0; 1275 } 1276 1277 static int hw_atl_b0_set_sys_clock(struct aq_hw_s *self, u64 time, u64 ts) 1278 { 1279 s64 delta = time - (self->ptp_clk_offset + ts); 1280 1281 return hw_atl_b0_adj_sys_clock(self, delta); 1282 } 1283 1284 static int hw_atl_b0_ts_to_sys_clock(struct aq_hw_s *self, u64 ts, u64 *time) 1285 { 1286 *time = self->ptp_clk_offset + ts; 1287 return 0; 1288 } 1289 1290 static int hw_atl_b0_adj_clock_freq(struct aq_hw_s *self, s32 ppb) 1291 { 1292 struct hw_fw_request_iface fwreq; 1293 size_t size; 1294 1295 memset(&fwreq, 0, sizeof(fwreq)); 1296 1297 fwreq.msg_id = HW_AQ_FW_REQUEST_PTP_ADJ_FREQ; 1298 hw_atl_b0_adj_params_get(AQ_HW_MAC_COUNTER_HZ, ppb, 1299 &fwreq.ptp_adj_freq.ns_mac, 1300 &fwreq.ptp_adj_freq.fns_mac); 1301 hw_atl_b0_adj_params_get(AQ_HW_PHY_COUNTER_HZ, ppb, 1302 &fwreq.ptp_adj_freq.ns_phy, 1303 &fwreq.ptp_adj_freq.fns_phy); 1304 hw_atl_b0_mac_adj_param_calc(&fwreq.ptp_adj_freq, 1305 AQ_HW_PHY_COUNTER_HZ, 1306 AQ_HW_MAC_COUNTER_HZ); 1307 1308 size = sizeof(fwreq.msg_id) + sizeof(fwreq.ptp_adj_freq); 1309 return self->aq_fw_ops->send_fw_request(self, &fwreq, size); 1310 } 1311 1312 static int hw_atl_b0_gpio_pulse(struct aq_hw_s *self, u32 index, 1313 u64 start, u32 period) 1314 { 1315 struct hw_fw_request_iface fwreq; 1316 size_t size; 1317 1318 memset(&fwreq, 0, sizeof(fwreq)); 1319 1320 fwreq.msg_id = HW_AQ_FW_REQUEST_PTP_GPIO_CTRL; 1321 fwreq.ptp_gpio_ctrl.index = index; 1322 fwreq.ptp_gpio_ctrl.period = period; 1323 /* Apply time offset */ 1324 fwreq.ptp_gpio_ctrl.start = start; 1325 1326 size = sizeof(fwreq.msg_id) + sizeof(fwreq.ptp_gpio_ctrl); 1327 return self->aq_fw_ops->send_fw_request(self, &fwreq, size); 1328 } 1329 1330 static int hw_atl_b0_extts_gpio_enable(struct aq_hw_s *self, u32 index, 1331 u32 enable) 1332 { 1333 /* Enable/disable Sync1588 GPIO Timestamping */ 1334 aq_phy_write_reg(self, MDIO_MMD_PCS, 0xc611, enable ? 0x71 : 0); 1335 1336 return 0; 1337 } 1338 1339 static int hw_atl_b0_get_sync_ts(struct aq_hw_s *self, u64 *ts) 1340 { 1341 u64 sec_l; 1342 u64 sec_h; 1343 u64 nsec_l; 1344 u64 nsec_h; 1345 1346 if (!ts) 1347 return -1; 1348 1349 /* PTP external GPIO clock seconds count 15:0 */ 1350 sec_l = aq_phy_read_reg(self, MDIO_MMD_PCS, 0xc914); 1351 /* PTP external GPIO clock seconds count 31:16 */ 1352 sec_h = aq_phy_read_reg(self, MDIO_MMD_PCS, 0xc915); 1353 /* PTP external GPIO clock nanoseconds count 15:0 */ 1354 nsec_l = aq_phy_read_reg(self, MDIO_MMD_PCS, 0xc916); 1355 /* PTP external GPIO clock nanoseconds count 31:16 */ 1356 nsec_h = aq_phy_read_reg(self, MDIO_MMD_PCS, 0xc917); 1357 1358 *ts = (nsec_h << 16) + nsec_l + ((sec_h << 16) + sec_l) * NSEC_PER_SEC; 1359 1360 return 0; 1361 } 1362 1363 static u16 hw_atl_b0_rx_extract_ts(struct aq_hw_s *self, u8 *p, 1364 unsigned int len, u64 *timestamp) 1365 { 1366 unsigned int offset = 14; 1367 struct ethhdr *eth; 1368 __be64 sec; 1369 __be32 ns; 1370 u8 *ptr; 1371 1372 if (len <= offset || !timestamp) 1373 return 0; 1374 1375 /* The TIMESTAMP in the end of package has following format: 1376 * (big-endian) 1377 * struct { 1378 * uint64_t sec; 1379 * uint32_t ns; 1380 * uint16_t stream_id; 1381 * }; 1382 */ 1383 ptr = p + (len - offset); 1384 memcpy(&sec, ptr, sizeof(sec)); 1385 ptr += sizeof(sec); 1386 memcpy(&ns, ptr, sizeof(ns)); 1387 1388 *timestamp = (be64_to_cpu(sec) & 0xffffffffffffllu) * NSEC_PER_SEC + 1389 be32_to_cpu(ns) + self->ptp_clk_offset; 1390 1391 eth = (struct ethhdr *)p; 1392 1393 return (eth->h_proto == htons(ETH_P_1588)) ? 12 : 14; 1394 } 1395 1396 static int hw_atl_b0_extract_hwts(struct aq_hw_s *self, u8 *p, unsigned int len, 1397 u64 *timestamp) 1398 { 1399 struct hw_atl_rxd_hwts_wb_s *hwts_wb = (struct hw_atl_rxd_hwts_wb_s *)p; 1400 u64 tmp, sec, ns; 1401 1402 sec = 0; 1403 tmp = (hwts_wb->sec_lw0 >> 2) & 0x3ff; 1404 sec += tmp; 1405 tmp = (u64)((hwts_wb->sec_lw1 >> 16) & 0xffff) << 10; 1406 sec += tmp; 1407 tmp = (u64)(hwts_wb->sec_hw & 0xfff) << 26; 1408 sec += tmp; 1409 tmp = (u64)((hwts_wb->sec_hw >> 22) & 0x3ff) << 38; 1410 sec += tmp; 1411 ns = sec * NSEC_PER_SEC + hwts_wb->ns; 1412 if (timestamp) 1413 *timestamp = ns + self->ptp_clk_offset; 1414 return 0; 1415 } 1416 1417 static int hw_atl_b0_hw_fl3l4_clear(struct aq_hw_s *self, 1418 struct aq_rx_filter_l3l4 *data) 1419 { 1420 u8 location = data->location; 1421 1422 if (!data->is_ipv6) { 1423 hw_atl_rpfl3l4_cmd_clear(self, location); 1424 hw_atl_rpf_l4_spd_set(self, 0U, location); 1425 hw_atl_rpf_l4_dpd_set(self, 0U, location); 1426 hw_atl_rpfl3l4_ipv4_src_addr_clear(self, location); 1427 hw_atl_rpfl3l4_ipv4_dest_addr_clear(self, location); 1428 } else { 1429 int i; 1430 1431 for (i = 0; i < HW_ATL_RX_CNT_REG_ADDR_IPV6; ++i) { 1432 hw_atl_rpfl3l4_cmd_clear(self, location + i); 1433 hw_atl_rpf_l4_spd_set(self, 0U, location + i); 1434 hw_atl_rpf_l4_dpd_set(self, 0U, location + i); 1435 } 1436 hw_atl_rpfl3l4_ipv6_src_addr_clear(self, location); 1437 hw_atl_rpfl3l4_ipv6_dest_addr_clear(self, location); 1438 } 1439 1440 return aq_hw_err_from_flags(self); 1441 } 1442 1443 static int hw_atl_b0_hw_fl3l4_set(struct aq_hw_s *self, 1444 struct aq_rx_filter_l3l4 *data) 1445 { 1446 u8 location = data->location; 1447 1448 hw_atl_b0_hw_fl3l4_clear(self, data); 1449 1450 if (data->cmd & (HW_ATL_RX_ENABLE_CMP_DEST_ADDR_L3 | 1451 HW_ATL_RX_ENABLE_CMP_SRC_ADDR_L3)) { 1452 if (!data->is_ipv6) { 1453 hw_atl_rpfl3l4_ipv4_dest_addr_set(self, 1454 location, 1455 data->ip_dst[0]); 1456 hw_atl_rpfl3l4_ipv4_src_addr_set(self, 1457 location, 1458 data->ip_src[0]); 1459 } else { 1460 hw_atl_rpfl3l4_ipv6_dest_addr_set(self, 1461 location, 1462 data->ip_dst); 1463 hw_atl_rpfl3l4_ipv6_src_addr_set(self, 1464 location, 1465 data->ip_src); 1466 } 1467 } 1468 1469 if (data->cmd & (HW_ATL_RX_ENABLE_CMP_DEST_PORT_L4 | 1470 HW_ATL_RX_ENABLE_CMP_SRC_PORT_L4)) { 1471 hw_atl_rpf_l4_dpd_set(self, data->p_dst, location); 1472 hw_atl_rpf_l4_spd_set(self, data->p_src, location); 1473 } 1474 1475 hw_atl_rpfl3l4_cmd_set(self, location, data->cmd); 1476 1477 return aq_hw_err_from_flags(self); 1478 } 1479 1480 static int hw_atl_b0_hw_fl2_set(struct aq_hw_s *self, 1481 struct aq_rx_filter_l2 *data) 1482 { 1483 hw_atl_rpf_etht_flr_en_set(self, 1U, data->location); 1484 hw_atl_rpf_etht_flr_set(self, data->ethertype, data->location); 1485 hw_atl_rpf_etht_user_priority_en_set(self, 1486 !!data->user_priority_en, 1487 data->location); 1488 if (data->user_priority_en) 1489 hw_atl_rpf_etht_user_priority_set(self, 1490 data->user_priority, 1491 data->location); 1492 1493 if (data->queue < 0) { 1494 hw_atl_rpf_etht_flr_act_set(self, 0U, data->location); 1495 hw_atl_rpf_etht_rx_queue_en_set(self, 0U, data->location); 1496 } else { 1497 hw_atl_rpf_etht_flr_act_set(self, 1U, data->location); 1498 hw_atl_rpf_etht_rx_queue_en_set(self, 1U, data->location); 1499 hw_atl_rpf_etht_rx_queue_set(self, data->queue, data->location); 1500 } 1501 1502 return aq_hw_err_from_flags(self); 1503 } 1504 1505 static int hw_atl_b0_hw_fl2_clear(struct aq_hw_s *self, 1506 struct aq_rx_filter_l2 *data) 1507 { 1508 hw_atl_rpf_etht_flr_en_set(self, 0U, data->location); 1509 hw_atl_rpf_etht_flr_set(self, 0U, data->location); 1510 hw_atl_rpf_etht_user_priority_en_set(self, 0U, data->location); 1511 1512 return aq_hw_err_from_flags(self); 1513 } 1514 1515 /** 1516 * @brief Set VLAN filter table 1517 * @details Configure VLAN filter table to accept (and assign the queue) traffic 1518 * for the particular vlan ids. 1519 * Note: use this function under vlan promisc mode not to lost the traffic 1520 * 1521 * @param aq_hw_s 1522 * @param aq_rx_filter_vlan VLAN filter configuration 1523 * @return 0 - OK, <0 - error 1524 */ 1525 static int hw_atl_b0_hw_vlan_set(struct aq_hw_s *self, 1526 struct aq_rx_filter_vlan *aq_vlans) 1527 { 1528 int i; 1529 1530 for (i = 0; i < AQ_VLAN_MAX_FILTERS; i++) { 1531 hw_atl_rpf_vlan_flr_en_set(self, 0U, i); 1532 hw_atl_rpf_vlan_rxq_en_flr_set(self, 0U, i); 1533 if (aq_vlans[i].enable) { 1534 hw_atl_rpf_vlan_id_flr_set(self, 1535 aq_vlans[i].vlan_id, 1536 i); 1537 hw_atl_rpf_vlan_flr_act_set(self, 1U, i); 1538 hw_atl_rpf_vlan_flr_en_set(self, 1U, i); 1539 if (aq_vlans[i].queue != 0xFF) { 1540 hw_atl_rpf_vlan_rxq_flr_set(self, 1541 aq_vlans[i].queue, 1542 i); 1543 hw_atl_rpf_vlan_rxq_en_flr_set(self, 1U, i); 1544 } 1545 } 1546 } 1547 1548 return aq_hw_err_from_flags(self); 1549 } 1550 1551 static int hw_atl_b0_hw_vlan_ctrl(struct aq_hw_s *self, bool enable) 1552 { 1553 /* set promisc in case of disabing the vland filter */ 1554 hw_atl_rpf_vlan_prom_mode_en_set(self, !enable); 1555 1556 return aq_hw_err_from_flags(self); 1557 } 1558 1559 static int hw_atl_b0_set_loopback(struct aq_hw_s *self, u32 mode, bool enable) 1560 { 1561 switch (mode) { 1562 case AQ_HW_LOOPBACK_DMA_SYS: 1563 hw_atl_tpb_tx_dma_sys_lbk_en_set(self, enable); 1564 hw_atl_rpb_dma_sys_lbk_set(self, enable); 1565 break; 1566 case AQ_HW_LOOPBACK_PKT_SYS: 1567 hw_atl_tpo_tx_pkt_sys_lbk_en_set(self, enable); 1568 hw_atl_rpf_tpo_to_rpf_sys_lbk_set(self, enable); 1569 break; 1570 case AQ_HW_LOOPBACK_DMA_NET: 1571 hw_atl_rpf_vlan_prom_mode_en_set(self, enable); 1572 hw_atl_rpfl2promiscuous_mode_en_set(self, enable); 1573 hw_atl_tpb_tx_tx_clk_gate_en_set(self, !enable); 1574 hw_atl_tpb_tx_dma_net_lbk_en_set(self, enable); 1575 hw_atl_rpb_dma_net_lbk_set(self, enable); 1576 break; 1577 default: 1578 return -EINVAL; 1579 } 1580 1581 return 0; 1582 } 1583 1584 const struct aq_hw_ops hw_atl_ops_b0 = { 1585 .hw_soft_reset = hw_atl_utils_soft_reset, 1586 .hw_prepare = hw_atl_utils_initfw, 1587 .hw_set_mac_address = hw_atl_b0_hw_mac_addr_set, 1588 .hw_init = hw_atl_b0_hw_init, 1589 .hw_reset = hw_atl_b0_hw_reset, 1590 .hw_start = hw_atl_b0_hw_start, 1591 .hw_ring_tx_start = hw_atl_b0_hw_ring_tx_start, 1592 .hw_ring_tx_stop = hw_atl_b0_hw_ring_tx_stop, 1593 .hw_ring_rx_start = hw_atl_b0_hw_ring_rx_start, 1594 .hw_ring_rx_stop = hw_atl_b0_hw_ring_rx_stop, 1595 .hw_stop = hw_atl_b0_hw_stop, 1596 1597 .hw_ring_tx_xmit = hw_atl_b0_hw_ring_tx_xmit, 1598 .hw_ring_tx_head_update = hw_atl_b0_hw_ring_tx_head_update, 1599 1600 .hw_ring_rx_receive = hw_atl_b0_hw_ring_rx_receive, 1601 .hw_ring_rx_fill = hw_atl_b0_hw_ring_rx_fill, 1602 1603 .hw_irq_enable = hw_atl_b0_hw_irq_enable, 1604 .hw_irq_disable = hw_atl_b0_hw_irq_disable, 1605 .hw_irq_read = hw_atl_b0_hw_irq_read, 1606 1607 .hw_ring_rx_init = hw_atl_b0_hw_ring_rx_init, 1608 .hw_ring_tx_init = hw_atl_b0_hw_ring_tx_init, 1609 .hw_packet_filter_set = hw_atl_b0_hw_packet_filter_set, 1610 .hw_filter_l2_set = hw_atl_b0_hw_fl2_set, 1611 .hw_filter_l2_clear = hw_atl_b0_hw_fl2_clear, 1612 .hw_filter_l3l4_set = hw_atl_b0_hw_fl3l4_set, 1613 .hw_filter_vlan_set = hw_atl_b0_hw_vlan_set, 1614 .hw_filter_vlan_ctrl = hw_atl_b0_hw_vlan_ctrl, 1615 .hw_multicast_list_set = hw_atl_b0_hw_multicast_list_set, 1616 .hw_interrupt_moderation_set = hw_atl_b0_hw_interrupt_moderation_set, 1617 .hw_rss_set = hw_atl_b0_hw_rss_set, 1618 .hw_rss_hash_set = hw_atl_b0_hw_rss_hash_set, 1619 .hw_tc_rate_limit_set = hw_atl_b0_hw_init_tx_tc_rate_limit, 1620 .hw_get_regs = hw_atl_utils_hw_get_regs, 1621 .hw_get_hw_stats = hw_atl_utils_get_hw_stats, 1622 .hw_get_fw_version = hw_atl_utils_get_fw_version, 1623 1624 .hw_ring_hwts_rx_fill = hw_atl_b0_hw_ring_hwts_rx_fill, 1625 .hw_ring_hwts_rx_receive = hw_atl_b0_hw_ring_hwts_rx_receive, 1626 1627 .hw_get_ptp_ts = hw_atl_b0_get_ptp_ts, 1628 .hw_adj_sys_clock = hw_atl_b0_adj_sys_clock, 1629 .hw_set_sys_clock = hw_atl_b0_set_sys_clock, 1630 .hw_ts_to_sys_clock = hw_atl_b0_ts_to_sys_clock, 1631 .hw_adj_clock_freq = hw_atl_b0_adj_clock_freq, 1632 .hw_gpio_pulse = hw_atl_b0_gpio_pulse, 1633 .hw_extts_gpio_enable = hw_atl_b0_extts_gpio_enable, 1634 .hw_get_sync_ts = hw_atl_b0_get_sync_ts, 1635 .rx_extract_ts = hw_atl_b0_rx_extract_ts, 1636 .extract_hwts = hw_atl_b0_extract_hwts, 1637 .hw_set_offload = hw_atl_b0_hw_offload_set, 1638 .hw_set_loopback = hw_atl_b0_set_loopback, 1639 .hw_set_fc = hw_atl_b0_set_fc, 1640 }; 1641