175a6faf6SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2bab6de8fSDavid VomLehn /* 3bab6de8fSDavid VomLehn * aQuantia Corporation Network Driver 4bab6de8fSDavid VomLehn * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved 5bab6de8fSDavid VomLehn */ 6bab6de8fSDavid VomLehn 7bab6de8fSDavid VomLehn /* File hw_atl_a0_internal.h: Definition of Atlantic A0 chip specific 8bab6de8fSDavid VomLehn * constants. 9bab6de8fSDavid VomLehn */ 10bab6de8fSDavid VomLehn 11bab6de8fSDavid VomLehn #ifndef HW_ATL_A0_INTERNAL_H 12bab6de8fSDavid VomLehn #define HW_ATL_A0_INTERNAL_H 13bab6de8fSDavid VomLehn 14bab6de8fSDavid VomLehn #include "../aq_common.h" 15bab6de8fSDavid VomLehn 16bab6de8fSDavid VomLehn #define HW_ATL_A0_MTU_JUMBO 9014U 17bab6de8fSDavid VomLehn 18bab6de8fSDavid VomLehn #define HW_ATL_A0_TX_RINGS 4U 19bab6de8fSDavid VomLehn #define HW_ATL_A0_RX_RINGS 4U 20bab6de8fSDavid VomLehn 21bab6de8fSDavid VomLehn #define HW_ATL_A0_RINGS_MAX 32U 22bab6de8fSDavid VomLehn #define HW_ATL_A0_TXD_SIZE 16U 23bab6de8fSDavid VomLehn #define HW_ATL_A0_RXD_SIZE 16U 24bab6de8fSDavid VomLehn 25bab6de8fSDavid VomLehn #define HW_ATL_A0_MAC 0U 26bab6de8fSDavid VomLehn #define HW_ATL_A0_MAC_MIN 1U 27bab6de8fSDavid VomLehn #define HW_ATL_A0_MAC_MAX 33U 28bab6de8fSDavid VomLehn 29bab6de8fSDavid VomLehn /* interrupts */ 30bab6de8fSDavid VomLehn #define HW_ATL_A0_ERR_INT 8U 31bab6de8fSDavid VomLehn #define HW_ATL_A0_INT_MASK 0xFFFFFFFFU 32bab6de8fSDavid VomLehn 33bab6de8fSDavid VomLehn #define HW_ATL_A0_TXD_CTL2_LEN 0xFFFFC000U 34bab6de8fSDavid VomLehn #define HW_ATL_A0_TXD_CTL2_CTX_EN 0x00002000U 35bab6de8fSDavid VomLehn #define HW_ATL_A0_TXD_CTL2_CTX_IDX 0x00001000U 36bab6de8fSDavid VomLehn 37bab6de8fSDavid VomLehn #define HW_ATL_A0_TXD_CTL_DESC_TYPE_TXD 0x00000001U 38bab6de8fSDavid VomLehn #define HW_ATL_A0_TXD_CTL_DESC_TYPE_TXC 0x00000002U 39bab6de8fSDavid VomLehn #define HW_ATL_A0_TXD_CTL_BLEN 0x000FFFF0U 40bab6de8fSDavid VomLehn #define HW_ATL_A0_TXD_CTL_DD 0x00100000U 41bab6de8fSDavid VomLehn #define HW_ATL_A0_TXD_CTL_EOP 0x00200000U 42bab6de8fSDavid VomLehn 43bab6de8fSDavid VomLehn #define HW_ATL_A0_TXD_CTL_CMD_X 0x3FC00000U 44bab6de8fSDavid VomLehn 45bab6de8fSDavid VomLehn #define HW_ATL_A0_TXD_CTL_CMD_VLAN BIT(22) 46bab6de8fSDavid VomLehn #define HW_ATL_A0_TXD_CTL_CMD_FCS BIT(23) 47bab6de8fSDavid VomLehn #define HW_ATL_A0_TXD_CTL_CMD_IPCSO BIT(24) 48bab6de8fSDavid VomLehn #define HW_ATL_A0_TXD_CTL_CMD_TUCSO BIT(25) 49bab6de8fSDavid VomLehn #define HW_ATL_A0_TXD_CTL_CMD_LSO BIT(26) 50bab6de8fSDavid VomLehn #define HW_ATL_A0_TXD_CTL_CMD_WB BIT(27) 51bab6de8fSDavid VomLehn #define HW_ATL_A0_TXD_CTL_CMD_VXLAN BIT(28) 52bab6de8fSDavid VomLehn 53bab6de8fSDavid VomLehn #define HW_ATL_A0_TXD_CTL_CMD_IPV6 BIT(21) 54bab6de8fSDavid VomLehn #define HW_ATL_A0_TXD_CTL_CMD_TCP BIT(22) 55bab6de8fSDavid VomLehn 56bab6de8fSDavid VomLehn #define HW_ATL_A0_MPI_CONTROL_ADR 0x0368U 57bab6de8fSDavid VomLehn #define HW_ATL_A0_MPI_STATE_ADR 0x036CU 58bab6de8fSDavid VomLehn 59bab6de8fSDavid VomLehn #define HW_ATL_A0_MPI_SPEED_MSK 0xFFFFU 60bab6de8fSDavid VomLehn #define HW_ATL_A0_MPI_SPEED_SHIFT 16U 61bab6de8fSDavid VomLehn 62bab6de8fSDavid VomLehn #define HW_ATL_A0_TXBUF_MAX 160U 63bab6de8fSDavid VomLehn #define HW_ATL_A0_RXBUF_MAX 320U 64bab6de8fSDavid VomLehn 65bab6de8fSDavid VomLehn #define HW_ATL_A0_RSS_REDIRECTION_MAX 64U 66bab6de8fSDavid VomLehn #define HW_ATL_A0_RSS_REDIRECTION_BITS 3U 67bab6de8fSDavid VomLehn 68bab6de8fSDavid VomLehn #define HW_ATL_A0_TC_MAX 1U 69bab6de8fSDavid VomLehn #define HW_ATL_A0_RSS_MAX 8U 70bab6de8fSDavid VomLehn 71bab6de8fSDavid VomLehn #define HW_ATL_A0_FW_SEMA_RAM 0x2U 72bab6de8fSDavid VomLehn 73bab6de8fSDavid VomLehn #define HW_ATL_A0_RXD_DD 0x1U 74bab6de8fSDavid VomLehn #define HW_ATL_A0_RXD_NCEA0 0x1U 75bab6de8fSDavid VomLehn 76bab6de8fSDavid VomLehn #define HW_ATL_A0_RXD_WB_STAT2_EOP 0x0002U 77bab6de8fSDavid VomLehn 78bab6de8fSDavid VomLehn #define HW_ATL_A0_UCP_0X370_REG 0x370U 79bab6de8fSDavid VomLehn 80bab6de8fSDavid VomLehn #define HW_ATL_A0_FW_VER_EXPECTED 0x01050006U 81bab6de8fSDavid VomLehn 82c1af5427SAnton Mikaev #define HW_ATL_A0_MIN_RXD \ 83c1af5427SAnton Mikaev (ALIGN(AQ_CFG_SKB_FRAGS_MAX + 1U, AQ_HW_RXD_MULTIPLE)) 84c1af5427SAnton Mikaev #define HW_ATL_A0_MIN_TXD \ 85c1af5427SAnton Mikaev (ALIGN(AQ_CFG_SKB_FRAGS_MAX + 1U, AQ_HW_TXD_MULTIPLE)) 86c1af5427SAnton Mikaev 87c1af5427SAnton Mikaev #define HW_ATL_A0_MAX_RXD 8184U 88c1af5427SAnton Mikaev #define HW_ATL_A0_MAX_TXD 8184U 89c1af5427SAnton Mikaev 90bab6de8fSDavid VomLehn #endif /* HW_ATL_A0_INTERNAL_H */ 91