1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * aQuantia Corporation Network Driver
4  * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
5  */
6 
7 /* File aq_pci_func.c: Definition of PCI functions. */
8 
9 #include <linux/interrupt.h>
10 #include <linux/module.h>
11 
12 #include "aq_main.h"
13 #include "aq_nic.h"
14 #include "aq_vec.h"
15 #include "aq_hw.h"
16 #include "aq_pci_func.h"
17 #include "hw_atl/hw_atl_a0.h"
18 #include "hw_atl/hw_atl_b0.h"
19 #include "aq_filters.h"
20 #include "aq_drvinfo.h"
21 
22 static const struct pci_device_id aq_pci_tbl[] = {
23 	{ PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_0001), },
24 	{ PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_D100), },
25 	{ PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_D107), },
26 	{ PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_D108), },
27 	{ PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_D109), },
28 
29 	{ PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC100), },
30 	{ PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC107), },
31 	{ PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC108), },
32 	{ PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC109), },
33 	{ PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC111), },
34 	{ PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC112), },
35 
36 	{ PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC100S), },
37 	{ PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC107S), },
38 	{ PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC108S), },
39 	{ PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC109S), },
40 	{ PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC111S), },
41 	{ PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC112S), },
42 
43 	{}
44 };
45 
46 static const struct aq_board_revision_s hw_atl_boards[] = {
47 	{ AQ_DEVICE_ID_0001,	AQ_HWREV_1,	&hw_atl_ops_a0, &hw_atl_a0_caps_aqc107, },
48 	{ AQ_DEVICE_ID_D100,	AQ_HWREV_1,	&hw_atl_ops_a0, &hw_atl_a0_caps_aqc100, },
49 	{ AQ_DEVICE_ID_D107,	AQ_HWREV_1,	&hw_atl_ops_a0, &hw_atl_a0_caps_aqc107, },
50 	{ AQ_DEVICE_ID_D108,	AQ_HWREV_1,	&hw_atl_ops_a0, &hw_atl_a0_caps_aqc108, },
51 	{ AQ_DEVICE_ID_D109,	AQ_HWREV_1,	&hw_atl_ops_a0, &hw_atl_a0_caps_aqc109, },
52 
53 	{ AQ_DEVICE_ID_0001,	AQ_HWREV_2,	&hw_atl_ops_b0, &hw_atl_b0_caps_aqc107, },
54 	{ AQ_DEVICE_ID_D100,	AQ_HWREV_2,	&hw_atl_ops_b0, &hw_atl_b0_caps_aqc100, },
55 	{ AQ_DEVICE_ID_D107,	AQ_HWREV_2,	&hw_atl_ops_b0, &hw_atl_b0_caps_aqc107, },
56 	{ AQ_DEVICE_ID_D108,	AQ_HWREV_2,	&hw_atl_ops_b0, &hw_atl_b0_caps_aqc108, },
57 	{ AQ_DEVICE_ID_D109,	AQ_HWREV_2,	&hw_atl_ops_b0, &hw_atl_b0_caps_aqc109, },
58 
59 	{ AQ_DEVICE_ID_AQC100,	AQ_HWREV_ANY,	&hw_atl_ops_b1, &hw_atl_b0_caps_aqc107, },
60 	{ AQ_DEVICE_ID_AQC107,	AQ_HWREV_ANY,	&hw_atl_ops_b1, &hw_atl_b0_caps_aqc107, },
61 	{ AQ_DEVICE_ID_AQC108,	AQ_HWREV_ANY,	&hw_atl_ops_b1, &hw_atl_b0_caps_aqc108, },
62 	{ AQ_DEVICE_ID_AQC109,	AQ_HWREV_ANY,	&hw_atl_ops_b1, &hw_atl_b0_caps_aqc109, },
63 	{ AQ_DEVICE_ID_AQC111,	AQ_HWREV_ANY,	&hw_atl_ops_b1, &hw_atl_b0_caps_aqc111, },
64 	{ AQ_DEVICE_ID_AQC112,	AQ_HWREV_ANY,	&hw_atl_ops_b1, &hw_atl_b0_caps_aqc112, },
65 
66 	{ AQ_DEVICE_ID_AQC100S,	AQ_HWREV_ANY,	&hw_atl_ops_b1, &hw_atl_b0_caps_aqc100s, },
67 	{ AQ_DEVICE_ID_AQC107S,	AQ_HWREV_ANY,	&hw_atl_ops_b1, &hw_atl_b0_caps_aqc107s, },
68 	{ AQ_DEVICE_ID_AQC108S,	AQ_HWREV_ANY,	&hw_atl_ops_b1, &hw_atl_b0_caps_aqc108s, },
69 	{ AQ_DEVICE_ID_AQC109S,	AQ_HWREV_ANY,	&hw_atl_ops_b1, &hw_atl_b0_caps_aqc109s, },
70 	{ AQ_DEVICE_ID_AQC111S,	AQ_HWREV_ANY,	&hw_atl_ops_b1, &hw_atl_b0_caps_aqc111s, },
71 	{ AQ_DEVICE_ID_AQC112S,	AQ_HWREV_ANY,	&hw_atl_ops_b1, &hw_atl_b0_caps_aqc112s, },
72 };
73 
74 MODULE_DEVICE_TABLE(pci, aq_pci_tbl);
75 
76 static int aq_pci_probe_get_hw_by_id(struct pci_dev *pdev,
77 				     const struct aq_hw_ops **ops,
78 				     const struct aq_hw_caps_s **caps)
79 {
80 	int i;
81 
82 	if (pdev->vendor != PCI_VENDOR_ID_AQUANTIA)
83 		return -EINVAL;
84 
85 	for (i = 0; i < ARRAY_SIZE(hw_atl_boards); i++) {
86 		if (hw_atl_boards[i].devid == pdev->device &&
87 		    (hw_atl_boards[i].revision == AQ_HWREV_ANY ||
88 		     hw_atl_boards[i].revision == pdev->revision)) {
89 			*ops = hw_atl_boards[i].ops;
90 			*caps = hw_atl_boards[i].caps;
91 			break;
92 		}
93 	}
94 
95 	if (i == ARRAY_SIZE(hw_atl_boards))
96 		return -EINVAL;
97 
98 	return 0;
99 }
100 
101 int aq_pci_func_init(struct pci_dev *pdev)
102 {
103 	int err;
104 
105 	err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
106 	if (!err) {
107 		err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
108 
109 	}
110 	if (err) {
111 		err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
112 		if (!err)
113 			err = pci_set_consistent_dma_mask(pdev,
114 							  DMA_BIT_MASK(32));
115 	}
116 	if (err != 0) {
117 		err = -ENOSR;
118 		goto err_exit;
119 	}
120 
121 	err = pci_request_regions(pdev, AQ_CFG_DRV_NAME "_mmio");
122 	if (err < 0)
123 		goto err_exit;
124 
125 	pci_set_master(pdev);
126 
127 	return 0;
128 
129 err_exit:
130 	return err;
131 }
132 
133 int aq_pci_func_alloc_irq(struct aq_nic_s *self, unsigned int i,
134 			  char *name, irq_handler_t irq_handler,
135 			  void *irq_arg, cpumask_t *affinity_mask)
136 {
137 	struct pci_dev *pdev = self->pdev;
138 	int err;
139 
140 	if (pdev->msix_enabled || pdev->msi_enabled)
141 		err = request_irq(pci_irq_vector(pdev, i), irq_handler, 0,
142 				  name, irq_arg);
143 	else
144 		err = request_irq(pci_irq_vector(pdev, i), aq_vec_isr_legacy,
145 				  IRQF_SHARED, name, irq_arg);
146 
147 	if (err >= 0) {
148 		self->msix_entry_mask |= (1 << i);
149 
150 		if (pdev->msix_enabled && affinity_mask)
151 			irq_set_affinity_hint(pci_irq_vector(pdev, i),
152 					      affinity_mask);
153 	}
154 
155 	return err;
156 }
157 
158 void aq_pci_func_free_irqs(struct aq_nic_s *self)
159 {
160 	struct pci_dev *pdev = self->pdev;
161 	unsigned int i;
162 	void *irq_data;
163 
164 	for (i = 32U; i--;) {
165 		if (!((1U << i) & self->msix_entry_mask))
166 			continue;
167 		if (self->aq_nic_cfg.link_irq_vec &&
168 		    i == self->aq_nic_cfg.link_irq_vec)
169 			irq_data = self;
170 		else if (i < AQ_CFG_VECS_MAX)
171 			irq_data = self->aq_vec[i];
172 		else
173 			continue;
174 
175 		if (pdev->msix_enabled)
176 			irq_set_affinity_hint(pci_irq_vector(pdev, i), NULL);
177 		free_irq(pci_irq_vector(pdev, i), irq_data);
178 		self->msix_entry_mask &= ~(1U << i);
179 	}
180 }
181 
182 unsigned int aq_pci_func_get_irq_type(struct aq_nic_s *self)
183 {
184 	if (self->pdev->msix_enabled)
185 		return AQ_HW_IRQ_MSIX;
186 	if (self->pdev->msi_enabled)
187 		return AQ_HW_IRQ_MSI;
188 	return AQ_HW_IRQ_LEGACY;
189 }
190 
191 static void aq_pci_free_irq_vectors(struct aq_nic_s *self)
192 {
193 	pci_free_irq_vectors(self->pdev);
194 }
195 
196 static int aq_pci_probe(struct pci_dev *pdev,
197 			const struct pci_device_id *pci_id)
198 {
199 	struct aq_nic_s *self;
200 	int err;
201 	struct net_device *ndev;
202 	resource_size_t mmio_pa;
203 	u32 bar;
204 	u32 numvecs;
205 
206 	err = pci_enable_device(pdev);
207 	if (err)
208 		return err;
209 
210 	err = aq_pci_func_init(pdev);
211 	if (err)
212 		goto err_pci_func;
213 
214 	ndev = aq_ndev_alloc();
215 	if (!ndev) {
216 		err = -ENOMEM;
217 		goto err_ndev;
218 	}
219 
220 	self = netdev_priv(ndev);
221 	self->pdev = pdev;
222 	SET_NETDEV_DEV(ndev, &pdev->dev);
223 	pci_set_drvdata(pdev, self);
224 
225 	mutex_init(&self->fwreq_mutex);
226 
227 	err = aq_pci_probe_get_hw_by_id(pdev, &self->aq_hw_ops,
228 					&aq_nic_get_cfg(self)->aq_hw_caps);
229 	if (err)
230 		goto err_ioremap;
231 
232 	self->aq_hw = kzalloc(sizeof(*self->aq_hw), GFP_KERNEL);
233 	if (!self->aq_hw) {
234 		err = -ENOMEM;
235 		goto err_ioremap;
236 	}
237 	self->aq_hw->aq_nic_cfg = aq_nic_get_cfg(self);
238 
239 	for (bar = 0; bar < 4; ++bar) {
240 		if (IORESOURCE_MEM & pci_resource_flags(pdev, bar)) {
241 			resource_size_t reg_sz;
242 
243 			mmio_pa = pci_resource_start(pdev, bar);
244 			if (mmio_pa == 0U) {
245 				err = -EIO;
246 				goto err_free_aq_hw;
247 			}
248 
249 			reg_sz = pci_resource_len(pdev, bar);
250 			if ((reg_sz <= 24 /*ATL_REGS_SIZE*/)) {
251 				err = -EIO;
252 				goto err_free_aq_hw;
253 			}
254 
255 			self->aq_hw->mmio = ioremap_nocache(mmio_pa, reg_sz);
256 			if (!self->aq_hw->mmio) {
257 				err = -EIO;
258 				goto err_free_aq_hw;
259 			}
260 			break;
261 		}
262 	}
263 
264 	if (bar == 4) {
265 		err = -EIO;
266 		goto err_free_aq_hw;
267 	}
268 
269 	numvecs = min((u8)AQ_CFG_VECS_DEF,
270 		      aq_nic_get_cfg(self)->aq_hw_caps->msix_irqs);
271 	numvecs = min(numvecs, num_online_cpus());
272 	numvecs += AQ_HW_SERVICE_IRQS;
273 	/*enable interrupts */
274 #if !AQ_CFG_FORCE_LEGACY_INT
275 	err = pci_alloc_irq_vectors(self->pdev, 1, numvecs,
276 				    PCI_IRQ_MSIX | PCI_IRQ_MSI |
277 				    PCI_IRQ_LEGACY);
278 
279 	if (err < 0)
280 		goto err_hwinit;
281 	numvecs = err;
282 #endif
283 	self->irqvecs = numvecs;
284 
285 	/* net device init */
286 	aq_nic_cfg_start(self);
287 
288 	aq_nic_ndev_init(self);
289 
290 	err = aq_nic_ndev_register(self);
291 	if (err < 0)
292 		goto err_register;
293 
294 	aq_drvinfo_init(ndev);
295 
296 	return 0;
297 
298 err_register:
299 	aq_nic_free_vectors(self);
300 	aq_pci_free_irq_vectors(self);
301 err_hwinit:
302 	iounmap(self->aq_hw->mmio);
303 err_free_aq_hw:
304 	kfree(self->aq_hw);
305 err_ioremap:
306 	free_netdev(ndev);
307 err_ndev:
308 	pci_release_regions(pdev);
309 err_pci_func:
310 	pci_disable_device(pdev);
311 	return err;
312 }
313 
314 static void aq_pci_remove(struct pci_dev *pdev)
315 {
316 	struct aq_nic_s *self = pci_get_drvdata(pdev);
317 
318 	if (self->ndev) {
319 		aq_clear_rxnfc_all_rules(self);
320 		if (self->ndev->reg_state == NETREG_REGISTERED)
321 			unregister_netdev(self->ndev);
322 		aq_nic_free_vectors(self);
323 		aq_pci_free_irq_vectors(self);
324 		iounmap(self->aq_hw->mmio);
325 		kfree(self->aq_hw);
326 		pci_release_regions(pdev);
327 		free_netdev(self->ndev);
328 	}
329 
330 	pci_disable_device(pdev);
331 }
332 
333 static void aq_pci_shutdown(struct pci_dev *pdev)
334 {
335 	struct aq_nic_s *self = pci_get_drvdata(pdev);
336 
337 	aq_nic_shutdown(self);
338 
339 	pci_disable_device(pdev);
340 
341 	if (system_state == SYSTEM_POWER_OFF) {
342 		pci_wake_from_d3(pdev, false);
343 		pci_set_power_state(pdev, PCI_D3hot);
344 	}
345 }
346 
347 static int aq_pci_suspend(struct pci_dev *pdev, pm_message_t pm_msg)
348 {
349 	struct aq_nic_s *self = pci_get_drvdata(pdev);
350 
351 	return aq_nic_change_pm_state(self, &pm_msg);
352 }
353 
354 static int aq_pci_resume(struct pci_dev *pdev)
355 {
356 	struct aq_nic_s *self = pci_get_drvdata(pdev);
357 	pm_message_t pm_msg = PMSG_RESTORE;
358 
359 	return aq_nic_change_pm_state(self, &pm_msg);
360 }
361 
362 static struct pci_driver aq_pci_ops = {
363 	.name = AQ_CFG_DRV_NAME,
364 	.id_table = aq_pci_tbl,
365 	.probe = aq_pci_probe,
366 	.remove = aq_pci_remove,
367 	.suspend = aq_pci_suspend,
368 	.resume = aq_pci_resume,
369 	.shutdown = aq_pci_shutdown,
370 };
371 
372 int aq_pci_func_register_driver(void)
373 {
374 	return pci_register_driver(&aq_pci_ops);
375 }
376 
377 void aq_pci_func_unregister_driver(void)
378 {
379 	pci_unregister_driver(&aq_pci_ops);
380 }
381 
382