1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * aQuantia Corporation Network Driver
4  * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
5  */
6 
7 /* File aq_hw_utils.c: Definitions of helper functions used across
8  * hardware layer.
9  */
10 
11 #include "aq_hw_utils.h"
12 #include "aq_hw.h"
13 #include "aq_nic.h"
14 
15 void aq_hw_write_reg_bit(struct aq_hw_s *aq_hw, u32 addr, u32 msk,
16 			 u32 shift, u32 val)
17 {
18 	if (msk ^ ~0) {
19 		u32 reg_old, reg_new;
20 
21 		reg_old = aq_hw_read_reg(aq_hw, addr);
22 		reg_new = (reg_old & (~msk)) | (val << shift);
23 
24 		if (reg_old != reg_new)
25 			aq_hw_write_reg(aq_hw, addr, reg_new);
26 	} else {
27 		aq_hw_write_reg(aq_hw, addr, val);
28 	}
29 }
30 
31 u32 aq_hw_read_reg_bit(struct aq_hw_s *aq_hw, u32 addr, u32 msk, u32 shift)
32 {
33 	return ((aq_hw_read_reg(aq_hw, addr) & msk) >> shift);
34 }
35 
36 u32 aq_hw_read_reg(struct aq_hw_s *hw, u32 reg)
37 {
38 	u32 value = readl(hw->mmio + reg);
39 
40 	if ((~0U) == value &&
41 	    (~0U) == readl(hw->mmio +
42 			   hw->aq_nic_cfg->aq_hw_caps->hw_alive_check_addr))
43 		aq_utils_obj_set(&hw->flags, AQ_HW_FLAG_ERR_UNPLUG);
44 
45 	return value;
46 }
47 
48 void aq_hw_write_reg(struct aq_hw_s *hw, u32 reg, u32 value)
49 {
50 	writel(value, hw->mmio + reg);
51 }
52 
53 /* Most of 64-bit registers are in LSW, MSW form.
54    Counters are normally implemented by HW as latched pairs:
55    reading LSW first locks MSW, to overcome LSW overflow
56  */
57 u64 aq_hw_read_reg64(struct aq_hw_s *hw, u32 reg)
58 {
59 	u64 value = aq_hw_read_reg(hw, reg);
60 
61 	value |= (u64)aq_hw_read_reg(hw, reg + 4) << 32;
62 
63 	return value;
64 }
65 
66 int aq_hw_err_from_flags(struct aq_hw_s *hw)
67 {
68 	int err = 0;
69 
70 	if (aq_utils_obj_test(&hw->flags, AQ_HW_FLAG_ERR_UNPLUG)) {
71 		err = -ENXIO;
72 		goto err_exit;
73 	}
74 	if (aq_utils_obj_test(&hw->flags, AQ_HW_FLAG_ERR_HW)) {
75 		err = -EIO;
76 		goto err_exit;
77 	}
78 
79 err_exit:
80 	return err;
81 }
82 
83 int aq_hw_num_tcs(struct aq_hw_s *hw)
84 {
85 	switch (hw->aq_nic_cfg->tc_mode) {
86 	case AQ_TC_MODE_8TCS:
87 		return 8;
88 	case AQ_TC_MODE_4TCS:
89 		return 4;
90 	default:
91 		break;
92 	}
93 
94 	return 1;
95 }
96 
97 int aq_hw_q_per_tc(struct aq_hw_s *hw)
98 {
99 	switch (hw->aq_nic_cfg->tc_mode) {
100 	case AQ_TC_MODE_8TCS:
101 		return 4;
102 	case AQ_TC_MODE_4TCS:
103 		return 8;
104 	default:
105 		return 4;
106 	}
107 }
108