1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * aQuantia Corporation Network Driver 4 * Copyright (C) 2014-2019 aQuantia Corporation. All rights reserved 5 */ 6 7 /* File aq_hw.h: Declaration of abstract interface for NIC hardware specific 8 * functions. 9 */ 10 11 #ifndef AQ_HW_H 12 #define AQ_HW_H 13 14 #include "aq_common.h" 15 #include "aq_rss.h" 16 #include "hw_atl/hw_atl_utils.h" 17 18 #define AQ_HW_MAC_COUNTER_HZ 312500000ll 19 #define AQ_HW_PHY_COUNTER_HZ 160000000ll 20 21 enum aq_tc_mode { 22 AQ_TC_MODE_INVALID = -1, 23 AQ_TC_MODE_8TCS, 24 AQ_TC_MODE_4TCS, 25 }; 26 27 #define AQ_RX_FIRST_LOC_FVLANID 0U 28 #define AQ_RX_LAST_LOC_FVLANID 15U 29 #define AQ_RX_FIRST_LOC_FETHERT 16U 30 #define AQ_RX_LAST_LOC_FETHERT 31U 31 #define AQ_RX_FIRST_LOC_FL3L4 32U 32 #define AQ_RX_LAST_LOC_FL3L4 39U 33 #define AQ_RX_MAX_RXNFC_LOC AQ_RX_LAST_LOC_FL3L4 34 #define AQ_VLAN_MAX_FILTERS \ 35 (AQ_RX_LAST_LOC_FVLANID - AQ_RX_FIRST_LOC_FVLANID + 1U) 36 #define AQ_RX_QUEUE_NOT_ASSIGNED 0xFFU 37 38 /* Used for rate to Mbps conversion */ 39 #define AQ_MBPS_DIVISOR 125000 /* 1000000 / 8 */ 40 41 /* NIC H/W capabilities */ 42 struct aq_hw_caps_s { 43 u64 hw_features; 44 u64 link_speed_msk; 45 unsigned int hw_priv_flags; 46 u32 media_type; 47 u32 rxds_max; 48 u32 txds_max; 49 u32 rxds_min; 50 u32 txds_min; 51 u32 txhwb_alignment; 52 u32 irq_mask; 53 u32 vecs; 54 u32 mtu; 55 u32 mac_regs_count; 56 u32 hw_alive_check_addr; 57 u8 msix_irqs; 58 u8 tcs_max; 59 u8 rxd_alignment; 60 u8 rxd_size; 61 u8 txd_alignment; 62 u8 txd_size; 63 u8 tx_rings; 64 u8 rx_rings; 65 bool flow_control; 66 bool is_64_dma; 67 u32 quirks; 68 u32 priv_data_len; 69 }; 70 71 struct aq_hw_link_status_s { 72 unsigned int mbps; 73 }; 74 75 struct aq_stats_s { 76 u64 uprc; 77 u64 mprc; 78 u64 bprc; 79 u64 erpt; 80 u64 uptc; 81 u64 mptc; 82 u64 bptc; 83 u64 erpr; 84 u64 mbtc; 85 u64 bbtc; 86 u64 mbrc; 87 u64 bbrc; 88 u64 ubrc; 89 u64 ubtc; 90 u64 dpc; 91 u64 dma_pkt_rc; 92 u64 dma_pkt_tc; 93 u64 dma_oct_rc; 94 u64 dma_oct_tc; 95 }; 96 97 #define AQ_HW_IRQ_INVALID 0U 98 #define AQ_HW_IRQ_LEGACY 1U 99 #define AQ_HW_IRQ_MSI 2U 100 #define AQ_HW_IRQ_MSIX 3U 101 102 #define AQ_HW_SERVICE_IRQS 1U 103 104 #define AQ_HW_POWER_STATE_D0 0U 105 #define AQ_HW_POWER_STATE_D3 3U 106 107 #define AQ_HW_FLAG_STARTED 0x00000004U 108 #define AQ_HW_FLAG_STOPPING 0x00000008U 109 #define AQ_HW_FLAG_RESETTING 0x00000010U 110 #define AQ_HW_FLAG_CLOSING 0x00000020U 111 #define AQ_HW_PTP_AVAILABLE 0x01000000U 112 #define AQ_HW_LINK_DOWN 0x04000000U 113 #define AQ_HW_FLAG_ERR_UNPLUG 0x40000000U 114 #define AQ_HW_FLAG_ERR_HW 0x80000000U 115 116 #define AQ_HW_FLAG_ERRORS (AQ_HW_FLAG_ERR_HW | AQ_HW_FLAG_ERR_UNPLUG) 117 118 #define AQ_NIC_FLAGS_IS_NOT_READY (AQ_NIC_FLAG_STOPPING | \ 119 AQ_NIC_FLAG_RESETTING | AQ_NIC_FLAG_CLOSING | \ 120 AQ_NIC_FLAG_ERR_UNPLUG | AQ_NIC_FLAG_ERR_HW) 121 122 #define AQ_NIC_FLAGS_IS_NOT_TX_READY (AQ_NIC_FLAGS_IS_NOT_READY | \ 123 AQ_NIC_LINK_DOWN) 124 125 #define AQ_HW_MEDIA_TYPE_TP 1U 126 #define AQ_HW_MEDIA_TYPE_FIBRE 2U 127 128 #define AQ_HW_TXD_MULTIPLE 8U 129 #define AQ_HW_RXD_MULTIPLE 8U 130 131 #define AQ_HW_QUEUES_MAX 32U 132 #define AQ_HW_MULTICAST_ADDRESS_MAX 32U 133 134 #define AQ_HW_PTP_TC 2U 135 136 #define AQ_HW_LED_BLINK 0x2U 137 #define AQ_HW_LED_DEFAULT 0x0U 138 139 enum aq_priv_flags { 140 AQ_HW_LOOPBACK_DMA_SYS, 141 AQ_HW_LOOPBACK_PKT_SYS, 142 AQ_HW_LOOPBACK_DMA_NET, 143 AQ_HW_LOOPBACK_PHYINT_SYS, 144 AQ_HW_LOOPBACK_PHYEXT_SYS, 145 }; 146 147 #define AQ_HW_LOOPBACK_MASK (BIT(AQ_HW_LOOPBACK_DMA_SYS) |\ 148 BIT(AQ_HW_LOOPBACK_PKT_SYS) |\ 149 BIT(AQ_HW_LOOPBACK_DMA_NET) |\ 150 BIT(AQ_HW_LOOPBACK_PHYINT_SYS) |\ 151 BIT(AQ_HW_LOOPBACK_PHYEXT_SYS)) 152 153 #define ATL_HW_CHIP_MIPS 0x00000001U 154 #define ATL_HW_CHIP_TPO2 0x00000002U 155 #define ATL_HW_CHIP_RPF2 0x00000004U 156 #define ATL_HW_CHIP_MPI_AQ 0x00000010U 157 #define ATL_HW_CHIP_ATLANTIC 0x00800000U 158 #define ATL_HW_CHIP_REVISION_A0 0x01000000U 159 #define ATL_HW_CHIP_REVISION_B0 0x02000000U 160 #define ATL_HW_CHIP_REVISION_B1 0x04000000U 161 #define ATL_HW_CHIP_ANTIGUA 0x08000000U 162 163 #define ATL_HW_IS_CHIP_FEATURE(_HW_, _F_) (!!(ATL_HW_CHIP_##_F_ & \ 164 (_HW_)->chip_features)) 165 166 struct aq_hw_s { 167 atomic_t flags; 168 u8 rbl_enabled:1; 169 struct aq_nic_cfg_s *aq_nic_cfg; 170 const struct aq_fw_ops *aq_fw_ops; 171 void __iomem *mmio; 172 struct aq_hw_link_status_s aq_link_status; 173 struct hw_atl_utils_mbox mbox; 174 struct hw_atl_stats_s last_stats; 175 struct aq_stats_s curr_stats; 176 u64 speed; 177 u32 itr_tx; 178 u32 itr_rx; 179 unsigned int chip_features; 180 u32 fw_ver_actual; 181 atomic_t dpc; 182 u32 mbox_addr; 183 u32 rpc_addr; 184 u32 settings_addr; 185 u32 rpc_tid; 186 struct hw_atl_utils_fw_rpc rpc; 187 s64 ptp_clk_offset; 188 u16 phy_id; 189 void *priv; 190 }; 191 192 struct aq_ring_s; 193 struct aq_ring_param_s; 194 struct sk_buff; 195 struct aq_rx_filter_l3l4; 196 197 struct aq_hw_ops { 198 199 int (*hw_ring_tx_xmit)(struct aq_hw_s *self, struct aq_ring_s *aq_ring, 200 unsigned int frags); 201 202 int (*hw_ring_rx_receive)(struct aq_hw_s *self, 203 struct aq_ring_s *aq_ring); 204 205 int (*hw_ring_rx_fill)(struct aq_hw_s *self, struct aq_ring_s *aq_ring, 206 unsigned int sw_tail_old); 207 208 int (*hw_ring_tx_head_update)(struct aq_hw_s *self, 209 struct aq_ring_s *aq_ring); 210 211 int (*hw_set_mac_address)(struct aq_hw_s *self, u8 *mac_addr); 212 213 int (*hw_soft_reset)(struct aq_hw_s *self); 214 215 int (*hw_prepare)(struct aq_hw_s *self, 216 const struct aq_fw_ops **fw_ops); 217 218 int (*hw_reset)(struct aq_hw_s *self); 219 220 int (*hw_init)(struct aq_hw_s *self, u8 *mac_addr); 221 222 int (*hw_start)(struct aq_hw_s *self); 223 224 int (*hw_stop)(struct aq_hw_s *self); 225 226 int (*hw_ring_tx_init)(struct aq_hw_s *self, struct aq_ring_s *aq_ring, 227 struct aq_ring_param_s *aq_ring_param); 228 229 int (*hw_ring_tx_start)(struct aq_hw_s *self, 230 struct aq_ring_s *aq_ring); 231 232 int (*hw_ring_tx_stop)(struct aq_hw_s *self, 233 struct aq_ring_s *aq_ring); 234 235 int (*hw_ring_rx_init)(struct aq_hw_s *self, 236 struct aq_ring_s *aq_ring, 237 struct aq_ring_param_s *aq_ring_param); 238 239 int (*hw_ring_rx_start)(struct aq_hw_s *self, 240 struct aq_ring_s *aq_ring); 241 242 int (*hw_ring_rx_stop)(struct aq_hw_s *self, 243 struct aq_ring_s *aq_ring); 244 245 int (*hw_irq_enable)(struct aq_hw_s *self, u64 mask); 246 247 int (*hw_irq_disable)(struct aq_hw_s *self, u64 mask); 248 249 int (*hw_irq_read)(struct aq_hw_s *self, u64 *mask); 250 251 int (*hw_packet_filter_set)(struct aq_hw_s *self, 252 unsigned int packet_filter); 253 254 int (*hw_filter_l3l4_set)(struct aq_hw_s *self, 255 struct aq_rx_filter_l3l4 *data); 256 257 int (*hw_filter_l3l4_clear)(struct aq_hw_s *self, 258 struct aq_rx_filter_l3l4 *data); 259 260 int (*hw_filter_l2_set)(struct aq_hw_s *self, 261 struct aq_rx_filter_l2 *data); 262 263 int (*hw_filter_l2_clear)(struct aq_hw_s *self, 264 struct aq_rx_filter_l2 *data); 265 266 int (*hw_filter_vlan_set)(struct aq_hw_s *self, 267 struct aq_rx_filter_vlan *aq_vlans); 268 269 int (*hw_filter_vlan_ctrl)(struct aq_hw_s *self, bool enable); 270 271 int (*hw_multicast_list_set)(struct aq_hw_s *self, 272 u8 ar_mac[AQ_HW_MULTICAST_ADDRESS_MAX] 273 [ETH_ALEN], 274 u32 count); 275 276 int (*hw_interrupt_moderation_set)(struct aq_hw_s *self); 277 278 int (*hw_rss_set)(struct aq_hw_s *self, 279 struct aq_rss_parameters *rss_params); 280 281 int (*hw_rss_hash_set)(struct aq_hw_s *self, 282 struct aq_rss_parameters *rss_params); 283 284 int (*hw_tc_rate_limit_set)(struct aq_hw_s *self); 285 286 int (*hw_get_regs)(struct aq_hw_s *self, 287 const struct aq_hw_caps_s *aq_hw_caps, 288 u32 *regs_buff); 289 290 struct aq_stats_s *(*hw_get_hw_stats)(struct aq_hw_s *self); 291 292 u32 (*hw_get_fw_version)(struct aq_hw_s *self); 293 294 int (*hw_set_offload)(struct aq_hw_s *self, 295 struct aq_nic_cfg_s *aq_nic_cfg); 296 297 int (*hw_ring_hwts_rx_fill)(struct aq_hw_s *self, 298 struct aq_ring_s *aq_ring); 299 300 int (*hw_ring_hwts_rx_receive)(struct aq_hw_s *self, 301 struct aq_ring_s *ring); 302 303 void (*hw_get_ptp_ts)(struct aq_hw_s *self, u64 *stamp); 304 305 int (*hw_adj_clock_freq)(struct aq_hw_s *self, s32 delta); 306 307 int (*hw_adj_sys_clock)(struct aq_hw_s *self, s64 delta); 308 309 int (*hw_set_sys_clock)(struct aq_hw_s *self, u64 time, u64 ts); 310 311 int (*hw_ts_to_sys_clock)(struct aq_hw_s *self, u64 ts, u64 *time); 312 313 int (*hw_gpio_pulse)(struct aq_hw_s *self, u32 index, u64 start, 314 u32 period); 315 316 int (*hw_extts_gpio_enable)(struct aq_hw_s *self, u32 index, 317 u32 enable); 318 319 int (*hw_get_sync_ts)(struct aq_hw_s *self, u64 *ts); 320 321 u16 (*rx_extract_ts)(struct aq_hw_s *self, u8 *p, unsigned int len, 322 u64 *timestamp); 323 324 int (*extract_hwts)(struct aq_hw_s *self, u8 *p, unsigned int len, 325 u64 *timestamp); 326 327 int (*hw_set_fc)(struct aq_hw_s *self, u32 fc, u32 tc); 328 329 int (*hw_set_loopback)(struct aq_hw_s *self, u32 mode, bool enable); 330 }; 331 332 struct aq_fw_ops { 333 int (*init)(struct aq_hw_s *self); 334 335 int (*deinit)(struct aq_hw_s *self); 336 337 int (*reset)(struct aq_hw_s *self); 338 339 int (*renegotiate)(struct aq_hw_s *self); 340 341 int (*get_mac_permanent)(struct aq_hw_s *self, u8 *mac); 342 343 int (*set_link_speed)(struct aq_hw_s *self, u32 speed); 344 345 int (*set_state)(struct aq_hw_s *self, 346 enum hal_atl_utils_fw_state_e state); 347 348 int (*update_link_status)(struct aq_hw_s *self); 349 350 int (*update_stats)(struct aq_hw_s *self); 351 352 int (*get_phy_temp)(struct aq_hw_s *self, int *temp); 353 354 u32 (*get_flow_control)(struct aq_hw_s *self, u32 *fcmode); 355 356 int (*set_flow_control)(struct aq_hw_s *self); 357 358 int (*led_control)(struct aq_hw_s *self, u32 mode); 359 360 int (*set_phyloopback)(struct aq_hw_s *self, u32 mode, bool enable); 361 362 int (*set_power)(struct aq_hw_s *self, unsigned int power_state, 363 u8 *mac); 364 365 int (*send_fw_request)(struct aq_hw_s *self, 366 const struct hw_fw_request_iface *fw_req, 367 size_t size); 368 369 void (*enable_ptp)(struct aq_hw_s *self, int enable); 370 371 void (*adjust_ptp)(struct aq_hw_s *self, uint64_t adj); 372 373 int (*set_eee_rate)(struct aq_hw_s *self, u32 speed); 374 375 int (*get_eee_rate)(struct aq_hw_s *self, u32 *rate, 376 u32 *supported_rates); 377 378 u32 (*get_link_capabilities)(struct aq_hw_s *self); 379 380 int (*send_macsec_req)(struct aq_hw_s *self, 381 struct macsec_msg_fw_request *msg, 382 struct macsec_msg_fw_response *resp); 383 }; 384 385 #endif /* AQ_HW_H */ 386