1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * aQuantia Corporation Network Driver 4 * Copyright (C) 2014-2019 aQuantia Corporation. All rights reserved 5 */ 6 7 /* File aq_hw.h: Declaration of abstract interface for NIC hardware specific 8 * functions. 9 */ 10 11 #ifndef AQ_HW_H 12 #define AQ_HW_H 13 14 #include "aq_common.h" 15 #include "aq_rss.h" 16 #include "hw_atl/hw_atl_utils.h" 17 18 #define AQ_HW_MAC_COUNTER_HZ 312500000ll 19 #define AQ_HW_PHY_COUNTER_HZ 160000000ll 20 21 enum aq_tc_mode { 22 AQ_TC_MODE_INVALID = -1, 23 AQ_TC_MODE_8TCS, 24 AQ_TC_MODE_4TCS, 25 }; 26 27 #define AQ_RX_FIRST_LOC_FVLANID 0U 28 #define AQ_RX_LAST_LOC_FVLANID 15U 29 #define AQ_RX_FIRST_LOC_FETHERT 16U 30 #define AQ_RX_LAST_LOC_FETHERT 31U 31 #define AQ_RX_FIRST_LOC_FL3L4 32U 32 #define AQ_RX_LAST_LOC_FL3L4 39U 33 #define AQ_RX_MAX_RXNFC_LOC AQ_RX_LAST_LOC_FL3L4 34 #define AQ_VLAN_MAX_FILTERS \ 35 (AQ_RX_LAST_LOC_FVLANID - AQ_RX_FIRST_LOC_FVLANID + 1U) 36 #define AQ_RX_QUEUE_NOT_ASSIGNED 0xFFU 37 38 /* Used for rate to Mbps conversion */ 39 #define AQ_MBPS_DIVISOR 125000 /* 1000000 / 8 */ 40 41 /* NIC H/W capabilities */ 42 struct aq_hw_caps_s { 43 u64 hw_features; 44 u64 link_speed_msk; 45 unsigned int hw_priv_flags; 46 u32 media_type; 47 u32 rxds_max; 48 u32 txds_max; 49 u32 rxds_min; 50 u32 txds_min; 51 u32 txhwb_alignment; 52 u32 irq_mask; 53 u32 vecs; 54 u32 mtu; 55 u32 mac_regs_count; 56 u32 hw_alive_check_addr; 57 u8 msix_irqs; 58 u8 tcs_max; 59 u8 rxd_alignment; 60 u8 rxd_size; 61 u8 txd_alignment; 62 u8 txd_size; 63 u8 tx_rings; 64 u8 rx_rings; 65 bool flow_control; 66 bool is_64_dma; 67 u32 priv_data_len; 68 }; 69 70 struct aq_hw_link_status_s { 71 unsigned int mbps; 72 }; 73 74 struct aq_stats_s { 75 u64 uprc; 76 u64 mprc; 77 u64 bprc; 78 u64 erpt; 79 u64 uptc; 80 u64 mptc; 81 u64 bptc; 82 u64 erpr; 83 u64 mbtc; 84 u64 bbtc; 85 u64 mbrc; 86 u64 bbrc; 87 u64 ubrc; 88 u64 ubtc; 89 u64 dpc; 90 u64 dma_pkt_rc; 91 u64 dma_pkt_tc; 92 u64 dma_oct_rc; 93 u64 dma_oct_tc; 94 }; 95 96 #define AQ_HW_IRQ_INVALID 0U 97 #define AQ_HW_IRQ_LEGACY 1U 98 #define AQ_HW_IRQ_MSI 2U 99 #define AQ_HW_IRQ_MSIX 3U 100 101 #define AQ_HW_SERVICE_IRQS 1U 102 103 #define AQ_HW_POWER_STATE_D0 0U 104 #define AQ_HW_POWER_STATE_D3 3U 105 106 #define AQ_HW_FLAG_STARTED 0x00000004U 107 #define AQ_HW_FLAG_STOPPING 0x00000008U 108 #define AQ_HW_FLAG_RESETTING 0x00000010U 109 #define AQ_HW_FLAG_CLOSING 0x00000020U 110 #define AQ_HW_PTP_AVAILABLE 0x01000000U 111 #define AQ_HW_LINK_DOWN 0x04000000U 112 #define AQ_HW_FLAG_ERR_UNPLUG 0x40000000U 113 #define AQ_HW_FLAG_ERR_HW 0x80000000U 114 115 #define AQ_HW_FLAG_ERRORS (AQ_HW_FLAG_ERR_HW | AQ_HW_FLAG_ERR_UNPLUG) 116 117 #define AQ_NIC_FLAGS_IS_NOT_READY (AQ_NIC_FLAG_STOPPING | \ 118 AQ_NIC_FLAG_RESETTING | AQ_NIC_FLAG_CLOSING | \ 119 AQ_NIC_FLAG_ERR_UNPLUG | AQ_NIC_FLAG_ERR_HW) 120 121 #define AQ_NIC_FLAGS_IS_NOT_TX_READY (AQ_NIC_FLAGS_IS_NOT_READY | \ 122 AQ_NIC_LINK_DOWN) 123 124 #define AQ_HW_MEDIA_TYPE_TP 1U 125 #define AQ_HW_MEDIA_TYPE_FIBRE 2U 126 127 #define AQ_HW_TXD_MULTIPLE 8U 128 #define AQ_HW_RXD_MULTIPLE 8U 129 130 #define AQ_HW_QUEUES_MAX 32U 131 #define AQ_HW_MULTICAST_ADDRESS_MAX 32U 132 133 #define AQ_HW_PTP_TC 2U 134 135 #define AQ_HW_LED_BLINK 0x2U 136 #define AQ_HW_LED_DEFAULT 0x0U 137 138 enum aq_priv_flags { 139 AQ_HW_LOOPBACK_DMA_SYS, 140 AQ_HW_LOOPBACK_PKT_SYS, 141 AQ_HW_LOOPBACK_DMA_NET, 142 AQ_HW_LOOPBACK_PHYINT_SYS, 143 AQ_HW_LOOPBACK_PHYEXT_SYS, 144 }; 145 146 #define AQ_HW_LOOPBACK_MASK (BIT(AQ_HW_LOOPBACK_DMA_SYS) |\ 147 BIT(AQ_HW_LOOPBACK_PKT_SYS) |\ 148 BIT(AQ_HW_LOOPBACK_DMA_NET) |\ 149 BIT(AQ_HW_LOOPBACK_PHYINT_SYS) |\ 150 BIT(AQ_HW_LOOPBACK_PHYEXT_SYS)) 151 152 #define ATL_HW_CHIP_MIPS 0x00000001U 153 #define ATL_HW_CHIP_TPO2 0x00000002U 154 #define ATL_HW_CHIP_RPF2 0x00000004U 155 #define ATL_HW_CHIP_MPI_AQ 0x00000010U 156 #define ATL_HW_CHIP_ATLANTIC 0x00800000U 157 #define ATL_HW_CHIP_REVISION_A0 0x01000000U 158 #define ATL_HW_CHIP_REVISION_B0 0x02000000U 159 #define ATL_HW_CHIP_REVISION_B1 0x04000000U 160 #define ATL_HW_CHIP_ANTIGUA 0x08000000U 161 162 #define ATL_HW_IS_CHIP_FEATURE(_HW_, _F_) (!!(ATL_HW_CHIP_##_F_ & \ 163 (_HW_)->chip_features)) 164 165 struct aq_hw_s { 166 atomic_t flags; 167 u8 rbl_enabled:1; 168 struct aq_nic_cfg_s *aq_nic_cfg; 169 const struct aq_fw_ops *aq_fw_ops; 170 void __iomem *mmio; 171 struct aq_hw_link_status_s aq_link_status; 172 struct hw_atl_utils_mbox mbox; 173 struct hw_atl_stats_s last_stats; 174 struct aq_stats_s curr_stats; 175 u64 speed; 176 u32 itr_tx; 177 u32 itr_rx; 178 unsigned int chip_features; 179 u32 fw_ver_actual; 180 atomic_t dpc; 181 u32 mbox_addr; 182 u32 rpc_addr; 183 u32 settings_addr; 184 u32 rpc_tid; 185 struct hw_atl_utils_fw_rpc rpc; 186 s64 ptp_clk_offset; 187 u16 phy_id; 188 void *priv; 189 }; 190 191 struct aq_ring_s; 192 struct aq_ring_param_s; 193 struct sk_buff; 194 struct aq_rx_filter_l3l4; 195 196 struct aq_hw_ops { 197 198 int (*hw_ring_tx_xmit)(struct aq_hw_s *self, struct aq_ring_s *aq_ring, 199 unsigned int frags); 200 201 int (*hw_ring_rx_receive)(struct aq_hw_s *self, 202 struct aq_ring_s *aq_ring); 203 204 int (*hw_ring_rx_fill)(struct aq_hw_s *self, struct aq_ring_s *aq_ring, 205 unsigned int sw_tail_old); 206 207 int (*hw_ring_tx_head_update)(struct aq_hw_s *self, 208 struct aq_ring_s *aq_ring); 209 210 int (*hw_set_mac_address)(struct aq_hw_s *self, u8 *mac_addr); 211 212 int (*hw_soft_reset)(struct aq_hw_s *self); 213 214 int (*hw_prepare)(struct aq_hw_s *self, 215 const struct aq_fw_ops **fw_ops); 216 217 int (*hw_reset)(struct aq_hw_s *self); 218 219 int (*hw_init)(struct aq_hw_s *self, u8 *mac_addr); 220 221 int (*hw_start)(struct aq_hw_s *self); 222 223 int (*hw_stop)(struct aq_hw_s *self); 224 225 int (*hw_ring_tx_init)(struct aq_hw_s *self, struct aq_ring_s *aq_ring, 226 struct aq_ring_param_s *aq_ring_param); 227 228 int (*hw_ring_tx_start)(struct aq_hw_s *self, 229 struct aq_ring_s *aq_ring); 230 231 int (*hw_ring_tx_stop)(struct aq_hw_s *self, 232 struct aq_ring_s *aq_ring); 233 234 int (*hw_ring_rx_init)(struct aq_hw_s *self, 235 struct aq_ring_s *aq_ring, 236 struct aq_ring_param_s *aq_ring_param); 237 238 int (*hw_ring_rx_start)(struct aq_hw_s *self, 239 struct aq_ring_s *aq_ring); 240 241 int (*hw_ring_rx_stop)(struct aq_hw_s *self, 242 struct aq_ring_s *aq_ring); 243 244 int (*hw_irq_enable)(struct aq_hw_s *self, u64 mask); 245 246 int (*hw_irq_disable)(struct aq_hw_s *self, u64 mask); 247 248 int (*hw_irq_read)(struct aq_hw_s *self, u64 *mask); 249 250 int (*hw_packet_filter_set)(struct aq_hw_s *self, 251 unsigned int packet_filter); 252 253 int (*hw_filter_l3l4_set)(struct aq_hw_s *self, 254 struct aq_rx_filter_l3l4 *data); 255 256 int (*hw_filter_l3l4_clear)(struct aq_hw_s *self, 257 struct aq_rx_filter_l3l4 *data); 258 259 int (*hw_filter_l2_set)(struct aq_hw_s *self, 260 struct aq_rx_filter_l2 *data); 261 262 int (*hw_filter_l2_clear)(struct aq_hw_s *self, 263 struct aq_rx_filter_l2 *data); 264 265 int (*hw_filter_vlan_set)(struct aq_hw_s *self, 266 struct aq_rx_filter_vlan *aq_vlans); 267 268 int (*hw_filter_vlan_ctrl)(struct aq_hw_s *self, bool enable); 269 270 int (*hw_multicast_list_set)(struct aq_hw_s *self, 271 u8 ar_mac[AQ_HW_MULTICAST_ADDRESS_MAX] 272 [ETH_ALEN], 273 u32 count); 274 275 int (*hw_interrupt_moderation_set)(struct aq_hw_s *self); 276 277 int (*hw_rss_set)(struct aq_hw_s *self, 278 struct aq_rss_parameters *rss_params); 279 280 int (*hw_rss_hash_set)(struct aq_hw_s *self, 281 struct aq_rss_parameters *rss_params); 282 283 int (*hw_tc_rate_limit_set)(struct aq_hw_s *self); 284 285 int (*hw_get_regs)(struct aq_hw_s *self, 286 const struct aq_hw_caps_s *aq_hw_caps, 287 u32 *regs_buff); 288 289 struct aq_stats_s *(*hw_get_hw_stats)(struct aq_hw_s *self); 290 291 u32 (*hw_get_fw_version)(struct aq_hw_s *self); 292 293 int (*hw_set_offload)(struct aq_hw_s *self, 294 struct aq_nic_cfg_s *aq_nic_cfg); 295 296 int (*hw_ring_hwts_rx_fill)(struct aq_hw_s *self, 297 struct aq_ring_s *aq_ring); 298 299 int (*hw_ring_hwts_rx_receive)(struct aq_hw_s *self, 300 struct aq_ring_s *ring); 301 302 void (*hw_get_ptp_ts)(struct aq_hw_s *self, u64 *stamp); 303 304 int (*hw_adj_clock_freq)(struct aq_hw_s *self, s32 delta); 305 306 int (*hw_adj_sys_clock)(struct aq_hw_s *self, s64 delta); 307 308 int (*hw_set_sys_clock)(struct aq_hw_s *self, u64 time, u64 ts); 309 310 int (*hw_ts_to_sys_clock)(struct aq_hw_s *self, u64 ts, u64 *time); 311 312 int (*hw_gpio_pulse)(struct aq_hw_s *self, u32 index, u64 start, 313 u32 period); 314 315 int (*hw_extts_gpio_enable)(struct aq_hw_s *self, u32 index, 316 u32 enable); 317 318 int (*hw_get_sync_ts)(struct aq_hw_s *self, u64 *ts); 319 320 u16 (*rx_extract_ts)(struct aq_hw_s *self, u8 *p, unsigned int len, 321 u64 *timestamp); 322 323 int (*extract_hwts)(struct aq_hw_s *self, u8 *p, unsigned int len, 324 u64 *timestamp); 325 326 int (*hw_set_fc)(struct aq_hw_s *self, u32 fc, u32 tc); 327 328 int (*hw_set_loopback)(struct aq_hw_s *self, u32 mode, bool enable); 329 }; 330 331 struct aq_fw_ops { 332 int (*init)(struct aq_hw_s *self); 333 334 int (*deinit)(struct aq_hw_s *self); 335 336 int (*reset)(struct aq_hw_s *self); 337 338 int (*renegotiate)(struct aq_hw_s *self); 339 340 int (*get_mac_permanent)(struct aq_hw_s *self, u8 *mac); 341 342 int (*set_link_speed)(struct aq_hw_s *self, u32 speed); 343 344 int (*set_state)(struct aq_hw_s *self, 345 enum hal_atl_utils_fw_state_e state); 346 347 int (*update_link_status)(struct aq_hw_s *self); 348 349 int (*update_stats)(struct aq_hw_s *self); 350 351 int (*get_phy_temp)(struct aq_hw_s *self, int *temp); 352 353 u32 (*get_flow_control)(struct aq_hw_s *self, u32 *fcmode); 354 355 int (*set_flow_control)(struct aq_hw_s *self); 356 357 int (*led_control)(struct aq_hw_s *self, u32 mode); 358 359 int (*set_phyloopback)(struct aq_hw_s *self, u32 mode, bool enable); 360 361 int (*set_power)(struct aq_hw_s *self, unsigned int power_state, 362 u8 *mac); 363 364 int (*send_fw_request)(struct aq_hw_s *self, 365 const struct hw_fw_request_iface *fw_req, 366 size_t size); 367 368 void (*enable_ptp)(struct aq_hw_s *self, int enable); 369 370 void (*adjust_ptp)(struct aq_hw_s *self, uint64_t adj); 371 372 int (*set_eee_rate)(struct aq_hw_s *self, u32 speed); 373 374 int (*get_eee_rate)(struct aq_hw_s *self, u32 *rate, 375 u32 *supported_rates); 376 377 u32 (*get_link_capabilities)(struct aq_hw_s *self); 378 379 int (*send_macsec_req)(struct aq_hw_s *self, 380 struct macsec_msg_fw_request *msg, 381 struct macsec_msg_fw_response *resp); 382 }; 383 384 #endif /* AQ_HW_H */ 385