1 /* Applied Micro X-Gene SoC Ethernet Driver 2 * 3 * Copyright (c) 2014, Applied Micro Circuits Corporation 4 * Authors: Iyappan Subramanian <isubramanian@apm.com> 5 * Keyur Chudgar <kchudgar@apm.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include <linux/of_gpio.h> 22 #include <linux/gpio.h> 23 #include "xgene_enet_main.h" 24 #include "xgene_enet_hw.h" 25 #include "xgene_enet_xgmac.h" 26 27 static void xgene_enet_wr_csr(struct xgene_enet_pdata *pdata, 28 u32 offset, u32 val) 29 { 30 void __iomem *addr = pdata->eth_csr_addr + offset; 31 32 iowrite32(val, addr); 33 } 34 35 static void xgene_enet_wr_ring_if(struct xgene_enet_pdata *pdata, 36 u32 offset, u32 val) 37 { 38 void __iomem *addr = pdata->eth_ring_if_addr + offset; 39 40 iowrite32(val, addr); 41 } 42 43 static void xgene_enet_wr_diag_csr(struct xgene_enet_pdata *pdata, 44 u32 offset, u32 val) 45 { 46 void __iomem *addr = pdata->eth_diag_csr_addr + offset; 47 48 iowrite32(val, addr); 49 } 50 51 static bool xgene_enet_wr_indirect(void __iomem *addr, void __iomem *wr, 52 void __iomem *cmd, void __iomem *cmd_done, 53 u32 wr_addr, u32 wr_data) 54 { 55 u32 done; 56 u8 wait = 10; 57 58 iowrite32(wr_addr, addr); 59 iowrite32(wr_data, wr); 60 iowrite32(XGENE_ENET_WR_CMD, cmd); 61 62 /* wait for write command to complete */ 63 while (!(done = ioread32(cmd_done)) && wait--) 64 udelay(1); 65 66 if (!done) 67 return false; 68 69 iowrite32(0, cmd); 70 71 return true; 72 } 73 74 static void xgene_enet_wr_mac(struct xgene_enet_pdata *pdata, 75 u32 wr_addr, u32 wr_data) 76 { 77 void __iomem *addr, *wr, *cmd, *cmd_done; 78 79 addr = pdata->mcx_mac_addr + MAC_ADDR_REG_OFFSET; 80 wr = pdata->mcx_mac_addr + MAC_WRITE_REG_OFFSET; 81 cmd = pdata->mcx_mac_addr + MAC_COMMAND_REG_OFFSET; 82 cmd_done = pdata->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET; 83 84 if (!xgene_enet_wr_indirect(addr, wr, cmd, cmd_done, wr_addr, wr_data)) 85 netdev_err(pdata->ndev, "MCX mac write failed, addr: %04x\n", 86 wr_addr); 87 } 88 89 static void xgene_enet_wr_pcs(struct xgene_enet_pdata *pdata, 90 u32 wr_addr, u32 wr_data) 91 { 92 void __iomem *addr, *wr, *cmd, *cmd_done; 93 94 addr = pdata->pcs_addr + PCS_ADDR_REG_OFFSET; 95 wr = pdata->pcs_addr + PCS_WRITE_REG_OFFSET; 96 cmd = pdata->pcs_addr + PCS_COMMAND_REG_OFFSET; 97 cmd_done = pdata->pcs_addr + PCS_COMMAND_DONE_REG_OFFSET; 98 99 if (!xgene_enet_wr_indirect(addr, wr, cmd, cmd_done, wr_addr, wr_data)) 100 netdev_err(pdata->ndev, "PCS write failed, addr: %04x\n", 101 wr_addr); 102 } 103 104 static void xgene_enet_wr_axg_csr(struct xgene_enet_pdata *pdata, 105 u32 offset, u32 val) 106 { 107 void __iomem *addr = pdata->mcx_mac_csr_addr + offset; 108 109 iowrite32(val, addr); 110 } 111 112 static void xgene_enet_rd_csr(struct xgene_enet_pdata *pdata, 113 u32 offset, u32 *val) 114 { 115 void __iomem *addr = pdata->eth_csr_addr + offset; 116 117 *val = ioread32(addr); 118 } 119 120 static void xgene_enet_rd_diag_csr(struct xgene_enet_pdata *pdata, 121 u32 offset, u32 *val) 122 { 123 void __iomem *addr = pdata->eth_diag_csr_addr + offset; 124 125 *val = ioread32(addr); 126 } 127 128 static bool xgene_enet_rd_indirect(void __iomem *addr, void __iomem *rd, 129 void __iomem *cmd, void __iomem *cmd_done, 130 u32 rd_addr, u32 *rd_data) 131 { 132 u32 done; 133 u8 wait = 10; 134 135 iowrite32(rd_addr, addr); 136 iowrite32(XGENE_ENET_RD_CMD, cmd); 137 138 /* wait for read command to complete */ 139 while (!(done = ioread32(cmd_done)) && wait--) 140 udelay(1); 141 142 if (!done) 143 return false; 144 145 *rd_data = ioread32(rd); 146 iowrite32(0, cmd); 147 148 return true; 149 } 150 151 static void xgene_enet_rd_mac(struct xgene_enet_pdata *pdata, 152 u32 rd_addr, u32 *rd_data) 153 { 154 void __iomem *addr, *rd, *cmd, *cmd_done; 155 156 addr = pdata->mcx_mac_addr + MAC_ADDR_REG_OFFSET; 157 rd = pdata->mcx_mac_addr + MAC_READ_REG_OFFSET; 158 cmd = pdata->mcx_mac_addr + MAC_COMMAND_REG_OFFSET; 159 cmd_done = pdata->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET; 160 161 if (!xgene_enet_rd_indirect(addr, rd, cmd, cmd_done, rd_addr, rd_data)) 162 netdev_err(pdata->ndev, "MCX mac read failed, addr: %04x\n", 163 rd_addr); 164 } 165 166 static bool xgene_enet_rd_pcs(struct xgene_enet_pdata *pdata, 167 u32 rd_addr, u32 *rd_data) 168 { 169 void __iomem *addr, *rd, *cmd, *cmd_done; 170 bool success; 171 172 addr = pdata->pcs_addr + PCS_ADDR_REG_OFFSET; 173 rd = pdata->pcs_addr + PCS_READ_REG_OFFSET; 174 cmd = pdata->pcs_addr + PCS_COMMAND_REG_OFFSET; 175 cmd_done = pdata->pcs_addr + PCS_COMMAND_DONE_REG_OFFSET; 176 177 success = xgene_enet_rd_indirect(addr, rd, cmd, cmd_done, rd_addr, rd_data); 178 if (!success) 179 netdev_err(pdata->ndev, "PCS read failed, addr: %04x\n", 180 rd_addr); 181 182 return success; 183 } 184 185 static void xgene_enet_rd_axg_csr(struct xgene_enet_pdata *pdata, 186 u32 offset, u32 *val) 187 { 188 void __iomem *addr = pdata->mcx_mac_csr_addr + offset; 189 190 *val = ioread32(addr); 191 } 192 193 static int xgene_enet_ecc_init(struct xgene_enet_pdata *pdata) 194 { 195 struct net_device *ndev = pdata->ndev; 196 u32 data; 197 u8 wait = 10; 198 199 xgene_enet_wr_diag_csr(pdata, ENET_CFG_MEM_RAM_SHUTDOWN_ADDR, 0x0); 200 do { 201 usleep_range(100, 110); 202 xgene_enet_rd_diag_csr(pdata, ENET_BLOCK_MEM_RDY_ADDR, &data); 203 } while ((data != 0xffffffff) && wait--); 204 205 if (data != 0xffffffff) { 206 netdev_err(ndev, "Failed to release memory from shutdown\n"); 207 return -ENODEV; 208 } 209 210 return 0; 211 } 212 213 static void xgene_enet_config_ring_if_assoc(struct xgene_enet_pdata *pdata) 214 { 215 xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIWQASSOC_ADDR, 0); 216 xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIFPQASSOC_ADDR, 0); 217 xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIQMLITEWQASSOC_ADDR, 0); 218 xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIQMLITEFPQASSOC_ADDR, 0); 219 } 220 221 static void xgene_xgmac_reset(struct xgene_enet_pdata *pdata) 222 { 223 xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_0, HSTMACRST); 224 xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_0, 0); 225 } 226 227 static void xgene_pcs_reset(struct xgene_enet_pdata *pdata) 228 { 229 u32 data; 230 231 if (!xgene_enet_rd_pcs(pdata, PCS_CONTROL_1, &data)) 232 return; 233 234 xgene_enet_wr_pcs(pdata, PCS_CONTROL_1, data | PCS_CTRL_PCS_RST); 235 xgene_enet_wr_pcs(pdata, PCS_CONTROL_1, data & ~PCS_CTRL_PCS_RST); 236 } 237 238 static void xgene_xgmac_set_mac_addr(struct xgene_enet_pdata *pdata) 239 { 240 u32 addr0, addr1; 241 u8 *dev_addr = pdata->ndev->dev_addr; 242 243 addr0 = (dev_addr[3] << 24) | (dev_addr[2] << 16) | 244 (dev_addr[1] << 8) | dev_addr[0]; 245 addr1 = (dev_addr[5] << 24) | (dev_addr[4] << 16); 246 247 xgene_enet_wr_mac(pdata, HSTMACADR_LSW_ADDR, addr0); 248 xgene_enet_wr_mac(pdata, HSTMACADR_MSW_ADDR, addr1); 249 } 250 251 static void xgene_xgmac_set_mss(struct xgene_enet_pdata *pdata, 252 u16 mss, u8 index) 253 { 254 u8 offset; 255 u32 data; 256 257 offset = (index < 2) ? 0 : 4; 258 xgene_enet_rd_csr(pdata, XG_TSIF_MSS_REG0_ADDR + offset, &data); 259 260 if (!(index & 0x1)) 261 data = SET_VAL(TSO_MSS1, data >> TSO_MSS1_POS) | 262 SET_VAL(TSO_MSS0, mss); 263 else 264 data = SET_VAL(TSO_MSS1, mss) | SET_VAL(TSO_MSS0, data); 265 266 xgene_enet_wr_csr(pdata, XG_TSIF_MSS_REG0_ADDR + offset, data); 267 } 268 269 static void xgene_xgmac_set_frame_size(struct xgene_enet_pdata *pdata, int size) 270 { 271 xgene_enet_wr_mac(pdata, HSTMAXFRAME_LENGTH_ADDR, 272 ((((size + 2) >> 2) << 16) | size)); 273 } 274 275 static u32 xgene_enet_link_status(struct xgene_enet_pdata *pdata) 276 { 277 u32 data; 278 279 xgene_enet_rd_csr(pdata, XG_LINK_STATUS_ADDR, &data); 280 281 return data; 282 } 283 284 static void xgene_xgmac_enable_tx_pause(struct xgene_enet_pdata *pdata, 285 bool enable) 286 { 287 u32 data; 288 289 xgene_enet_rd_axg_csr(pdata, XGENET_CSR_ECM_CFG_0_ADDR, &data); 290 291 if (enable) 292 data |= MULTI_DPF_AUTOCTRL | PAUSE_XON_EN; 293 else 294 data &= ~(MULTI_DPF_AUTOCTRL | PAUSE_XON_EN); 295 296 xgene_enet_wr_axg_csr(pdata, XGENET_CSR_ECM_CFG_0_ADDR, data); 297 } 298 299 static void xgene_xgmac_flowctl_tx(struct xgene_enet_pdata *pdata, bool enable) 300 { 301 u32 data; 302 303 xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1, &data); 304 305 if (enable) 306 data |= HSTTCTLEN; 307 else 308 data &= ~HSTTCTLEN; 309 310 xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data); 311 312 pdata->mac_ops->enable_tx_pause(pdata, enable); 313 } 314 315 static void xgene_xgmac_flowctl_rx(struct xgene_enet_pdata *pdata, bool enable) 316 { 317 u32 data; 318 319 xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1, &data); 320 321 if (enable) 322 data |= HSTRCTLEN; 323 else 324 data &= ~HSTRCTLEN; 325 326 xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data); 327 } 328 329 static void xgene_xgmac_init(struct xgene_enet_pdata *pdata) 330 { 331 u32 data; 332 333 xgene_xgmac_reset(pdata); 334 335 xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1, &data); 336 data |= HSTPPEN; 337 data &= ~HSTLENCHK; 338 xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data); 339 340 xgene_xgmac_set_mac_addr(pdata); 341 342 xgene_enet_rd_csr(pdata, XG_RSIF_CONFIG_REG_ADDR, &data); 343 data |= CFG_RSIF_FPBUFF_TIMEOUT_EN; 344 /* Errata 10GE_1 - FIFO threshold default value incorrect */ 345 RSIF_CLE_BUFF_THRESH_SET(&data, XG_RSIF_CLE_BUFF_THRESH); 346 xgene_enet_wr_csr(pdata, XG_RSIF_CONFIG_REG_ADDR, data); 347 348 /* Errata 10GE_1 - FIFO threshold default value incorrect */ 349 xgene_enet_rd_csr(pdata, XG_RSIF_CONFIG1_REG_ADDR, &data); 350 RSIF_PLC_CLE_BUFF_THRESH_SET(&data, XG_RSIF_PLC_CLE_BUFF_THRESH); 351 xgene_enet_wr_csr(pdata, XG_RSIF_CONFIG1_REG_ADDR, data); 352 353 xgene_enet_rd_csr(pdata, XG_ENET_SPARE_CFG_REG_ADDR, &data); 354 data |= BIT(12); 355 xgene_enet_wr_csr(pdata, XG_ENET_SPARE_CFG_REG_ADDR, data); 356 xgene_enet_wr_csr(pdata, XG_ENET_SPARE_CFG_REG_1_ADDR, 0x82); 357 xgene_enet_wr_csr(pdata, XGENET_RX_DV_GATE_REG_0_ADDR, 0); 358 xgene_enet_wr_csr(pdata, XG_CFG_BYPASS_ADDR, RESUME_TX); 359 360 /* Configure HW pause frame generation */ 361 xgene_enet_rd_axg_csr(pdata, XGENET_CSR_MULTI_DPF0_ADDR, &data); 362 data = (DEF_QUANTA << 16) | (data & 0xFFFF); 363 xgene_enet_wr_axg_csr(pdata, XGENET_CSR_MULTI_DPF0_ADDR, data); 364 365 if (pdata->enet_id != XGENE_ENET1) { 366 xgene_enet_rd_axg_csr(pdata, XGENET_CSR_MULTI_DPF1_ADDR, &data); 367 data = (NORM_PAUSE_OPCODE << 16) | (data & 0xFFFF); 368 xgene_enet_wr_axg_csr(pdata, XGENET_CSR_MULTI_DPF1_ADDR, data); 369 } 370 371 data = (XG_DEF_PAUSE_OFF_THRES << 16) | XG_DEF_PAUSE_THRES; 372 xgene_enet_wr_csr(pdata, XG_RXBUF_PAUSE_THRESH, data); 373 374 xgene_xgmac_flowctl_tx(pdata, pdata->tx_pause); 375 xgene_xgmac_flowctl_rx(pdata, pdata->rx_pause); 376 } 377 378 static void xgene_xgmac_rx_enable(struct xgene_enet_pdata *pdata) 379 { 380 u32 data; 381 382 xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1, &data); 383 xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data | HSTRFEN); 384 } 385 386 static void xgene_xgmac_tx_enable(struct xgene_enet_pdata *pdata) 387 { 388 u32 data; 389 390 xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1, &data); 391 xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data | HSTTFEN); 392 } 393 394 static void xgene_xgmac_rx_disable(struct xgene_enet_pdata *pdata) 395 { 396 u32 data; 397 398 xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1, &data); 399 xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data & ~HSTRFEN); 400 } 401 402 static void xgene_xgmac_tx_disable(struct xgene_enet_pdata *pdata) 403 { 404 u32 data; 405 406 xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1, &data); 407 xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data & ~HSTTFEN); 408 } 409 410 static int xgene_enet_reset(struct xgene_enet_pdata *pdata) 411 { 412 struct device *dev = &pdata->pdev->dev; 413 414 if (!xgene_ring_mgr_init(pdata)) 415 return -ENODEV; 416 417 if (dev->of_node) { 418 clk_prepare_enable(pdata->clk); 419 udelay(5); 420 clk_disable_unprepare(pdata->clk); 421 udelay(5); 422 clk_prepare_enable(pdata->clk); 423 udelay(5); 424 } else { 425 #ifdef CONFIG_ACPI 426 if (acpi_has_method(ACPI_HANDLE(&pdata->pdev->dev), "_RST")) { 427 acpi_evaluate_object(ACPI_HANDLE(&pdata->pdev->dev), 428 "_RST", NULL, NULL); 429 } else if (acpi_has_method(ACPI_HANDLE(&pdata->pdev->dev), 430 "_INI")) { 431 acpi_evaluate_object(ACPI_HANDLE(&pdata->pdev->dev), 432 "_INI", NULL, NULL); 433 } 434 #endif 435 } 436 437 xgene_enet_ecc_init(pdata); 438 xgene_enet_config_ring_if_assoc(pdata); 439 440 return 0; 441 } 442 443 static void xgene_enet_xgcle_bypass(struct xgene_enet_pdata *pdata, 444 u32 dst_ring_num, u16 bufpool_id, 445 u16 nxtbufpool_id) 446 { 447 u32 cb, fpsel, nxtfpsel; 448 449 xgene_enet_rd_csr(pdata, XCLE_BYPASS_REG0_ADDR, &cb); 450 cb |= CFG_CLE_BYPASS_EN0; 451 CFG_CLE_IP_PROTOCOL0_SET(&cb, 3); 452 xgene_enet_wr_csr(pdata, XCLE_BYPASS_REG0_ADDR, cb); 453 454 fpsel = xgene_enet_get_fpsel(bufpool_id); 455 nxtfpsel = xgene_enet_get_fpsel(nxtbufpool_id); 456 xgene_enet_rd_csr(pdata, XCLE_BYPASS_REG1_ADDR, &cb); 457 CFG_CLE_DSTQID0_SET(&cb, dst_ring_num); 458 CFG_CLE_FPSEL0_SET(&cb, fpsel); 459 CFG_CLE_NXTFPSEL0_SET(&cb, nxtfpsel); 460 xgene_enet_wr_csr(pdata, XCLE_BYPASS_REG1_ADDR, cb); 461 pr_info("+ cle_bypass: fpsel: %d nxtfpsel: %d\n", fpsel, nxtfpsel); 462 } 463 464 static void xgene_enet_shutdown(struct xgene_enet_pdata *pdata) 465 { 466 struct device *dev = &pdata->pdev->dev; 467 struct xgene_enet_desc_ring *ring; 468 u32 pb; 469 int i; 470 471 pb = 0; 472 for (i = 0; i < pdata->rxq_cnt; i++) { 473 ring = pdata->rx_ring[i]->buf_pool; 474 pb |= BIT(xgene_enet_get_fpsel(ring->id)); 475 ring = pdata->rx_ring[i]->page_pool; 476 if (ring) 477 pb |= BIT(xgene_enet_get_fpsel(ring->id)); 478 } 479 xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIFPRESET_ADDR, pb); 480 481 pb = 0; 482 for (i = 0; i < pdata->txq_cnt; i++) { 483 ring = pdata->tx_ring[i]; 484 pb |= BIT(xgene_enet_ring_bufnum(ring->id)); 485 } 486 xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIWQRESET_ADDR, pb); 487 488 if (dev->of_node) { 489 if (!IS_ERR(pdata->clk)) 490 clk_disable_unprepare(pdata->clk); 491 } 492 } 493 494 static void xgene_enet_clear(struct xgene_enet_pdata *pdata, 495 struct xgene_enet_desc_ring *ring) 496 { 497 u32 addr, data; 498 499 if (xgene_enet_is_bufpool(ring->id)) { 500 addr = ENET_CFGSSQMIFPRESET_ADDR; 501 data = BIT(xgene_enet_get_fpsel(ring->id)); 502 } else { 503 addr = ENET_CFGSSQMIWQRESET_ADDR; 504 data = BIT(xgene_enet_ring_bufnum(ring->id)); 505 } 506 507 xgene_enet_wr_ring_if(pdata, addr, data); 508 } 509 510 static int xgene_enet_gpio_lookup(struct xgene_enet_pdata *pdata) 511 { 512 struct device *dev = &pdata->pdev->dev; 513 514 pdata->sfp_rdy = gpiod_get(dev, "rxlos", GPIOD_IN); 515 if (IS_ERR(pdata->sfp_rdy)) 516 pdata->sfp_rdy = gpiod_get(dev, "sfp", GPIOD_IN); 517 518 if (IS_ERR(pdata->sfp_rdy)) 519 return -ENODEV; 520 521 return 0; 522 } 523 524 static void xgene_enet_link_state(struct work_struct *work) 525 { 526 struct xgene_enet_pdata *pdata = container_of(to_delayed_work(work), 527 struct xgene_enet_pdata, link_work); 528 struct net_device *ndev = pdata->ndev; 529 u32 link_status, poll_interval; 530 531 link_status = xgene_enet_link_status(pdata); 532 if (pdata->sfp_gpio_en && link_status && 533 (!IS_ERR(pdata->sfp_rdy) || !xgene_enet_gpio_lookup(pdata)) && 534 !gpiod_get_value(pdata->sfp_rdy)) 535 link_status = 0; 536 537 if (link_status) { 538 if (!netif_carrier_ok(ndev)) { 539 netif_carrier_on(ndev); 540 xgene_xgmac_rx_enable(pdata); 541 xgene_xgmac_tx_enable(pdata); 542 netdev_info(ndev, "Link is Up - 10Gbps\n"); 543 } 544 poll_interval = PHY_POLL_LINK_ON; 545 } else { 546 if (netif_carrier_ok(ndev)) { 547 xgene_xgmac_rx_disable(pdata); 548 xgene_xgmac_tx_disable(pdata); 549 netif_carrier_off(ndev); 550 netdev_info(ndev, "Link is Down\n"); 551 } 552 poll_interval = PHY_POLL_LINK_OFF; 553 554 xgene_pcs_reset(pdata); 555 } 556 557 schedule_delayed_work(&pdata->link_work, poll_interval); 558 } 559 560 const struct xgene_mac_ops xgene_xgmac_ops = { 561 .init = xgene_xgmac_init, 562 .reset = xgene_xgmac_reset, 563 .rx_enable = xgene_xgmac_rx_enable, 564 .tx_enable = xgene_xgmac_tx_enable, 565 .rx_disable = xgene_xgmac_rx_disable, 566 .tx_disable = xgene_xgmac_tx_disable, 567 .set_mac_addr = xgene_xgmac_set_mac_addr, 568 .set_framesize = xgene_xgmac_set_frame_size, 569 .set_mss = xgene_xgmac_set_mss, 570 .link_state = xgene_enet_link_state, 571 .enable_tx_pause = xgene_xgmac_enable_tx_pause, 572 .flowctl_rx = xgene_xgmac_flowctl_rx, 573 .flowctl_tx = xgene_xgmac_flowctl_tx 574 }; 575 576 const struct xgene_port_ops xgene_xgport_ops = { 577 .reset = xgene_enet_reset, 578 .clear = xgene_enet_clear, 579 .cle_bypass = xgene_enet_xgcle_bypass, 580 .shutdown = xgene_enet_shutdown, 581 }; 582