1 /* Applied Micro X-Gene SoC Ethernet Driver
2  *
3  * Copyright (c) 2014, Applied Micro Circuits Corporation
4  * Authors: Iyappan Subramanian <isubramanian@apm.com>
5  *	    Keyur Chudgar <kchudgar@apm.com>
6  *
7  * This program is free software; you can redistribute  it and/or modify it
8  * under  the terms of  the GNU General  Public License as published by the
9  * Free Software Foundation;  either version 2 of the  License, or (at your
10  * option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
19  */
20 
21 #include "xgene_enet_main.h"
22 #include "xgene_enet_hw.h"
23 #include "xgene_enet_sgmac.h"
24 
25 static void xgene_enet_wr_csr(struct xgene_enet_pdata *p, u32 offset, u32 val)
26 {
27 	iowrite32(val, p->eth_csr_addr + offset);
28 }
29 
30 static void xgene_enet_wr_ring_if(struct xgene_enet_pdata *p,
31 				  u32 offset, u32 val)
32 {
33 	iowrite32(val, p->eth_ring_if_addr + offset);
34 }
35 
36 static void xgene_enet_wr_diag_csr(struct xgene_enet_pdata *p,
37 				   u32 offset, u32 val)
38 {
39 	iowrite32(val, p->eth_diag_csr_addr + offset);
40 }
41 
42 static bool xgene_enet_wr_indirect(struct xgene_indirect_ctl *ctl,
43 				   u32 wr_addr, u32 wr_data)
44 {
45 	int i;
46 
47 	iowrite32(wr_addr, ctl->addr);
48 	iowrite32(wr_data, ctl->ctl);
49 	iowrite32(XGENE_ENET_WR_CMD, ctl->cmd);
50 
51 	/* wait for write command to complete */
52 	for (i = 0; i < 10; i++) {
53 		if (ioread32(ctl->cmd_done)) {
54 			iowrite32(0, ctl->cmd);
55 			return true;
56 		}
57 		udelay(1);
58 	}
59 
60 	return false;
61 }
62 
63 static void xgene_enet_wr_mac(struct xgene_enet_pdata *p,
64 			      u32 wr_addr, u32 wr_data)
65 {
66 	struct xgene_indirect_ctl ctl = {
67 		.addr = p->mcx_mac_addr + MAC_ADDR_REG_OFFSET,
68 		.ctl = p->mcx_mac_addr + MAC_WRITE_REG_OFFSET,
69 		.cmd = p->mcx_mac_addr + MAC_COMMAND_REG_OFFSET,
70 		.cmd_done = p->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET
71 	};
72 
73 	if (!xgene_enet_wr_indirect(&ctl, wr_addr, wr_data))
74 		netdev_err(p->ndev, "mac write failed, addr: %04x\n", wr_addr);
75 }
76 
77 static u32 xgene_enet_rd_csr(struct xgene_enet_pdata *p, u32 offset)
78 {
79 	return ioread32(p->eth_csr_addr + offset);
80 }
81 
82 static u32 xgene_enet_rd_diag_csr(struct xgene_enet_pdata *p, u32 offset)
83 {
84 	return ioread32(p->eth_diag_csr_addr + offset);
85 }
86 
87 static u32 xgene_enet_rd_indirect(struct xgene_indirect_ctl *ctl, u32 rd_addr)
88 {
89 	u32 rd_data;
90 	int i;
91 
92 	iowrite32(rd_addr, ctl->addr);
93 	iowrite32(XGENE_ENET_RD_CMD, ctl->cmd);
94 
95 	/* wait for read command to complete */
96 	for (i = 0; i < 10; i++) {
97 		if (ioread32(ctl->cmd_done)) {
98 			rd_data = ioread32(ctl->ctl);
99 			iowrite32(0, ctl->cmd);
100 
101 			return rd_data;
102 		}
103 		udelay(1);
104 	}
105 
106 	pr_err("%s: mac read failed, addr: %04x\n", __func__, rd_addr);
107 
108 	return 0;
109 }
110 
111 static u32 xgene_enet_rd_mac(struct xgene_enet_pdata *p, u32 rd_addr)
112 {
113 	struct xgene_indirect_ctl ctl = {
114 		.addr = p->mcx_mac_addr + MAC_ADDR_REG_OFFSET,
115 		.ctl = p->mcx_mac_addr + MAC_READ_REG_OFFSET,
116 		.cmd = p->mcx_mac_addr + MAC_COMMAND_REG_OFFSET,
117 		.cmd_done = p->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET
118 	};
119 
120 	return xgene_enet_rd_indirect(&ctl, rd_addr);
121 }
122 
123 static int xgene_enet_ecc_init(struct xgene_enet_pdata *p)
124 {
125 	struct net_device *ndev = p->ndev;
126 	u32 data;
127 	int i;
128 
129 	xgene_enet_wr_diag_csr(p, ENET_CFG_MEM_RAM_SHUTDOWN_ADDR, 0);
130 	for (i = 0; i < 10 && data != ~0U ; i++) {
131 		usleep_range(100, 110);
132 		data = xgene_enet_rd_diag_csr(p, ENET_BLOCK_MEM_RDY_ADDR);
133 	}
134 
135 	if (data != ~0U) {
136 		netdev_err(ndev, "Failed to release memory from shutdown\n");
137 		return -ENODEV;
138 	}
139 
140 	return 0;
141 }
142 
143 static void xgene_enet_config_ring_if_assoc(struct xgene_enet_pdata *p)
144 {
145 	u32 val = 0xffffffff;
146 
147 	xgene_enet_wr_ring_if(p, ENET_CFGSSQMIWQASSOC_ADDR, val);
148 	xgene_enet_wr_ring_if(p, ENET_CFGSSQMIFPQASSOC_ADDR, val);
149 }
150 
151 static void xgene_mii_phy_write(struct xgene_enet_pdata *p, u8 phy_id,
152 				u32 reg, u16 data)
153 {
154 	u32 addr, wr_data, done;
155 	int i;
156 
157 	addr = PHY_ADDR(phy_id) | REG_ADDR(reg);
158 	xgene_enet_wr_mac(p, MII_MGMT_ADDRESS_ADDR, addr);
159 
160 	wr_data = PHY_CONTROL(data);
161 	xgene_enet_wr_mac(p, MII_MGMT_CONTROL_ADDR, wr_data);
162 
163 	for (i = 0; i < 10; i++) {
164 		done = xgene_enet_rd_mac(p, MII_MGMT_INDICATORS_ADDR);
165 		if (!(done & BUSY_MASK))
166 			return;
167 		usleep_range(10, 20);
168 	}
169 
170 	netdev_err(p->ndev, "MII_MGMT write failed\n");
171 }
172 
173 static u32 xgene_mii_phy_read(struct xgene_enet_pdata *p, u8 phy_id, u32 reg)
174 {
175 	u32 addr, data, done;
176 	int i;
177 
178 	addr = PHY_ADDR(phy_id) | REG_ADDR(reg);
179 	xgene_enet_wr_mac(p, MII_MGMT_ADDRESS_ADDR, addr);
180 	xgene_enet_wr_mac(p, MII_MGMT_COMMAND_ADDR, READ_CYCLE_MASK);
181 
182 	for (i = 0; i < 10; i++) {
183 		done = xgene_enet_rd_mac(p, MII_MGMT_INDICATORS_ADDR);
184 		if (!(done & BUSY_MASK)) {
185 			data = xgene_enet_rd_mac(p, MII_MGMT_STATUS_ADDR);
186 			xgene_enet_wr_mac(p, MII_MGMT_COMMAND_ADDR, 0);
187 
188 			return data;
189 		}
190 		usleep_range(10, 20);
191 	}
192 
193 	netdev_err(p->ndev, "MII_MGMT read failed\n");
194 
195 	return 0;
196 }
197 
198 static void xgene_sgmac_reset(struct xgene_enet_pdata *p)
199 {
200 	xgene_enet_wr_mac(p, MAC_CONFIG_1_ADDR, SOFT_RESET1);
201 	xgene_enet_wr_mac(p, MAC_CONFIG_1_ADDR, 0);
202 }
203 
204 static void xgene_sgmac_set_mac_addr(struct xgene_enet_pdata *p)
205 {
206 	u32 addr0, addr1;
207 	u8 *dev_addr = p->ndev->dev_addr;
208 
209 	addr0 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
210 		(dev_addr[1] << 8) | dev_addr[0];
211 	xgene_enet_wr_mac(p, STATION_ADDR0_ADDR, addr0);
212 
213 	addr1 = xgene_enet_rd_mac(p, STATION_ADDR1_ADDR);
214 	addr1 |= (dev_addr[5] << 24) | (dev_addr[4] << 16);
215 	xgene_enet_wr_mac(p, STATION_ADDR1_ADDR, addr1);
216 }
217 
218 static u32 xgene_enet_link_status(struct xgene_enet_pdata *p)
219 {
220 	u32 data;
221 
222 	data = xgene_mii_phy_read(p, INT_PHY_ADDR,
223 				  SGMII_BASE_PAGE_ABILITY_ADDR >> 2);
224 
225 	return data & LINK_UP;
226 }
227 
228 static void xgene_sgmac_init(struct xgene_enet_pdata *p)
229 {
230 	u32 data, loop = 10;
231 
232 	xgene_sgmac_reset(p);
233 
234 	/* Enable auto-negotiation */
235 	xgene_mii_phy_write(p, INT_PHY_ADDR, SGMII_CONTROL_ADDR >> 2, 0x1000);
236 	xgene_mii_phy_write(p, INT_PHY_ADDR, SGMII_TBI_CONTROL_ADDR >> 2, 0);
237 
238 	while (loop--) {
239 		data = xgene_mii_phy_read(p, INT_PHY_ADDR,
240 					  SGMII_STATUS_ADDR >> 2);
241 		if ((data & AUTO_NEG_COMPLETE) && (data & LINK_STATUS))
242 			break;
243 		usleep_range(10, 20);
244 	}
245 	if (!(data & AUTO_NEG_COMPLETE) || !(data & LINK_STATUS))
246 		netdev_err(p->ndev, "Auto-negotiation failed\n");
247 
248 	data = xgene_enet_rd_mac(p, MAC_CONFIG_2_ADDR);
249 	ENET_INTERFACE_MODE2_SET(&data, 2);
250 	xgene_enet_wr_mac(p, MAC_CONFIG_2_ADDR, data | FULL_DUPLEX2);
251 	xgene_enet_wr_mac(p, INTERFACE_CONTROL_ADDR, ENET_GHD_MODE);
252 
253 	data = xgene_enet_rd_csr(p, ENET_SPARE_CFG_REG_ADDR);
254 	data |= MPA_IDLE_WITH_QMI_EMPTY;
255 	xgene_enet_wr_csr(p, ENET_SPARE_CFG_REG_ADDR, data);
256 
257 	xgene_sgmac_set_mac_addr(p);
258 
259 	data = xgene_enet_rd_csr(p, DEBUG_REG_ADDR);
260 	data |= CFG_BYPASS_UNISEC_TX | CFG_BYPASS_UNISEC_RX;
261 	xgene_enet_wr_csr(p, DEBUG_REG_ADDR, data);
262 
263 	/* Adjust MDC clock frequency */
264 	data = xgene_enet_rd_mac(p, MII_MGMT_CONFIG_ADDR);
265 	MGMT_CLOCK_SEL_SET(&data, 7);
266 	xgene_enet_wr_mac(p, MII_MGMT_CONFIG_ADDR, data);
267 
268 	/* Enable drop if bufpool not available */
269 	data = xgene_enet_rd_csr(p, RSIF_CONFIG_REG_ADDR);
270 	data |= CFG_RSIF_FPBUFF_TIMEOUT_EN;
271 	xgene_enet_wr_csr(p, RSIF_CONFIG_REG_ADDR, data);
272 
273 	/* Rtype should be copied from FP */
274 	xgene_enet_wr_csr(p, RSIF_RAM_DBG_REG0_ADDR, 0);
275 
276 	/* Bypass traffic gating */
277 	xgene_enet_wr_csr(p, CFG_LINK_AGGR_RESUME_0_ADDR, TX_PORT0);
278 	xgene_enet_wr_csr(p, CFG_BYPASS_ADDR, RESUME_TX);
279 	xgene_enet_wr_csr(p, SG_RX_DV_GATE_REG_0_ADDR, RESUME_RX0);
280 }
281 
282 static void xgene_sgmac_rxtx(struct xgene_enet_pdata *p, u32 bits, bool set)
283 {
284 	u32 data;
285 
286 	data = xgene_enet_rd_mac(p, MAC_CONFIG_1_ADDR);
287 
288 	if (set)
289 		data |= bits;
290 	else
291 		data &= ~bits;
292 
293 	xgene_enet_wr_mac(p, MAC_CONFIG_1_ADDR, data);
294 }
295 
296 static void xgene_sgmac_rx_enable(struct xgene_enet_pdata *p)
297 {
298 	xgene_sgmac_rxtx(p, RX_EN, true);
299 }
300 
301 static void xgene_sgmac_tx_enable(struct xgene_enet_pdata *p)
302 {
303 	xgene_sgmac_rxtx(p, TX_EN, true);
304 }
305 
306 static void xgene_sgmac_rx_disable(struct xgene_enet_pdata *p)
307 {
308 	xgene_sgmac_rxtx(p, RX_EN, false);
309 }
310 
311 static void xgene_sgmac_tx_disable(struct xgene_enet_pdata *p)
312 {
313 	xgene_sgmac_rxtx(p, TX_EN, false);
314 }
315 
316 static void xgene_enet_reset(struct xgene_enet_pdata *p)
317 {
318 	clk_prepare_enable(p->clk);
319 	clk_disable_unprepare(p->clk);
320 	clk_prepare_enable(p->clk);
321 
322 	xgene_enet_ecc_init(p);
323 	xgene_enet_config_ring_if_assoc(p);
324 }
325 
326 static void xgene_enet_cle_bypass(struct xgene_enet_pdata *p,
327 				  u32 dst_ring_num, u16 bufpool_id)
328 {
329 	u32 data, fpsel;
330 
331 	data = CFG_CLE_BYPASS_EN0;
332 	xgene_enet_wr_csr(p, CLE_BYPASS_REG0_0_ADDR, data);
333 
334 	fpsel = xgene_enet_ring_bufnum(bufpool_id) - 0x20;
335 	data = CFG_CLE_DSTQID0(dst_ring_num) | CFG_CLE_FPSEL0(fpsel);
336 	xgene_enet_wr_csr(p, CLE_BYPASS_REG1_0_ADDR, data);
337 }
338 
339 static void xgene_enet_shutdown(struct xgene_enet_pdata *p)
340 {
341 	clk_disable_unprepare(p->clk);
342 }
343 
344 static void xgene_enet_link_state(struct work_struct *work)
345 {
346 	struct xgene_enet_pdata *p = container_of(to_delayed_work(work),
347 				     struct xgene_enet_pdata, link_work);
348 	struct net_device *ndev = p->ndev;
349 	u32 link, poll_interval;
350 
351 	link = xgene_enet_link_status(p);
352 	if (link) {
353 		if (!netif_carrier_ok(ndev)) {
354 			netif_carrier_on(ndev);
355 			xgene_sgmac_init(p);
356 			xgene_sgmac_rx_enable(p);
357 			xgene_sgmac_tx_enable(p);
358 			netdev_info(ndev, "Link is Up - 1Gbps\n");
359 		}
360 		poll_interval = PHY_POLL_LINK_ON;
361 	} else {
362 		if (netif_carrier_ok(ndev)) {
363 			xgene_sgmac_rx_disable(p);
364 			xgene_sgmac_tx_disable(p);
365 			netif_carrier_off(ndev);
366 			netdev_info(ndev, "Link is Down\n");
367 		}
368 		poll_interval = PHY_POLL_LINK_OFF;
369 	}
370 
371 	schedule_delayed_work(&p->link_work, poll_interval);
372 }
373 
374 struct xgene_mac_ops xgene_sgmac_ops = {
375 	.init		= xgene_sgmac_init,
376 	.reset		= xgene_sgmac_reset,
377 	.rx_enable	= xgene_sgmac_rx_enable,
378 	.tx_enable	= xgene_sgmac_tx_enable,
379 	.rx_disable	= xgene_sgmac_rx_disable,
380 	.tx_disable	= xgene_sgmac_tx_disable,
381 	.set_mac_addr	= xgene_sgmac_set_mac_addr,
382 	.link_state	= xgene_enet_link_state
383 };
384 
385 struct xgene_port_ops xgene_sgport_ops = {
386 	.reset		= xgene_enet_reset,
387 	.cle_bypass	= xgene_enet_cle_bypass,
388 	.shutdown	= xgene_enet_shutdown
389 };
390