1 /* Applied Micro X-Gene SoC Ethernet Driver 2 * 3 * Copyright (c) 2014, Applied Micro Circuits Corporation 4 * Authors: Iyappan Subramanian <isubramanian@apm.com> 5 * Ravi Patel <rapatel@apm.com> 6 * Keyur Chudgar <kchudgar@apm.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program. If not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include <linux/gpio.h> 23 #include "xgene_enet_main.h" 24 #include "xgene_enet_hw.h" 25 #include "xgene_enet_sgmac.h" 26 #include "xgene_enet_xgmac.h" 27 28 #define RES_ENET_CSR 0 29 #define RES_RING_CSR 1 30 #define RES_RING_CMD 2 31 32 static const struct of_device_id xgene_enet_of_match[]; 33 static const struct acpi_device_id xgene_enet_acpi_match[]; 34 35 static void xgene_enet_init_bufpool(struct xgene_enet_desc_ring *buf_pool) 36 { 37 struct xgene_enet_raw_desc16 *raw_desc; 38 int i; 39 40 if (!buf_pool) 41 return; 42 43 for (i = 0; i < buf_pool->slots; i++) { 44 raw_desc = &buf_pool->raw_desc16[i]; 45 46 /* Hardware expects descriptor in little endian format */ 47 raw_desc->m0 = cpu_to_le64(i | 48 SET_VAL(FPQNUM, buf_pool->dst_ring_num) | 49 SET_VAL(STASH, 3)); 50 } 51 } 52 53 static u16 xgene_enet_get_data_len(u64 bufdatalen) 54 { 55 u16 hw_len, mask; 56 57 hw_len = GET_VAL(BUFDATALEN, bufdatalen); 58 59 if (unlikely(hw_len == 0x7800)) { 60 return 0; 61 } else if (!(hw_len & BIT(14))) { 62 mask = GENMASK(13, 0); 63 return (hw_len & mask) ? (hw_len & mask) : SIZE_16K; 64 } else if (!(hw_len & GENMASK(13, 12))) { 65 mask = GENMASK(11, 0); 66 return (hw_len & mask) ? (hw_len & mask) : SIZE_4K; 67 } else { 68 mask = GENMASK(11, 0); 69 return (hw_len & mask) ? (hw_len & mask) : SIZE_2K; 70 } 71 } 72 73 static u16 xgene_enet_set_data_len(u32 size) 74 { 75 u16 hw_len; 76 77 hw_len = (size == SIZE_4K) ? BIT(14) : 0; 78 79 return hw_len; 80 } 81 82 static int xgene_enet_refill_pagepool(struct xgene_enet_desc_ring *buf_pool, 83 u32 nbuf) 84 { 85 struct xgene_enet_raw_desc16 *raw_desc; 86 struct xgene_enet_pdata *pdata; 87 struct net_device *ndev; 88 dma_addr_t dma_addr; 89 struct device *dev; 90 struct page *page; 91 u32 slots, tail; 92 u16 hw_len; 93 int i; 94 95 if (unlikely(!buf_pool)) 96 return 0; 97 98 ndev = buf_pool->ndev; 99 pdata = netdev_priv(ndev); 100 dev = ndev_to_dev(ndev); 101 slots = buf_pool->slots - 1; 102 tail = buf_pool->tail; 103 104 for (i = 0; i < nbuf; i++) { 105 raw_desc = &buf_pool->raw_desc16[tail]; 106 107 page = dev_alloc_page(); 108 if (unlikely(!page)) 109 return -ENOMEM; 110 111 dma_addr = dma_map_page(dev, page, 0, 112 PAGE_SIZE, DMA_FROM_DEVICE); 113 if (unlikely(dma_mapping_error(dev, dma_addr))) { 114 put_page(page); 115 return -ENOMEM; 116 } 117 118 hw_len = xgene_enet_set_data_len(PAGE_SIZE); 119 raw_desc->m1 = cpu_to_le64(SET_VAL(DATAADDR, dma_addr) | 120 SET_VAL(BUFDATALEN, hw_len) | 121 SET_BIT(COHERENT)); 122 123 buf_pool->frag_page[tail] = page; 124 tail = (tail + 1) & slots; 125 } 126 127 pdata->ring_ops->wr_cmd(buf_pool, nbuf); 128 buf_pool->tail = tail; 129 130 return 0; 131 } 132 133 static int xgene_enet_refill_bufpool(struct xgene_enet_desc_ring *buf_pool, 134 u32 nbuf) 135 { 136 struct sk_buff *skb; 137 struct xgene_enet_raw_desc16 *raw_desc; 138 struct xgene_enet_pdata *pdata; 139 struct net_device *ndev; 140 struct device *dev; 141 dma_addr_t dma_addr; 142 u32 tail = buf_pool->tail; 143 u32 slots = buf_pool->slots - 1; 144 u16 bufdatalen, len; 145 int i; 146 147 ndev = buf_pool->ndev; 148 dev = ndev_to_dev(buf_pool->ndev); 149 pdata = netdev_priv(ndev); 150 151 bufdatalen = BUF_LEN_CODE_2K | (SKB_BUFFER_SIZE & GENMASK(11, 0)); 152 len = XGENE_ENET_STD_MTU; 153 154 for (i = 0; i < nbuf; i++) { 155 raw_desc = &buf_pool->raw_desc16[tail]; 156 157 skb = netdev_alloc_skb_ip_align(ndev, len); 158 if (unlikely(!skb)) 159 return -ENOMEM; 160 161 dma_addr = dma_map_single(dev, skb->data, len, DMA_FROM_DEVICE); 162 if (dma_mapping_error(dev, dma_addr)) { 163 netdev_err(ndev, "DMA mapping error\n"); 164 dev_kfree_skb_any(skb); 165 return -EINVAL; 166 } 167 168 buf_pool->rx_skb[tail] = skb; 169 170 raw_desc->m1 = cpu_to_le64(SET_VAL(DATAADDR, dma_addr) | 171 SET_VAL(BUFDATALEN, bufdatalen) | 172 SET_BIT(COHERENT)); 173 tail = (tail + 1) & slots; 174 } 175 176 pdata->ring_ops->wr_cmd(buf_pool, nbuf); 177 buf_pool->tail = tail; 178 179 return 0; 180 } 181 182 static u8 xgene_enet_hdr_len(const void *data) 183 { 184 const struct ethhdr *eth = data; 185 186 return (eth->h_proto == htons(ETH_P_8021Q)) ? VLAN_ETH_HLEN : ETH_HLEN; 187 } 188 189 static void xgene_enet_delete_bufpool(struct xgene_enet_desc_ring *buf_pool) 190 { 191 struct device *dev = ndev_to_dev(buf_pool->ndev); 192 struct xgene_enet_raw_desc16 *raw_desc; 193 dma_addr_t dma_addr; 194 int i; 195 196 /* Free up the buffers held by hardware */ 197 for (i = 0; i < buf_pool->slots; i++) { 198 if (buf_pool->rx_skb[i]) { 199 dev_kfree_skb_any(buf_pool->rx_skb[i]); 200 201 raw_desc = &buf_pool->raw_desc16[i]; 202 dma_addr = GET_VAL(DATAADDR, le64_to_cpu(raw_desc->m1)); 203 dma_unmap_single(dev, dma_addr, XGENE_ENET_MAX_MTU, 204 DMA_FROM_DEVICE); 205 } 206 } 207 } 208 209 static void xgene_enet_delete_pagepool(struct xgene_enet_desc_ring *buf_pool) 210 { 211 struct device *dev = ndev_to_dev(buf_pool->ndev); 212 dma_addr_t dma_addr; 213 struct page *page; 214 int i; 215 216 /* Free up the buffers held by hardware */ 217 for (i = 0; i < buf_pool->slots; i++) { 218 page = buf_pool->frag_page[i]; 219 if (page) { 220 dma_addr = buf_pool->frag_dma_addr[i]; 221 dma_unmap_page(dev, dma_addr, PAGE_SIZE, 222 DMA_FROM_DEVICE); 223 put_page(page); 224 } 225 } 226 } 227 228 static irqreturn_t xgene_enet_rx_irq(const int irq, void *data) 229 { 230 struct xgene_enet_desc_ring *rx_ring = data; 231 232 if (napi_schedule_prep(&rx_ring->napi)) { 233 disable_irq_nosync(irq); 234 __napi_schedule(&rx_ring->napi); 235 } 236 237 return IRQ_HANDLED; 238 } 239 240 static int xgene_enet_tx_completion(struct xgene_enet_desc_ring *cp_ring, 241 struct xgene_enet_raw_desc *raw_desc) 242 { 243 struct xgene_enet_pdata *pdata = netdev_priv(cp_ring->ndev); 244 struct sk_buff *skb; 245 struct device *dev; 246 skb_frag_t *frag; 247 dma_addr_t *frag_dma_addr; 248 u16 skb_index; 249 u8 status; 250 int i, ret = 0; 251 u8 mss_index; 252 253 skb_index = GET_VAL(USERINFO, le64_to_cpu(raw_desc->m0)); 254 skb = cp_ring->cp_skb[skb_index]; 255 frag_dma_addr = &cp_ring->frag_dma_addr[skb_index * MAX_SKB_FRAGS]; 256 257 dev = ndev_to_dev(cp_ring->ndev); 258 dma_unmap_single(dev, GET_VAL(DATAADDR, le64_to_cpu(raw_desc->m1)), 259 skb_headlen(skb), 260 DMA_TO_DEVICE); 261 262 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 263 frag = &skb_shinfo(skb)->frags[i]; 264 dma_unmap_page(dev, frag_dma_addr[i], skb_frag_size(frag), 265 DMA_TO_DEVICE); 266 } 267 268 if (GET_BIT(ET, le64_to_cpu(raw_desc->m3))) { 269 mss_index = GET_VAL(MSS, le64_to_cpu(raw_desc->m3)); 270 spin_lock(&pdata->mss_lock); 271 pdata->mss_refcnt[mss_index]--; 272 spin_unlock(&pdata->mss_lock); 273 } 274 275 /* Checking for error */ 276 status = GET_VAL(LERR, le64_to_cpu(raw_desc->m0)); 277 if (unlikely(status > 2)) { 278 xgene_enet_parse_error(cp_ring, netdev_priv(cp_ring->ndev), 279 status); 280 ret = -EIO; 281 } 282 283 if (likely(skb)) { 284 dev_kfree_skb_any(skb); 285 } else { 286 netdev_err(cp_ring->ndev, "completion skb is NULL\n"); 287 ret = -EIO; 288 } 289 290 return ret; 291 } 292 293 static int xgene_enet_setup_mss(struct net_device *ndev, u32 mss) 294 { 295 struct xgene_enet_pdata *pdata = netdev_priv(ndev); 296 bool mss_index_found = false; 297 int mss_index; 298 int i; 299 300 spin_lock(&pdata->mss_lock); 301 302 /* Reuse the slot if MSS matches */ 303 for (i = 0; !mss_index_found && i < NUM_MSS_REG; i++) { 304 if (pdata->mss[i] == mss) { 305 pdata->mss_refcnt[i]++; 306 mss_index = i; 307 mss_index_found = true; 308 } 309 } 310 311 /* Overwrite the slot with ref_count = 0 */ 312 for (i = 0; !mss_index_found && i < NUM_MSS_REG; i++) { 313 if (!pdata->mss_refcnt[i]) { 314 pdata->mss_refcnt[i]++; 315 pdata->mac_ops->set_mss(pdata, mss, i); 316 pdata->mss[i] = mss; 317 mss_index = i; 318 mss_index_found = true; 319 } 320 } 321 322 spin_unlock(&pdata->mss_lock); 323 324 /* No slots with ref_count = 0 available, return busy */ 325 if (!mss_index_found) 326 return -EBUSY; 327 328 return mss_index; 329 } 330 331 static int xgene_enet_work_msg(struct sk_buff *skb, u64 *hopinfo) 332 { 333 struct net_device *ndev = skb->dev; 334 struct iphdr *iph; 335 u8 l3hlen = 0, l4hlen = 0; 336 u8 ethhdr, proto = 0, csum_enable = 0; 337 u32 hdr_len, mss = 0; 338 u32 i, len, nr_frags; 339 int mss_index; 340 341 ethhdr = xgene_enet_hdr_len(skb->data); 342 343 if (unlikely(skb->protocol != htons(ETH_P_IP)) && 344 unlikely(skb->protocol != htons(ETH_P_8021Q))) 345 goto out; 346 347 if (unlikely(!(skb->dev->features & NETIF_F_IP_CSUM))) 348 goto out; 349 350 iph = ip_hdr(skb); 351 if (unlikely(ip_is_fragment(iph))) 352 goto out; 353 354 if (likely(iph->protocol == IPPROTO_TCP)) { 355 l4hlen = tcp_hdrlen(skb) >> 2; 356 csum_enable = 1; 357 proto = TSO_IPPROTO_TCP; 358 if (ndev->features & NETIF_F_TSO) { 359 hdr_len = ethhdr + ip_hdrlen(skb) + tcp_hdrlen(skb); 360 mss = skb_shinfo(skb)->gso_size; 361 362 if (skb_is_nonlinear(skb)) { 363 len = skb_headlen(skb); 364 nr_frags = skb_shinfo(skb)->nr_frags; 365 366 for (i = 0; i < 2 && i < nr_frags; i++) 367 len += skb_shinfo(skb)->frags[i].size; 368 369 /* HW requires header must reside in 3 buffer */ 370 if (unlikely(hdr_len > len)) { 371 if (skb_linearize(skb)) 372 return 0; 373 } 374 } 375 376 if (!mss || ((skb->len - hdr_len) <= mss)) 377 goto out; 378 379 mss_index = xgene_enet_setup_mss(ndev, mss); 380 if (unlikely(mss_index < 0)) 381 return -EBUSY; 382 383 *hopinfo |= SET_BIT(ET) | SET_VAL(MSS, mss_index); 384 } 385 } else if (iph->protocol == IPPROTO_UDP) { 386 l4hlen = UDP_HDR_SIZE; 387 csum_enable = 1; 388 } 389 out: 390 l3hlen = ip_hdrlen(skb) >> 2; 391 *hopinfo |= SET_VAL(TCPHDR, l4hlen) | 392 SET_VAL(IPHDR, l3hlen) | 393 SET_VAL(ETHHDR, ethhdr) | 394 SET_VAL(EC, csum_enable) | 395 SET_VAL(IS, proto) | 396 SET_BIT(IC) | 397 SET_BIT(TYPE_ETH_WORK_MESSAGE); 398 399 return 0; 400 } 401 402 static u16 xgene_enet_encode_len(u16 len) 403 { 404 return (len == BUFLEN_16K) ? 0 : len; 405 } 406 407 static void xgene_set_addr_len(__le64 *desc, u32 idx, dma_addr_t addr, u32 len) 408 { 409 desc[idx ^ 1] = cpu_to_le64(SET_VAL(DATAADDR, addr) | 410 SET_VAL(BUFDATALEN, len)); 411 } 412 413 static __le64 *xgene_enet_get_exp_bufs(struct xgene_enet_desc_ring *ring) 414 { 415 __le64 *exp_bufs; 416 417 exp_bufs = &ring->exp_bufs[ring->exp_buf_tail * MAX_EXP_BUFFS]; 418 memset(exp_bufs, 0, sizeof(__le64) * MAX_EXP_BUFFS); 419 ring->exp_buf_tail = (ring->exp_buf_tail + 1) & ((ring->slots / 2) - 1); 420 421 return exp_bufs; 422 } 423 424 static dma_addr_t *xgene_get_frag_dma_array(struct xgene_enet_desc_ring *ring) 425 { 426 return &ring->cp_ring->frag_dma_addr[ring->tail * MAX_SKB_FRAGS]; 427 } 428 429 static int xgene_enet_setup_tx_desc(struct xgene_enet_desc_ring *tx_ring, 430 struct sk_buff *skb) 431 { 432 struct device *dev = ndev_to_dev(tx_ring->ndev); 433 struct xgene_enet_pdata *pdata = netdev_priv(tx_ring->ndev); 434 struct xgene_enet_raw_desc *raw_desc; 435 __le64 *exp_desc = NULL, *exp_bufs = NULL; 436 dma_addr_t dma_addr, pbuf_addr, *frag_dma_addr; 437 skb_frag_t *frag; 438 u16 tail = tx_ring->tail; 439 u64 hopinfo = 0; 440 u32 len, hw_len; 441 u8 ll = 0, nv = 0, idx = 0; 442 bool split = false; 443 u32 size, offset, ell_bytes = 0; 444 u32 i, fidx, nr_frags, count = 1; 445 int ret; 446 447 raw_desc = &tx_ring->raw_desc[tail]; 448 tail = (tail + 1) & (tx_ring->slots - 1); 449 memset(raw_desc, 0, sizeof(struct xgene_enet_raw_desc)); 450 451 ret = xgene_enet_work_msg(skb, &hopinfo); 452 if (ret) 453 return ret; 454 455 raw_desc->m3 = cpu_to_le64(SET_VAL(HENQNUM, tx_ring->dst_ring_num) | 456 hopinfo); 457 458 len = skb_headlen(skb); 459 hw_len = xgene_enet_encode_len(len); 460 461 dma_addr = dma_map_single(dev, skb->data, len, DMA_TO_DEVICE); 462 if (dma_mapping_error(dev, dma_addr)) { 463 netdev_err(tx_ring->ndev, "DMA mapping error\n"); 464 return -EINVAL; 465 } 466 467 /* Hardware expects descriptor in little endian format */ 468 raw_desc->m1 = cpu_to_le64(SET_VAL(DATAADDR, dma_addr) | 469 SET_VAL(BUFDATALEN, hw_len) | 470 SET_BIT(COHERENT)); 471 472 if (!skb_is_nonlinear(skb)) 473 goto out; 474 475 /* scatter gather */ 476 nv = 1; 477 exp_desc = (void *)&tx_ring->raw_desc[tail]; 478 tail = (tail + 1) & (tx_ring->slots - 1); 479 memset(exp_desc, 0, sizeof(struct xgene_enet_raw_desc)); 480 481 nr_frags = skb_shinfo(skb)->nr_frags; 482 for (i = nr_frags; i < 4 ; i++) 483 exp_desc[i ^ 1] = cpu_to_le64(LAST_BUFFER); 484 485 frag_dma_addr = xgene_get_frag_dma_array(tx_ring); 486 487 for (i = 0, fidx = 0; split || (fidx < nr_frags); i++) { 488 if (!split) { 489 frag = &skb_shinfo(skb)->frags[fidx]; 490 size = skb_frag_size(frag); 491 offset = 0; 492 493 pbuf_addr = skb_frag_dma_map(dev, frag, 0, size, 494 DMA_TO_DEVICE); 495 if (dma_mapping_error(dev, pbuf_addr)) 496 return -EINVAL; 497 498 frag_dma_addr[fidx] = pbuf_addr; 499 fidx++; 500 501 if (size > BUFLEN_16K) 502 split = true; 503 } 504 505 if (size > BUFLEN_16K) { 506 len = BUFLEN_16K; 507 size -= BUFLEN_16K; 508 } else { 509 len = size; 510 split = false; 511 } 512 513 dma_addr = pbuf_addr + offset; 514 hw_len = xgene_enet_encode_len(len); 515 516 switch (i) { 517 case 0: 518 case 1: 519 case 2: 520 xgene_set_addr_len(exp_desc, i, dma_addr, hw_len); 521 break; 522 case 3: 523 if (split || (fidx != nr_frags)) { 524 exp_bufs = xgene_enet_get_exp_bufs(tx_ring); 525 xgene_set_addr_len(exp_bufs, idx, dma_addr, 526 hw_len); 527 idx++; 528 ell_bytes += len; 529 } else { 530 xgene_set_addr_len(exp_desc, i, dma_addr, 531 hw_len); 532 } 533 break; 534 default: 535 xgene_set_addr_len(exp_bufs, idx, dma_addr, hw_len); 536 idx++; 537 ell_bytes += len; 538 break; 539 } 540 541 if (split) 542 offset += BUFLEN_16K; 543 } 544 count++; 545 546 if (idx) { 547 ll = 1; 548 dma_addr = dma_map_single(dev, exp_bufs, 549 sizeof(u64) * MAX_EXP_BUFFS, 550 DMA_TO_DEVICE); 551 if (dma_mapping_error(dev, dma_addr)) { 552 dev_kfree_skb_any(skb); 553 return -EINVAL; 554 } 555 i = ell_bytes >> LL_BYTES_LSB_LEN; 556 exp_desc[2] = cpu_to_le64(SET_VAL(DATAADDR, dma_addr) | 557 SET_VAL(LL_BYTES_MSB, i) | 558 SET_VAL(LL_LEN, idx)); 559 raw_desc->m2 = cpu_to_le64(SET_VAL(LL_BYTES_LSB, ell_bytes)); 560 } 561 562 out: 563 raw_desc->m0 = cpu_to_le64(SET_VAL(LL, ll) | SET_VAL(NV, nv) | 564 SET_VAL(USERINFO, tx_ring->tail)); 565 tx_ring->cp_ring->cp_skb[tx_ring->tail] = skb; 566 pdata->tx_level[tx_ring->cp_ring->index] += count; 567 tx_ring->tail = tail; 568 569 return count; 570 } 571 572 static netdev_tx_t xgene_enet_start_xmit(struct sk_buff *skb, 573 struct net_device *ndev) 574 { 575 struct xgene_enet_pdata *pdata = netdev_priv(ndev); 576 struct xgene_enet_desc_ring *tx_ring; 577 int index = skb->queue_mapping; 578 u32 tx_level = pdata->tx_level[index]; 579 int count; 580 581 tx_ring = pdata->tx_ring[index]; 582 if (tx_level < pdata->txc_level[index]) 583 tx_level += ((typeof(pdata->tx_level[index]))~0U); 584 585 if ((tx_level - pdata->txc_level[index]) > pdata->tx_qcnt_hi) { 586 netif_stop_subqueue(ndev, index); 587 return NETDEV_TX_BUSY; 588 } 589 590 if (skb_padto(skb, XGENE_MIN_ENET_FRAME_SIZE)) 591 return NETDEV_TX_OK; 592 593 count = xgene_enet_setup_tx_desc(tx_ring, skb); 594 if (count == -EBUSY) 595 return NETDEV_TX_BUSY; 596 597 if (count <= 0) { 598 dev_kfree_skb_any(skb); 599 return NETDEV_TX_OK; 600 } 601 602 skb_tx_timestamp(skb); 603 604 tx_ring->tx_packets++; 605 tx_ring->tx_bytes += skb->len; 606 607 pdata->ring_ops->wr_cmd(tx_ring, count); 608 return NETDEV_TX_OK; 609 } 610 611 static void xgene_enet_skip_csum(struct sk_buff *skb) 612 { 613 struct iphdr *iph = ip_hdr(skb); 614 615 if (!ip_is_fragment(iph) || 616 (iph->protocol != IPPROTO_TCP && iph->protocol != IPPROTO_UDP)) { 617 skb->ip_summed = CHECKSUM_UNNECESSARY; 618 } 619 } 620 621 static void xgene_enet_free_pagepool(struct xgene_enet_desc_ring *buf_pool, 622 struct xgene_enet_raw_desc *raw_desc, 623 struct xgene_enet_raw_desc *exp_desc) 624 { 625 __le64 *desc = (void *)exp_desc; 626 dma_addr_t dma_addr; 627 struct device *dev; 628 struct page *page; 629 u16 slots, head; 630 u32 frag_size; 631 int i; 632 633 if (!buf_pool || !raw_desc || !exp_desc || 634 (!GET_VAL(NV, le64_to_cpu(raw_desc->m0)))) 635 return; 636 637 dev = ndev_to_dev(buf_pool->ndev); 638 head = buf_pool->head; 639 640 for (i = 0; i < 4; i++) { 641 frag_size = xgene_enet_get_data_len(le64_to_cpu(desc[i ^ 1])); 642 if (!frag_size) 643 break; 644 645 dma_addr = GET_VAL(DATAADDR, le64_to_cpu(desc[i ^ 1])); 646 dma_unmap_page(dev, dma_addr, PAGE_SIZE, DMA_FROM_DEVICE); 647 648 page = buf_pool->frag_page[head]; 649 put_page(page); 650 651 buf_pool->frag_page[head] = NULL; 652 head = (head + 1) & slots; 653 } 654 buf_pool->head = head; 655 } 656 657 static int xgene_enet_rx_frame(struct xgene_enet_desc_ring *rx_ring, 658 struct xgene_enet_raw_desc *raw_desc, 659 struct xgene_enet_raw_desc *exp_desc) 660 { 661 struct xgene_enet_desc_ring *buf_pool, *page_pool; 662 u32 datalen, frag_size, skb_index; 663 struct net_device *ndev; 664 dma_addr_t dma_addr; 665 struct sk_buff *skb; 666 struct device *dev; 667 struct page *page; 668 u16 slots, head; 669 int i, ret = 0; 670 __le64 *desc; 671 u8 status; 672 bool nv; 673 674 ndev = rx_ring->ndev; 675 dev = ndev_to_dev(rx_ring->ndev); 676 buf_pool = rx_ring->buf_pool; 677 page_pool = rx_ring->page_pool; 678 679 dma_unmap_single(dev, GET_VAL(DATAADDR, le64_to_cpu(raw_desc->m1)), 680 XGENE_ENET_STD_MTU, DMA_FROM_DEVICE); 681 skb_index = GET_VAL(USERINFO, le64_to_cpu(raw_desc->m0)); 682 skb = buf_pool->rx_skb[skb_index]; 683 buf_pool->rx_skb[skb_index] = NULL; 684 685 /* checking for error */ 686 status = (GET_VAL(ELERR, le64_to_cpu(raw_desc->m0)) << LERR_LEN) || 687 GET_VAL(LERR, le64_to_cpu(raw_desc->m0)); 688 if (unlikely(status > 2)) { 689 dev_kfree_skb_any(skb); 690 xgene_enet_free_pagepool(page_pool, raw_desc, exp_desc); 691 xgene_enet_parse_error(rx_ring, netdev_priv(rx_ring->ndev), 692 status); 693 ret = -EIO; 694 goto out; 695 } 696 697 /* strip off CRC as HW isn't doing this */ 698 datalen = xgene_enet_get_data_len(le64_to_cpu(raw_desc->m1)); 699 700 nv = GET_VAL(NV, le64_to_cpu(raw_desc->m0)); 701 if (!nv) 702 datalen -= 4; 703 704 skb_put(skb, datalen); 705 prefetch(skb->data - NET_IP_ALIGN); 706 707 if (!nv) 708 goto skip_jumbo; 709 710 slots = page_pool->slots - 1; 711 head = page_pool->head; 712 desc = (void *)exp_desc; 713 714 for (i = 0; i < 4; i++) { 715 frag_size = xgene_enet_get_data_len(le64_to_cpu(desc[i ^ 1])); 716 if (!frag_size) 717 break; 718 719 dma_addr = GET_VAL(DATAADDR, le64_to_cpu(desc[i ^ 1])); 720 dma_unmap_page(dev, dma_addr, PAGE_SIZE, DMA_FROM_DEVICE); 721 722 page = page_pool->frag_page[head]; 723 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, 0, 724 frag_size, PAGE_SIZE); 725 726 datalen += frag_size; 727 728 page_pool->frag_page[head] = NULL; 729 head = (head + 1) & slots; 730 } 731 732 page_pool->head = head; 733 rx_ring->npagepool -= skb_shinfo(skb)->nr_frags; 734 735 skip_jumbo: 736 skb_checksum_none_assert(skb); 737 skb->protocol = eth_type_trans(skb, ndev); 738 if (likely((ndev->features & NETIF_F_IP_CSUM) && 739 skb->protocol == htons(ETH_P_IP))) { 740 xgene_enet_skip_csum(skb); 741 } 742 743 rx_ring->rx_packets++; 744 rx_ring->rx_bytes += datalen; 745 napi_gro_receive(&rx_ring->napi, skb); 746 747 out: 748 if (rx_ring->npagepool <= 0) { 749 ret = xgene_enet_refill_pagepool(page_pool, NUM_NXTBUFPOOL); 750 rx_ring->npagepool = NUM_NXTBUFPOOL; 751 if (ret) 752 return ret; 753 } 754 755 if (--rx_ring->nbufpool == 0) { 756 ret = xgene_enet_refill_bufpool(buf_pool, NUM_BUFPOOL); 757 rx_ring->nbufpool = NUM_BUFPOOL; 758 } 759 760 return ret; 761 } 762 763 static bool is_rx_desc(struct xgene_enet_raw_desc *raw_desc) 764 { 765 return GET_VAL(FPQNUM, le64_to_cpu(raw_desc->m0)) ? true : false; 766 } 767 768 static int xgene_enet_process_ring(struct xgene_enet_desc_ring *ring, 769 int budget) 770 { 771 struct net_device *ndev = ring->ndev; 772 struct xgene_enet_pdata *pdata = netdev_priv(ndev); 773 struct xgene_enet_raw_desc *raw_desc, *exp_desc; 774 u16 head = ring->head; 775 u16 slots = ring->slots - 1; 776 int ret, desc_count, count = 0, processed = 0; 777 bool is_completion; 778 779 do { 780 raw_desc = &ring->raw_desc[head]; 781 desc_count = 0; 782 is_completion = false; 783 exp_desc = NULL; 784 if (unlikely(xgene_enet_is_desc_slot_empty(raw_desc))) 785 break; 786 787 /* read fpqnum field after dataaddr field */ 788 dma_rmb(); 789 if (GET_BIT(NV, le64_to_cpu(raw_desc->m0))) { 790 head = (head + 1) & slots; 791 exp_desc = &ring->raw_desc[head]; 792 793 if (unlikely(xgene_enet_is_desc_slot_empty(exp_desc))) { 794 head = (head - 1) & slots; 795 break; 796 } 797 dma_rmb(); 798 count++; 799 desc_count++; 800 } 801 if (is_rx_desc(raw_desc)) { 802 ret = xgene_enet_rx_frame(ring, raw_desc, exp_desc); 803 } else { 804 ret = xgene_enet_tx_completion(ring, raw_desc); 805 is_completion = true; 806 } 807 xgene_enet_mark_desc_slot_empty(raw_desc); 808 if (exp_desc) 809 xgene_enet_mark_desc_slot_empty(exp_desc); 810 811 head = (head + 1) & slots; 812 count++; 813 desc_count++; 814 processed++; 815 if (is_completion) 816 pdata->txc_level[ring->index] += desc_count; 817 818 if (ret) 819 break; 820 } while (--budget); 821 822 if (likely(count)) { 823 pdata->ring_ops->wr_cmd(ring, -count); 824 ring->head = head; 825 826 if (__netif_subqueue_stopped(ndev, ring->index)) 827 netif_start_subqueue(ndev, ring->index); 828 } 829 830 return processed; 831 } 832 833 static int xgene_enet_napi(struct napi_struct *napi, const int budget) 834 { 835 struct xgene_enet_desc_ring *ring; 836 int processed; 837 838 ring = container_of(napi, struct xgene_enet_desc_ring, napi); 839 processed = xgene_enet_process_ring(ring, budget); 840 841 if (processed != budget) { 842 napi_complete(napi); 843 enable_irq(ring->irq); 844 } 845 846 return processed; 847 } 848 849 static void xgene_enet_timeout(struct net_device *ndev) 850 { 851 struct xgene_enet_pdata *pdata = netdev_priv(ndev); 852 struct netdev_queue *txq; 853 int i; 854 855 pdata->mac_ops->reset(pdata); 856 857 for (i = 0; i < pdata->txq_cnt; i++) { 858 txq = netdev_get_tx_queue(ndev, i); 859 txq->trans_start = jiffies; 860 netif_tx_start_queue(txq); 861 } 862 } 863 864 static void xgene_enet_set_irq_name(struct net_device *ndev) 865 { 866 struct xgene_enet_pdata *pdata = netdev_priv(ndev); 867 struct xgene_enet_desc_ring *ring; 868 int i; 869 870 for (i = 0; i < pdata->rxq_cnt; i++) { 871 ring = pdata->rx_ring[i]; 872 if (!pdata->cq_cnt) { 873 snprintf(ring->irq_name, IRQ_ID_SIZE, "%s-rx-txc", 874 ndev->name); 875 } else { 876 snprintf(ring->irq_name, IRQ_ID_SIZE, "%s-rx-%d", 877 ndev->name, i); 878 } 879 } 880 881 for (i = 0; i < pdata->cq_cnt; i++) { 882 ring = pdata->tx_ring[i]->cp_ring; 883 snprintf(ring->irq_name, IRQ_ID_SIZE, "%s-txc-%d", 884 ndev->name, i); 885 } 886 } 887 888 static int xgene_enet_register_irq(struct net_device *ndev) 889 { 890 struct xgene_enet_pdata *pdata = netdev_priv(ndev); 891 struct device *dev = ndev_to_dev(ndev); 892 struct xgene_enet_desc_ring *ring; 893 int ret = 0, i; 894 895 xgene_enet_set_irq_name(ndev); 896 for (i = 0; i < pdata->rxq_cnt; i++) { 897 ring = pdata->rx_ring[i]; 898 irq_set_status_flags(ring->irq, IRQ_DISABLE_UNLAZY); 899 ret = devm_request_irq(dev, ring->irq, xgene_enet_rx_irq, 900 0, ring->irq_name, ring); 901 if (ret) { 902 netdev_err(ndev, "Failed to request irq %s\n", 903 ring->irq_name); 904 } 905 } 906 907 for (i = 0; i < pdata->cq_cnt; i++) { 908 ring = pdata->tx_ring[i]->cp_ring; 909 irq_set_status_flags(ring->irq, IRQ_DISABLE_UNLAZY); 910 ret = devm_request_irq(dev, ring->irq, xgene_enet_rx_irq, 911 0, ring->irq_name, ring); 912 if (ret) { 913 netdev_err(ndev, "Failed to request irq %s\n", 914 ring->irq_name); 915 } 916 } 917 918 return ret; 919 } 920 921 static void xgene_enet_free_irq(struct net_device *ndev) 922 { 923 struct xgene_enet_pdata *pdata; 924 struct xgene_enet_desc_ring *ring; 925 struct device *dev; 926 int i; 927 928 pdata = netdev_priv(ndev); 929 dev = ndev_to_dev(ndev); 930 931 for (i = 0; i < pdata->rxq_cnt; i++) { 932 ring = pdata->rx_ring[i]; 933 irq_clear_status_flags(ring->irq, IRQ_DISABLE_UNLAZY); 934 devm_free_irq(dev, ring->irq, ring); 935 } 936 937 for (i = 0; i < pdata->cq_cnt; i++) { 938 ring = pdata->tx_ring[i]->cp_ring; 939 irq_clear_status_flags(ring->irq, IRQ_DISABLE_UNLAZY); 940 devm_free_irq(dev, ring->irq, ring); 941 } 942 } 943 944 static void xgene_enet_napi_enable(struct xgene_enet_pdata *pdata) 945 { 946 struct napi_struct *napi; 947 int i; 948 949 for (i = 0; i < pdata->rxq_cnt; i++) { 950 napi = &pdata->rx_ring[i]->napi; 951 napi_enable(napi); 952 } 953 954 for (i = 0; i < pdata->cq_cnt; i++) { 955 napi = &pdata->tx_ring[i]->cp_ring->napi; 956 napi_enable(napi); 957 } 958 } 959 960 static void xgene_enet_napi_disable(struct xgene_enet_pdata *pdata) 961 { 962 struct napi_struct *napi; 963 int i; 964 965 for (i = 0; i < pdata->rxq_cnt; i++) { 966 napi = &pdata->rx_ring[i]->napi; 967 napi_disable(napi); 968 } 969 970 for (i = 0; i < pdata->cq_cnt; i++) { 971 napi = &pdata->tx_ring[i]->cp_ring->napi; 972 napi_disable(napi); 973 } 974 } 975 976 static int xgene_enet_open(struct net_device *ndev) 977 { 978 struct xgene_enet_pdata *pdata = netdev_priv(ndev); 979 const struct xgene_mac_ops *mac_ops = pdata->mac_ops; 980 int ret; 981 982 ret = netif_set_real_num_tx_queues(ndev, pdata->txq_cnt); 983 if (ret) 984 return ret; 985 986 ret = netif_set_real_num_rx_queues(ndev, pdata->rxq_cnt); 987 if (ret) 988 return ret; 989 990 xgene_enet_napi_enable(pdata); 991 ret = xgene_enet_register_irq(ndev); 992 if (ret) 993 return ret; 994 995 if (ndev->phydev) { 996 phy_start(ndev->phydev); 997 } else { 998 schedule_delayed_work(&pdata->link_work, PHY_POLL_LINK_OFF); 999 netif_carrier_off(ndev); 1000 } 1001 1002 mac_ops->tx_enable(pdata); 1003 mac_ops->rx_enable(pdata); 1004 netif_tx_start_all_queues(ndev); 1005 1006 return ret; 1007 } 1008 1009 static int xgene_enet_close(struct net_device *ndev) 1010 { 1011 struct xgene_enet_pdata *pdata = netdev_priv(ndev); 1012 const struct xgene_mac_ops *mac_ops = pdata->mac_ops; 1013 int i; 1014 1015 netif_tx_stop_all_queues(ndev); 1016 mac_ops->tx_disable(pdata); 1017 mac_ops->rx_disable(pdata); 1018 1019 if (ndev->phydev) 1020 phy_stop(ndev->phydev); 1021 else 1022 cancel_delayed_work_sync(&pdata->link_work); 1023 1024 xgene_enet_free_irq(ndev); 1025 xgene_enet_napi_disable(pdata); 1026 for (i = 0; i < pdata->rxq_cnt; i++) 1027 xgene_enet_process_ring(pdata->rx_ring[i], -1); 1028 1029 return 0; 1030 } 1031 static void xgene_enet_delete_ring(struct xgene_enet_desc_ring *ring) 1032 { 1033 struct xgene_enet_pdata *pdata; 1034 struct device *dev; 1035 1036 pdata = netdev_priv(ring->ndev); 1037 dev = ndev_to_dev(ring->ndev); 1038 1039 pdata->ring_ops->clear(ring); 1040 dmam_free_coherent(dev, ring->size, ring->desc_addr, ring->dma); 1041 } 1042 1043 static void xgene_enet_delete_desc_rings(struct xgene_enet_pdata *pdata) 1044 { 1045 struct xgene_enet_desc_ring *buf_pool, *page_pool; 1046 struct xgene_enet_desc_ring *ring; 1047 int i; 1048 1049 for (i = 0; i < pdata->txq_cnt; i++) { 1050 ring = pdata->tx_ring[i]; 1051 if (ring) { 1052 xgene_enet_delete_ring(ring); 1053 pdata->port_ops->clear(pdata, ring); 1054 if (pdata->cq_cnt) 1055 xgene_enet_delete_ring(ring->cp_ring); 1056 pdata->tx_ring[i] = NULL; 1057 } 1058 1059 } 1060 1061 for (i = 0; i < pdata->rxq_cnt; i++) { 1062 ring = pdata->rx_ring[i]; 1063 if (ring) { 1064 page_pool = ring->page_pool; 1065 if (page_pool) { 1066 xgene_enet_delete_pagepool(page_pool); 1067 xgene_enet_delete_ring(page_pool); 1068 pdata->port_ops->clear(pdata, page_pool); 1069 } 1070 1071 buf_pool = ring->buf_pool; 1072 xgene_enet_delete_bufpool(buf_pool); 1073 xgene_enet_delete_ring(buf_pool); 1074 pdata->port_ops->clear(pdata, buf_pool); 1075 1076 xgene_enet_delete_ring(ring); 1077 pdata->rx_ring[i] = NULL; 1078 } 1079 1080 } 1081 } 1082 1083 static int xgene_enet_get_ring_size(struct device *dev, 1084 enum xgene_enet_ring_cfgsize cfgsize) 1085 { 1086 int size = -EINVAL; 1087 1088 switch (cfgsize) { 1089 case RING_CFGSIZE_512B: 1090 size = 0x200; 1091 break; 1092 case RING_CFGSIZE_2KB: 1093 size = 0x800; 1094 break; 1095 case RING_CFGSIZE_16KB: 1096 size = 0x4000; 1097 break; 1098 case RING_CFGSIZE_64KB: 1099 size = 0x10000; 1100 break; 1101 case RING_CFGSIZE_512KB: 1102 size = 0x80000; 1103 break; 1104 default: 1105 dev_err(dev, "Unsupported cfg ring size %d\n", cfgsize); 1106 break; 1107 } 1108 1109 return size; 1110 } 1111 1112 static void xgene_enet_free_desc_ring(struct xgene_enet_desc_ring *ring) 1113 { 1114 struct xgene_enet_pdata *pdata; 1115 struct device *dev; 1116 1117 if (!ring) 1118 return; 1119 1120 dev = ndev_to_dev(ring->ndev); 1121 pdata = netdev_priv(ring->ndev); 1122 1123 if (ring->desc_addr) { 1124 pdata->ring_ops->clear(ring); 1125 dmam_free_coherent(dev, ring->size, ring->desc_addr, ring->dma); 1126 } 1127 devm_kfree(dev, ring); 1128 } 1129 1130 static void xgene_enet_free_desc_rings(struct xgene_enet_pdata *pdata) 1131 { 1132 struct xgene_enet_desc_ring *page_pool; 1133 struct device *dev = &pdata->pdev->dev; 1134 struct xgene_enet_desc_ring *ring; 1135 void *p; 1136 int i; 1137 1138 for (i = 0; i < pdata->txq_cnt; i++) { 1139 ring = pdata->tx_ring[i]; 1140 if (ring) { 1141 if (ring->cp_ring && ring->cp_ring->cp_skb) 1142 devm_kfree(dev, ring->cp_ring->cp_skb); 1143 1144 if (ring->cp_ring && pdata->cq_cnt) 1145 xgene_enet_free_desc_ring(ring->cp_ring); 1146 1147 xgene_enet_free_desc_ring(ring); 1148 } 1149 1150 } 1151 1152 for (i = 0; i < pdata->rxq_cnt; i++) { 1153 ring = pdata->rx_ring[i]; 1154 if (ring) { 1155 if (ring->buf_pool) { 1156 if (ring->buf_pool->rx_skb) 1157 devm_kfree(dev, ring->buf_pool->rx_skb); 1158 1159 xgene_enet_free_desc_ring(ring->buf_pool); 1160 } 1161 1162 page_pool = ring->page_pool; 1163 if (page_pool) { 1164 p = page_pool->frag_page; 1165 if (p) 1166 devm_kfree(dev, p); 1167 1168 p = page_pool->frag_dma_addr; 1169 if (p) 1170 devm_kfree(dev, p); 1171 } 1172 1173 xgene_enet_free_desc_ring(ring); 1174 } 1175 } 1176 } 1177 1178 static bool is_irq_mbox_required(struct xgene_enet_pdata *pdata, 1179 struct xgene_enet_desc_ring *ring) 1180 { 1181 if ((pdata->enet_id == XGENE_ENET2) && 1182 (xgene_enet_ring_owner(ring->id) == RING_OWNER_CPU)) { 1183 return true; 1184 } 1185 1186 return false; 1187 } 1188 1189 static void __iomem *xgene_enet_ring_cmd_base(struct xgene_enet_pdata *pdata, 1190 struct xgene_enet_desc_ring *ring) 1191 { 1192 u8 num_ring_id_shift = pdata->ring_ops->num_ring_id_shift; 1193 1194 return pdata->ring_cmd_addr + (ring->num << num_ring_id_shift); 1195 } 1196 1197 static struct xgene_enet_desc_ring *xgene_enet_create_desc_ring( 1198 struct net_device *ndev, u32 ring_num, 1199 enum xgene_enet_ring_cfgsize cfgsize, u32 ring_id) 1200 { 1201 struct xgene_enet_pdata *pdata = netdev_priv(ndev); 1202 struct device *dev = ndev_to_dev(ndev); 1203 struct xgene_enet_desc_ring *ring; 1204 void *irq_mbox_addr; 1205 int size; 1206 1207 size = xgene_enet_get_ring_size(dev, cfgsize); 1208 if (size < 0) 1209 return NULL; 1210 1211 ring = devm_kzalloc(dev, sizeof(struct xgene_enet_desc_ring), 1212 GFP_KERNEL); 1213 if (!ring) 1214 return NULL; 1215 1216 ring->ndev = ndev; 1217 ring->num = ring_num; 1218 ring->cfgsize = cfgsize; 1219 ring->id = ring_id; 1220 1221 ring->desc_addr = dmam_alloc_coherent(dev, size, &ring->dma, 1222 GFP_KERNEL | __GFP_ZERO); 1223 if (!ring->desc_addr) { 1224 devm_kfree(dev, ring); 1225 return NULL; 1226 } 1227 ring->size = size; 1228 1229 if (is_irq_mbox_required(pdata, ring)) { 1230 irq_mbox_addr = dmam_alloc_coherent(dev, INTR_MBOX_SIZE, 1231 &ring->irq_mbox_dma, 1232 GFP_KERNEL | __GFP_ZERO); 1233 if (!irq_mbox_addr) { 1234 dmam_free_coherent(dev, size, ring->desc_addr, 1235 ring->dma); 1236 devm_kfree(dev, ring); 1237 return NULL; 1238 } 1239 ring->irq_mbox_addr = irq_mbox_addr; 1240 } 1241 1242 ring->cmd_base = xgene_enet_ring_cmd_base(pdata, ring); 1243 ring->cmd = ring->cmd_base + INC_DEC_CMD_ADDR; 1244 ring = pdata->ring_ops->setup(ring); 1245 netdev_dbg(ndev, "ring info: num=%d size=%d id=%d slots=%d\n", 1246 ring->num, ring->size, ring->id, ring->slots); 1247 1248 return ring; 1249 } 1250 1251 static u16 xgene_enet_get_ring_id(enum xgene_ring_owner owner, u8 bufnum) 1252 { 1253 return (owner << 6) | (bufnum & GENMASK(5, 0)); 1254 } 1255 1256 static enum xgene_ring_owner xgene_derive_ring_owner(struct xgene_enet_pdata *p) 1257 { 1258 enum xgene_ring_owner owner; 1259 1260 if (p->enet_id == XGENE_ENET1) { 1261 switch (p->phy_mode) { 1262 case PHY_INTERFACE_MODE_SGMII: 1263 owner = RING_OWNER_ETH0; 1264 break; 1265 default: 1266 owner = (!p->port_id) ? RING_OWNER_ETH0 : 1267 RING_OWNER_ETH1; 1268 break; 1269 } 1270 } else { 1271 owner = (!p->port_id) ? RING_OWNER_ETH0 : RING_OWNER_ETH1; 1272 } 1273 1274 return owner; 1275 } 1276 1277 static u8 xgene_start_cpu_bufnum(struct xgene_enet_pdata *pdata) 1278 { 1279 struct device *dev = &pdata->pdev->dev; 1280 u32 cpu_bufnum; 1281 int ret; 1282 1283 ret = device_property_read_u32(dev, "channel", &cpu_bufnum); 1284 1285 return (!ret) ? cpu_bufnum : pdata->cpu_bufnum; 1286 } 1287 1288 static int xgene_enet_create_desc_rings(struct net_device *ndev) 1289 { 1290 struct xgene_enet_desc_ring *rx_ring, *tx_ring, *cp_ring; 1291 struct xgene_enet_pdata *pdata = netdev_priv(ndev); 1292 struct xgene_enet_desc_ring *page_pool = NULL; 1293 struct xgene_enet_desc_ring *buf_pool = NULL; 1294 struct device *dev = ndev_to_dev(ndev); 1295 u8 eth_bufnum = pdata->eth_bufnum; 1296 u8 bp_bufnum = pdata->bp_bufnum; 1297 u16 ring_num = pdata->ring_num; 1298 enum xgene_ring_owner owner; 1299 dma_addr_t dma_exp_bufs; 1300 u16 ring_id, slots; 1301 __le64 *exp_bufs; 1302 int i, ret, size; 1303 u8 cpu_bufnum; 1304 1305 cpu_bufnum = xgene_start_cpu_bufnum(pdata); 1306 1307 for (i = 0; i < pdata->rxq_cnt; i++) { 1308 /* allocate rx descriptor ring */ 1309 owner = xgene_derive_ring_owner(pdata); 1310 ring_id = xgene_enet_get_ring_id(RING_OWNER_CPU, cpu_bufnum++); 1311 rx_ring = xgene_enet_create_desc_ring(ndev, ring_num++, 1312 RING_CFGSIZE_16KB, 1313 ring_id); 1314 if (!rx_ring) { 1315 ret = -ENOMEM; 1316 goto err; 1317 } 1318 1319 /* allocate buffer pool for receiving packets */ 1320 owner = xgene_derive_ring_owner(pdata); 1321 ring_id = xgene_enet_get_ring_id(owner, bp_bufnum++); 1322 buf_pool = xgene_enet_create_desc_ring(ndev, ring_num++, 1323 RING_CFGSIZE_16KB, 1324 ring_id); 1325 if (!buf_pool) { 1326 ret = -ENOMEM; 1327 goto err; 1328 } 1329 1330 rx_ring->nbufpool = NUM_BUFPOOL; 1331 rx_ring->npagepool = NUM_NXTBUFPOOL; 1332 rx_ring->irq = pdata->irqs[i]; 1333 buf_pool->rx_skb = devm_kcalloc(dev, buf_pool->slots, 1334 sizeof(struct sk_buff *), 1335 GFP_KERNEL); 1336 if (!buf_pool->rx_skb) { 1337 ret = -ENOMEM; 1338 goto err; 1339 } 1340 1341 buf_pool->dst_ring_num = xgene_enet_dst_ring_num(buf_pool); 1342 rx_ring->buf_pool = buf_pool; 1343 pdata->rx_ring[i] = rx_ring; 1344 1345 if ((pdata->enet_id == XGENE_ENET1 && pdata->rxq_cnt > 4) || 1346 (pdata->enet_id == XGENE_ENET2 && pdata->rxq_cnt > 16)) { 1347 break; 1348 } 1349 1350 /* allocate next buffer pool for jumbo packets */ 1351 owner = xgene_derive_ring_owner(pdata); 1352 ring_id = xgene_enet_get_ring_id(owner, bp_bufnum++); 1353 page_pool = xgene_enet_create_desc_ring(ndev, ring_num++, 1354 RING_CFGSIZE_16KB, 1355 ring_id); 1356 if (!page_pool) { 1357 ret = -ENOMEM; 1358 goto err; 1359 } 1360 1361 slots = page_pool->slots; 1362 page_pool->frag_page = devm_kcalloc(dev, slots, 1363 sizeof(struct page *), 1364 GFP_KERNEL); 1365 if (!page_pool->frag_page) { 1366 ret = -ENOMEM; 1367 goto err; 1368 } 1369 1370 page_pool->frag_dma_addr = devm_kcalloc(dev, slots, 1371 sizeof(dma_addr_t), 1372 GFP_KERNEL); 1373 if (!page_pool->frag_dma_addr) { 1374 ret = -ENOMEM; 1375 goto err; 1376 } 1377 1378 page_pool->dst_ring_num = xgene_enet_dst_ring_num(page_pool); 1379 rx_ring->page_pool = page_pool; 1380 } 1381 1382 for (i = 0; i < pdata->txq_cnt; i++) { 1383 /* allocate tx descriptor ring */ 1384 owner = xgene_derive_ring_owner(pdata); 1385 ring_id = xgene_enet_get_ring_id(owner, eth_bufnum++); 1386 tx_ring = xgene_enet_create_desc_ring(ndev, ring_num++, 1387 RING_CFGSIZE_16KB, 1388 ring_id); 1389 if (!tx_ring) { 1390 ret = -ENOMEM; 1391 goto err; 1392 } 1393 1394 size = (tx_ring->slots / 2) * sizeof(__le64) * MAX_EXP_BUFFS; 1395 exp_bufs = dmam_alloc_coherent(dev, size, &dma_exp_bufs, 1396 GFP_KERNEL | __GFP_ZERO); 1397 if (!exp_bufs) { 1398 ret = -ENOMEM; 1399 goto err; 1400 } 1401 tx_ring->exp_bufs = exp_bufs; 1402 1403 pdata->tx_ring[i] = tx_ring; 1404 1405 if (!pdata->cq_cnt) { 1406 cp_ring = pdata->rx_ring[i]; 1407 } else { 1408 /* allocate tx completion descriptor ring */ 1409 ring_id = xgene_enet_get_ring_id(RING_OWNER_CPU, 1410 cpu_bufnum++); 1411 cp_ring = xgene_enet_create_desc_ring(ndev, ring_num++, 1412 RING_CFGSIZE_16KB, 1413 ring_id); 1414 if (!cp_ring) { 1415 ret = -ENOMEM; 1416 goto err; 1417 } 1418 1419 cp_ring->irq = pdata->irqs[pdata->rxq_cnt + i]; 1420 cp_ring->index = i; 1421 } 1422 1423 cp_ring->cp_skb = devm_kcalloc(dev, tx_ring->slots, 1424 sizeof(struct sk_buff *), 1425 GFP_KERNEL); 1426 if (!cp_ring->cp_skb) { 1427 ret = -ENOMEM; 1428 goto err; 1429 } 1430 1431 size = sizeof(dma_addr_t) * MAX_SKB_FRAGS; 1432 cp_ring->frag_dma_addr = devm_kcalloc(dev, tx_ring->slots, 1433 size, GFP_KERNEL); 1434 if (!cp_ring->frag_dma_addr) { 1435 devm_kfree(dev, cp_ring->cp_skb); 1436 ret = -ENOMEM; 1437 goto err; 1438 } 1439 1440 tx_ring->cp_ring = cp_ring; 1441 tx_ring->dst_ring_num = xgene_enet_dst_ring_num(cp_ring); 1442 } 1443 1444 if (pdata->ring_ops->coalesce) 1445 pdata->ring_ops->coalesce(pdata->tx_ring[0]); 1446 pdata->tx_qcnt_hi = pdata->tx_ring[0]->slots - 128; 1447 1448 return 0; 1449 1450 err: 1451 xgene_enet_free_desc_rings(pdata); 1452 return ret; 1453 } 1454 1455 static struct rtnl_link_stats64 *xgene_enet_get_stats64( 1456 struct net_device *ndev, 1457 struct rtnl_link_stats64 *storage) 1458 { 1459 struct xgene_enet_pdata *pdata = netdev_priv(ndev); 1460 struct rtnl_link_stats64 *stats = &pdata->stats; 1461 struct xgene_enet_desc_ring *ring; 1462 int i; 1463 1464 memset(stats, 0, sizeof(struct rtnl_link_stats64)); 1465 for (i = 0; i < pdata->txq_cnt; i++) { 1466 ring = pdata->tx_ring[i]; 1467 if (ring) { 1468 stats->tx_packets += ring->tx_packets; 1469 stats->tx_bytes += ring->tx_bytes; 1470 } 1471 } 1472 1473 for (i = 0; i < pdata->rxq_cnt; i++) { 1474 ring = pdata->rx_ring[i]; 1475 if (ring) { 1476 stats->rx_packets += ring->rx_packets; 1477 stats->rx_bytes += ring->rx_bytes; 1478 stats->rx_errors += ring->rx_length_errors + 1479 ring->rx_crc_errors + 1480 ring->rx_frame_errors + 1481 ring->rx_fifo_errors; 1482 stats->rx_dropped += ring->rx_dropped; 1483 } 1484 } 1485 memcpy(storage, stats, sizeof(struct rtnl_link_stats64)); 1486 1487 return storage; 1488 } 1489 1490 static int xgene_enet_set_mac_address(struct net_device *ndev, void *addr) 1491 { 1492 struct xgene_enet_pdata *pdata = netdev_priv(ndev); 1493 int ret; 1494 1495 ret = eth_mac_addr(ndev, addr); 1496 if (ret) 1497 return ret; 1498 pdata->mac_ops->set_mac_addr(pdata); 1499 1500 return ret; 1501 } 1502 1503 static int xgene_change_mtu(struct net_device *ndev, int new_mtu) 1504 { 1505 struct xgene_enet_pdata *pdata = netdev_priv(ndev); 1506 int frame_size; 1507 1508 if (!netif_running(ndev)) 1509 return 0; 1510 1511 frame_size = (new_mtu > ETH_DATA_LEN) ? (new_mtu + 18) : 0x600; 1512 1513 xgene_enet_close(ndev); 1514 ndev->mtu = new_mtu; 1515 pdata->mac_ops->set_framesize(pdata, frame_size); 1516 xgene_enet_open(ndev); 1517 1518 return 0; 1519 } 1520 1521 static const struct net_device_ops xgene_ndev_ops = { 1522 .ndo_open = xgene_enet_open, 1523 .ndo_stop = xgene_enet_close, 1524 .ndo_start_xmit = xgene_enet_start_xmit, 1525 .ndo_tx_timeout = xgene_enet_timeout, 1526 .ndo_get_stats64 = xgene_enet_get_stats64, 1527 .ndo_change_mtu = xgene_change_mtu, 1528 .ndo_set_mac_address = xgene_enet_set_mac_address, 1529 }; 1530 1531 #ifdef CONFIG_ACPI 1532 static void xgene_get_port_id_acpi(struct device *dev, 1533 struct xgene_enet_pdata *pdata) 1534 { 1535 acpi_status status; 1536 u64 temp; 1537 1538 status = acpi_evaluate_integer(ACPI_HANDLE(dev), "_SUN", NULL, &temp); 1539 if (ACPI_FAILURE(status)) { 1540 pdata->port_id = 0; 1541 } else { 1542 pdata->port_id = temp; 1543 } 1544 1545 return; 1546 } 1547 #endif 1548 1549 static void xgene_get_port_id_dt(struct device *dev, struct xgene_enet_pdata *pdata) 1550 { 1551 u32 id = 0; 1552 1553 of_property_read_u32(dev->of_node, "port-id", &id); 1554 1555 pdata->port_id = id & BIT(0); 1556 1557 return; 1558 } 1559 1560 static int xgene_get_tx_delay(struct xgene_enet_pdata *pdata) 1561 { 1562 struct device *dev = &pdata->pdev->dev; 1563 int delay, ret; 1564 1565 ret = of_property_read_u32(dev->of_node, "tx-delay", &delay); 1566 if (ret) { 1567 pdata->tx_delay = 4; 1568 return 0; 1569 } 1570 1571 if (delay < 0 || delay > 7) { 1572 dev_err(dev, "Invalid tx-delay specified\n"); 1573 return -EINVAL; 1574 } 1575 1576 pdata->tx_delay = delay; 1577 1578 return 0; 1579 } 1580 1581 static int xgene_get_rx_delay(struct xgene_enet_pdata *pdata) 1582 { 1583 struct device *dev = &pdata->pdev->dev; 1584 int delay, ret; 1585 1586 ret = of_property_read_u32(dev->of_node, "rx-delay", &delay); 1587 if (ret) { 1588 pdata->rx_delay = 2; 1589 return 0; 1590 } 1591 1592 if (delay < 0 || delay > 7) { 1593 dev_err(dev, "Invalid rx-delay specified\n"); 1594 return -EINVAL; 1595 } 1596 1597 pdata->rx_delay = delay; 1598 1599 return 0; 1600 } 1601 1602 static int xgene_enet_get_irqs(struct xgene_enet_pdata *pdata) 1603 { 1604 struct platform_device *pdev = pdata->pdev; 1605 struct device *dev = &pdev->dev; 1606 int i, ret, max_irqs; 1607 1608 if (pdata->phy_mode == PHY_INTERFACE_MODE_RGMII) 1609 max_irqs = 1; 1610 else if (pdata->phy_mode == PHY_INTERFACE_MODE_SGMII) 1611 max_irqs = 2; 1612 else 1613 max_irqs = XGENE_MAX_ENET_IRQ; 1614 1615 for (i = 0; i < max_irqs; i++) { 1616 ret = platform_get_irq(pdev, i); 1617 if (ret <= 0) { 1618 if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) { 1619 max_irqs = i; 1620 pdata->rxq_cnt = max_irqs / 2; 1621 pdata->txq_cnt = max_irqs / 2; 1622 pdata->cq_cnt = max_irqs / 2; 1623 break; 1624 } 1625 dev_err(dev, "Unable to get ENET IRQ\n"); 1626 ret = ret ? : -ENXIO; 1627 return ret; 1628 } 1629 pdata->irqs[i] = ret; 1630 } 1631 1632 return 0; 1633 } 1634 1635 static int xgene_enet_check_phy_handle(struct xgene_enet_pdata *pdata) 1636 { 1637 int ret; 1638 1639 if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) 1640 return 0; 1641 1642 if (!IS_ENABLED(CONFIG_MDIO_XGENE)) 1643 return 0; 1644 1645 ret = xgene_enet_phy_connect(pdata->ndev); 1646 if (!ret) 1647 pdata->mdio_driver = true; 1648 1649 return 0; 1650 } 1651 1652 static void xgene_enet_gpiod_get(struct xgene_enet_pdata *pdata) 1653 { 1654 struct device *dev = &pdata->pdev->dev; 1655 1656 pdata->sfp_gpio_en = false; 1657 if (pdata->phy_mode != PHY_INTERFACE_MODE_XGMII || 1658 (!device_property_present(dev, "sfp-gpios") && 1659 !device_property_present(dev, "rxlos-gpios"))) 1660 return; 1661 1662 pdata->sfp_gpio_en = true; 1663 pdata->sfp_rdy = gpiod_get(dev, "rxlos", GPIOD_IN); 1664 if (IS_ERR(pdata->sfp_rdy)) 1665 pdata->sfp_rdy = gpiod_get(dev, "sfp", GPIOD_IN); 1666 } 1667 1668 static int xgene_enet_get_resources(struct xgene_enet_pdata *pdata) 1669 { 1670 struct platform_device *pdev; 1671 struct net_device *ndev; 1672 struct device *dev; 1673 struct resource *res; 1674 void __iomem *base_addr; 1675 u32 offset; 1676 int ret = 0; 1677 1678 pdev = pdata->pdev; 1679 dev = &pdev->dev; 1680 ndev = pdata->ndev; 1681 1682 res = platform_get_resource(pdev, IORESOURCE_MEM, RES_ENET_CSR); 1683 if (!res) { 1684 dev_err(dev, "Resource enet_csr not defined\n"); 1685 return -ENODEV; 1686 } 1687 pdata->base_addr = devm_ioremap(dev, res->start, resource_size(res)); 1688 if (!pdata->base_addr) { 1689 dev_err(dev, "Unable to retrieve ENET Port CSR region\n"); 1690 return -ENOMEM; 1691 } 1692 1693 res = platform_get_resource(pdev, IORESOURCE_MEM, RES_RING_CSR); 1694 if (!res) { 1695 dev_err(dev, "Resource ring_csr not defined\n"); 1696 return -ENODEV; 1697 } 1698 pdata->ring_csr_addr = devm_ioremap(dev, res->start, 1699 resource_size(res)); 1700 if (!pdata->ring_csr_addr) { 1701 dev_err(dev, "Unable to retrieve ENET Ring CSR region\n"); 1702 return -ENOMEM; 1703 } 1704 1705 res = platform_get_resource(pdev, IORESOURCE_MEM, RES_RING_CMD); 1706 if (!res) { 1707 dev_err(dev, "Resource ring_cmd not defined\n"); 1708 return -ENODEV; 1709 } 1710 pdata->ring_cmd_addr = devm_ioremap(dev, res->start, 1711 resource_size(res)); 1712 if (!pdata->ring_cmd_addr) { 1713 dev_err(dev, "Unable to retrieve ENET Ring command region\n"); 1714 return -ENOMEM; 1715 } 1716 1717 if (dev->of_node) 1718 xgene_get_port_id_dt(dev, pdata); 1719 #ifdef CONFIG_ACPI 1720 else 1721 xgene_get_port_id_acpi(dev, pdata); 1722 #endif 1723 1724 if (!device_get_mac_address(dev, ndev->dev_addr, ETH_ALEN)) 1725 eth_hw_addr_random(ndev); 1726 1727 memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len); 1728 1729 pdata->phy_mode = device_get_phy_mode(dev); 1730 if (pdata->phy_mode < 0) { 1731 dev_err(dev, "Unable to get phy-connection-type\n"); 1732 return pdata->phy_mode; 1733 } 1734 if (pdata->phy_mode != PHY_INTERFACE_MODE_RGMII && 1735 pdata->phy_mode != PHY_INTERFACE_MODE_SGMII && 1736 pdata->phy_mode != PHY_INTERFACE_MODE_XGMII) { 1737 dev_err(dev, "Incorrect phy-connection-type specified\n"); 1738 return -ENODEV; 1739 } 1740 1741 ret = xgene_get_tx_delay(pdata); 1742 if (ret) 1743 return ret; 1744 1745 ret = xgene_get_rx_delay(pdata); 1746 if (ret) 1747 return ret; 1748 1749 ret = xgene_enet_get_irqs(pdata); 1750 if (ret) 1751 return ret; 1752 1753 ret = xgene_enet_check_phy_handle(pdata); 1754 if (ret) 1755 return ret; 1756 1757 xgene_enet_gpiod_get(pdata); 1758 1759 pdata->clk = devm_clk_get(&pdev->dev, NULL); 1760 if (IS_ERR(pdata->clk)) { 1761 /* Firmware may have set up the clock already. */ 1762 dev_info(dev, "clocks have been setup already\n"); 1763 } 1764 1765 if (pdata->phy_mode != PHY_INTERFACE_MODE_XGMII) 1766 base_addr = pdata->base_addr - (pdata->port_id * MAC_OFFSET); 1767 else 1768 base_addr = pdata->base_addr; 1769 pdata->eth_csr_addr = base_addr + BLOCK_ETH_CSR_OFFSET; 1770 pdata->cle.base = base_addr + BLOCK_ETH_CLE_CSR_OFFSET; 1771 pdata->eth_ring_if_addr = base_addr + BLOCK_ETH_RING_IF_OFFSET; 1772 pdata->eth_diag_csr_addr = base_addr + BLOCK_ETH_DIAG_CSR_OFFSET; 1773 if (pdata->phy_mode == PHY_INTERFACE_MODE_RGMII || 1774 pdata->phy_mode == PHY_INTERFACE_MODE_SGMII) { 1775 pdata->mcx_mac_addr = pdata->base_addr + BLOCK_ETH_MAC_OFFSET; 1776 offset = (pdata->enet_id == XGENE_ENET1) ? 1777 BLOCK_ETH_MAC_CSR_OFFSET : 1778 X2_BLOCK_ETH_MAC_CSR_OFFSET; 1779 pdata->mcx_mac_csr_addr = base_addr + offset; 1780 } else { 1781 pdata->mcx_mac_addr = base_addr + BLOCK_AXG_MAC_OFFSET; 1782 pdata->mcx_mac_csr_addr = base_addr + BLOCK_AXG_MAC_CSR_OFFSET; 1783 pdata->pcs_addr = base_addr + BLOCK_PCS_OFFSET; 1784 } 1785 pdata->rx_buff_cnt = NUM_PKT_BUF; 1786 1787 return 0; 1788 } 1789 1790 static int xgene_enet_init_hw(struct xgene_enet_pdata *pdata) 1791 { 1792 struct xgene_enet_cle *enet_cle = &pdata->cle; 1793 struct xgene_enet_desc_ring *page_pool; 1794 struct net_device *ndev = pdata->ndev; 1795 struct xgene_enet_desc_ring *buf_pool; 1796 u16 dst_ring_num, ring_id; 1797 int i, ret; 1798 u32 count; 1799 1800 ret = pdata->port_ops->reset(pdata); 1801 if (ret) 1802 return ret; 1803 1804 ret = xgene_enet_create_desc_rings(ndev); 1805 if (ret) { 1806 netdev_err(ndev, "Error in ring configuration\n"); 1807 return ret; 1808 } 1809 1810 /* setup buffer pool */ 1811 for (i = 0; i < pdata->rxq_cnt; i++) { 1812 buf_pool = pdata->rx_ring[i]->buf_pool; 1813 xgene_enet_init_bufpool(buf_pool); 1814 page_pool = pdata->rx_ring[i]->page_pool; 1815 xgene_enet_init_bufpool(page_pool); 1816 1817 count = pdata->rx_buff_cnt; 1818 ret = xgene_enet_refill_bufpool(buf_pool, count); 1819 if (ret) 1820 goto err; 1821 1822 ret = xgene_enet_refill_pagepool(page_pool, count); 1823 if (ret) 1824 goto err; 1825 1826 } 1827 1828 dst_ring_num = xgene_enet_dst_ring_num(pdata->rx_ring[0]); 1829 buf_pool = pdata->rx_ring[0]->buf_pool; 1830 if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) { 1831 /* Initialize and Enable PreClassifier Tree */ 1832 enet_cle->max_nodes = 512; 1833 enet_cle->max_dbptrs = 1024; 1834 enet_cle->parsers = 3; 1835 enet_cle->active_parser = PARSER_ALL; 1836 enet_cle->ptree.start_node = 0; 1837 enet_cle->ptree.start_dbptr = 0; 1838 enet_cle->jump_bytes = 8; 1839 ret = pdata->cle_ops->cle_init(pdata); 1840 if (ret) { 1841 netdev_err(ndev, "Preclass Tree init error\n"); 1842 goto err; 1843 } 1844 1845 } else { 1846 dst_ring_num = xgene_enet_dst_ring_num(pdata->rx_ring[0]); 1847 buf_pool = pdata->rx_ring[0]->buf_pool; 1848 page_pool = pdata->rx_ring[0]->page_pool; 1849 ring_id = (page_pool) ? page_pool->id : 0; 1850 pdata->port_ops->cle_bypass(pdata, dst_ring_num, 1851 buf_pool->id, ring_id); 1852 } 1853 1854 ndev->max_mtu = XGENE_ENET_MAX_MTU; 1855 pdata->phy_speed = SPEED_UNKNOWN; 1856 pdata->mac_ops->init(pdata); 1857 1858 return ret; 1859 1860 err: 1861 xgene_enet_delete_desc_rings(pdata); 1862 return ret; 1863 } 1864 1865 static void xgene_enet_setup_ops(struct xgene_enet_pdata *pdata) 1866 { 1867 switch (pdata->phy_mode) { 1868 case PHY_INTERFACE_MODE_RGMII: 1869 pdata->mac_ops = &xgene_gmac_ops; 1870 pdata->port_ops = &xgene_gport_ops; 1871 pdata->rm = RM3; 1872 pdata->rxq_cnt = 1; 1873 pdata->txq_cnt = 1; 1874 pdata->cq_cnt = 0; 1875 break; 1876 case PHY_INTERFACE_MODE_SGMII: 1877 pdata->mac_ops = &xgene_sgmac_ops; 1878 pdata->port_ops = &xgene_sgport_ops; 1879 pdata->rm = RM1; 1880 pdata->rxq_cnt = 1; 1881 pdata->txq_cnt = 1; 1882 pdata->cq_cnt = 1; 1883 break; 1884 default: 1885 pdata->mac_ops = &xgene_xgmac_ops; 1886 pdata->port_ops = &xgene_xgport_ops; 1887 pdata->cle_ops = &xgene_cle3in_ops; 1888 pdata->rm = RM0; 1889 if (!pdata->rxq_cnt) { 1890 pdata->rxq_cnt = XGENE_NUM_RX_RING; 1891 pdata->txq_cnt = XGENE_NUM_TX_RING; 1892 pdata->cq_cnt = XGENE_NUM_TXC_RING; 1893 } 1894 break; 1895 } 1896 1897 if (pdata->enet_id == XGENE_ENET1) { 1898 switch (pdata->port_id) { 1899 case 0: 1900 if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) { 1901 pdata->cpu_bufnum = X2_START_CPU_BUFNUM_0; 1902 pdata->eth_bufnum = X2_START_ETH_BUFNUM_0; 1903 pdata->bp_bufnum = X2_START_BP_BUFNUM_0; 1904 pdata->ring_num = START_RING_NUM_0; 1905 } else { 1906 pdata->cpu_bufnum = START_CPU_BUFNUM_0; 1907 pdata->eth_bufnum = START_ETH_BUFNUM_0; 1908 pdata->bp_bufnum = START_BP_BUFNUM_0; 1909 pdata->ring_num = START_RING_NUM_0; 1910 } 1911 break; 1912 case 1: 1913 if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) { 1914 pdata->cpu_bufnum = XG_START_CPU_BUFNUM_1; 1915 pdata->eth_bufnum = XG_START_ETH_BUFNUM_1; 1916 pdata->bp_bufnum = XG_START_BP_BUFNUM_1; 1917 pdata->ring_num = XG_START_RING_NUM_1; 1918 } else { 1919 pdata->cpu_bufnum = START_CPU_BUFNUM_1; 1920 pdata->eth_bufnum = START_ETH_BUFNUM_1; 1921 pdata->bp_bufnum = START_BP_BUFNUM_1; 1922 pdata->ring_num = START_RING_NUM_1; 1923 } 1924 break; 1925 default: 1926 break; 1927 } 1928 pdata->ring_ops = &xgene_ring1_ops; 1929 } else { 1930 switch (pdata->port_id) { 1931 case 0: 1932 pdata->cpu_bufnum = X2_START_CPU_BUFNUM_0; 1933 pdata->eth_bufnum = X2_START_ETH_BUFNUM_0; 1934 pdata->bp_bufnum = X2_START_BP_BUFNUM_0; 1935 pdata->ring_num = X2_START_RING_NUM_0; 1936 break; 1937 case 1: 1938 pdata->cpu_bufnum = X2_START_CPU_BUFNUM_1; 1939 pdata->eth_bufnum = X2_START_ETH_BUFNUM_1; 1940 pdata->bp_bufnum = X2_START_BP_BUFNUM_1; 1941 pdata->ring_num = X2_START_RING_NUM_1; 1942 break; 1943 default: 1944 break; 1945 } 1946 pdata->rm = RM0; 1947 pdata->ring_ops = &xgene_ring2_ops; 1948 } 1949 } 1950 1951 static void xgene_enet_napi_add(struct xgene_enet_pdata *pdata) 1952 { 1953 struct napi_struct *napi; 1954 int i; 1955 1956 for (i = 0; i < pdata->rxq_cnt; i++) { 1957 napi = &pdata->rx_ring[i]->napi; 1958 netif_napi_add(pdata->ndev, napi, xgene_enet_napi, 1959 NAPI_POLL_WEIGHT); 1960 } 1961 1962 for (i = 0; i < pdata->cq_cnt; i++) { 1963 napi = &pdata->tx_ring[i]->cp_ring->napi; 1964 netif_napi_add(pdata->ndev, napi, xgene_enet_napi, 1965 NAPI_POLL_WEIGHT); 1966 } 1967 } 1968 1969 static int xgene_enet_probe(struct platform_device *pdev) 1970 { 1971 struct net_device *ndev; 1972 struct xgene_enet_pdata *pdata; 1973 struct device *dev = &pdev->dev; 1974 void (*link_state)(struct work_struct *); 1975 const struct of_device_id *of_id; 1976 int ret; 1977 1978 ndev = alloc_etherdev_mqs(sizeof(struct xgene_enet_pdata), 1979 XGENE_NUM_RX_RING, XGENE_NUM_TX_RING); 1980 if (!ndev) 1981 return -ENOMEM; 1982 1983 pdata = netdev_priv(ndev); 1984 1985 pdata->pdev = pdev; 1986 pdata->ndev = ndev; 1987 SET_NETDEV_DEV(ndev, dev); 1988 platform_set_drvdata(pdev, pdata); 1989 ndev->netdev_ops = &xgene_ndev_ops; 1990 xgene_enet_set_ethtool_ops(ndev); 1991 ndev->features |= NETIF_F_IP_CSUM | 1992 NETIF_F_GSO | 1993 NETIF_F_GRO | 1994 NETIF_F_SG; 1995 1996 of_id = of_match_device(xgene_enet_of_match, &pdev->dev); 1997 if (of_id) { 1998 pdata->enet_id = (enum xgene_enet_id)of_id->data; 1999 } 2000 #ifdef CONFIG_ACPI 2001 else { 2002 const struct acpi_device_id *acpi_id; 2003 2004 acpi_id = acpi_match_device(xgene_enet_acpi_match, &pdev->dev); 2005 if (acpi_id) 2006 pdata->enet_id = (enum xgene_enet_id) acpi_id->driver_data; 2007 } 2008 #endif 2009 if (!pdata->enet_id) { 2010 ret = -ENODEV; 2011 goto err; 2012 } 2013 2014 ret = xgene_enet_get_resources(pdata); 2015 if (ret) 2016 goto err; 2017 2018 xgene_enet_setup_ops(pdata); 2019 2020 if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) { 2021 ndev->features |= NETIF_F_TSO; 2022 spin_lock_init(&pdata->mss_lock); 2023 } 2024 ndev->hw_features = ndev->features; 2025 2026 ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(64)); 2027 if (ret) { 2028 netdev_err(ndev, "No usable DMA configuration\n"); 2029 goto err; 2030 } 2031 2032 ret = xgene_enet_init_hw(pdata); 2033 if (ret) 2034 goto err; 2035 2036 link_state = pdata->mac_ops->link_state; 2037 if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) { 2038 INIT_DELAYED_WORK(&pdata->link_work, link_state); 2039 } else if (!pdata->mdio_driver) { 2040 if (pdata->phy_mode == PHY_INTERFACE_MODE_RGMII) 2041 ret = xgene_enet_mdio_config(pdata); 2042 else 2043 INIT_DELAYED_WORK(&pdata->link_work, link_state); 2044 2045 if (ret) 2046 goto err1; 2047 } 2048 2049 xgene_enet_napi_add(pdata); 2050 ret = register_netdev(ndev); 2051 if (ret) { 2052 netdev_err(ndev, "Failed to register netdev\n"); 2053 goto err2; 2054 } 2055 2056 return 0; 2057 2058 err2: 2059 /* 2060 * If necessary, free_netdev() will call netif_napi_del() and undo 2061 * the effects of xgene_enet_napi_add()'s calls to netif_napi_add(). 2062 */ 2063 2064 if (pdata->mdio_driver) 2065 xgene_enet_phy_disconnect(pdata); 2066 else if (pdata->phy_mode == PHY_INTERFACE_MODE_RGMII) 2067 xgene_enet_mdio_remove(pdata); 2068 err1: 2069 xgene_enet_delete_desc_rings(pdata); 2070 err: 2071 free_netdev(ndev); 2072 return ret; 2073 } 2074 2075 static int xgene_enet_remove(struct platform_device *pdev) 2076 { 2077 struct xgene_enet_pdata *pdata; 2078 struct net_device *ndev; 2079 2080 pdata = platform_get_drvdata(pdev); 2081 ndev = pdata->ndev; 2082 2083 rtnl_lock(); 2084 if (netif_running(ndev)) 2085 dev_close(ndev); 2086 rtnl_unlock(); 2087 2088 if (pdata->mdio_driver) 2089 xgene_enet_phy_disconnect(pdata); 2090 else if (pdata->phy_mode == PHY_INTERFACE_MODE_RGMII) 2091 xgene_enet_mdio_remove(pdata); 2092 2093 unregister_netdev(ndev); 2094 pdata->port_ops->shutdown(pdata); 2095 xgene_enet_delete_desc_rings(pdata); 2096 free_netdev(ndev); 2097 2098 return 0; 2099 } 2100 2101 static void xgene_enet_shutdown(struct platform_device *pdev) 2102 { 2103 struct xgene_enet_pdata *pdata; 2104 2105 pdata = platform_get_drvdata(pdev); 2106 if (!pdata) 2107 return; 2108 2109 if (!pdata->ndev) 2110 return; 2111 2112 xgene_enet_remove(pdev); 2113 } 2114 2115 #ifdef CONFIG_ACPI 2116 static const struct acpi_device_id xgene_enet_acpi_match[] = { 2117 { "APMC0D05", XGENE_ENET1}, 2118 { "APMC0D30", XGENE_ENET1}, 2119 { "APMC0D31", XGENE_ENET1}, 2120 { "APMC0D3F", XGENE_ENET1}, 2121 { "APMC0D26", XGENE_ENET2}, 2122 { "APMC0D25", XGENE_ENET2}, 2123 { } 2124 }; 2125 MODULE_DEVICE_TABLE(acpi, xgene_enet_acpi_match); 2126 #endif 2127 2128 #ifdef CONFIG_OF 2129 static const struct of_device_id xgene_enet_of_match[] = { 2130 {.compatible = "apm,xgene-enet", .data = (void *)XGENE_ENET1}, 2131 {.compatible = "apm,xgene1-sgenet", .data = (void *)XGENE_ENET1}, 2132 {.compatible = "apm,xgene1-xgenet", .data = (void *)XGENE_ENET1}, 2133 {.compatible = "apm,xgene2-sgenet", .data = (void *)XGENE_ENET2}, 2134 {.compatible = "apm,xgene2-xgenet", .data = (void *)XGENE_ENET2}, 2135 {}, 2136 }; 2137 2138 MODULE_DEVICE_TABLE(of, xgene_enet_of_match); 2139 #endif 2140 2141 static struct platform_driver xgene_enet_driver = { 2142 .driver = { 2143 .name = "xgene-enet", 2144 .of_match_table = of_match_ptr(xgene_enet_of_match), 2145 .acpi_match_table = ACPI_PTR(xgene_enet_acpi_match), 2146 }, 2147 .probe = xgene_enet_probe, 2148 .remove = xgene_enet_remove, 2149 .shutdown = xgene_enet_shutdown, 2150 }; 2151 2152 module_platform_driver(xgene_enet_driver); 2153 2154 MODULE_DESCRIPTION("APM X-Gene SoC Ethernet driver"); 2155 MODULE_VERSION(XGENE_DRV_VERSION); 2156 MODULE_AUTHOR("Iyappan Subramanian <isubramanian@apm.com>"); 2157 MODULE_AUTHOR("Keyur Chudgar <kchudgar@apm.com>"); 2158 MODULE_LICENSE("GPL"); 2159