1 /* Applied Micro X-Gene SoC Ethernet Driver 2 * 3 * Copyright (c) 2014, Applied Micro Circuits Corporation 4 * Authors: Iyappan Subramanian <isubramanian@apm.com> 5 * Ravi Patel <rapatel@apm.com> 6 * Keyur Chudgar <kchudgar@apm.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program. If not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include "xgene_enet_main.h" 23 #include "xgene_enet_hw.h" 24 #include "xgene_enet_sgmac.h" 25 #include "xgene_enet_xgmac.h" 26 27 #define RES_ENET_CSR 0 28 #define RES_RING_CSR 1 29 #define RES_RING_CMD 2 30 31 static const struct of_device_id xgene_enet_of_match[]; 32 static const struct acpi_device_id xgene_enet_acpi_match[]; 33 34 static void xgene_enet_init_bufpool(struct xgene_enet_desc_ring *buf_pool) 35 { 36 struct xgene_enet_raw_desc16 *raw_desc; 37 int i; 38 39 for (i = 0; i < buf_pool->slots; i++) { 40 raw_desc = &buf_pool->raw_desc16[i]; 41 42 /* Hardware expects descriptor in little endian format */ 43 raw_desc->m0 = cpu_to_le64(i | 44 SET_VAL(FPQNUM, buf_pool->dst_ring_num) | 45 SET_VAL(STASH, 3)); 46 } 47 } 48 49 static int xgene_enet_refill_bufpool(struct xgene_enet_desc_ring *buf_pool, 50 u32 nbuf) 51 { 52 struct sk_buff *skb; 53 struct xgene_enet_raw_desc16 *raw_desc; 54 struct xgene_enet_pdata *pdata; 55 struct net_device *ndev; 56 struct device *dev; 57 dma_addr_t dma_addr; 58 u32 tail = buf_pool->tail; 59 u32 slots = buf_pool->slots - 1; 60 u16 bufdatalen, len; 61 int i; 62 63 ndev = buf_pool->ndev; 64 dev = ndev_to_dev(buf_pool->ndev); 65 pdata = netdev_priv(ndev); 66 bufdatalen = BUF_LEN_CODE_2K | (SKB_BUFFER_SIZE & GENMASK(11, 0)); 67 len = XGENE_ENET_MAX_MTU; 68 69 for (i = 0; i < nbuf; i++) { 70 raw_desc = &buf_pool->raw_desc16[tail]; 71 72 skb = netdev_alloc_skb_ip_align(ndev, len); 73 if (unlikely(!skb)) 74 return -ENOMEM; 75 buf_pool->rx_skb[tail] = skb; 76 77 dma_addr = dma_map_single(dev, skb->data, len, DMA_FROM_DEVICE); 78 if (dma_mapping_error(dev, dma_addr)) { 79 netdev_err(ndev, "DMA mapping error\n"); 80 dev_kfree_skb_any(skb); 81 return -EINVAL; 82 } 83 84 raw_desc->m1 = cpu_to_le64(SET_VAL(DATAADDR, dma_addr) | 85 SET_VAL(BUFDATALEN, bufdatalen) | 86 SET_BIT(COHERENT)); 87 tail = (tail + 1) & slots; 88 } 89 90 pdata->ring_ops->wr_cmd(buf_pool, nbuf); 91 buf_pool->tail = tail; 92 93 return 0; 94 } 95 96 static u16 xgene_enet_dst_ring_num(struct xgene_enet_desc_ring *ring) 97 { 98 struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev); 99 100 return ((u16)pdata->rm << 10) | ring->num; 101 } 102 103 static u8 xgene_enet_hdr_len(const void *data) 104 { 105 const struct ethhdr *eth = data; 106 107 return (eth->h_proto == htons(ETH_P_8021Q)) ? VLAN_ETH_HLEN : ETH_HLEN; 108 } 109 110 static void xgene_enet_delete_bufpool(struct xgene_enet_desc_ring *buf_pool) 111 { 112 struct xgene_enet_pdata *pdata = netdev_priv(buf_pool->ndev); 113 struct xgene_enet_raw_desc16 *raw_desc; 114 u32 slots = buf_pool->slots - 1; 115 u32 tail = buf_pool->tail; 116 u32 userinfo; 117 int i, len; 118 119 len = pdata->ring_ops->len(buf_pool); 120 for (i = 0; i < len; i++) { 121 tail = (tail - 1) & slots; 122 raw_desc = &buf_pool->raw_desc16[tail]; 123 124 /* Hardware stores descriptor in little endian format */ 125 userinfo = GET_VAL(USERINFO, le64_to_cpu(raw_desc->m0)); 126 dev_kfree_skb_any(buf_pool->rx_skb[userinfo]); 127 } 128 129 pdata->ring_ops->wr_cmd(buf_pool, -len); 130 buf_pool->tail = tail; 131 } 132 133 static irqreturn_t xgene_enet_rx_irq(const int irq, void *data) 134 { 135 struct xgene_enet_desc_ring *rx_ring = data; 136 137 if (napi_schedule_prep(&rx_ring->napi)) { 138 disable_irq_nosync(irq); 139 __napi_schedule(&rx_ring->napi); 140 } 141 142 return IRQ_HANDLED; 143 } 144 145 static int xgene_enet_tx_completion(struct xgene_enet_desc_ring *cp_ring, 146 struct xgene_enet_raw_desc *raw_desc) 147 { 148 struct sk_buff *skb; 149 struct device *dev; 150 skb_frag_t *frag; 151 dma_addr_t *frag_dma_addr; 152 u16 skb_index; 153 u8 status; 154 int i, ret = 0; 155 156 skb_index = GET_VAL(USERINFO, le64_to_cpu(raw_desc->m0)); 157 skb = cp_ring->cp_skb[skb_index]; 158 frag_dma_addr = &cp_ring->frag_dma_addr[skb_index * MAX_SKB_FRAGS]; 159 160 dev = ndev_to_dev(cp_ring->ndev); 161 dma_unmap_single(dev, GET_VAL(DATAADDR, le64_to_cpu(raw_desc->m1)), 162 skb_headlen(skb), 163 DMA_TO_DEVICE); 164 165 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 166 frag = &skb_shinfo(skb)->frags[i]; 167 dma_unmap_page(dev, frag_dma_addr[i], skb_frag_size(frag), 168 DMA_TO_DEVICE); 169 } 170 171 /* Checking for error */ 172 status = GET_VAL(LERR, le64_to_cpu(raw_desc->m0)); 173 if (unlikely(status > 2)) { 174 xgene_enet_parse_error(cp_ring, netdev_priv(cp_ring->ndev), 175 status); 176 ret = -EIO; 177 } 178 179 if (likely(skb)) { 180 dev_kfree_skb_any(skb); 181 } else { 182 netdev_err(cp_ring->ndev, "completion skb is NULL\n"); 183 ret = -EIO; 184 } 185 186 return ret; 187 } 188 189 static u64 xgene_enet_work_msg(struct sk_buff *skb) 190 { 191 struct net_device *ndev = skb->dev; 192 struct xgene_enet_pdata *pdata = netdev_priv(ndev); 193 struct iphdr *iph; 194 u8 l3hlen = 0, l4hlen = 0; 195 u8 ethhdr, proto = 0, csum_enable = 0; 196 u64 hopinfo = 0; 197 u32 hdr_len, mss = 0; 198 u32 i, len, nr_frags; 199 200 ethhdr = xgene_enet_hdr_len(skb->data); 201 202 if (unlikely(skb->protocol != htons(ETH_P_IP)) && 203 unlikely(skb->protocol != htons(ETH_P_8021Q))) 204 goto out; 205 206 if (unlikely(!(skb->dev->features & NETIF_F_IP_CSUM))) 207 goto out; 208 209 iph = ip_hdr(skb); 210 if (unlikely(ip_is_fragment(iph))) 211 goto out; 212 213 if (likely(iph->protocol == IPPROTO_TCP)) { 214 l4hlen = tcp_hdrlen(skb) >> 2; 215 csum_enable = 1; 216 proto = TSO_IPPROTO_TCP; 217 if (ndev->features & NETIF_F_TSO) { 218 hdr_len = ethhdr + ip_hdrlen(skb) + tcp_hdrlen(skb); 219 mss = skb_shinfo(skb)->gso_size; 220 221 if (skb_is_nonlinear(skb)) { 222 len = skb_headlen(skb); 223 nr_frags = skb_shinfo(skb)->nr_frags; 224 225 for (i = 0; i < 2 && i < nr_frags; i++) 226 len += skb_shinfo(skb)->frags[i].size; 227 228 /* HW requires header must reside in 3 buffer */ 229 if (unlikely(hdr_len > len)) { 230 if (skb_linearize(skb)) 231 return 0; 232 } 233 } 234 235 if (!mss || ((skb->len - hdr_len) <= mss)) 236 goto out; 237 238 if (mss != pdata->mss) { 239 pdata->mss = mss; 240 pdata->mac_ops->set_mss(pdata); 241 } 242 hopinfo |= SET_BIT(ET); 243 } 244 } else if (iph->protocol == IPPROTO_UDP) { 245 l4hlen = UDP_HDR_SIZE; 246 csum_enable = 1; 247 } 248 out: 249 l3hlen = ip_hdrlen(skb) >> 2; 250 hopinfo |= SET_VAL(TCPHDR, l4hlen) | 251 SET_VAL(IPHDR, l3hlen) | 252 SET_VAL(ETHHDR, ethhdr) | 253 SET_VAL(EC, csum_enable) | 254 SET_VAL(IS, proto) | 255 SET_BIT(IC) | 256 SET_BIT(TYPE_ETH_WORK_MESSAGE); 257 258 return hopinfo; 259 } 260 261 static u16 xgene_enet_encode_len(u16 len) 262 { 263 return (len == BUFLEN_16K) ? 0 : len; 264 } 265 266 static void xgene_set_addr_len(__le64 *desc, u32 idx, dma_addr_t addr, u32 len) 267 { 268 desc[idx ^ 1] = cpu_to_le64(SET_VAL(DATAADDR, addr) | 269 SET_VAL(BUFDATALEN, len)); 270 } 271 272 static __le64 *xgene_enet_get_exp_bufs(struct xgene_enet_desc_ring *ring) 273 { 274 __le64 *exp_bufs; 275 276 exp_bufs = &ring->exp_bufs[ring->exp_buf_tail * MAX_EXP_BUFFS]; 277 memset(exp_bufs, 0, sizeof(__le64) * MAX_EXP_BUFFS); 278 ring->exp_buf_tail = (ring->exp_buf_tail + 1) & ((ring->slots / 2) - 1); 279 280 return exp_bufs; 281 } 282 283 static dma_addr_t *xgene_get_frag_dma_array(struct xgene_enet_desc_ring *ring) 284 { 285 return &ring->cp_ring->frag_dma_addr[ring->tail * MAX_SKB_FRAGS]; 286 } 287 288 static int xgene_enet_setup_tx_desc(struct xgene_enet_desc_ring *tx_ring, 289 struct sk_buff *skb) 290 { 291 struct device *dev = ndev_to_dev(tx_ring->ndev); 292 struct xgene_enet_pdata *pdata = netdev_priv(tx_ring->ndev); 293 struct xgene_enet_raw_desc *raw_desc; 294 __le64 *exp_desc = NULL, *exp_bufs = NULL; 295 dma_addr_t dma_addr, pbuf_addr, *frag_dma_addr; 296 skb_frag_t *frag; 297 u16 tail = tx_ring->tail; 298 u64 hopinfo; 299 u32 len, hw_len; 300 u8 ll = 0, nv = 0, idx = 0; 301 bool split = false; 302 u32 size, offset, ell_bytes = 0; 303 u32 i, fidx, nr_frags, count = 1; 304 305 raw_desc = &tx_ring->raw_desc[tail]; 306 tail = (tail + 1) & (tx_ring->slots - 1); 307 memset(raw_desc, 0, sizeof(struct xgene_enet_raw_desc)); 308 309 hopinfo = xgene_enet_work_msg(skb); 310 if (!hopinfo) 311 return -EINVAL; 312 raw_desc->m3 = cpu_to_le64(SET_VAL(HENQNUM, tx_ring->dst_ring_num) | 313 hopinfo); 314 315 len = skb_headlen(skb); 316 hw_len = xgene_enet_encode_len(len); 317 318 dma_addr = dma_map_single(dev, skb->data, len, DMA_TO_DEVICE); 319 if (dma_mapping_error(dev, dma_addr)) { 320 netdev_err(tx_ring->ndev, "DMA mapping error\n"); 321 return -EINVAL; 322 } 323 324 /* Hardware expects descriptor in little endian format */ 325 raw_desc->m1 = cpu_to_le64(SET_VAL(DATAADDR, dma_addr) | 326 SET_VAL(BUFDATALEN, hw_len) | 327 SET_BIT(COHERENT)); 328 329 if (!skb_is_nonlinear(skb)) 330 goto out; 331 332 /* scatter gather */ 333 nv = 1; 334 exp_desc = (void *)&tx_ring->raw_desc[tail]; 335 tail = (tail + 1) & (tx_ring->slots - 1); 336 memset(exp_desc, 0, sizeof(struct xgene_enet_raw_desc)); 337 338 nr_frags = skb_shinfo(skb)->nr_frags; 339 for (i = nr_frags; i < 4 ; i++) 340 exp_desc[i ^ 1] = cpu_to_le64(LAST_BUFFER); 341 342 frag_dma_addr = xgene_get_frag_dma_array(tx_ring); 343 344 for (i = 0, fidx = 0; split || (fidx < nr_frags); i++) { 345 if (!split) { 346 frag = &skb_shinfo(skb)->frags[fidx]; 347 size = skb_frag_size(frag); 348 offset = 0; 349 350 pbuf_addr = skb_frag_dma_map(dev, frag, 0, size, 351 DMA_TO_DEVICE); 352 if (dma_mapping_error(dev, pbuf_addr)) 353 return -EINVAL; 354 355 frag_dma_addr[fidx] = pbuf_addr; 356 fidx++; 357 358 if (size > BUFLEN_16K) 359 split = true; 360 } 361 362 if (size > BUFLEN_16K) { 363 len = BUFLEN_16K; 364 size -= BUFLEN_16K; 365 } else { 366 len = size; 367 split = false; 368 } 369 370 dma_addr = pbuf_addr + offset; 371 hw_len = xgene_enet_encode_len(len); 372 373 switch (i) { 374 case 0: 375 case 1: 376 case 2: 377 xgene_set_addr_len(exp_desc, i, dma_addr, hw_len); 378 break; 379 case 3: 380 if (split || (fidx != nr_frags)) { 381 exp_bufs = xgene_enet_get_exp_bufs(tx_ring); 382 xgene_set_addr_len(exp_bufs, idx, dma_addr, 383 hw_len); 384 idx++; 385 ell_bytes += len; 386 } else { 387 xgene_set_addr_len(exp_desc, i, dma_addr, 388 hw_len); 389 } 390 break; 391 default: 392 xgene_set_addr_len(exp_bufs, idx, dma_addr, hw_len); 393 idx++; 394 ell_bytes += len; 395 break; 396 } 397 398 if (split) 399 offset += BUFLEN_16K; 400 } 401 count++; 402 403 if (idx) { 404 ll = 1; 405 dma_addr = dma_map_single(dev, exp_bufs, 406 sizeof(u64) * MAX_EXP_BUFFS, 407 DMA_TO_DEVICE); 408 if (dma_mapping_error(dev, dma_addr)) { 409 dev_kfree_skb_any(skb); 410 return -EINVAL; 411 } 412 i = ell_bytes >> LL_BYTES_LSB_LEN; 413 exp_desc[2] = cpu_to_le64(SET_VAL(DATAADDR, dma_addr) | 414 SET_VAL(LL_BYTES_MSB, i) | 415 SET_VAL(LL_LEN, idx)); 416 raw_desc->m2 = cpu_to_le64(SET_VAL(LL_BYTES_LSB, ell_bytes)); 417 } 418 419 out: 420 raw_desc->m0 = cpu_to_le64(SET_VAL(LL, ll) | SET_VAL(NV, nv) | 421 SET_VAL(USERINFO, tx_ring->tail)); 422 tx_ring->cp_ring->cp_skb[tx_ring->tail] = skb; 423 pdata->tx_level += count; 424 tx_ring->tail = tail; 425 426 return count; 427 } 428 429 static netdev_tx_t xgene_enet_start_xmit(struct sk_buff *skb, 430 struct net_device *ndev) 431 { 432 struct xgene_enet_pdata *pdata = netdev_priv(ndev); 433 struct xgene_enet_desc_ring *tx_ring = pdata->tx_ring; 434 u32 tx_level = pdata->tx_level; 435 int count; 436 437 if (tx_level < pdata->txc_level) 438 tx_level += ((typeof(pdata->tx_level))~0U); 439 440 if ((tx_level - pdata->txc_level) > pdata->tx_qcnt_hi) { 441 netif_stop_queue(ndev); 442 return NETDEV_TX_BUSY; 443 } 444 445 if (skb_padto(skb, XGENE_MIN_ENET_FRAME_SIZE)) 446 return NETDEV_TX_OK; 447 448 count = xgene_enet_setup_tx_desc(tx_ring, skb); 449 if (count <= 0) { 450 dev_kfree_skb_any(skb); 451 return NETDEV_TX_OK; 452 } 453 454 skb_tx_timestamp(skb); 455 456 pdata->stats.tx_packets++; 457 pdata->stats.tx_bytes += skb->len; 458 459 pdata->ring_ops->wr_cmd(tx_ring, count); 460 return NETDEV_TX_OK; 461 } 462 463 static void xgene_enet_skip_csum(struct sk_buff *skb) 464 { 465 struct iphdr *iph = ip_hdr(skb); 466 467 if (!ip_is_fragment(iph) || 468 (iph->protocol != IPPROTO_TCP && iph->protocol != IPPROTO_UDP)) { 469 skb->ip_summed = CHECKSUM_UNNECESSARY; 470 } 471 } 472 473 static int xgene_enet_rx_frame(struct xgene_enet_desc_ring *rx_ring, 474 struct xgene_enet_raw_desc *raw_desc) 475 { 476 struct net_device *ndev; 477 struct xgene_enet_pdata *pdata; 478 struct device *dev; 479 struct xgene_enet_desc_ring *buf_pool; 480 u32 datalen, skb_index; 481 struct sk_buff *skb; 482 u8 status; 483 int ret = 0; 484 485 ndev = rx_ring->ndev; 486 pdata = netdev_priv(ndev); 487 dev = ndev_to_dev(rx_ring->ndev); 488 buf_pool = rx_ring->buf_pool; 489 490 dma_unmap_single(dev, GET_VAL(DATAADDR, le64_to_cpu(raw_desc->m1)), 491 XGENE_ENET_MAX_MTU, DMA_FROM_DEVICE); 492 skb_index = GET_VAL(USERINFO, le64_to_cpu(raw_desc->m0)); 493 skb = buf_pool->rx_skb[skb_index]; 494 495 /* checking for error */ 496 status = GET_VAL(LERR, le64_to_cpu(raw_desc->m0)); 497 if (unlikely(status > 2)) { 498 dev_kfree_skb_any(skb); 499 xgene_enet_parse_error(rx_ring, netdev_priv(rx_ring->ndev), 500 status); 501 pdata->stats.rx_dropped++; 502 ret = -EIO; 503 goto out; 504 } 505 506 /* strip off CRC as HW isn't doing this */ 507 datalen = GET_VAL(BUFDATALEN, le64_to_cpu(raw_desc->m1)); 508 datalen = (datalen & DATALEN_MASK) - 4; 509 prefetch(skb->data - NET_IP_ALIGN); 510 skb_put(skb, datalen); 511 512 skb_checksum_none_assert(skb); 513 skb->protocol = eth_type_trans(skb, ndev); 514 if (likely((ndev->features & NETIF_F_IP_CSUM) && 515 skb->protocol == htons(ETH_P_IP))) { 516 xgene_enet_skip_csum(skb); 517 } 518 519 pdata->stats.rx_packets++; 520 pdata->stats.rx_bytes += datalen; 521 napi_gro_receive(&rx_ring->napi, skb); 522 out: 523 if (--rx_ring->nbufpool == 0) { 524 ret = xgene_enet_refill_bufpool(buf_pool, NUM_BUFPOOL); 525 rx_ring->nbufpool = NUM_BUFPOOL; 526 } 527 528 return ret; 529 } 530 531 static bool is_rx_desc(struct xgene_enet_raw_desc *raw_desc) 532 { 533 return GET_VAL(FPQNUM, le64_to_cpu(raw_desc->m0)) ? true : false; 534 } 535 536 static int xgene_enet_process_ring(struct xgene_enet_desc_ring *ring, 537 int budget) 538 { 539 struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev); 540 struct xgene_enet_raw_desc *raw_desc, *exp_desc; 541 u16 head = ring->head; 542 u16 slots = ring->slots - 1; 543 int ret, desc_count, count = 0, processed = 0; 544 bool is_completion; 545 546 do { 547 raw_desc = &ring->raw_desc[head]; 548 desc_count = 0; 549 is_completion = false; 550 exp_desc = NULL; 551 if (unlikely(xgene_enet_is_desc_slot_empty(raw_desc))) 552 break; 553 554 /* read fpqnum field after dataaddr field */ 555 dma_rmb(); 556 if (GET_BIT(NV, le64_to_cpu(raw_desc->m0))) { 557 head = (head + 1) & slots; 558 exp_desc = &ring->raw_desc[head]; 559 560 if (unlikely(xgene_enet_is_desc_slot_empty(exp_desc))) { 561 head = (head - 1) & slots; 562 break; 563 } 564 dma_rmb(); 565 count++; 566 desc_count++; 567 } 568 if (is_rx_desc(raw_desc)) { 569 ret = xgene_enet_rx_frame(ring, raw_desc); 570 } else { 571 ret = xgene_enet_tx_completion(ring, raw_desc); 572 is_completion = true; 573 } 574 xgene_enet_mark_desc_slot_empty(raw_desc); 575 if (exp_desc) 576 xgene_enet_mark_desc_slot_empty(exp_desc); 577 578 head = (head + 1) & slots; 579 count++; 580 desc_count++; 581 processed++; 582 if (is_completion) 583 pdata->txc_level += desc_count; 584 585 if (ret) 586 break; 587 } while (--budget); 588 589 if (likely(count)) { 590 pdata->ring_ops->wr_cmd(ring, -count); 591 ring->head = head; 592 593 if (netif_queue_stopped(ring->ndev)) 594 netif_start_queue(ring->ndev); 595 } 596 597 return processed; 598 } 599 600 static int xgene_enet_napi(struct napi_struct *napi, const int budget) 601 { 602 struct xgene_enet_desc_ring *ring; 603 int processed; 604 605 ring = container_of(napi, struct xgene_enet_desc_ring, napi); 606 processed = xgene_enet_process_ring(ring, budget); 607 608 if (processed != budget) { 609 napi_complete(napi); 610 enable_irq(ring->irq); 611 } 612 613 return processed; 614 } 615 616 static void xgene_enet_timeout(struct net_device *ndev) 617 { 618 struct xgene_enet_pdata *pdata = netdev_priv(ndev); 619 620 pdata->mac_ops->reset(pdata); 621 } 622 623 static int xgene_enet_register_irq(struct net_device *ndev) 624 { 625 struct xgene_enet_pdata *pdata = netdev_priv(ndev); 626 struct device *dev = ndev_to_dev(ndev); 627 struct xgene_enet_desc_ring *ring; 628 int ret; 629 630 ring = pdata->rx_ring; 631 ret = devm_request_irq(dev, ring->irq, xgene_enet_rx_irq, 632 IRQF_SHARED, ring->irq_name, ring); 633 if (ret) 634 netdev_err(ndev, "Failed to request irq %s\n", ring->irq_name); 635 636 if (pdata->cq_cnt) { 637 ring = pdata->tx_ring->cp_ring; 638 ret = devm_request_irq(dev, ring->irq, xgene_enet_rx_irq, 639 IRQF_SHARED, ring->irq_name, ring); 640 if (ret) { 641 netdev_err(ndev, "Failed to request irq %s\n", 642 ring->irq_name); 643 } 644 } 645 646 return ret; 647 } 648 649 static void xgene_enet_free_irq(struct net_device *ndev) 650 { 651 struct xgene_enet_pdata *pdata; 652 struct device *dev; 653 654 pdata = netdev_priv(ndev); 655 dev = ndev_to_dev(ndev); 656 devm_free_irq(dev, pdata->rx_ring->irq, pdata->rx_ring); 657 658 if (pdata->cq_cnt) { 659 devm_free_irq(dev, pdata->tx_ring->cp_ring->irq, 660 pdata->tx_ring->cp_ring); 661 } 662 } 663 664 static void xgene_enet_napi_enable(struct xgene_enet_pdata *pdata) 665 { 666 struct napi_struct *napi; 667 668 napi = &pdata->rx_ring->napi; 669 napi_enable(napi); 670 671 if (pdata->cq_cnt) { 672 napi = &pdata->tx_ring->cp_ring->napi; 673 napi_enable(napi); 674 } 675 } 676 677 static void xgene_enet_napi_disable(struct xgene_enet_pdata *pdata) 678 { 679 struct napi_struct *napi; 680 681 napi = &pdata->rx_ring->napi; 682 napi_disable(napi); 683 684 if (pdata->cq_cnt) { 685 napi = &pdata->tx_ring->cp_ring->napi; 686 napi_disable(napi); 687 } 688 } 689 690 static int xgene_enet_open(struct net_device *ndev) 691 { 692 struct xgene_enet_pdata *pdata = netdev_priv(ndev); 693 struct xgene_mac_ops *mac_ops = pdata->mac_ops; 694 int ret; 695 696 mac_ops->tx_enable(pdata); 697 mac_ops->rx_enable(pdata); 698 699 xgene_enet_napi_enable(pdata); 700 ret = xgene_enet_register_irq(ndev); 701 if (ret) 702 return ret; 703 704 if (pdata->phy_mode == PHY_INTERFACE_MODE_RGMII) 705 phy_start(pdata->phy_dev); 706 else 707 schedule_delayed_work(&pdata->link_work, PHY_POLL_LINK_OFF); 708 709 netif_start_queue(ndev); 710 711 return ret; 712 } 713 714 static int xgene_enet_close(struct net_device *ndev) 715 { 716 struct xgene_enet_pdata *pdata = netdev_priv(ndev); 717 struct xgene_mac_ops *mac_ops = pdata->mac_ops; 718 719 netif_stop_queue(ndev); 720 721 if (pdata->phy_mode == PHY_INTERFACE_MODE_RGMII) 722 phy_stop(pdata->phy_dev); 723 else 724 cancel_delayed_work_sync(&pdata->link_work); 725 726 mac_ops->tx_disable(pdata); 727 mac_ops->rx_disable(pdata); 728 729 xgene_enet_free_irq(ndev); 730 xgene_enet_napi_disable(pdata); 731 xgene_enet_process_ring(pdata->rx_ring, -1); 732 733 return 0; 734 } 735 736 static void xgene_enet_delete_ring(struct xgene_enet_desc_ring *ring) 737 { 738 struct xgene_enet_pdata *pdata; 739 struct device *dev; 740 741 pdata = netdev_priv(ring->ndev); 742 dev = ndev_to_dev(ring->ndev); 743 744 pdata->ring_ops->clear(ring); 745 dma_free_coherent(dev, ring->size, ring->desc_addr, ring->dma); 746 } 747 748 static void xgene_enet_delete_desc_rings(struct xgene_enet_pdata *pdata) 749 { 750 struct xgene_enet_desc_ring *buf_pool; 751 752 if (pdata->tx_ring) { 753 xgene_enet_delete_ring(pdata->tx_ring); 754 pdata->tx_ring = NULL; 755 } 756 757 if (pdata->rx_ring) { 758 buf_pool = pdata->rx_ring->buf_pool; 759 xgene_enet_delete_bufpool(buf_pool); 760 xgene_enet_delete_ring(buf_pool); 761 xgene_enet_delete_ring(pdata->rx_ring); 762 pdata->rx_ring = NULL; 763 } 764 } 765 766 static int xgene_enet_get_ring_size(struct device *dev, 767 enum xgene_enet_ring_cfgsize cfgsize) 768 { 769 int size = -EINVAL; 770 771 switch (cfgsize) { 772 case RING_CFGSIZE_512B: 773 size = 0x200; 774 break; 775 case RING_CFGSIZE_2KB: 776 size = 0x800; 777 break; 778 case RING_CFGSIZE_16KB: 779 size = 0x4000; 780 break; 781 case RING_CFGSIZE_64KB: 782 size = 0x10000; 783 break; 784 case RING_CFGSIZE_512KB: 785 size = 0x80000; 786 break; 787 default: 788 dev_err(dev, "Unsupported cfg ring size %d\n", cfgsize); 789 break; 790 } 791 792 return size; 793 } 794 795 static void xgene_enet_free_desc_ring(struct xgene_enet_desc_ring *ring) 796 { 797 struct xgene_enet_pdata *pdata; 798 struct device *dev; 799 800 if (!ring) 801 return; 802 803 dev = ndev_to_dev(ring->ndev); 804 pdata = netdev_priv(ring->ndev); 805 806 if (ring->desc_addr) { 807 pdata->ring_ops->clear(ring); 808 dma_free_coherent(dev, ring->size, ring->desc_addr, ring->dma); 809 } 810 devm_kfree(dev, ring); 811 } 812 813 static void xgene_enet_free_desc_rings(struct xgene_enet_pdata *pdata) 814 { 815 struct device *dev = &pdata->pdev->dev; 816 struct xgene_enet_desc_ring *ring; 817 818 ring = pdata->tx_ring; 819 if (ring) { 820 if (ring->cp_ring && ring->cp_ring->cp_skb) 821 devm_kfree(dev, ring->cp_ring->cp_skb); 822 if (ring->cp_ring && pdata->cq_cnt) 823 xgene_enet_free_desc_ring(ring->cp_ring); 824 xgene_enet_free_desc_ring(ring); 825 } 826 827 ring = pdata->rx_ring; 828 if (ring) { 829 if (ring->buf_pool) { 830 if (ring->buf_pool->rx_skb) 831 devm_kfree(dev, ring->buf_pool->rx_skb); 832 xgene_enet_free_desc_ring(ring->buf_pool); 833 } 834 xgene_enet_free_desc_ring(ring); 835 } 836 } 837 838 static bool is_irq_mbox_required(struct xgene_enet_pdata *pdata, 839 struct xgene_enet_desc_ring *ring) 840 { 841 if ((pdata->enet_id == XGENE_ENET2) && 842 (xgene_enet_ring_owner(ring->id) == RING_OWNER_CPU)) { 843 return true; 844 } 845 846 return false; 847 } 848 849 static void __iomem *xgene_enet_ring_cmd_base(struct xgene_enet_pdata *pdata, 850 struct xgene_enet_desc_ring *ring) 851 { 852 u8 num_ring_id_shift = pdata->ring_ops->num_ring_id_shift; 853 854 return pdata->ring_cmd_addr + (ring->num << num_ring_id_shift); 855 } 856 857 static struct xgene_enet_desc_ring *xgene_enet_create_desc_ring( 858 struct net_device *ndev, u32 ring_num, 859 enum xgene_enet_ring_cfgsize cfgsize, u32 ring_id) 860 { 861 struct xgene_enet_desc_ring *ring; 862 struct xgene_enet_pdata *pdata = netdev_priv(ndev); 863 struct device *dev = ndev_to_dev(ndev); 864 int size; 865 866 size = xgene_enet_get_ring_size(dev, cfgsize); 867 if (size < 0) 868 return NULL; 869 870 ring = devm_kzalloc(dev, sizeof(struct xgene_enet_desc_ring), 871 GFP_KERNEL); 872 if (!ring) 873 return NULL; 874 875 ring->ndev = ndev; 876 ring->num = ring_num; 877 ring->cfgsize = cfgsize; 878 ring->id = ring_id; 879 880 ring->desc_addr = dma_zalloc_coherent(dev, size, &ring->dma, 881 GFP_KERNEL); 882 if (!ring->desc_addr) { 883 devm_kfree(dev, ring); 884 return NULL; 885 } 886 ring->size = size; 887 888 if (is_irq_mbox_required(pdata, ring)) { 889 ring->irq_mbox_addr = dma_zalloc_coherent(dev, INTR_MBOX_SIZE, 890 &ring->irq_mbox_dma, GFP_KERNEL); 891 if (!ring->irq_mbox_addr) { 892 dma_free_coherent(dev, size, ring->desc_addr, 893 ring->dma); 894 devm_kfree(dev, ring); 895 return NULL; 896 } 897 } 898 899 ring->cmd_base = xgene_enet_ring_cmd_base(pdata, ring); 900 ring->cmd = ring->cmd_base + INC_DEC_CMD_ADDR; 901 ring = pdata->ring_ops->setup(ring); 902 netdev_dbg(ndev, "ring info: num=%d size=%d id=%d slots=%d\n", 903 ring->num, ring->size, ring->id, ring->slots); 904 905 return ring; 906 } 907 908 static u16 xgene_enet_get_ring_id(enum xgene_ring_owner owner, u8 bufnum) 909 { 910 return (owner << 6) | (bufnum & GENMASK(5, 0)); 911 } 912 913 static enum xgene_ring_owner xgene_derive_ring_owner(struct xgene_enet_pdata *p) 914 { 915 enum xgene_ring_owner owner; 916 917 if (p->enet_id == XGENE_ENET1) { 918 switch (p->phy_mode) { 919 case PHY_INTERFACE_MODE_SGMII: 920 owner = RING_OWNER_ETH0; 921 break; 922 default: 923 owner = (!p->port_id) ? RING_OWNER_ETH0 : 924 RING_OWNER_ETH1; 925 break; 926 } 927 } else { 928 owner = (!p->port_id) ? RING_OWNER_ETH0 : RING_OWNER_ETH1; 929 } 930 931 return owner; 932 } 933 934 static int xgene_enet_create_desc_rings(struct net_device *ndev) 935 { 936 struct xgene_enet_pdata *pdata = netdev_priv(ndev); 937 struct device *dev = ndev_to_dev(ndev); 938 struct xgene_enet_desc_ring *rx_ring, *tx_ring, *cp_ring; 939 struct xgene_enet_desc_ring *buf_pool = NULL; 940 enum xgene_ring_owner owner; 941 dma_addr_t dma_exp_bufs; 942 u8 cpu_bufnum = pdata->cpu_bufnum; 943 u8 eth_bufnum = pdata->eth_bufnum; 944 u8 bp_bufnum = pdata->bp_bufnum; 945 u16 ring_num = pdata->ring_num; 946 u16 ring_id; 947 int ret, size; 948 949 /* allocate rx descriptor ring */ 950 owner = xgene_derive_ring_owner(pdata); 951 ring_id = xgene_enet_get_ring_id(RING_OWNER_CPU, cpu_bufnum++); 952 rx_ring = xgene_enet_create_desc_ring(ndev, ring_num++, 953 RING_CFGSIZE_16KB, ring_id); 954 if (!rx_ring) { 955 ret = -ENOMEM; 956 goto err; 957 } 958 959 /* allocate buffer pool for receiving packets */ 960 owner = xgene_derive_ring_owner(pdata); 961 ring_id = xgene_enet_get_ring_id(owner, bp_bufnum++); 962 buf_pool = xgene_enet_create_desc_ring(ndev, ring_num++, 963 RING_CFGSIZE_2KB, ring_id); 964 if (!buf_pool) { 965 ret = -ENOMEM; 966 goto err; 967 } 968 969 rx_ring->nbufpool = NUM_BUFPOOL; 970 rx_ring->buf_pool = buf_pool; 971 rx_ring->irq = pdata->rx_irq; 972 if (!pdata->cq_cnt) { 973 snprintf(rx_ring->irq_name, IRQ_ID_SIZE, "%s-rx-txc", 974 ndev->name); 975 } else { 976 snprintf(rx_ring->irq_name, IRQ_ID_SIZE, "%s-rx", ndev->name); 977 } 978 buf_pool->rx_skb = devm_kcalloc(dev, buf_pool->slots, 979 sizeof(struct sk_buff *), GFP_KERNEL); 980 if (!buf_pool->rx_skb) { 981 ret = -ENOMEM; 982 goto err; 983 } 984 985 buf_pool->dst_ring_num = xgene_enet_dst_ring_num(buf_pool); 986 rx_ring->buf_pool = buf_pool; 987 pdata->rx_ring = rx_ring; 988 989 /* allocate tx descriptor ring */ 990 owner = xgene_derive_ring_owner(pdata); 991 ring_id = xgene_enet_get_ring_id(owner, eth_bufnum++); 992 tx_ring = xgene_enet_create_desc_ring(ndev, ring_num++, 993 RING_CFGSIZE_16KB, ring_id); 994 if (!tx_ring) { 995 ret = -ENOMEM; 996 goto err; 997 } 998 999 size = (tx_ring->slots / 2) * sizeof(__le64) * MAX_EXP_BUFFS; 1000 tx_ring->exp_bufs = dma_zalloc_coherent(dev, size, &dma_exp_bufs, 1001 GFP_KERNEL); 1002 if (!tx_ring->exp_bufs) { 1003 ret = -ENOMEM; 1004 goto err; 1005 } 1006 1007 pdata->tx_ring = tx_ring; 1008 1009 if (!pdata->cq_cnt) { 1010 cp_ring = pdata->rx_ring; 1011 } else { 1012 /* allocate tx completion descriptor ring */ 1013 ring_id = xgene_enet_get_ring_id(RING_OWNER_CPU, cpu_bufnum++); 1014 cp_ring = xgene_enet_create_desc_ring(ndev, ring_num++, 1015 RING_CFGSIZE_16KB, 1016 ring_id); 1017 if (!cp_ring) { 1018 ret = -ENOMEM; 1019 goto err; 1020 } 1021 cp_ring->irq = pdata->txc_irq; 1022 snprintf(cp_ring->irq_name, IRQ_ID_SIZE, "%s-txc", ndev->name); 1023 } 1024 1025 cp_ring->cp_skb = devm_kcalloc(dev, tx_ring->slots, 1026 sizeof(struct sk_buff *), GFP_KERNEL); 1027 if (!cp_ring->cp_skb) { 1028 ret = -ENOMEM; 1029 goto err; 1030 } 1031 1032 size = sizeof(dma_addr_t) * MAX_SKB_FRAGS; 1033 cp_ring->frag_dma_addr = devm_kcalloc(dev, tx_ring->slots, 1034 size, GFP_KERNEL); 1035 if (!cp_ring->frag_dma_addr) { 1036 devm_kfree(dev, cp_ring->cp_skb); 1037 ret = -ENOMEM; 1038 goto err; 1039 } 1040 1041 pdata->tx_ring->cp_ring = cp_ring; 1042 pdata->tx_ring->dst_ring_num = xgene_enet_dst_ring_num(cp_ring); 1043 1044 pdata->tx_qcnt_hi = pdata->tx_ring->slots - 128; 1045 1046 return 0; 1047 1048 err: 1049 xgene_enet_free_desc_rings(pdata); 1050 return ret; 1051 } 1052 1053 static struct rtnl_link_stats64 *xgene_enet_get_stats64( 1054 struct net_device *ndev, 1055 struct rtnl_link_stats64 *storage) 1056 { 1057 struct xgene_enet_pdata *pdata = netdev_priv(ndev); 1058 struct rtnl_link_stats64 *stats = &pdata->stats; 1059 1060 stats->rx_errors += stats->rx_length_errors + 1061 stats->rx_crc_errors + 1062 stats->rx_frame_errors + 1063 stats->rx_fifo_errors; 1064 memcpy(storage, &pdata->stats, sizeof(struct rtnl_link_stats64)); 1065 1066 return storage; 1067 } 1068 1069 static int xgene_enet_set_mac_address(struct net_device *ndev, void *addr) 1070 { 1071 struct xgene_enet_pdata *pdata = netdev_priv(ndev); 1072 int ret; 1073 1074 ret = eth_mac_addr(ndev, addr); 1075 if (ret) 1076 return ret; 1077 pdata->mac_ops->set_mac_addr(pdata); 1078 1079 return ret; 1080 } 1081 1082 static const struct net_device_ops xgene_ndev_ops = { 1083 .ndo_open = xgene_enet_open, 1084 .ndo_stop = xgene_enet_close, 1085 .ndo_start_xmit = xgene_enet_start_xmit, 1086 .ndo_tx_timeout = xgene_enet_timeout, 1087 .ndo_get_stats64 = xgene_enet_get_stats64, 1088 .ndo_change_mtu = eth_change_mtu, 1089 .ndo_set_mac_address = xgene_enet_set_mac_address, 1090 }; 1091 1092 #ifdef CONFIG_ACPI 1093 static int xgene_get_port_id_acpi(struct device *dev, 1094 struct xgene_enet_pdata *pdata) 1095 { 1096 acpi_status status; 1097 u64 temp; 1098 1099 status = acpi_evaluate_integer(ACPI_HANDLE(dev), "_SUN", NULL, &temp); 1100 if (ACPI_FAILURE(status)) { 1101 pdata->port_id = 0; 1102 } else { 1103 pdata->port_id = temp; 1104 } 1105 1106 return 0; 1107 } 1108 #endif 1109 1110 static int xgene_get_port_id_dt(struct device *dev, struct xgene_enet_pdata *pdata) 1111 { 1112 u32 id = 0; 1113 int ret; 1114 1115 ret = of_property_read_u32(dev->of_node, "port-id", &id); 1116 if (ret) { 1117 pdata->port_id = 0; 1118 ret = 0; 1119 } else { 1120 pdata->port_id = id & BIT(0); 1121 } 1122 1123 return ret; 1124 } 1125 1126 static int xgene_get_tx_delay(struct xgene_enet_pdata *pdata) 1127 { 1128 struct device *dev = &pdata->pdev->dev; 1129 int delay, ret; 1130 1131 ret = of_property_read_u32(dev->of_node, "tx-delay", &delay); 1132 if (ret) { 1133 pdata->tx_delay = 4; 1134 return 0; 1135 } 1136 1137 if (delay < 0 || delay > 7) { 1138 dev_err(dev, "Invalid tx-delay specified\n"); 1139 return -EINVAL; 1140 } 1141 1142 pdata->tx_delay = delay; 1143 1144 return 0; 1145 } 1146 1147 static int xgene_get_rx_delay(struct xgene_enet_pdata *pdata) 1148 { 1149 struct device *dev = &pdata->pdev->dev; 1150 int delay, ret; 1151 1152 ret = of_property_read_u32(dev->of_node, "rx-delay", &delay); 1153 if (ret) { 1154 pdata->rx_delay = 2; 1155 return 0; 1156 } 1157 1158 if (delay < 0 || delay > 7) { 1159 dev_err(dev, "Invalid rx-delay specified\n"); 1160 return -EINVAL; 1161 } 1162 1163 pdata->rx_delay = delay; 1164 1165 return 0; 1166 } 1167 1168 static int xgene_enet_get_resources(struct xgene_enet_pdata *pdata) 1169 { 1170 struct platform_device *pdev; 1171 struct net_device *ndev; 1172 struct device *dev; 1173 struct resource *res; 1174 void __iomem *base_addr; 1175 u32 offset; 1176 int ret = 0; 1177 1178 pdev = pdata->pdev; 1179 dev = &pdev->dev; 1180 ndev = pdata->ndev; 1181 1182 res = platform_get_resource(pdev, IORESOURCE_MEM, RES_ENET_CSR); 1183 if (!res) { 1184 dev_err(dev, "Resource enet_csr not defined\n"); 1185 return -ENODEV; 1186 } 1187 pdata->base_addr = devm_ioremap(dev, res->start, resource_size(res)); 1188 if (!pdata->base_addr) { 1189 dev_err(dev, "Unable to retrieve ENET Port CSR region\n"); 1190 return -ENOMEM; 1191 } 1192 1193 res = platform_get_resource(pdev, IORESOURCE_MEM, RES_RING_CSR); 1194 if (!res) { 1195 dev_err(dev, "Resource ring_csr not defined\n"); 1196 return -ENODEV; 1197 } 1198 pdata->ring_csr_addr = devm_ioremap(dev, res->start, 1199 resource_size(res)); 1200 if (!pdata->ring_csr_addr) { 1201 dev_err(dev, "Unable to retrieve ENET Ring CSR region\n"); 1202 return -ENOMEM; 1203 } 1204 1205 res = platform_get_resource(pdev, IORESOURCE_MEM, RES_RING_CMD); 1206 if (!res) { 1207 dev_err(dev, "Resource ring_cmd not defined\n"); 1208 return -ENODEV; 1209 } 1210 pdata->ring_cmd_addr = devm_ioremap(dev, res->start, 1211 resource_size(res)); 1212 if (!pdata->ring_cmd_addr) { 1213 dev_err(dev, "Unable to retrieve ENET Ring command region\n"); 1214 return -ENOMEM; 1215 } 1216 1217 if (dev->of_node) 1218 ret = xgene_get_port_id_dt(dev, pdata); 1219 #ifdef CONFIG_ACPI 1220 else 1221 ret = xgene_get_port_id_acpi(dev, pdata); 1222 #endif 1223 if (ret) 1224 return ret; 1225 1226 if (!device_get_mac_address(dev, ndev->dev_addr, ETH_ALEN)) 1227 eth_hw_addr_random(ndev); 1228 1229 memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len); 1230 1231 pdata->phy_mode = device_get_phy_mode(dev); 1232 if (pdata->phy_mode < 0) { 1233 dev_err(dev, "Unable to get phy-connection-type\n"); 1234 return pdata->phy_mode; 1235 } 1236 if (pdata->phy_mode != PHY_INTERFACE_MODE_RGMII && 1237 pdata->phy_mode != PHY_INTERFACE_MODE_SGMII && 1238 pdata->phy_mode != PHY_INTERFACE_MODE_XGMII) { 1239 dev_err(dev, "Incorrect phy-connection-type specified\n"); 1240 return -ENODEV; 1241 } 1242 1243 ret = xgene_get_tx_delay(pdata); 1244 if (ret) 1245 return ret; 1246 1247 ret = xgene_get_rx_delay(pdata); 1248 if (ret) 1249 return ret; 1250 1251 ret = platform_get_irq(pdev, 0); 1252 if (ret <= 0) { 1253 dev_err(dev, "Unable to get ENET Rx IRQ\n"); 1254 ret = ret ? : -ENXIO; 1255 return ret; 1256 } 1257 pdata->rx_irq = ret; 1258 1259 if (pdata->phy_mode != PHY_INTERFACE_MODE_RGMII) { 1260 ret = platform_get_irq(pdev, 1); 1261 if (ret <= 0) { 1262 pdata->cq_cnt = 0; 1263 dev_info(dev, "Unable to get Tx completion IRQ," 1264 "using Rx IRQ instead\n"); 1265 } else { 1266 pdata->cq_cnt = XGENE_MAX_TXC_RINGS; 1267 pdata->txc_irq = ret; 1268 } 1269 } 1270 1271 pdata->clk = devm_clk_get(&pdev->dev, NULL); 1272 if (IS_ERR(pdata->clk)) { 1273 /* Firmware may have set up the clock already. */ 1274 dev_info(dev, "clocks have been setup already\n"); 1275 } 1276 1277 if (pdata->phy_mode != PHY_INTERFACE_MODE_XGMII) 1278 base_addr = pdata->base_addr - (pdata->port_id * MAC_OFFSET); 1279 else 1280 base_addr = pdata->base_addr; 1281 pdata->eth_csr_addr = base_addr + BLOCK_ETH_CSR_OFFSET; 1282 pdata->eth_ring_if_addr = base_addr + BLOCK_ETH_RING_IF_OFFSET; 1283 pdata->eth_diag_csr_addr = base_addr + BLOCK_ETH_DIAG_CSR_OFFSET; 1284 if (pdata->phy_mode == PHY_INTERFACE_MODE_RGMII || 1285 pdata->phy_mode == PHY_INTERFACE_MODE_SGMII) { 1286 pdata->mcx_mac_addr = pdata->base_addr + BLOCK_ETH_MAC_OFFSET; 1287 offset = (pdata->enet_id == XGENE_ENET1) ? 1288 BLOCK_ETH_MAC_CSR_OFFSET : 1289 X2_BLOCK_ETH_MAC_CSR_OFFSET; 1290 pdata->mcx_mac_csr_addr = base_addr + offset; 1291 } else { 1292 pdata->mcx_mac_addr = base_addr + BLOCK_AXG_MAC_OFFSET; 1293 pdata->mcx_mac_csr_addr = base_addr + BLOCK_AXG_MAC_CSR_OFFSET; 1294 } 1295 pdata->rx_buff_cnt = NUM_PKT_BUF; 1296 1297 return 0; 1298 } 1299 1300 static int xgene_enet_init_hw(struct xgene_enet_pdata *pdata) 1301 { 1302 struct net_device *ndev = pdata->ndev; 1303 struct xgene_enet_desc_ring *buf_pool; 1304 u16 dst_ring_num; 1305 int ret; 1306 1307 ret = pdata->port_ops->reset(pdata); 1308 if (ret) 1309 return ret; 1310 1311 ret = xgene_enet_create_desc_rings(ndev); 1312 if (ret) { 1313 netdev_err(ndev, "Error in ring configuration\n"); 1314 return ret; 1315 } 1316 1317 /* setup buffer pool */ 1318 buf_pool = pdata->rx_ring->buf_pool; 1319 xgene_enet_init_bufpool(buf_pool); 1320 ret = xgene_enet_refill_bufpool(buf_pool, pdata->rx_buff_cnt); 1321 if (ret) { 1322 xgene_enet_delete_desc_rings(pdata); 1323 return ret; 1324 } 1325 1326 dst_ring_num = xgene_enet_dst_ring_num(pdata->rx_ring); 1327 pdata->port_ops->cle_bypass(pdata, dst_ring_num, buf_pool->id); 1328 pdata->mac_ops->init(pdata); 1329 1330 return ret; 1331 } 1332 1333 static void xgene_enet_setup_ops(struct xgene_enet_pdata *pdata) 1334 { 1335 switch (pdata->phy_mode) { 1336 case PHY_INTERFACE_MODE_RGMII: 1337 pdata->mac_ops = &xgene_gmac_ops; 1338 pdata->port_ops = &xgene_gport_ops; 1339 pdata->rm = RM3; 1340 break; 1341 case PHY_INTERFACE_MODE_SGMII: 1342 pdata->mac_ops = &xgene_sgmac_ops; 1343 pdata->port_ops = &xgene_sgport_ops; 1344 pdata->rm = RM1; 1345 break; 1346 default: 1347 pdata->mac_ops = &xgene_xgmac_ops; 1348 pdata->port_ops = &xgene_xgport_ops; 1349 pdata->rm = RM0; 1350 break; 1351 } 1352 1353 if (pdata->enet_id == XGENE_ENET1) { 1354 switch (pdata->port_id) { 1355 case 0: 1356 pdata->cpu_bufnum = START_CPU_BUFNUM_0; 1357 pdata->eth_bufnum = START_ETH_BUFNUM_0; 1358 pdata->bp_bufnum = START_BP_BUFNUM_0; 1359 pdata->ring_num = START_RING_NUM_0; 1360 break; 1361 case 1: 1362 if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) { 1363 pdata->cpu_bufnum = XG_START_CPU_BUFNUM_1; 1364 pdata->eth_bufnum = XG_START_ETH_BUFNUM_1; 1365 pdata->bp_bufnum = XG_START_BP_BUFNUM_1; 1366 pdata->ring_num = XG_START_RING_NUM_1; 1367 } else { 1368 pdata->cpu_bufnum = START_CPU_BUFNUM_1; 1369 pdata->eth_bufnum = START_ETH_BUFNUM_1; 1370 pdata->bp_bufnum = START_BP_BUFNUM_1; 1371 pdata->ring_num = START_RING_NUM_1; 1372 } 1373 break; 1374 default: 1375 break; 1376 } 1377 pdata->ring_ops = &xgene_ring1_ops; 1378 } else { 1379 switch (pdata->port_id) { 1380 case 0: 1381 pdata->cpu_bufnum = X2_START_CPU_BUFNUM_0; 1382 pdata->eth_bufnum = X2_START_ETH_BUFNUM_0; 1383 pdata->bp_bufnum = X2_START_BP_BUFNUM_0; 1384 pdata->ring_num = X2_START_RING_NUM_0; 1385 break; 1386 case 1: 1387 pdata->cpu_bufnum = X2_START_CPU_BUFNUM_1; 1388 pdata->eth_bufnum = X2_START_ETH_BUFNUM_1; 1389 pdata->bp_bufnum = X2_START_BP_BUFNUM_1; 1390 pdata->ring_num = X2_START_RING_NUM_1; 1391 break; 1392 default: 1393 break; 1394 } 1395 pdata->rm = RM0; 1396 pdata->ring_ops = &xgene_ring2_ops; 1397 } 1398 } 1399 1400 static void xgene_enet_napi_add(struct xgene_enet_pdata *pdata) 1401 { 1402 struct napi_struct *napi; 1403 1404 napi = &pdata->rx_ring->napi; 1405 netif_napi_add(pdata->ndev, napi, xgene_enet_napi, NAPI_POLL_WEIGHT); 1406 1407 if (pdata->cq_cnt) { 1408 napi = &pdata->tx_ring->cp_ring->napi; 1409 netif_napi_add(pdata->ndev, napi, xgene_enet_napi, 1410 NAPI_POLL_WEIGHT); 1411 } 1412 } 1413 1414 static void xgene_enet_napi_del(struct xgene_enet_pdata *pdata) 1415 { 1416 struct napi_struct *napi; 1417 1418 napi = &pdata->rx_ring->napi; 1419 netif_napi_del(napi); 1420 1421 if (pdata->cq_cnt) { 1422 napi = &pdata->tx_ring->cp_ring->napi; 1423 netif_napi_del(napi); 1424 } 1425 } 1426 1427 static int xgene_enet_probe(struct platform_device *pdev) 1428 { 1429 struct net_device *ndev; 1430 struct xgene_enet_pdata *pdata; 1431 struct device *dev = &pdev->dev; 1432 struct xgene_mac_ops *mac_ops; 1433 const struct of_device_id *of_id; 1434 int ret; 1435 1436 ndev = alloc_etherdev(sizeof(struct xgene_enet_pdata)); 1437 if (!ndev) 1438 return -ENOMEM; 1439 1440 pdata = netdev_priv(ndev); 1441 1442 pdata->pdev = pdev; 1443 pdata->ndev = ndev; 1444 SET_NETDEV_DEV(ndev, dev); 1445 platform_set_drvdata(pdev, pdata); 1446 ndev->netdev_ops = &xgene_ndev_ops; 1447 xgene_enet_set_ethtool_ops(ndev); 1448 ndev->features |= NETIF_F_IP_CSUM | 1449 NETIF_F_GSO | 1450 NETIF_F_GRO | 1451 NETIF_F_SG; 1452 1453 of_id = of_match_device(xgene_enet_of_match, &pdev->dev); 1454 if (of_id) { 1455 pdata->enet_id = (enum xgene_enet_id)of_id->data; 1456 } 1457 #ifdef CONFIG_ACPI 1458 else { 1459 const struct acpi_device_id *acpi_id; 1460 1461 acpi_id = acpi_match_device(xgene_enet_acpi_match, &pdev->dev); 1462 if (acpi_id) 1463 pdata->enet_id = (enum xgene_enet_id) acpi_id->driver_data; 1464 } 1465 #endif 1466 if (!pdata->enet_id) { 1467 free_netdev(ndev); 1468 return -ENODEV; 1469 } 1470 1471 ret = xgene_enet_get_resources(pdata); 1472 if (ret) 1473 goto err; 1474 1475 xgene_enet_setup_ops(pdata); 1476 1477 if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) { 1478 ndev->features |= NETIF_F_TSO; 1479 pdata->mss = XGENE_ENET_MSS; 1480 } 1481 ndev->hw_features = ndev->features; 1482 1483 ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(64)); 1484 if (ret) { 1485 netdev_err(ndev, "No usable DMA configuration\n"); 1486 goto err; 1487 } 1488 1489 ret = register_netdev(ndev); 1490 if (ret) { 1491 netdev_err(ndev, "Failed to register netdev\n"); 1492 goto err; 1493 } 1494 1495 ret = xgene_enet_init_hw(pdata); 1496 if (ret) 1497 goto err; 1498 1499 mac_ops = pdata->mac_ops; 1500 if (pdata->phy_mode == PHY_INTERFACE_MODE_RGMII) { 1501 ret = xgene_enet_mdio_config(pdata); 1502 if (ret) 1503 goto err; 1504 } else { 1505 INIT_DELAYED_WORK(&pdata->link_work, mac_ops->link_state); 1506 } 1507 1508 xgene_enet_napi_add(pdata); 1509 return 0; 1510 err: 1511 unregister_netdev(ndev); 1512 free_netdev(ndev); 1513 return ret; 1514 } 1515 1516 static int xgene_enet_remove(struct platform_device *pdev) 1517 { 1518 struct xgene_enet_pdata *pdata; 1519 struct xgene_mac_ops *mac_ops; 1520 struct net_device *ndev; 1521 1522 pdata = platform_get_drvdata(pdev); 1523 mac_ops = pdata->mac_ops; 1524 ndev = pdata->ndev; 1525 1526 mac_ops->rx_disable(pdata); 1527 mac_ops->tx_disable(pdata); 1528 1529 xgene_enet_napi_del(pdata); 1530 if (pdata->phy_mode == PHY_INTERFACE_MODE_RGMII) 1531 xgene_enet_mdio_remove(pdata); 1532 unregister_netdev(ndev); 1533 xgene_enet_delete_desc_rings(pdata); 1534 pdata->port_ops->shutdown(pdata); 1535 free_netdev(ndev); 1536 1537 return 0; 1538 } 1539 1540 #ifdef CONFIG_ACPI 1541 static const struct acpi_device_id xgene_enet_acpi_match[] = { 1542 { "APMC0D05", XGENE_ENET1}, 1543 { "APMC0D30", XGENE_ENET1}, 1544 { "APMC0D31", XGENE_ENET1}, 1545 { "APMC0D3F", XGENE_ENET1}, 1546 { "APMC0D26", XGENE_ENET2}, 1547 { "APMC0D25", XGENE_ENET2}, 1548 { } 1549 }; 1550 MODULE_DEVICE_TABLE(acpi, xgene_enet_acpi_match); 1551 #endif 1552 1553 #ifdef CONFIG_OF 1554 static const struct of_device_id xgene_enet_of_match[] = { 1555 {.compatible = "apm,xgene-enet", .data = (void *)XGENE_ENET1}, 1556 {.compatible = "apm,xgene1-sgenet", .data = (void *)XGENE_ENET1}, 1557 {.compatible = "apm,xgene1-xgenet", .data = (void *)XGENE_ENET1}, 1558 {.compatible = "apm,xgene2-sgenet", .data = (void *)XGENE_ENET2}, 1559 {.compatible = "apm,xgene2-xgenet", .data = (void *)XGENE_ENET2}, 1560 {}, 1561 }; 1562 1563 MODULE_DEVICE_TABLE(of, xgene_enet_of_match); 1564 #endif 1565 1566 static struct platform_driver xgene_enet_driver = { 1567 .driver = { 1568 .name = "xgene-enet", 1569 .of_match_table = of_match_ptr(xgene_enet_of_match), 1570 .acpi_match_table = ACPI_PTR(xgene_enet_acpi_match), 1571 }, 1572 .probe = xgene_enet_probe, 1573 .remove = xgene_enet_remove, 1574 }; 1575 1576 module_platform_driver(xgene_enet_driver); 1577 1578 MODULE_DESCRIPTION("APM X-Gene SoC Ethernet driver"); 1579 MODULE_VERSION(XGENE_DRV_VERSION); 1580 MODULE_AUTHOR("Iyappan Subramanian <isubramanian@apm.com>"); 1581 MODULE_AUTHOR("Keyur Chudgar <kchudgar@apm.com>"); 1582 MODULE_LICENSE("GPL"); 1583