1 /* Applied Micro X-Gene SoC Ethernet Driver 2 * 3 * Copyright (c) 2014, Applied Micro Circuits Corporation 4 * Authors: Iyappan Subramanian <isubramanian@apm.com> 5 * Ravi Patel <rapatel@apm.com> 6 * Keyur Chudgar <kchudgar@apm.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program. If not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include <linux/gpio.h> 23 #include "xgene_enet_main.h" 24 #include "xgene_enet_hw.h" 25 #include "xgene_enet_sgmac.h" 26 #include "xgene_enet_xgmac.h" 27 28 #define RES_ENET_CSR 0 29 #define RES_RING_CSR 1 30 #define RES_RING_CMD 2 31 32 static const struct of_device_id xgene_enet_of_match[]; 33 static const struct acpi_device_id xgene_enet_acpi_match[]; 34 35 static void xgene_enet_init_bufpool(struct xgene_enet_desc_ring *buf_pool) 36 { 37 struct xgene_enet_raw_desc16 *raw_desc; 38 int i; 39 40 if (!buf_pool) 41 return; 42 43 for (i = 0; i < buf_pool->slots; i++) { 44 raw_desc = &buf_pool->raw_desc16[i]; 45 46 /* Hardware expects descriptor in little endian format */ 47 raw_desc->m0 = cpu_to_le64(i | 48 SET_VAL(FPQNUM, buf_pool->dst_ring_num) | 49 SET_VAL(STASH, 3)); 50 } 51 } 52 53 static u16 xgene_enet_get_data_len(u64 bufdatalen) 54 { 55 u16 hw_len, mask; 56 57 hw_len = GET_VAL(BUFDATALEN, bufdatalen); 58 59 if (unlikely(hw_len == 0x7800)) { 60 return 0; 61 } else if (!(hw_len & BIT(14))) { 62 mask = GENMASK(13, 0); 63 return (hw_len & mask) ? (hw_len & mask) : SIZE_16K; 64 } else if (!(hw_len & GENMASK(13, 12))) { 65 mask = GENMASK(11, 0); 66 return (hw_len & mask) ? (hw_len & mask) : SIZE_4K; 67 } else { 68 mask = GENMASK(11, 0); 69 return (hw_len & mask) ? (hw_len & mask) : SIZE_2K; 70 } 71 } 72 73 static u16 xgene_enet_set_data_len(u32 size) 74 { 75 u16 hw_len; 76 77 hw_len = (size == SIZE_4K) ? BIT(14) : 0; 78 79 return hw_len; 80 } 81 82 static int xgene_enet_refill_pagepool(struct xgene_enet_desc_ring *buf_pool, 83 u32 nbuf) 84 { 85 struct xgene_enet_raw_desc16 *raw_desc; 86 struct xgene_enet_pdata *pdata; 87 struct net_device *ndev; 88 dma_addr_t dma_addr; 89 struct device *dev; 90 struct page *page; 91 u32 slots, tail; 92 u16 hw_len; 93 int i; 94 95 if (unlikely(!buf_pool)) 96 return 0; 97 98 ndev = buf_pool->ndev; 99 pdata = netdev_priv(ndev); 100 dev = ndev_to_dev(ndev); 101 slots = buf_pool->slots - 1; 102 tail = buf_pool->tail; 103 104 for (i = 0; i < nbuf; i++) { 105 raw_desc = &buf_pool->raw_desc16[tail]; 106 107 page = dev_alloc_page(); 108 if (unlikely(!page)) 109 return -ENOMEM; 110 111 dma_addr = dma_map_page(dev, page, 0, 112 PAGE_SIZE, DMA_FROM_DEVICE); 113 if (unlikely(dma_mapping_error(dev, dma_addr))) { 114 put_page(page); 115 return -ENOMEM; 116 } 117 118 hw_len = xgene_enet_set_data_len(PAGE_SIZE); 119 raw_desc->m1 = cpu_to_le64(SET_VAL(DATAADDR, dma_addr) | 120 SET_VAL(BUFDATALEN, hw_len) | 121 SET_BIT(COHERENT)); 122 123 buf_pool->frag_page[tail] = page; 124 tail = (tail + 1) & slots; 125 } 126 127 pdata->ring_ops->wr_cmd(buf_pool, nbuf); 128 buf_pool->tail = tail; 129 130 return 0; 131 } 132 133 static int xgene_enet_refill_bufpool(struct xgene_enet_desc_ring *buf_pool, 134 u32 nbuf) 135 { 136 struct sk_buff *skb; 137 struct xgene_enet_raw_desc16 *raw_desc; 138 struct xgene_enet_pdata *pdata; 139 struct net_device *ndev; 140 struct device *dev; 141 dma_addr_t dma_addr; 142 u32 tail = buf_pool->tail; 143 u32 slots = buf_pool->slots - 1; 144 u16 bufdatalen, len; 145 int i; 146 147 ndev = buf_pool->ndev; 148 dev = ndev_to_dev(buf_pool->ndev); 149 pdata = netdev_priv(ndev); 150 151 bufdatalen = BUF_LEN_CODE_2K | (SKB_BUFFER_SIZE & GENMASK(11, 0)); 152 len = XGENE_ENET_STD_MTU; 153 154 for (i = 0; i < nbuf; i++) { 155 raw_desc = &buf_pool->raw_desc16[tail]; 156 157 skb = netdev_alloc_skb_ip_align(ndev, len); 158 if (unlikely(!skb)) 159 return -ENOMEM; 160 161 dma_addr = dma_map_single(dev, skb->data, len, DMA_FROM_DEVICE); 162 if (dma_mapping_error(dev, dma_addr)) { 163 netdev_err(ndev, "DMA mapping error\n"); 164 dev_kfree_skb_any(skb); 165 return -EINVAL; 166 } 167 168 buf_pool->rx_skb[tail] = skb; 169 170 raw_desc->m1 = cpu_to_le64(SET_VAL(DATAADDR, dma_addr) | 171 SET_VAL(BUFDATALEN, bufdatalen) | 172 SET_BIT(COHERENT)); 173 tail = (tail + 1) & slots; 174 } 175 176 pdata->ring_ops->wr_cmd(buf_pool, nbuf); 177 buf_pool->tail = tail; 178 179 return 0; 180 } 181 182 static u8 xgene_enet_hdr_len(const void *data) 183 { 184 const struct ethhdr *eth = data; 185 186 return (eth->h_proto == htons(ETH_P_8021Q)) ? VLAN_ETH_HLEN : ETH_HLEN; 187 } 188 189 static void xgene_enet_delete_bufpool(struct xgene_enet_desc_ring *buf_pool) 190 { 191 struct device *dev = ndev_to_dev(buf_pool->ndev); 192 struct xgene_enet_raw_desc16 *raw_desc; 193 dma_addr_t dma_addr; 194 int i; 195 196 /* Free up the buffers held by hardware */ 197 for (i = 0; i < buf_pool->slots; i++) { 198 if (buf_pool->rx_skb[i]) { 199 dev_kfree_skb_any(buf_pool->rx_skb[i]); 200 201 raw_desc = &buf_pool->raw_desc16[i]; 202 dma_addr = GET_VAL(DATAADDR, le64_to_cpu(raw_desc->m1)); 203 dma_unmap_single(dev, dma_addr, XGENE_ENET_MAX_MTU, 204 DMA_FROM_DEVICE); 205 } 206 } 207 } 208 209 static void xgene_enet_delete_pagepool(struct xgene_enet_desc_ring *buf_pool) 210 { 211 struct device *dev = ndev_to_dev(buf_pool->ndev); 212 dma_addr_t dma_addr; 213 struct page *page; 214 int i; 215 216 /* Free up the buffers held by hardware */ 217 for (i = 0; i < buf_pool->slots; i++) { 218 page = buf_pool->frag_page[i]; 219 if (page) { 220 dma_addr = buf_pool->frag_dma_addr[i]; 221 dma_unmap_page(dev, dma_addr, PAGE_SIZE, 222 DMA_FROM_DEVICE); 223 put_page(page); 224 } 225 } 226 } 227 228 static irqreturn_t xgene_enet_rx_irq(const int irq, void *data) 229 { 230 struct xgene_enet_desc_ring *rx_ring = data; 231 232 if (napi_schedule_prep(&rx_ring->napi)) { 233 disable_irq_nosync(irq); 234 __napi_schedule(&rx_ring->napi); 235 } 236 237 return IRQ_HANDLED; 238 } 239 240 static int xgene_enet_tx_completion(struct xgene_enet_desc_ring *cp_ring, 241 struct xgene_enet_raw_desc *raw_desc) 242 { 243 struct xgene_enet_pdata *pdata = netdev_priv(cp_ring->ndev); 244 struct sk_buff *skb; 245 struct device *dev; 246 skb_frag_t *frag; 247 dma_addr_t *frag_dma_addr; 248 u16 skb_index; 249 u8 status; 250 int i, ret = 0; 251 u8 mss_index; 252 253 skb_index = GET_VAL(USERINFO, le64_to_cpu(raw_desc->m0)); 254 skb = cp_ring->cp_skb[skb_index]; 255 frag_dma_addr = &cp_ring->frag_dma_addr[skb_index * MAX_SKB_FRAGS]; 256 257 dev = ndev_to_dev(cp_ring->ndev); 258 dma_unmap_single(dev, GET_VAL(DATAADDR, le64_to_cpu(raw_desc->m1)), 259 skb_headlen(skb), 260 DMA_TO_DEVICE); 261 262 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 263 frag = &skb_shinfo(skb)->frags[i]; 264 dma_unmap_page(dev, frag_dma_addr[i], skb_frag_size(frag), 265 DMA_TO_DEVICE); 266 } 267 268 if (GET_BIT(ET, le64_to_cpu(raw_desc->m3))) { 269 mss_index = GET_VAL(MSS, le64_to_cpu(raw_desc->m3)); 270 spin_lock(&pdata->mss_lock); 271 pdata->mss_refcnt[mss_index]--; 272 spin_unlock(&pdata->mss_lock); 273 } 274 275 /* Checking for error */ 276 status = GET_VAL(LERR, le64_to_cpu(raw_desc->m0)); 277 if (unlikely(status > 2)) { 278 xgene_enet_parse_error(cp_ring, netdev_priv(cp_ring->ndev), 279 status); 280 ret = -EIO; 281 } 282 283 if (likely(skb)) { 284 dev_kfree_skb_any(skb); 285 } else { 286 netdev_err(cp_ring->ndev, "completion skb is NULL\n"); 287 ret = -EIO; 288 } 289 290 return ret; 291 } 292 293 static int xgene_enet_setup_mss(struct net_device *ndev, u32 mss) 294 { 295 struct xgene_enet_pdata *pdata = netdev_priv(ndev); 296 int mss_index = -EBUSY; 297 int i; 298 299 spin_lock(&pdata->mss_lock); 300 301 /* Reuse the slot if MSS matches */ 302 for (i = 0; mss_index < 0 && i < NUM_MSS_REG; i++) { 303 if (pdata->mss[i] == mss) { 304 pdata->mss_refcnt[i]++; 305 mss_index = i; 306 } 307 } 308 309 /* Overwrite the slot with ref_count = 0 */ 310 for (i = 0; mss_index < 0 && i < NUM_MSS_REG; i++) { 311 if (!pdata->mss_refcnt[i]) { 312 pdata->mss_refcnt[i]++; 313 pdata->mac_ops->set_mss(pdata, mss, i); 314 pdata->mss[i] = mss; 315 mss_index = i; 316 } 317 } 318 319 spin_unlock(&pdata->mss_lock); 320 321 return mss_index; 322 } 323 324 static int xgene_enet_work_msg(struct sk_buff *skb, u64 *hopinfo) 325 { 326 struct net_device *ndev = skb->dev; 327 struct iphdr *iph; 328 u8 l3hlen = 0, l4hlen = 0; 329 u8 ethhdr, proto = 0, csum_enable = 0; 330 u32 hdr_len, mss = 0; 331 u32 i, len, nr_frags; 332 int mss_index; 333 334 ethhdr = xgene_enet_hdr_len(skb->data); 335 336 if (unlikely(skb->protocol != htons(ETH_P_IP)) && 337 unlikely(skb->protocol != htons(ETH_P_8021Q))) 338 goto out; 339 340 if (unlikely(!(skb->dev->features & NETIF_F_IP_CSUM))) 341 goto out; 342 343 iph = ip_hdr(skb); 344 if (unlikely(ip_is_fragment(iph))) 345 goto out; 346 347 if (likely(iph->protocol == IPPROTO_TCP)) { 348 l4hlen = tcp_hdrlen(skb) >> 2; 349 csum_enable = 1; 350 proto = TSO_IPPROTO_TCP; 351 if (ndev->features & NETIF_F_TSO) { 352 hdr_len = ethhdr + ip_hdrlen(skb) + tcp_hdrlen(skb); 353 mss = skb_shinfo(skb)->gso_size; 354 355 if (skb_is_nonlinear(skb)) { 356 len = skb_headlen(skb); 357 nr_frags = skb_shinfo(skb)->nr_frags; 358 359 for (i = 0; i < 2 && i < nr_frags; i++) 360 len += skb_shinfo(skb)->frags[i].size; 361 362 /* HW requires header must reside in 3 buffer */ 363 if (unlikely(hdr_len > len)) { 364 if (skb_linearize(skb)) 365 return 0; 366 } 367 } 368 369 if (!mss || ((skb->len - hdr_len) <= mss)) 370 goto out; 371 372 mss_index = xgene_enet_setup_mss(ndev, mss); 373 if (unlikely(mss_index < 0)) 374 return -EBUSY; 375 376 *hopinfo |= SET_BIT(ET) | SET_VAL(MSS, mss_index); 377 } 378 } else if (iph->protocol == IPPROTO_UDP) { 379 l4hlen = UDP_HDR_SIZE; 380 csum_enable = 1; 381 } 382 out: 383 l3hlen = ip_hdrlen(skb) >> 2; 384 *hopinfo |= SET_VAL(TCPHDR, l4hlen) | 385 SET_VAL(IPHDR, l3hlen) | 386 SET_VAL(ETHHDR, ethhdr) | 387 SET_VAL(EC, csum_enable) | 388 SET_VAL(IS, proto) | 389 SET_BIT(IC) | 390 SET_BIT(TYPE_ETH_WORK_MESSAGE); 391 392 return 0; 393 } 394 395 static u16 xgene_enet_encode_len(u16 len) 396 { 397 return (len == BUFLEN_16K) ? 0 : len; 398 } 399 400 static void xgene_set_addr_len(__le64 *desc, u32 idx, dma_addr_t addr, u32 len) 401 { 402 desc[idx ^ 1] = cpu_to_le64(SET_VAL(DATAADDR, addr) | 403 SET_VAL(BUFDATALEN, len)); 404 } 405 406 static __le64 *xgene_enet_get_exp_bufs(struct xgene_enet_desc_ring *ring) 407 { 408 __le64 *exp_bufs; 409 410 exp_bufs = &ring->exp_bufs[ring->exp_buf_tail * MAX_EXP_BUFFS]; 411 memset(exp_bufs, 0, sizeof(__le64) * MAX_EXP_BUFFS); 412 ring->exp_buf_tail = (ring->exp_buf_tail + 1) & ((ring->slots / 2) - 1); 413 414 return exp_bufs; 415 } 416 417 static dma_addr_t *xgene_get_frag_dma_array(struct xgene_enet_desc_ring *ring) 418 { 419 return &ring->cp_ring->frag_dma_addr[ring->tail * MAX_SKB_FRAGS]; 420 } 421 422 static int xgene_enet_setup_tx_desc(struct xgene_enet_desc_ring *tx_ring, 423 struct sk_buff *skb) 424 { 425 struct device *dev = ndev_to_dev(tx_ring->ndev); 426 struct xgene_enet_pdata *pdata = netdev_priv(tx_ring->ndev); 427 struct xgene_enet_raw_desc *raw_desc; 428 __le64 *exp_desc = NULL, *exp_bufs = NULL; 429 dma_addr_t dma_addr, pbuf_addr, *frag_dma_addr; 430 skb_frag_t *frag; 431 u16 tail = tx_ring->tail; 432 u64 hopinfo = 0; 433 u32 len, hw_len; 434 u8 ll = 0, nv = 0, idx = 0; 435 bool split = false; 436 u32 size, offset, ell_bytes = 0; 437 u32 i, fidx, nr_frags, count = 1; 438 int ret; 439 440 raw_desc = &tx_ring->raw_desc[tail]; 441 tail = (tail + 1) & (tx_ring->slots - 1); 442 memset(raw_desc, 0, sizeof(struct xgene_enet_raw_desc)); 443 444 ret = xgene_enet_work_msg(skb, &hopinfo); 445 if (ret) 446 return ret; 447 448 raw_desc->m3 = cpu_to_le64(SET_VAL(HENQNUM, tx_ring->dst_ring_num) | 449 hopinfo); 450 451 len = skb_headlen(skb); 452 hw_len = xgene_enet_encode_len(len); 453 454 dma_addr = dma_map_single(dev, skb->data, len, DMA_TO_DEVICE); 455 if (dma_mapping_error(dev, dma_addr)) { 456 netdev_err(tx_ring->ndev, "DMA mapping error\n"); 457 return -EINVAL; 458 } 459 460 /* Hardware expects descriptor in little endian format */ 461 raw_desc->m1 = cpu_to_le64(SET_VAL(DATAADDR, dma_addr) | 462 SET_VAL(BUFDATALEN, hw_len) | 463 SET_BIT(COHERENT)); 464 465 if (!skb_is_nonlinear(skb)) 466 goto out; 467 468 /* scatter gather */ 469 nv = 1; 470 exp_desc = (void *)&tx_ring->raw_desc[tail]; 471 tail = (tail + 1) & (tx_ring->slots - 1); 472 memset(exp_desc, 0, sizeof(struct xgene_enet_raw_desc)); 473 474 nr_frags = skb_shinfo(skb)->nr_frags; 475 for (i = nr_frags; i < 4 ; i++) 476 exp_desc[i ^ 1] = cpu_to_le64(LAST_BUFFER); 477 478 frag_dma_addr = xgene_get_frag_dma_array(tx_ring); 479 480 for (i = 0, fidx = 0; split || (fidx < nr_frags); i++) { 481 if (!split) { 482 frag = &skb_shinfo(skb)->frags[fidx]; 483 size = skb_frag_size(frag); 484 offset = 0; 485 486 pbuf_addr = skb_frag_dma_map(dev, frag, 0, size, 487 DMA_TO_DEVICE); 488 if (dma_mapping_error(dev, pbuf_addr)) 489 return -EINVAL; 490 491 frag_dma_addr[fidx] = pbuf_addr; 492 fidx++; 493 494 if (size > BUFLEN_16K) 495 split = true; 496 } 497 498 if (size > BUFLEN_16K) { 499 len = BUFLEN_16K; 500 size -= BUFLEN_16K; 501 } else { 502 len = size; 503 split = false; 504 } 505 506 dma_addr = pbuf_addr + offset; 507 hw_len = xgene_enet_encode_len(len); 508 509 switch (i) { 510 case 0: 511 case 1: 512 case 2: 513 xgene_set_addr_len(exp_desc, i, dma_addr, hw_len); 514 break; 515 case 3: 516 if (split || (fidx != nr_frags)) { 517 exp_bufs = xgene_enet_get_exp_bufs(tx_ring); 518 xgene_set_addr_len(exp_bufs, idx, dma_addr, 519 hw_len); 520 idx++; 521 ell_bytes += len; 522 } else { 523 xgene_set_addr_len(exp_desc, i, dma_addr, 524 hw_len); 525 } 526 break; 527 default: 528 xgene_set_addr_len(exp_bufs, idx, dma_addr, hw_len); 529 idx++; 530 ell_bytes += len; 531 break; 532 } 533 534 if (split) 535 offset += BUFLEN_16K; 536 } 537 count++; 538 539 if (idx) { 540 ll = 1; 541 dma_addr = dma_map_single(dev, exp_bufs, 542 sizeof(u64) * MAX_EXP_BUFFS, 543 DMA_TO_DEVICE); 544 if (dma_mapping_error(dev, dma_addr)) { 545 dev_kfree_skb_any(skb); 546 return -EINVAL; 547 } 548 i = ell_bytes >> LL_BYTES_LSB_LEN; 549 exp_desc[2] = cpu_to_le64(SET_VAL(DATAADDR, dma_addr) | 550 SET_VAL(LL_BYTES_MSB, i) | 551 SET_VAL(LL_LEN, idx)); 552 raw_desc->m2 = cpu_to_le64(SET_VAL(LL_BYTES_LSB, ell_bytes)); 553 } 554 555 out: 556 raw_desc->m0 = cpu_to_le64(SET_VAL(LL, ll) | SET_VAL(NV, nv) | 557 SET_VAL(USERINFO, tx_ring->tail)); 558 tx_ring->cp_ring->cp_skb[tx_ring->tail] = skb; 559 pdata->tx_level[tx_ring->cp_ring->index] += count; 560 tx_ring->tail = tail; 561 562 return count; 563 } 564 565 static netdev_tx_t xgene_enet_start_xmit(struct sk_buff *skb, 566 struct net_device *ndev) 567 { 568 struct xgene_enet_pdata *pdata = netdev_priv(ndev); 569 struct xgene_enet_desc_ring *tx_ring; 570 int index = skb->queue_mapping; 571 u32 tx_level = pdata->tx_level[index]; 572 int count; 573 574 tx_ring = pdata->tx_ring[index]; 575 if (tx_level < pdata->txc_level[index]) 576 tx_level += ((typeof(pdata->tx_level[index]))~0U); 577 578 if ((tx_level - pdata->txc_level[index]) > pdata->tx_qcnt_hi) { 579 netif_stop_subqueue(ndev, index); 580 return NETDEV_TX_BUSY; 581 } 582 583 if (skb_padto(skb, XGENE_MIN_ENET_FRAME_SIZE)) 584 return NETDEV_TX_OK; 585 586 count = xgene_enet_setup_tx_desc(tx_ring, skb); 587 if (count == -EBUSY) 588 return NETDEV_TX_BUSY; 589 590 if (count <= 0) { 591 dev_kfree_skb_any(skb); 592 return NETDEV_TX_OK; 593 } 594 595 skb_tx_timestamp(skb); 596 597 tx_ring->tx_packets++; 598 tx_ring->tx_bytes += skb->len; 599 600 pdata->ring_ops->wr_cmd(tx_ring, count); 601 return NETDEV_TX_OK; 602 } 603 604 static void xgene_enet_rx_csum(struct sk_buff *skb) 605 { 606 struct net_device *ndev = skb->dev; 607 struct iphdr *iph = ip_hdr(skb); 608 609 if (!(ndev->features & NETIF_F_RXCSUM)) 610 return; 611 612 if (skb->protocol != htons(ETH_P_IP)) 613 return; 614 615 if (ip_is_fragment(iph)) 616 return; 617 618 if (iph->protocol != IPPROTO_TCP && iph->protocol != IPPROTO_UDP) 619 return; 620 621 skb->ip_summed = CHECKSUM_UNNECESSARY; 622 } 623 624 static void xgene_enet_free_pagepool(struct xgene_enet_desc_ring *buf_pool, 625 struct xgene_enet_raw_desc *raw_desc, 626 struct xgene_enet_raw_desc *exp_desc) 627 { 628 __le64 *desc = (void *)exp_desc; 629 dma_addr_t dma_addr; 630 struct device *dev; 631 struct page *page; 632 u16 slots, head; 633 u32 frag_size; 634 int i; 635 636 if (!buf_pool || !raw_desc || !exp_desc || 637 (!GET_VAL(NV, le64_to_cpu(raw_desc->m0)))) 638 return; 639 640 dev = ndev_to_dev(buf_pool->ndev); 641 slots = buf_pool->slots - 1; 642 head = buf_pool->head; 643 644 for (i = 0; i < 4; i++) { 645 frag_size = xgene_enet_get_data_len(le64_to_cpu(desc[i ^ 1])); 646 if (!frag_size) 647 break; 648 649 dma_addr = GET_VAL(DATAADDR, le64_to_cpu(desc[i ^ 1])); 650 dma_unmap_page(dev, dma_addr, PAGE_SIZE, DMA_FROM_DEVICE); 651 652 page = buf_pool->frag_page[head]; 653 put_page(page); 654 655 buf_pool->frag_page[head] = NULL; 656 head = (head + 1) & slots; 657 } 658 buf_pool->head = head; 659 } 660 661 /* Errata 10GE_8 and ENET_11 - allow packet with length <=64B */ 662 static bool xgene_enet_errata_10GE_8(struct sk_buff *skb, u32 len, u8 status) 663 { 664 if (status == INGRESS_PKT_LEN && len == ETHER_MIN_PACKET) { 665 if (ntohs(eth_hdr(skb)->h_proto) < 46) 666 return true; 667 } 668 669 return false; 670 } 671 672 static int xgene_enet_rx_frame(struct xgene_enet_desc_ring *rx_ring, 673 struct xgene_enet_raw_desc *raw_desc, 674 struct xgene_enet_raw_desc *exp_desc) 675 { 676 struct xgene_enet_desc_ring *buf_pool, *page_pool; 677 u32 datalen, frag_size, skb_index; 678 struct xgene_enet_pdata *pdata; 679 struct net_device *ndev; 680 dma_addr_t dma_addr; 681 struct sk_buff *skb; 682 struct device *dev; 683 struct page *page; 684 u16 slots, head; 685 int i, ret = 0; 686 __le64 *desc; 687 u8 status; 688 bool nv; 689 690 ndev = rx_ring->ndev; 691 pdata = netdev_priv(ndev); 692 dev = ndev_to_dev(rx_ring->ndev); 693 buf_pool = rx_ring->buf_pool; 694 page_pool = rx_ring->page_pool; 695 696 dma_unmap_single(dev, GET_VAL(DATAADDR, le64_to_cpu(raw_desc->m1)), 697 XGENE_ENET_STD_MTU, DMA_FROM_DEVICE); 698 skb_index = GET_VAL(USERINFO, le64_to_cpu(raw_desc->m0)); 699 skb = buf_pool->rx_skb[skb_index]; 700 buf_pool->rx_skb[skb_index] = NULL; 701 702 datalen = xgene_enet_get_data_len(le64_to_cpu(raw_desc->m1)); 703 skb_put(skb, datalen); 704 prefetch(skb->data - NET_IP_ALIGN); 705 skb->protocol = eth_type_trans(skb, ndev); 706 707 /* checking for error */ 708 status = (GET_VAL(ELERR, le64_to_cpu(raw_desc->m0)) << LERR_LEN) | 709 GET_VAL(LERR, le64_to_cpu(raw_desc->m0)); 710 if (unlikely(status)) { 711 if (!xgene_enet_errata_10GE_8(skb, datalen, status)) { 712 dev_kfree_skb_any(skb); 713 xgene_enet_free_pagepool(page_pool, raw_desc, exp_desc); 714 xgene_enet_parse_error(rx_ring, pdata, status); 715 goto out; 716 } 717 } 718 719 nv = GET_VAL(NV, le64_to_cpu(raw_desc->m0)); 720 if (!nv) { 721 /* strip off CRC as HW isn't doing this */ 722 datalen -= 4; 723 goto skip_jumbo; 724 } 725 726 slots = page_pool->slots - 1; 727 head = page_pool->head; 728 desc = (void *)exp_desc; 729 730 for (i = 0; i < 4; i++) { 731 frag_size = xgene_enet_get_data_len(le64_to_cpu(desc[i ^ 1])); 732 if (!frag_size) 733 break; 734 735 dma_addr = GET_VAL(DATAADDR, le64_to_cpu(desc[i ^ 1])); 736 dma_unmap_page(dev, dma_addr, PAGE_SIZE, DMA_FROM_DEVICE); 737 738 page = page_pool->frag_page[head]; 739 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, 0, 740 frag_size, PAGE_SIZE); 741 742 datalen += frag_size; 743 744 page_pool->frag_page[head] = NULL; 745 head = (head + 1) & slots; 746 } 747 748 page_pool->head = head; 749 rx_ring->npagepool -= skb_shinfo(skb)->nr_frags; 750 751 skip_jumbo: 752 skb_checksum_none_assert(skb); 753 xgene_enet_rx_csum(skb); 754 755 rx_ring->rx_packets++; 756 rx_ring->rx_bytes += datalen; 757 napi_gro_receive(&rx_ring->napi, skb); 758 759 out: 760 if (rx_ring->npagepool <= 0) { 761 ret = xgene_enet_refill_pagepool(page_pool, NUM_NXTBUFPOOL); 762 rx_ring->npagepool = NUM_NXTBUFPOOL; 763 if (ret) 764 return ret; 765 } 766 767 if (--rx_ring->nbufpool == 0) { 768 ret = xgene_enet_refill_bufpool(buf_pool, NUM_BUFPOOL); 769 rx_ring->nbufpool = NUM_BUFPOOL; 770 } 771 772 return ret; 773 } 774 775 static bool is_rx_desc(struct xgene_enet_raw_desc *raw_desc) 776 { 777 return GET_VAL(FPQNUM, le64_to_cpu(raw_desc->m0)) ? true : false; 778 } 779 780 static int xgene_enet_process_ring(struct xgene_enet_desc_ring *ring, 781 int budget) 782 { 783 struct net_device *ndev = ring->ndev; 784 struct xgene_enet_pdata *pdata = netdev_priv(ndev); 785 struct xgene_enet_raw_desc *raw_desc, *exp_desc; 786 u16 head = ring->head; 787 u16 slots = ring->slots - 1; 788 int ret, desc_count, count = 0, processed = 0; 789 bool is_completion; 790 791 do { 792 raw_desc = &ring->raw_desc[head]; 793 desc_count = 0; 794 is_completion = false; 795 exp_desc = NULL; 796 if (unlikely(xgene_enet_is_desc_slot_empty(raw_desc))) 797 break; 798 799 /* read fpqnum field after dataaddr field */ 800 dma_rmb(); 801 if (GET_BIT(NV, le64_to_cpu(raw_desc->m0))) { 802 head = (head + 1) & slots; 803 exp_desc = &ring->raw_desc[head]; 804 805 if (unlikely(xgene_enet_is_desc_slot_empty(exp_desc))) { 806 head = (head - 1) & slots; 807 break; 808 } 809 dma_rmb(); 810 count++; 811 desc_count++; 812 } 813 if (is_rx_desc(raw_desc)) { 814 ret = xgene_enet_rx_frame(ring, raw_desc, exp_desc); 815 } else { 816 ret = xgene_enet_tx_completion(ring, raw_desc); 817 is_completion = true; 818 } 819 xgene_enet_mark_desc_slot_empty(raw_desc); 820 if (exp_desc) 821 xgene_enet_mark_desc_slot_empty(exp_desc); 822 823 head = (head + 1) & slots; 824 count++; 825 desc_count++; 826 processed++; 827 if (is_completion) 828 pdata->txc_level[ring->index] += desc_count; 829 830 if (ret) 831 break; 832 } while (--budget); 833 834 if (likely(count)) { 835 pdata->ring_ops->wr_cmd(ring, -count); 836 ring->head = head; 837 838 if (__netif_subqueue_stopped(ndev, ring->index)) 839 netif_start_subqueue(ndev, ring->index); 840 } 841 842 return processed; 843 } 844 845 static int xgene_enet_napi(struct napi_struct *napi, const int budget) 846 { 847 struct xgene_enet_desc_ring *ring; 848 int processed; 849 850 ring = container_of(napi, struct xgene_enet_desc_ring, napi); 851 processed = xgene_enet_process_ring(ring, budget); 852 853 if (processed != budget) { 854 napi_complete_done(napi, processed); 855 enable_irq(ring->irq); 856 } 857 858 return processed; 859 } 860 861 static void xgene_enet_timeout(struct net_device *ndev) 862 { 863 struct xgene_enet_pdata *pdata = netdev_priv(ndev); 864 struct netdev_queue *txq; 865 int i; 866 867 pdata->mac_ops->reset(pdata); 868 869 for (i = 0; i < pdata->txq_cnt; i++) { 870 txq = netdev_get_tx_queue(ndev, i); 871 txq->trans_start = jiffies; 872 netif_tx_start_queue(txq); 873 } 874 } 875 876 static void xgene_enet_set_irq_name(struct net_device *ndev) 877 { 878 struct xgene_enet_pdata *pdata = netdev_priv(ndev); 879 struct xgene_enet_desc_ring *ring; 880 int i; 881 882 for (i = 0; i < pdata->rxq_cnt; i++) { 883 ring = pdata->rx_ring[i]; 884 if (!pdata->cq_cnt) { 885 snprintf(ring->irq_name, IRQ_ID_SIZE, "%s-rx-txc", 886 ndev->name); 887 } else { 888 snprintf(ring->irq_name, IRQ_ID_SIZE, "%s-rx-%d", 889 ndev->name, i); 890 } 891 } 892 893 for (i = 0; i < pdata->cq_cnt; i++) { 894 ring = pdata->tx_ring[i]->cp_ring; 895 snprintf(ring->irq_name, IRQ_ID_SIZE, "%s-txc-%d", 896 ndev->name, i); 897 } 898 } 899 900 static int xgene_enet_register_irq(struct net_device *ndev) 901 { 902 struct xgene_enet_pdata *pdata = netdev_priv(ndev); 903 struct device *dev = ndev_to_dev(ndev); 904 struct xgene_enet_desc_ring *ring; 905 int ret = 0, i; 906 907 xgene_enet_set_irq_name(ndev); 908 for (i = 0; i < pdata->rxq_cnt; i++) { 909 ring = pdata->rx_ring[i]; 910 irq_set_status_flags(ring->irq, IRQ_DISABLE_UNLAZY); 911 ret = devm_request_irq(dev, ring->irq, xgene_enet_rx_irq, 912 0, ring->irq_name, ring); 913 if (ret) { 914 netdev_err(ndev, "Failed to request irq %s\n", 915 ring->irq_name); 916 } 917 } 918 919 for (i = 0; i < pdata->cq_cnt; i++) { 920 ring = pdata->tx_ring[i]->cp_ring; 921 irq_set_status_flags(ring->irq, IRQ_DISABLE_UNLAZY); 922 ret = devm_request_irq(dev, ring->irq, xgene_enet_rx_irq, 923 0, ring->irq_name, ring); 924 if (ret) { 925 netdev_err(ndev, "Failed to request irq %s\n", 926 ring->irq_name); 927 } 928 } 929 930 return ret; 931 } 932 933 static void xgene_enet_free_irq(struct net_device *ndev) 934 { 935 struct xgene_enet_pdata *pdata; 936 struct xgene_enet_desc_ring *ring; 937 struct device *dev; 938 int i; 939 940 pdata = netdev_priv(ndev); 941 dev = ndev_to_dev(ndev); 942 943 for (i = 0; i < pdata->rxq_cnt; i++) { 944 ring = pdata->rx_ring[i]; 945 irq_clear_status_flags(ring->irq, IRQ_DISABLE_UNLAZY); 946 devm_free_irq(dev, ring->irq, ring); 947 } 948 949 for (i = 0; i < pdata->cq_cnt; i++) { 950 ring = pdata->tx_ring[i]->cp_ring; 951 irq_clear_status_flags(ring->irq, IRQ_DISABLE_UNLAZY); 952 devm_free_irq(dev, ring->irq, ring); 953 } 954 } 955 956 static void xgene_enet_napi_enable(struct xgene_enet_pdata *pdata) 957 { 958 struct napi_struct *napi; 959 int i; 960 961 for (i = 0; i < pdata->rxq_cnt; i++) { 962 napi = &pdata->rx_ring[i]->napi; 963 napi_enable(napi); 964 } 965 966 for (i = 0; i < pdata->cq_cnt; i++) { 967 napi = &pdata->tx_ring[i]->cp_ring->napi; 968 napi_enable(napi); 969 } 970 } 971 972 static void xgene_enet_napi_disable(struct xgene_enet_pdata *pdata) 973 { 974 struct napi_struct *napi; 975 int i; 976 977 for (i = 0; i < pdata->rxq_cnt; i++) { 978 napi = &pdata->rx_ring[i]->napi; 979 napi_disable(napi); 980 } 981 982 for (i = 0; i < pdata->cq_cnt; i++) { 983 napi = &pdata->tx_ring[i]->cp_ring->napi; 984 napi_disable(napi); 985 } 986 } 987 988 static int xgene_enet_open(struct net_device *ndev) 989 { 990 struct xgene_enet_pdata *pdata = netdev_priv(ndev); 991 const struct xgene_mac_ops *mac_ops = pdata->mac_ops; 992 int ret; 993 994 ret = netif_set_real_num_tx_queues(ndev, pdata->txq_cnt); 995 if (ret) 996 return ret; 997 998 ret = netif_set_real_num_rx_queues(ndev, pdata->rxq_cnt); 999 if (ret) 1000 return ret; 1001 1002 xgene_enet_napi_enable(pdata); 1003 ret = xgene_enet_register_irq(ndev); 1004 if (ret) 1005 return ret; 1006 1007 if (ndev->phydev) { 1008 phy_start(ndev->phydev); 1009 } else { 1010 schedule_delayed_work(&pdata->link_work, PHY_POLL_LINK_OFF); 1011 netif_carrier_off(ndev); 1012 } 1013 1014 mac_ops->tx_enable(pdata); 1015 mac_ops->rx_enable(pdata); 1016 netif_tx_start_all_queues(ndev); 1017 1018 return ret; 1019 } 1020 1021 static int xgene_enet_close(struct net_device *ndev) 1022 { 1023 struct xgene_enet_pdata *pdata = netdev_priv(ndev); 1024 const struct xgene_mac_ops *mac_ops = pdata->mac_ops; 1025 int i; 1026 1027 netif_tx_stop_all_queues(ndev); 1028 mac_ops->tx_disable(pdata); 1029 mac_ops->rx_disable(pdata); 1030 1031 if (ndev->phydev) 1032 phy_stop(ndev->phydev); 1033 else 1034 cancel_delayed_work_sync(&pdata->link_work); 1035 1036 xgene_enet_free_irq(ndev); 1037 xgene_enet_napi_disable(pdata); 1038 for (i = 0; i < pdata->rxq_cnt; i++) 1039 xgene_enet_process_ring(pdata->rx_ring[i], -1); 1040 1041 return 0; 1042 } 1043 static void xgene_enet_delete_ring(struct xgene_enet_desc_ring *ring) 1044 { 1045 struct xgene_enet_pdata *pdata; 1046 struct device *dev; 1047 1048 pdata = netdev_priv(ring->ndev); 1049 dev = ndev_to_dev(ring->ndev); 1050 1051 pdata->ring_ops->clear(ring); 1052 dmam_free_coherent(dev, ring->size, ring->desc_addr, ring->dma); 1053 } 1054 1055 static void xgene_enet_delete_desc_rings(struct xgene_enet_pdata *pdata) 1056 { 1057 struct xgene_enet_desc_ring *buf_pool, *page_pool; 1058 struct xgene_enet_desc_ring *ring; 1059 int i; 1060 1061 for (i = 0; i < pdata->txq_cnt; i++) { 1062 ring = pdata->tx_ring[i]; 1063 if (ring) { 1064 xgene_enet_delete_ring(ring); 1065 pdata->port_ops->clear(pdata, ring); 1066 if (pdata->cq_cnt) 1067 xgene_enet_delete_ring(ring->cp_ring); 1068 pdata->tx_ring[i] = NULL; 1069 } 1070 1071 } 1072 1073 for (i = 0; i < pdata->rxq_cnt; i++) { 1074 ring = pdata->rx_ring[i]; 1075 if (ring) { 1076 page_pool = ring->page_pool; 1077 if (page_pool) { 1078 xgene_enet_delete_pagepool(page_pool); 1079 xgene_enet_delete_ring(page_pool); 1080 pdata->port_ops->clear(pdata, page_pool); 1081 } 1082 1083 buf_pool = ring->buf_pool; 1084 xgene_enet_delete_bufpool(buf_pool); 1085 xgene_enet_delete_ring(buf_pool); 1086 pdata->port_ops->clear(pdata, buf_pool); 1087 1088 xgene_enet_delete_ring(ring); 1089 pdata->rx_ring[i] = NULL; 1090 } 1091 1092 } 1093 } 1094 1095 static int xgene_enet_get_ring_size(struct device *dev, 1096 enum xgene_enet_ring_cfgsize cfgsize) 1097 { 1098 int size = -EINVAL; 1099 1100 switch (cfgsize) { 1101 case RING_CFGSIZE_512B: 1102 size = 0x200; 1103 break; 1104 case RING_CFGSIZE_2KB: 1105 size = 0x800; 1106 break; 1107 case RING_CFGSIZE_16KB: 1108 size = 0x4000; 1109 break; 1110 case RING_CFGSIZE_64KB: 1111 size = 0x10000; 1112 break; 1113 case RING_CFGSIZE_512KB: 1114 size = 0x80000; 1115 break; 1116 default: 1117 dev_err(dev, "Unsupported cfg ring size %d\n", cfgsize); 1118 break; 1119 } 1120 1121 return size; 1122 } 1123 1124 static void xgene_enet_free_desc_ring(struct xgene_enet_desc_ring *ring) 1125 { 1126 struct xgene_enet_pdata *pdata; 1127 struct device *dev; 1128 1129 if (!ring) 1130 return; 1131 1132 dev = ndev_to_dev(ring->ndev); 1133 pdata = netdev_priv(ring->ndev); 1134 1135 if (ring->desc_addr) { 1136 pdata->ring_ops->clear(ring); 1137 dmam_free_coherent(dev, ring->size, ring->desc_addr, ring->dma); 1138 } 1139 devm_kfree(dev, ring); 1140 } 1141 1142 static void xgene_enet_free_desc_rings(struct xgene_enet_pdata *pdata) 1143 { 1144 struct xgene_enet_desc_ring *page_pool; 1145 struct device *dev = &pdata->pdev->dev; 1146 struct xgene_enet_desc_ring *ring; 1147 void *p; 1148 int i; 1149 1150 for (i = 0; i < pdata->txq_cnt; i++) { 1151 ring = pdata->tx_ring[i]; 1152 if (ring) { 1153 if (ring->cp_ring && ring->cp_ring->cp_skb) 1154 devm_kfree(dev, ring->cp_ring->cp_skb); 1155 1156 if (ring->cp_ring && pdata->cq_cnt) 1157 xgene_enet_free_desc_ring(ring->cp_ring); 1158 1159 xgene_enet_free_desc_ring(ring); 1160 } 1161 1162 } 1163 1164 for (i = 0; i < pdata->rxq_cnt; i++) { 1165 ring = pdata->rx_ring[i]; 1166 if (ring) { 1167 if (ring->buf_pool) { 1168 if (ring->buf_pool->rx_skb) 1169 devm_kfree(dev, ring->buf_pool->rx_skb); 1170 1171 xgene_enet_free_desc_ring(ring->buf_pool); 1172 } 1173 1174 page_pool = ring->page_pool; 1175 if (page_pool) { 1176 p = page_pool->frag_page; 1177 if (p) 1178 devm_kfree(dev, p); 1179 1180 p = page_pool->frag_dma_addr; 1181 if (p) 1182 devm_kfree(dev, p); 1183 } 1184 1185 xgene_enet_free_desc_ring(ring); 1186 } 1187 } 1188 } 1189 1190 static bool is_irq_mbox_required(struct xgene_enet_pdata *pdata, 1191 struct xgene_enet_desc_ring *ring) 1192 { 1193 if ((pdata->enet_id == XGENE_ENET2) && 1194 (xgene_enet_ring_owner(ring->id) == RING_OWNER_CPU)) { 1195 return true; 1196 } 1197 1198 return false; 1199 } 1200 1201 static void __iomem *xgene_enet_ring_cmd_base(struct xgene_enet_pdata *pdata, 1202 struct xgene_enet_desc_ring *ring) 1203 { 1204 u8 num_ring_id_shift = pdata->ring_ops->num_ring_id_shift; 1205 1206 return pdata->ring_cmd_addr + (ring->num << num_ring_id_shift); 1207 } 1208 1209 static struct xgene_enet_desc_ring *xgene_enet_create_desc_ring( 1210 struct net_device *ndev, u32 ring_num, 1211 enum xgene_enet_ring_cfgsize cfgsize, u32 ring_id) 1212 { 1213 struct xgene_enet_pdata *pdata = netdev_priv(ndev); 1214 struct device *dev = ndev_to_dev(ndev); 1215 struct xgene_enet_desc_ring *ring; 1216 void *irq_mbox_addr; 1217 int size; 1218 1219 size = xgene_enet_get_ring_size(dev, cfgsize); 1220 if (size < 0) 1221 return NULL; 1222 1223 ring = devm_kzalloc(dev, sizeof(struct xgene_enet_desc_ring), 1224 GFP_KERNEL); 1225 if (!ring) 1226 return NULL; 1227 1228 ring->ndev = ndev; 1229 ring->num = ring_num; 1230 ring->cfgsize = cfgsize; 1231 ring->id = ring_id; 1232 1233 ring->desc_addr = dmam_alloc_coherent(dev, size, &ring->dma, 1234 GFP_KERNEL | __GFP_ZERO); 1235 if (!ring->desc_addr) { 1236 devm_kfree(dev, ring); 1237 return NULL; 1238 } 1239 ring->size = size; 1240 1241 if (is_irq_mbox_required(pdata, ring)) { 1242 irq_mbox_addr = dmam_alloc_coherent(dev, INTR_MBOX_SIZE, 1243 &ring->irq_mbox_dma, 1244 GFP_KERNEL | __GFP_ZERO); 1245 if (!irq_mbox_addr) { 1246 dmam_free_coherent(dev, size, ring->desc_addr, 1247 ring->dma); 1248 devm_kfree(dev, ring); 1249 return NULL; 1250 } 1251 ring->irq_mbox_addr = irq_mbox_addr; 1252 } 1253 1254 ring->cmd_base = xgene_enet_ring_cmd_base(pdata, ring); 1255 ring->cmd = ring->cmd_base + INC_DEC_CMD_ADDR; 1256 ring = pdata->ring_ops->setup(ring); 1257 netdev_dbg(ndev, "ring info: num=%d size=%d id=%d slots=%d\n", 1258 ring->num, ring->size, ring->id, ring->slots); 1259 1260 return ring; 1261 } 1262 1263 static u16 xgene_enet_get_ring_id(enum xgene_ring_owner owner, u8 bufnum) 1264 { 1265 return (owner << 6) | (bufnum & GENMASK(5, 0)); 1266 } 1267 1268 static enum xgene_ring_owner xgene_derive_ring_owner(struct xgene_enet_pdata *p) 1269 { 1270 enum xgene_ring_owner owner; 1271 1272 if (p->enet_id == XGENE_ENET1) { 1273 switch (p->phy_mode) { 1274 case PHY_INTERFACE_MODE_SGMII: 1275 owner = RING_OWNER_ETH0; 1276 break; 1277 default: 1278 owner = (!p->port_id) ? RING_OWNER_ETH0 : 1279 RING_OWNER_ETH1; 1280 break; 1281 } 1282 } else { 1283 owner = (!p->port_id) ? RING_OWNER_ETH0 : RING_OWNER_ETH1; 1284 } 1285 1286 return owner; 1287 } 1288 1289 static u8 xgene_start_cpu_bufnum(struct xgene_enet_pdata *pdata) 1290 { 1291 struct device *dev = &pdata->pdev->dev; 1292 u32 cpu_bufnum; 1293 int ret; 1294 1295 ret = device_property_read_u32(dev, "channel", &cpu_bufnum); 1296 1297 return (!ret) ? cpu_bufnum : pdata->cpu_bufnum; 1298 } 1299 1300 static int xgene_enet_create_desc_rings(struct net_device *ndev) 1301 { 1302 struct xgene_enet_desc_ring *rx_ring, *tx_ring, *cp_ring; 1303 struct xgene_enet_pdata *pdata = netdev_priv(ndev); 1304 struct xgene_enet_desc_ring *page_pool = NULL; 1305 struct xgene_enet_desc_ring *buf_pool = NULL; 1306 struct device *dev = ndev_to_dev(ndev); 1307 u8 eth_bufnum = pdata->eth_bufnum; 1308 u8 bp_bufnum = pdata->bp_bufnum; 1309 u16 ring_num = pdata->ring_num; 1310 enum xgene_ring_owner owner; 1311 dma_addr_t dma_exp_bufs; 1312 u16 ring_id, slots; 1313 __le64 *exp_bufs; 1314 int i, ret, size; 1315 u8 cpu_bufnum; 1316 1317 cpu_bufnum = xgene_start_cpu_bufnum(pdata); 1318 1319 for (i = 0; i < pdata->rxq_cnt; i++) { 1320 /* allocate rx descriptor ring */ 1321 owner = xgene_derive_ring_owner(pdata); 1322 ring_id = xgene_enet_get_ring_id(RING_OWNER_CPU, cpu_bufnum++); 1323 rx_ring = xgene_enet_create_desc_ring(ndev, ring_num++, 1324 RING_CFGSIZE_16KB, 1325 ring_id); 1326 if (!rx_ring) { 1327 ret = -ENOMEM; 1328 goto err; 1329 } 1330 1331 /* allocate buffer pool for receiving packets */ 1332 owner = xgene_derive_ring_owner(pdata); 1333 ring_id = xgene_enet_get_ring_id(owner, bp_bufnum++); 1334 buf_pool = xgene_enet_create_desc_ring(ndev, ring_num++, 1335 RING_CFGSIZE_16KB, 1336 ring_id); 1337 if (!buf_pool) { 1338 ret = -ENOMEM; 1339 goto err; 1340 } 1341 1342 rx_ring->nbufpool = NUM_BUFPOOL; 1343 rx_ring->npagepool = NUM_NXTBUFPOOL; 1344 rx_ring->irq = pdata->irqs[i]; 1345 buf_pool->rx_skb = devm_kcalloc(dev, buf_pool->slots, 1346 sizeof(struct sk_buff *), 1347 GFP_KERNEL); 1348 if (!buf_pool->rx_skb) { 1349 ret = -ENOMEM; 1350 goto err; 1351 } 1352 1353 buf_pool->dst_ring_num = xgene_enet_dst_ring_num(buf_pool); 1354 rx_ring->buf_pool = buf_pool; 1355 pdata->rx_ring[i] = rx_ring; 1356 1357 if ((pdata->enet_id == XGENE_ENET1 && pdata->rxq_cnt > 4) || 1358 (pdata->enet_id == XGENE_ENET2 && pdata->rxq_cnt > 16)) { 1359 break; 1360 } 1361 1362 /* allocate next buffer pool for jumbo packets */ 1363 owner = xgene_derive_ring_owner(pdata); 1364 ring_id = xgene_enet_get_ring_id(owner, bp_bufnum++); 1365 page_pool = xgene_enet_create_desc_ring(ndev, ring_num++, 1366 RING_CFGSIZE_16KB, 1367 ring_id); 1368 if (!page_pool) { 1369 ret = -ENOMEM; 1370 goto err; 1371 } 1372 1373 slots = page_pool->slots; 1374 page_pool->frag_page = devm_kcalloc(dev, slots, 1375 sizeof(struct page *), 1376 GFP_KERNEL); 1377 if (!page_pool->frag_page) { 1378 ret = -ENOMEM; 1379 goto err; 1380 } 1381 1382 page_pool->frag_dma_addr = devm_kcalloc(dev, slots, 1383 sizeof(dma_addr_t), 1384 GFP_KERNEL); 1385 if (!page_pool->frag_dma_addr) { 1386 ret = -ENOMEM; 1387 goto err; 1388 } 1389 1390 page_pool->dst_ring_num = xgene_enet_dst_ring_num(page_pool); 1391 rx_ring->page_pool = page_pool; 1392 } 1393 1394 for (i = 0; i < pdata->txq_cnt; i++) { 1395 /* allocate tx descriptor ring */ 1396 owner = xgene_derive_ring_owner(pdata); 1397 ring_id = xgene_enet_get_ring_id(owner, eth_bufnum++); 1398 tx_ring = xgene_enet_create_desc_ring(ndev, ring_num++, 1399 RING_CFGSIZE_16KB, 1400 ring_id); 1401 if (!tx_ring) { 1402 ret = -ENOMEM; 1403 goto err; 1404 } 1405 1406 size = (tx_ring->slots / 2) * sizeof(__le64) * MAX_EXP_BUFFS; 1407 exp_bufs = dmam_alloc_coherent(dev, size, &dma_exp_bufs, 1408 GFP_KERNEL | __GFP_ZERO); 1409 if (!exp_bufs) { 1410 ret = -ENOMEM; 1411 goto err; 1412 } 1413 tx_ring->exp_bufs = exp_bufs; 1414 1415 pdata->tx_ring[i] = tx_ring; 1416 1417 if (!pdata->cq_cnt) { 1418 cp_ring = pdata->rx_ring[i]; 1419 } else { 1420 /* allocate tx completion descriptor ring */ 1421 ring_id = xgene_enet_get_ring_id(RING_OWNER_CPU, 1422 cpu_bufnum++); 1423 cp_ring = xgene_enet_create_desc_ring(ndev, ring_num++, 1424 RING_CFGSIZE_16KB, 1425 ring_id); 1426 if (!cp_ring) { 1427 ret = -ENOMEM; 1428 goto err; 1429 } 1430 1431 cp_ring->irq = pdata->irqs[pdata->rxq_cnt + i]; 1432 cp_ring->index = i; 1433 } 1434 1435 cp_ring->cp_skb = devm_kcalloc(dev, tx_ring->slots, 1436 sizeof(struct sk_buff *), 1437 GFP_KERNEL); 1438 if (!cp_ring->cp_skb) { 1439 ret = -ENOMEM; 1440 goto err; 1441 } 1442 1443 size = sizeof(dma_addr_t) * MAX_SKB_FRAGS; 1444 cp_ring->frag_dma_addr = devm_kcalloc(dev, tx_ring->slots, 1445 size, GFP_KERNEL); 1446 if (!cp_ring->frag_dma_addr) { 1447 devm_kfree(dev, cp_ring->cp_skb); 1448 ret = -ENOMEM; 1449 goto err; 1450 } 1451 1452 tx_ring->cp_ring = cp_ring; 1453 tx_ring->dst_ring_num = xgene_enet_dst_ring_num(cp_ring); 1454 } 1455 1456 if (pdata->ring_ops->coalesce) 1457 pdata->ring_ops->coalesce(pdata->tx_ring[0]); 1458 pdata->tx_qcnt_hi = pdata->tx_ring[0]->slots - 128; 1459 1460 return 0; 1461 1462 err: 1463 xgene_enet_free_desc_rings(pdata); 1464 return ret; 1465 } 1466 1467 static void xgene_enet_get_stats64( 1468 struct net_device *ndev, 1469 struct rtnl_link_stats64 *storage) 1470 { 1471 struct xgene_enet_pdata *pdata = netdev_priv(ndev); 1472 struct rtnl_link_stats64 *stats = &pdata->stats; 1473 struct xgene_enet_desc_ring *ring; 1474 int i; 1475 1476 for (i = 0; i < pdata->txq_cnt; i++) { 1477 ring = pdata->tx_ring[i]; 1478 if (ring) { 1479 stats->tx_packets += ring->tx_packets; 1480 stats->tx_bytes += ring->tx_bytes; 1481 } 1482 } 1483 1484 for (i = 0; i < pdata->rxq_cnt; i++) { 1485 ring = pdata->rx_ring[i]; 1486 if (ring) { 1487 stats->rx_packets += ring->rx_packets; 1488 stats->rx_bytes += ring->rx_bytes; 1489 stats->rx_errors += ring->rx_length_errors + 1490 ring->rx_crc_errors + 1491 ring->rx_frame_errors + 1492 ring->rx_fifo_errors; 1493 stats->rx_dropped += ring->rx_dropped; 1494 } 1495 } 1496 memcpy(storage, stats, sizeof(struct rtnl_link_stats64)); 1497 } 1498 1499 static int xgene_enet_set_mac_address(struct net_device *ndev, void *addr) 1500 { 1501 struct xgene_enet_pdata *pdata = netdev_priv(ndev); 1502 int ret; 1503 1504 ret = eth_mac_addr(ndev, addr); 1505 if (ret) 1506 return ret; 1507 pdata->mac_ops->set_mac_addr(pdata); 1508 1509 return ret; 1510 } 1511 1512 static int xgene_change_mtu(struct net_device *ndev, int new_mtu) 1513 { 1514 struct xgene_enet_pdata *pdata = netdev_priv(ndev); 1515 int frame_size; 1516 1517 if (!netif_running(ndev)) 1518 return 0; 1519 1520 frame_size = (new_mtu > ETH_DATA_LEN) ? (new_mtu + 18) : 0x600; 1521 1522 xgene_enet_close(ndev); 1523 ndev->mtu = new_mtu; 1524 pdata->mac_ops->set_framesize(pdata, frame_size); 1525 xgene_enet_open(ndev); 1526 1527 return 0; 1528 } 1529 1530 static const struct net_device_ops xgene_ndev_ops = { 1531 .ndo_open = xgene_enet_open, 1532 .ndo_stop = xgene_enet_close, 1533 .ndo_start_xmit = xgene_enet_start_xmit, 1534 .ndo_tx_timeout = xgene_enet_timeout, 1535 .ndo_get_stats64 = xgene_enet_get_stats64, 1536 .ndo_change_mtu = xgene_change_mtu, 1537 .ndo_set_mac_address = xgene_enet_set_mac_address, 1538 }; 1539 1540 #ifdef CONFIG_ACPI 1541 static void xgene_get_port_id_acpi(struct device *dev, 1542 struct xgene_enet_pdata *pdata) 1543 { 1544 acpi_status status; 1545 u64 temp; 1546 1547 status = acpi_evaluate_integer(ACPI_HANDLE(dev), "_SUN", NULL, &temp); 1548 if (ACPI_FAILURE(status)) { 1549 pdata->port_id = 0; 1550 } else { 1551 pdata->port_id = temp; 1552 } 1553 1554 return; 1555 } 1556 #endif 1557 1558 static void xgene_get_port_id_dt(struct device *dev, struct xgene_enet_pdata *pdata) 1559 { 1560 u32 id = 0; 1561 1562 of_property_read_u32(dev->of_node, "port-id", &id); 1563 1564 pdata->port_id = id & BIT(0); 1565 1566 return; 1567 } 1568 1569 static int xgene_get_tx_delay(struct xgene_enet_pdata *pdata) 1570 { 1571 struct device *dev = &pdata->pdev->dev; 1572 int delay, ret; 1573 1574 ret = of_property_read_u32(dev->of_node, "tx-delay", &delay); 1575 if (ret) { 1576 pdata->tx_delay = 4; 1577 return 0; 1578 } 1579 1580 if (delay < 0 || delay > 7) { 1581 dev_err(dev, "Invalid tx-delay specified\n"); 1582 return -EINVAL; 1583 } 1584 1585 pdata->tx_delay = delay; 1586 1587 return 0; 1588 } 1589 1590 static int xgene_get_rx_delay(struct xgene_enet_pdata *pdata) 1591 { 1592 struct device *dev = &pdata->pdev->dev; 1593 int delay, ret; 1594 1595 ret = of_property_read_u32(dev->of_node, "rx-delay", &delay); 1596 if (ret) { 1597 pdata->rx_delay = 2; 1598 return 0; 1599 } 1600 1601 if (delay < 0 || delay > 7) { 1602 dev_err(dev, "Invalid rx-delay specified\n"); 1603 return -EINVAL; 1604 } 1605 1606 pdata->rx_delay = delay; 1607 1608 return 0; 1609 } 1610 1611 static int xgene_enet_get_irqs(struct xgene_enet_pdata *pdata) 1612 { 1613 struct platform_device *pdev = pdata->pdev; 1614 struct device *dev = &pdev->dev; 1615 int i, ret, max_irqs; 1616 1617 if (pdata->phy_mode == PHY_INTERFACE_MODE_RGMII) 1618 max_irqs = 1; 1619 else if (pdata->phy_mode == PHY_INTERFACE_MODE_SGMII) 1620 max_irqs = 2; 1621 else 1622 max_irqs = XGENE_MAX_ENET_IRQ; 1623 1624 for (i = 0; i < max_irqs; i++) { 1625 ret = platform_get_irq(pdev, i); 1626 if (ret <= 0) { 1627 if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) { 1628 max_irqs = i; 1629 pdata->rxq_cnt = max_irqs / 2; 1630 pdata->txq_cnt = max_irqs / 2; 1631 pdata->cq_cnt = max_irqs / 2; 1632 break; 1633 } 1634 dev_err(dev, "Unable to get ENET IRQ\n"); 1635 ret = ret ? : -ENXIO; 1636 return ret; 1637 } 1638 pdata->irqs[i] = ret; 1639 } 1640 1641 return 0; 1642 } 1643 1644 static int xgene_enet_check_phy_handle(struct xgene_enet_pdata *pdata) 1645 { 1646 int ret; 1647 1648 if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) 1649 return 0; 1650 1651 if (!IS_ENABLED(CONFIG_MDIO_XGENE)) 1652 return 0; 1653 1654 ret = xgene_enet_phy_connect(pdata->ndev); 1655 if (!ret) 1656 pdata->mdio_driver = true; 1657 1658 return 0; 1659 } 1660 1661 static void xgene_enet_gpiod_get(struct xgene_enet_pdata *pdata) 1662 { 1663 struct device *dev = &pdata->pdev->dev; 1664 1665 pdata->sfp_gpio_en = false; 1666 if (pdata->phy_mode != PHY_INTERFACE_MODE_XGMII || 1667 (!device_property_present(dev, "sfp-gpios") && 1668 !device_property_present(dev, "rxlos-gpios"))) 1669 return; 1670 1671 pdata->sfp_gpio_en = true; 1672 pdata->sfp_rdy = gpiod_get(dev, "rxlos", GPIOD_IN); 1673 if (IS_ERR(pdata->sfp_rdy)) 1674 pdata->sfp_rdy = gpiod_get(dev, "sfp", GPIOD_IN); 1675 } 1676 1677 static int xgene_enet_get_resources(struct xgene_enet_pdata *pdata) 1678 { 1679 struct platform_device *pdev; 1680 struct net_device *ndev; 1681 struct device *dev; 1682 struct resource *res; 1683 void __iomem *base_addr; 1684 u32 offset; 1685 int ret = 0; 1686 1687 pdev = pdata->pdev; 1688 dev = &pdev->dev; 1689 ndev = pdata->ndev; 1690 1691 res = platform_get_resource(pdev, IORESOURCE_MEM, RES_ENET_CSR); 1692 if (!res) { 1693 dev_err(dev, "Resource enet_csr not defined\n"); 1694 return -ENODEV; 1695 } 1696 pdata->base_addr = devm_ioremap(dev, res->start, resource_size(res)); 1697 if (!pdata->base_addr) { 1698 dev_err(dev, "Unable to retrieve ENET Port CSR region\n"); 1699 return -ENOMEM; 1700 } 1701 1702 res = platform_get_resource(pdev, IORESOURCE_MEM, RES_RING_CSR); 1703 if (!res) { 1704 dev_err(dev, "Resource ring_csr not defined\n"); 1705 return -ENODEV; 1706 } 1707 pdata->ring_csr_addr = devm_ioremap(dev, res->start, 1708 resource_size(res)); 1709 if (!pdata->ring_csr_addr) { 1710 dev_err(dev, "Unable to retrieve ENET Ring CSR region\n"); 1711 return -ENOMEM; 1712 } 1713 1714 res = platform_get_resource(pdev, IORESOURCE_MEM, RES_RING_CMD); 1715 if (!res) { 1716 dev_err(dev, "Resource ring_cmd not defined\n"); 1717 return -ENODEV; 1718 } 1719 pdata->ring_cmd_addr = devm_ioremap(dev, res->start, 1720 resource_size(res)); 1721 if (!pdata->ring_cmd_addr) { 1722 dev_err(dev, "Unable to retrieve ENET Ring command region\n"); 1723 return -ENOMEM; 1724 } 1725 1726 if (dev->of_node) 1727 xgene_get_port_id_dt(dev, pdata); 1728 #ifdef CONFIG_ACPI 1729 else 1730 xgene_get_port_id_acpi(dev, pdata); 1731 #endif 1732 1733 if (!device_get_mac_address(dev, ndev->dev_addr, ETH_ALEN)) 1734 eth_hw_addr_random(ndev); 1735 1736 memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len); 1737 1738 pdata->phy_mode = device_get_phy_mode(dev); 1739 if (pdata->phy_mode < 0) { 1740 dev_err(dev, "Unable to get phy-connection-type\n"); 1741 return pdata->phy_mode; 1742 } 1743 if (pdata->phy_mode != PHY_INTERFACE_MODE_RGMII && 1744 pdata->phy_mode != PHY_INTERFACE_MODE_SGMII && 1745 pdata->phy_mode != PHY_INTERFACE_MODE_XGMII) { 1746 dev_err(dev, "Incorrect phy-connection-type specified\n"); 1747 return -ENODEV; 1748 } 1749 1750 ret = xgene_get_tx_delay(pdata); 1751 if (ret) 1752 return ret; 1753 1754 ret = xgene_get_rx_delay(pdata); 1755 if (ret) 1756 return ret; 1757 1758 ret = xgene_enet_get_irqs(pdata); 1759 if (ret) 1760 return ret; 1761 1762 ret = xgene_enet_check_phy_handle(pdata); 1763 if (ret) 1764 return ret; 1765 1766 xgene_enet_gpiod_get(pdata); 1767 1768 pdata->clk = devm_clk_get(&pdev->dev, NULL); 1769 if (IS_ERR(pdata->clk)) { 1770 /* Abort if the clock is defined but couldn't be retrived. 1771 * Always abort if the clock is missing on DT system as 1772 * the driver can't cope with this case. 1773 */ 1774 if (PTR_ERR(pdata->clk) != -ENOENT || dev->of_node) 1775 return PTR_ERR(pdata->clk); 1776 /* Firmware may have set up the clock already. */ 1777 dev_info(dev, "clocks have been setup already\n"); 1778 } 1779 1780 if (pdata->phy_mode != PHY_INTERFACE_MODE_XGMII) 1781 base_addr = pdata->base_addr - (pdata->port_id * MAC_OFFSET); 1782 else 1783 base_addr = pdata->base_addr; 1784 pdata->eth_csr_addr = base_addr + BLOCK_ETH_CSR_OFFSET; 1785 pdata->cle.base = base_addr + BLOCK_ETH_CLE_CSR_OFFSET; 1786 pdata->eth_ring_if_addr = base_addr + BLOCK_ETH_RING_IF_OFFSET; 1787 pdata->eth_diag_csr_addr = base_addr + BLOCK_ETH_DIAG_CSR_OFFSET; 1788 if (pdata->phy_mode == PHY_INTERFACE_MODE_RGMII || 1789 pdata->phy_mode == PHY_INTERFACE_MODE_SGMII) { 1790 pdata->mcx_mac_addr = pdata->base_addr + BLOCK_ETH_MAC_OFFSET; 1791 offset = (pdata->enet_id == XGENE_ENET1) ? 1792 BLOCK_ETH_MAC_CSR_OFFSET : 1793 X2_BLOCK_ETH_MAC_CSR_OFFSET; 1794 pdata->mcx_mac_csr_addr = base_addr + offset; 1795 } else { 1796 pdata->mcx_mac_addr = base_addr + BLOCK_AXG_MAC_OFFSET; 1797 pdata->mcx_mac_csr_addr = base_addr + BLOCK_AXG_MAC_CSR_OFFSET; 1798 pdata->pcs_addr = base_addr + BLOCK_PCS_OFFSET; 1799 } 1800 pdata->rx_buff_cnt = NUM_PKT_BUF; 1801 1802 return 0; 1803 } 1804 1805 static int xgene_enet_init_hw(struct xgene_enet_pdata *pdata) 1806 { 1807 struct xgene_enet_cle *enet_cle = &pdata->cle; 1808 struct xgene_enet_desc_ring *page_pool; 1809 struct net_device *ndev = pdata->ndev; 1810 struct xgene_enet_desc_ring *buf_pool; 1811 u16 dst_ring_num, ring_id; 1812 int i, ret; 1813 u32 count; 1814 1815 ret = pdata->port_ops->reset(pdata); 1816 if (ret) 1817 return ret; 1818 1819 ret = xgene_enet_create_desc_rings(ndev); 1820 if (ret) { 1821 netdev_err(ndev, "Error in ring configuration\n"); 1822 return ret; 1823 } 1824 1825 /* setup buffer pool */ 1826 for (i = 0; i < pdata->rxq_cnt; i++) { 1827 buf_pool = pdata->rx_ring[i]->buf_pool; 1828 xgene_enet_init_bufpool(buf_pool); 1829 page_pool = pdata->rx_ring[i]->page_pool; 1830 xgene_enet_init_bufpool(page_pool); 1831 1832 count = pdata->rx_buff_cnt; 1833 ret = xgene_enet_refill_bufpool(buf_pool, count); 1834 if (ret) 1835 goto err; 1836 1837 ret = xgene_enet_refill_pagepool(page_pool, count); 1838 if (ret) 1839 goto err; 1840 1841 } 1842 1843 dst_ring_num = xgene_enet_dst_ring_num(pdata->rx_ring[0]); 1844 buf_pool = pdata->rx_ring[0]->buf_pool; 1845 if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) { 1846 /* Initialize and Enable PreClassifier Tree */ 1847 enet_cle->max_nodes = 512; 1848 enet_cle->max_dbptrs = 1024; 1849 enet_cle->parsers = 3; 1850 enet_cle->active_parser = PARSER_ALL; 1851 enet_cle->ptree.start_node = 0; 1852 enet_cle->ptree.start_dbptr = 0; 1853 enet_cle->jump_bytes = 8; 1854 ret = pdata->cle_ops->cle_init(pdata); 1855 if (ret) { 1856 netdev_err(ndev, "Preclass Tree init error\n"); 1857 goto err; 1858 } 1859 1860 } else { 1861 dst_ring_num = xgene_enet_dst_ring_num(pdata->rx_ring[0]); 1862 buf_pool = pdata->rx_ring[0]->buf_pool; 1863 page_pool = pdata->rx_ring[0]->page_pool; 1864 ring_id = (page_pool) ? page_pool->id : 0; 1865 pdata->port_ops->cle_bypass(pdata, dst_ring_num, 1866 buf_pool->id, ring_id); 1867 } 1868 1869 ndev->max_mtu = XGENE_ENET_MAX_MTU; 1870 pdata->phy_speed = SPEED_UNKNOWN; 1871 pdata->mac_ops->init(pdata); 1872 1873 return ret; 1874 1875 err: 1876 xgene_enet_delete_desc_rings(pdata); 1877 return ret; 1878 } 1879 1880 static void xgene_enet_setup_ops(struct xgene_enet_pdata *pdata) 1881 { 1882 switch (pdata->phy_mode) { 1883 case PHY_INTERFACE_MODE_RGMII: 1884 pdata->mac_ops = &xgene_gmac_ops; 1885 pdata->port_ops = &xgene_gport_ops; 1886 pdata->rm = RM3; 1887 pdata->rxq_cnt = 1; 1888 pdata->txq_cnt = 1; 1889 pdata->cq_cnt = 0; 1890 break; 1891 case PHY_INTERFACE_MODE_SGMII: 1892 pdata->mac_ops = &xgene_sgmac_ops; 1893 pdata->port_ops = &xgene_sgport_ops; 1894 pdata->rm = RM1; 1895 pdata->rxq_cnt = 1; 1896 pdata->txq_cnt = 1; 1897 pdata->cq_cnt = 1; 1898 break; 1899 default: 1900 pdata->mac_ops = &xgene_xgmac_ops; 1901 pdata->port_ops = &xgene_xgport_ops; 1902 pdata->cle_ops = &xgene_cle3in_ops; 1903 pdata->rm = RM0; 1904 if (!pdata->rxq_cnt) { 1905 pdata->rxq_cnt = XGENE_NUM_RX_RING; 1906 pdata->txq_cnt = XGENE_NUM_TX_RING; 1907 pdata->cq_cnt = XGENE_NUM_TXC_RING; 1908 } 1909 break; 1910 } 1911 1912 if (pdata->enet_id == XGENE_ENET1) { 1913 switch (pdata->port_id) { 1914 case 0: 1915 if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) { 1916 pdata->cpu_bufnum = X2_START_CPU_BUFNUM_0; 1917 pdata->eth_bufnum = X2_START_ETH_BUFNUM_0; 1918 pdata->bp_bufnum = X2_START_BP_BUFNUM_0; 1919 pdata->ring_num = START_RING_NUM_0; 1920 } else { 1921 pdata->cpu_bufnum = START_CPU_BUFNUM_0; 1922 pdata->eth_bufnum = START_ETH_BUFNUM_0; 1923 pdata->bp_bufnum = START_BP_BUFNUM_0; 1924 pdata->ring_num = START_RING_NUM_0; 1925 } 1926 break; 1927 case 1: 1928 if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) { 1929 pdata->cpu_bufnum = XG_START_CPU_BUFNUM_1; 1930 pdata->eth_bufnum = XG_START_ETH_BUFNUM_1; 1931 pdata->bp_bufnum = XG_START_BP_BUFNUM_1; 1932 pdata->ring_num = XG_START_RING_NUM_1; 1933 } else { 1934 pdata->cpu_bufnum = START_CPU_BUFNUM_1; 1935 pdata->eth_bufnum = START_ETH_BUFNUM_1; 1936 pdata->bp_bufnum = START_BP_BUFNUM_1; 1937 pdata->ring_num = START_RING_NUM_1; 1938 } 1939 break; 1940 default: 1941 break; 1942 } 1943 pdata->ring_ops = &xgene_ring1_ops; 1944 } else { 1945 switch (pdata->port_id) { 1946 case 0: 1947 pdata->cpu_bufnum = X2_START_CPU_BUFNUM_0; 1948 pdata->eth_bufnum = X2_START_ETH_BUFNUM_0; 1949 pdata->bp_bufnum = X2_START_BP_BUFNUM_0; 1950 pdata->ring_num = X2_START_RING_NUM_0; 1951 break; 1952 case 1: 1953 pdata->cpu_bufnum = X2_START_CPU_BUFNUM_1; 1954 pdata->eth_bufnum = X2_START_ETH_BUFNUM_1; 1955 pdata->bp_bufnum = X2_START_BP_BUFNUM_1; 1956 pdata->ring_num = X2_START_RING_NUM_1; 1957 break; 1958 default: 1959 break; 1960 } 1961 pdata->rm = RM0; 1962 pdata->ring_ops = &xgene_ring2_ops; 1963 } 1964 } 1965 1966 static void xgene_enet_napi_add(struct xgene_enet_pdata *pdata) 1967 { 1968 struct napi_struct *napi; 1969 int i; 1970 1971 for (i = 0; i < pdata->rxq_cnt; i++) { 1972 napi = &pdata->rx_ring[i]->napi; 1973 netif_napi_add(pdata->ndev, napi, xgene_enet_napi, 1974 NAPI_POLL_WEIGHT); 1975 } 1976 1977 for (i = 0; i < pdata->cq_cnt; i++) { 1978 napi = &pdata->tx_ring[i]->cp_ring->napi; 1979 netif_napi_add(pdata->ndev, napi, xgene_enet_napi, 1980 NAPI_POLL_WEIGHT); 1981 } 1982 } 1983 1984 #ifdef CONFIG_ACPI 1985 static const struct acpi_device_id xgene_enet_acpi_match[] = { 1986 { "APMC0D05", XGENE_ENET1}, 1987 { "APMC0D30", XGENE_ENET1}, 1988 { "APMC0D31", XGENE_ENET1}, 1989 { "APMC0D3F", XGENE_ENET1}, 1990 { "APMC0D26", XGENE_ENET2}, 1991 { "APMC0D25", XGENE_ENET2}, 1992 { } 1993 }; 1994 MODULE_DEVICE_TABLE(acpi, xgene_enet_acpi_match); 1995 #endif 1996 1997 static const struct of_device_id xgene_enet_of_match[] = { 1998 {.compatible = "apm,xgene-enet", .data = (void *)XGENE_ENET1}, 1999 {.compatible = "apm,xgene1-sgenet", .data = (void *)XGENE_ENET1}, 2000 {.compatible = "apm,xgene1-xgenet", .data = (void *)XGENE_ENET1}, 2001 {.compatible = "apm,xgene2-sgenet", .data = (void *)XGENE_ENET2}, 2002 {.compatible = "apm,xgene2-xgenet", .data = (void *)XGENE_ENET2}, 2003 {}, 2004 }; 2005 2006 MODULE_DEVICE_TABLE(of, xgene_enet_of_match); 2007 2008 static int xgene_enet_probe(struct platform_device *pdev) 2009 { 2010 struct net_device *ndev; 2011 struct xgene_enet_pdata *pdata; 2012 struct device *dev = &pdev->dev; 2013 void (*link_state)(struct work_struct *); 2014 const struct of_device_id *of_id; 2015 int ret; 2016 2017 ndev = alloc_etherdev_mqs(sizeof(struct xgene_enet_pdata), 2018 XGENE_NUM_RX_RING, XGENE_NUM_TX_RING); 2019 if (!ndev) 2020 return -ENOMEM; 2021 2022 pdata = netdev_priv(ndev); 2023 2024 pdata->pdev = pdev; 2025 pdata->ndev = ndev; 2026 SET_NETDEV_DEV(ndev, dev); 2027 platform_set_drvdata(pdev, pdata); 2028 ndev->netdev_ops = &xgene_ndev_ops; 2029 xgene_enet_set_ethtool_ops(ndev); 2030 ndev->features |= NETIF_F_IP_CSUM | 2031 NETIF_F_GSO | 2032 NETIF_F_GRO | 2033 NETIF_F_SG; 2034 2035 of_id = of_match_device(xgene_enet_of_match, &pdev->dev); 2036 if (of_id) { 2037 pdata->enet_id = (enum xgene_enet_id)of_id->data; 2038 } 2039 #ifdef CONFIG_ACPI 2040 else { 2041 const struct acpi_device_id *acpi_id; 2042 2043 acpi_id = acpi_match_device(xgene_enet_acpi_match, &pdev->dev); 2044 if (acpi_id) 2045 pdata->enet_id = (enum xgene_enet_id) acpi_id->driver_data; 2046 } 2047 #endif 2048 if (!pdata->enet_id) { 2049 ret = -ENODEV; 2050 goto err; 2051 } 2052 2053 ret = xgene_enet_get_resources(pdata); 2054 if (ret) 2055 goto err; 2056 2057 xgene_enet_setup_ops(pdata); 2058 2059 if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) { 2060 ndev->features |= NETIF_F_TSO | NETIF_F_RXCSUM; 2061 spin_lock_init(&pdata->mss_lock); 2062 } 2063 ndev->hw_features = ndev->features; 2064 2065 ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(64)); 2066 if (ret) { 2067 netdev_err(ndev, "No usable DMA configuration\n"); 2068 goto err; 2069 } 2070 2071 ret = xgene_enet_init_hw(pdata); 2072 if (ret) 2073 goto err; 2074 2075 link_state = pdata->mac_ops->link_state; 2076 if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) { 2077 INIT_DELAYED_WORK(&pdata->link_work, link_state); 2078 } else if (!pdata->mdio_driver) { 2079 if (pdata->phy_mode == PHY_INTERFACE_MODE_RGMII) 2080 ret = xgene_enet_mdio_config(pdata); 2081 else 2082 INIT_DELAYED_WORK(&pdata->link_work, link_state); 2083 2084 if (ret) 2085 goto err1; 2086 } 2087 2088 xgene_enet_napi_add(pdata); 2089 ret = register_netdev(ndev); 2090 if (ret) { 2091 netdev_err(ndev, "Failed to register netdev\n"); 2092 goto err2; 2093 } 2094 2095 return 0; 2096 2097 err2: 2098 /* 2099 * If necessary, free_netdev() will call netif_napi_del() and undo 2100 * the effects of xgene_enet_napi_add()'s calls to netif_napi_add(). 2101 */ 2102 2103 if (pdata->mdio_driver) 2104 xgene_enet_phy_disconnect(pdata); 2105 else if (pdata->phy_mode == PHY_INTERFACE_MODE_RGMII) 2106 xgene_enet_mdio_remove(pdata); 2107 err1: 2108 xgene_enet_delete_desc_rings(pdata); 2109 err: 2110 free_netdev(ndev); 2111 return ret; 2112 } 2113 2114 static int xgene_enet_remove(struct platform_device *pdev) 2115 { 2116 struct xgene_enet_pdata *pdata; 2117 struct net_device *ndev; 2118 2119 pdata = platform_get_drvdata(pdev); 2120 ndev = pdata->ndev; 2121 2122 rtnl_lock(); 2123 if (netif_running(ndev)) 2124 dev_close(ndev); 2125 rtnl_unlock(); 2126 2127 if (pdata->mdio_driver) 2128 xgene_enet_phy_disconnect(pdata); 2129 else if (pdata->phy_mode == PHY_INTERFACE_MODE_RGMII) 2130 xgene_enet_mdio_remove(pdata); 2131 2132 unregister_netdev(ndev); 2133 pdata->port_ops->shutdown(pdata); 2134 xgene_enet_delete_desc_rings(pdata); 2135 free_netdev(ndev); 2136 2137 return 0; 2138 } 2139 2140 static void xgene_enet_shutdown(struct platform_device *pdev) 2141 { 2142 struct xgene_enet_pdata *pdata; 2143 2144 pdata = platform_get_drvdata(pdev); 2145 if (!pdata) 2146 return; 2147 2148 if (!pdata->ndev) 2149 return; 2150 2151 xgene_enet_remove(pdev); 2152 } 2153 2154 static struct platform_driver xgene_enet_driver = { 2155 .driver = { 2156 .name = "xgene-enet", 2157 .of_match_table = of_match_ptr(xgene_enet_of_match), 2158 .acpi_match_table = ACPI_PTR(xgene_enet_acpi_match), 2159 }, 2160 .probe = xgene_enet_probe, 2161 .remove = xgene_enet_remove, 2162 .shutdown = xgene_enet_shutdown, 2163 }; 2164 2165 module_platform_driver(xgene_enet_driver); 2166 2167 MODULE_DESCRIPTION("APM X-Gene SoC Ethernet driver"); 2168 MODULE_VERSION(XGENE_DRV_VERSION); 2169 MODULE_AUTHOR("Iyappan Subramanian <isubramanian@apm.com>"); 2170 MODULE_AUTHOR("Keyur Chudgar <kchudgar@apm.com>"); 2171 MODULE_LICENSE("GPL"); 2172