1 /* Applied Micro X-Gene SoC Ethernet Driver 2 * 3 * Copyright (c) 2014, Applied Micro Circuits Corporation 4 * Authors: Iyappan Subramanian <isubramanian@apm.com> 5 * Ravi Patel <rapatel@apm.com> 6 * Keyur Chudgar <kchudgar@apm.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program. If not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #ifndef __XGENE_ENET_HW_H__ 23 #define __XGENE_ENET_HW_H__ 24 25 #include "xgene_enet_main.h" 26 27 struct xgene_enet_pdata; 28 struct xgene_enet_stats; 29 struct xgene_enet_desc_ring; 30 31 /* clears and then set bits */ 32 static inline void xgene_set_bits(u32 *dst, u32 val, u32 start, u32 len) 33 { 34 u32 end = start + len - 1; 35 u32 mask = GENMASK(end, start); 36 37 *dst &= ~mask; 38 *dst |= (val << start) & mask; 39 } 40 41 static inline u32 xgene_get_bits(u32 val, u32 start, u32 end) 42 { 43 return (val & GENMASK(end, start)) >> start; 44 } 45 46 enum xgene_enet_rm { 47 RM0, 48 RM1, 49 RM3 = 3 50 }; 51 52 #define CSR_RING_ID 0x0008 53 #define OVERWRITE BIT(31) 54 #define IS_BUFFER_POOL BIT(20) 55 #define PREFETCH_BUF_EN BIT(21) 56 #define CSR_RING_ID_BUF 0x000c 57 #define CSR_PBM_COAL 0x0014 58 #define CSR_PBM_CTICK1 0x001c 59 #define CSR_PBM_CTICK2 0x0020 60 #define CSR_THRESHOLD0_SET1 0x0030 61 #define CSR_THRESHOLD1_SET1 0x0034 62 #define CSR_RING_NE_INT_MODE 0x017c 63 #define CSR_RING_CONFIG 0x006c 64 #define CSR_RING_WR_BASE 0x0070 65 #define NUM_RING_CONFIG 5 66 #define BUFPOOL_MODE 3 67 #define INC_DEC_CMD_ADDR 0x002c 68 #define UDP_HDR_SIZE 2 69 #define BUF_LEN_CODE_2K 0x5000 70 71 #define CREATE_MASK(pos, len) GENMASK((pos)+(len)-1, (pos)) 72 #define CREATE_MASK_ULL(pos, len) GENMASK_ULL((pos)+(len)-1, (pos)) 73 74 /* Empty slot soft signature */ 75 #define EMPTY_SLOT_INDEX 1 76 #define EMPTY_SLOT ~0ULL 77 78 #define WORK_DESC_SIZE 32 79 #define BUFPOOL_DESC_SIZE 16 80 81 #define RING_OWNER_MASK GENMASK(9, 6) 82 #define RING_BUFNUM_MASK GENMASK(5, 0) 83 84 #define SELTHRSH_POS 3 85 #define SELTHRSH_LEN 3 86 #define RINGADDRL_POS 5 87 #define RINGADDRL_LEN 27 88 #define RINGADDRH_POS 0 89 #define RINGADDRH_LEN 7 90 #define RINGSIZE_POS 23 91 #define RINGSIZE_LEN 3 92 #define RINGTYPE_POS 19 93 #define RINGTYPE_LEN 2 94 #define RINGMODE_POS 20 95 #define RINGMODE_LEN 3 96 #define RECOMTIMEOUTL_POS 28 97 #define RECOMTIMEOUTL_LEN 4 98 #define RECOMTIMEOUTH_POS 0 99 #define RECOMTIMEOUTH_LEN 3 100 #define NUMMSGSINQ_POS 1 101 #define NUMMSGSINQ_LEN 16 102 #define ACCEPTLERR BIT(19) 103 #define QCOHERENT BIT(4) 104 #define RECOMBBUF BIT(27) 105 106 #define MAC_OFFSET 0x30 107 #define OFFSET_4 0x04 108 #define OFFSET_8 0x08 109 110 #define BLOCK_ETH_CSR_OFFSET 0x2000 111 #define BLOCK_ETH_CLE_CSR_OFFSET 0x6000 112 #define BLOCK_ETH_RING_IF_OFFSET 0x9000 113 #define BLOCK_ETH_CLKRST_CSR_OFFSET 0xc000 114 #define BLOCK_ETH_DIAG_CSR_OFFSET 0xD000 115 #define BLOCK_ETH_MAC_OFFSET 0x0000 116 #define BLOCK_ETH_MAC_CSR_OFFSET 0x2800 117 118 #define CLKEN_ADDR 0xc208 119 #define SRST_ADDR 0xc200 120 121 #define MAC_ADDR_REG_OFFSET 0x00 122 #define MAC_COMMAND_REG_OFFSET 0x04 123 #define MAC_WRITE_REG_OFFSET 0x08 124 #define MAC_READ_REG_OFFSET 0x0c 125 #define MAC_COMMAND_DONE_REG_OFFSET 0x10 126 127 #define PCS_ADDR_REG_OFFSET 0x00 128 #define PCS_COMMAND_REG_OFFSET 0x04 129 #define PCS_WRITE_REG_OFFSET 0x08 130 #define PCS_READ_REG_OFFSET 0x0c 131 #define PCS_COMMAND_DONE_REG_OFFSET 0x10 132 133 #define MII_MGMT_CONFIG_ADDR 0x20 134 #define MII_MGMT_COMMAND_ADDR 0x24 135 #define MII_MGMT_ADDRESS_ADDR 0x28 136 #define MII_MGMT_CONTROL_ADDR 0x2c 137 #define MII_MGMT_STATUS_ADDR 0x30 138 #define MII_MGMT_INDICATORS_ADDR 0x34 139 140 #define BUSY_MASK BIT(0) 141 #define READ_CYCLE_MASK BIT(0) 142 #define PHY_CONTROL_SET(dst, val) xgene_set_bits(dst, val, 0, 16) 143 144 #define ENET_SPARE_CFG_REG_ADDR 0x0750 145 #define RSIF_CONFIG_REG_ADDR 0x0010 146 #define RSIF_RAM_DBG_REG0_ADDR 0x0048 147 #define RGMII_REG_0_ADDR 0x07e0 148 #define CFG_LINK_AGGR_RESUME_0_ADDR 0x07c8 149 #define DEBUG_REG_ADDR 0x0700 150 #define CFG_BYPASS_ADDR 0x0294 151 #define CLE_BYPASS_REG0_0_ADDR 0x0490 152 #define CLE_BYPASS_REG1_0_ADDR 0x0494 153 #define CFG_RSIF_FPBUFF_TIMEOUT_EN BIT(31) 154 #define RESUME_TX BIT(0) 155 #define CFG_SPEED_1250 BIT(24) 156 #define TX_PORT0 BIT(0) 157 #define CFG_BYPASS_UNISEC_TX BIT(2) 158 #define CFG_BYPASS_UNISEC_RX BIT(1) 159 #define CFG_CLE_BYPASS_EN0 BIT(31) 160 #define CFG_TXCLK_MUXSEL0_SET(dst, val) xgene_set_bits(dst, val, 29, 3) 161 #define CFG_RXCLK_MUXSEL0_SET(dst, val) xgene_set_bits(dst, val, 26, 3) 162 163 #define CFG_CLE_IP_PROTOCOL0_SET(dst, val) xgene_set_bits(dst, val, 16, 2) 164 #define CFG_CLE_DSTQID0_SET(dst, val) xgene_set_bits(dst, val, 0, 12) 165 #define CFG_CLE_FPSEL0_SET(dst, val) xgene_set_bits(dst, val, 16, 4) 166 #define CFG_MACMODE_SET(dst, val) xgene_set_bits(dst, val, 18, 2) 167 #define CFG_WAITASYNCRD_SET(dst, val) xgene_set_bits(dst, val, 0, 16) 168 #define CFG_CLE_DSTQID0(val) (val & GENMASK(11, 0)) 169 #define CFG_CLE_FPSEL0(val) ((val << 16) & GENMASK(19, 16)) 170 #define ICM_CONFIG0_REG_0_ADDR 0x0400 171 #define ICM_CONFIG2_REG_0_ADDR 0x0410 172 #define RX_DV_GATE_REG_0_ADDR 0x05fc 173 #define TX_DV_GATE_EN0 BIT(2) 174 #define RX_DV_GATE_EN0 BIT(1) 175 #define RESUME_RX0 BIT(0) 176 #define ENET_CFGSSQMIFPRESET_ADDR 0x14 177 #define ENET_CFGSSQMIWQRESET_ADDR 0x1c 178 #define ENET_CFGSSQMIWQASSOC_ADDR 0xe0 179 #define ENET_CFGSSQMIFPQASSOC_ADDR 0xdc 180 #define ENET_CFGSSQMIQMLITEFPQASSOC_ADDR 0xf0 181 #define ENET_CFGSSQMIQMLITEWQASSOC_ADDR 0xf4 182 #define ENET_CFG_MEM_RAM_SHUTDOWN_ADDR 0x70 183 #define ENET_BLOCK_MEM_RDY_ADDR 0x74 184 #define MAC_CONFIG_1_ADDR 0x00 185 #define MAC_CONFIG_2_ADDR 0x04 186 #define MAX_FRAME_LEN_ADDR 0x10 187 #define INTERFACE_CONTROL_ADDR 0x38 188 #define STATION_ADDR0_ADDR 0x40 189 #define STATION_ADDR1_ADDR 0x44 190 #define PHY_ADDR_SET(dst, val) xgene_set_bits(dst, val, 8, 5) 191 #define REG_ADDR_SET(dst, val) xgene_set_bits(dst, val, 0, 5) 192 #define ENET_INTERFACE_MODE2_SET(dst, val) xgene_set_bits(dst, val, 8, 2) 193 #define MGMT_CLOCK_SEL_SET(dst, val) xgene_set_bits(dst, val, 0, 3) 194 #define SOFT_RESET1 BIT(31) 195 #define TX_EN BIT(0) 196 #define RX_EN BIT(2) 197 #define ENET_LHD_MODE BIT(25) 198 #define ENET_GHD_MODE BIT(26) 199 #define FULL_DUPLEX2 BIT(0) 200 #define PAD_CRC BIT(2) 201 #define SCAN_AUTO_INCR BIT(5) 202 #define TBYT_ADDR 0x38 203 #define TPKT_ADDR 0x39 204 #define TDRP_ADDR 0x45 205 #define TFCS_ADDR 0x47 206 #define TUND_ADDR 0x4a 207 208 #define TSO_IPPROTO_TCP 1 209 210 #define USERINFO_POS 0 211 #define USERINFO_LEN 32 212 #define FPQNUM_POS 32 213 #define FPQNUM_LEN 12 214 #define ELERR_POS 46 215 #define ELERR_LEN 2 216 #define NV_POS 50 217 #define NV_LEN 1 218 #define LL_POS 51 219 #define LL_LEN 1 220 #define LERR_POS 60 221 #define LERR_LEN 3 222 #define STASH_POS 52 223 #define STASH_LEN 2 224 #define BUFDATALEN_POS 48 225 #define BUFDATALEN_LEN 15 226 #define DATAADDR_POS 0 227 #define DATAADDR_LEN 42 228 #define COHERENT_POS 63 229 #define HENQNUM_POS 48 230 #define HENQNUM_LEN 12 231 #define TYPESEL_POS 44 232 #define TYPESEL_LEN 4 233 #define ETHHDR_POS 12 234 #define ETHHDR_LEN 8 235 #define IC_POS 35 /* Insert CRC */ 236 #define TCPHDR_POS 0 237 #define TCPHDR_LEN 6 238 #define IPHDR_POS 6 239 #define IPHDR_LEN 6 240 #define MSS_POS 20 241 #define MSS_LEN 2 242 #define EC_POS 22 /* Enable checksum */ 243 #define EC_LEN 1 244 #define ET_POS 23 /* Enable TSO */ 245 #define IS_POS 24 /* IP protocol select */ 246 #define IS_LEN 1 247 #define TYPE_ETH_WORK_MESSAGE_POS 44 248 #define LL_BYTES_MSB_POS 56 249 #define LL_BYTES_MSB_LEN 8 250 #define LL_BYTES_LSB_POS 48 251 #define LL_BYTES_LSB_LEN 12 252 #define LL_LEN_POS 48 253 #define LL_LEN_LEN 8 254 #define DATALEN_MASK GENMASK(11, 0) 255 256 #define LAST_BUFFER (0x7800ULL << BUFDATALEN_POS) 257 258 #define TSO_MSS0_POS 0 259 #define TSO_MSS0_LEN 14 260 #define TSO_MSS1_POS 16 261 #define TSO_MSS1_LEN 14 262 263 struct xgene_enet_raw_desc { 264 __le64 m0; 265 __le64 m1; 266 __le64 m2; 267 __le64 m3; 268 }; 269 270 struct xgene_enet_raw_desc16 { 271 __le64 m0; 272 __le64 m1; 273 }; 274 275 static inline void xgene_enet_mark_desc_slot_empty(void *desc_slot_ptr) 276 { 277 __le64 *desc_slot = desc_slot_ptr; 278 279 desc_slot[EMPTY_SLOT_INDEX] = cpu_to_le64(EMPTY_SLOT); 280 } 281 282 static inline bool xgene_enet_is_desc_slot_empty(void *desc_slot_ptr) 283 { 284 __le64 *desc_slot = desc_slot_ptr; 285 286 return (desc_slot[EMPTY_SLOT_INDEX] == cpu_to_le64(EMPTY_SLOT)); 287 } 288 289 enum xgene_enet_ring_cfgsize { 290 RING_CFGSIZE_512B, 291 RING_CFGSIZE_2KB, 292 RING_CFGSIZE_16KB, 293 RING_CFGSIZE_64KB, 294 RING_CFGSIZE_512KB, 295 RING_CFGSIZE_INVALID 296 }; 297 298 enum xgene_enet_ring_type { 299 RING_DISABLED, 300 RING_REGULAR, 301 RING_BUFPOOL 302 }; 303 304 enum xgene_ring_owner { 305 RING_OWNER_ETH0, 306 RING_OWNER_ETH1, 307 RING_OWNER_CPU = 15, 308 RING_OWNER_INVALID 309 }; 310 311 enum xgene_enet_ring_bufnum { 312 RING_BUFNUM_REGULAR = 0x0, 313 RING_BUFNUM_BUFPOOL = 0x20, 314 RING_BUFNUM_INVALID 315 }; 316 317 enum xgene_enet_err_code { 318 HBF_READ_DATA = 3, 319 HBF_LL_READ = 4, 320 BAD_WORK_MSG = 6, 321 BUFPOOL_TIMEOUT = 15, 322 INGRESS_CRC = 16, 323 INGRESS_CHECKSUM = 17, 324 INGRESS_TRUNC_FRAME = 18, 325 INGRESS_PKT_LEN = 19, 326 INGRESS_PKT_UNDER = 20, 327 INGRESS_FIFO_OVERRUN = 21, 328 INGRESS_CHECKSUM_COMPUTE = 26, 329 ERR_CODE_INVALID 330 }; 331 332 static inline enum xgene_ring_owner xgene_enet_ring_owner(u16 id) 333 { 334 return (id & RING_OWNER_MASK) >> 6; 335 } 336 337 static inline u8 xgene_enet_ring_bufnum(u16 id) 338 { 339 return id & RING_BUFNUM_MASK; 340 } 341 342 static inline bool xgene_enet_is_bufpool(u16 id) 343 { 344 return ((id & RING_BUFNUM_MASK) >= 0x20) ? true : false; 345 } 346 347 static inline u16 xgene_enet_get_numslots(u16 id, u32 size) 348 { 349 bool is_bufpool = xgene_enet_is_bufpool(id); 350 351 return (is_bufpool) ? size / BUFPOOL_DESC_SIZE : 352 size / WORK_DESC_SIZE; 353 } 354 355 void xgene_enet_parse_error(struct xgene_enet_desc_ring *ring, 356 struct xgene_enet_pdata *pdata, 357 enum xgene_enet_err_code status); 358 359 int xgene_enet_mdio_config(struct xgene_enet_pdata *pdata); 360 void xgene_enet_mdio_remove(struct xgene_enet_pdata *pdata); 361 bool xgene_ring_mgr_init(struct xgene_enet_pdata *p); 362 int xgene_enet_phy_connect(struct net_device *ndev); 363 void xgene_enet_phy_disconnect(struct xgene_enet_pdata *pdata); 364 365 extern const struct xgene_mac_ops xgene_gmac_ops; 366 extern const struct xgene_port_ops xgene_gport_ops; 367 extern struct xgene_ring_ops xgene_ring1_ops; 368 369 #endif /* __XGENE_ENET_HW_H__ */ 370