1 /* Applied Micro X-Gene SoC Ethernet Driver 2 * 3 * Copyright (c) 2014, Applied Micro Circuits Corporation 4 * Authors: Iyappan Subramanian <isubramanian@apm.com> 5 * Ravi Patel <rapatel@apm.com> 6 * Keyur Chudgar <kchudgar@apm.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program. If not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #ifndef __XGENE_ENET_HW_H__ 23 #define __XGENE_ENET_HW_H__ 24 25 #include "xgene_enet_main.h" 26 27 struct xgene_enet_pdata; 28 struct xgene_enet_stats; 29 struct xgene_enet_desc_ring; 30 31 /* clears and then set bits */ 32 static inline void xgene_set_bits(u32 *dst, u32 val, u32 start, u32 len) 33 { 34 u32 end = start + len - 1; 35 u32 mask = GENMASK(end, start); 36 37 *dst &= ~mask; 38 *dst |= (val << start) & mask; 39 } 40 41 static inline u32 xgene_get_bits(u32 val, u32 start, u32 end) 42 { 43 return (val & GENMASK(end, start)) >> start; 44 } 45 46 enum xgene_enet_rm { 47 RM0, 48 RM1, 49 RM3 = 3 50 }; 51 52 #define CSR_RING_ID 0x0008 53 #define OVERWRITE BIT(31) 54 #define IS_BUFFER_POOL BIT(20) 55 #define PREFETCH_BUF_EN BIT(21) 56 #define CSR_RING_ID_BUF 0x000c 57 #define CSR_PBM_COAL 0x0014 58 #define CSR_PBM_CTICK1 0x001c 59 #define CSR_PBM_CTICK2 0x0020 60 #define CSR_THRESHOLD0_SET1 0x0030 61 #define CSR_THRESHOLD1_SET1 0x0034 62 #define CSR_RING_NE_INT_MODE 0x017c 63 #define CSR_RING_CONFIG 0x006c 64 #define CSR_RING_WR_BASE 0x0070 65 #define NUM_RING_CONFIG 5 66 #define BUFPOOL_MODE 3 67 #define INC_DEC_CMD_ADDR 0x002c 68 #define UDP_HDR_SIZE 2 69 #define BUF_LEN_CODE_2K 0x5000 70 71 #define CREATE_MASK(pos, len) GENMASK((pos)+(len)-1, (pos)) 72 #define CREATE_MASK_ULL(pos, len) GENMASK_ULL((pos)+(len)-1, (pos)) 73 74 /* Empty slot soft signature */ 75 #define EMPTY_SLOT_INDEX 1 76 #define EMPTY_SLOT ~0ULL 77 78 #define WORK_DESC_SIZE 32 79 #define BUFPOOL_DESC_SIZE 16 80 81 #define RING_OWNER_MASK GENMASK(9, 6) 82 #define RING_BUFNUM_MASK GENMASK(5, 0) 83 84 #define SELTHRSH_POS 3 85 #define SELTHRSH_LEN 3 86 #define RINGADDRL_POS 5 87 #define RINGADDRL_LEN 27 88 #define RINGADDRH_POS 0 89 #define RINGADDRH_LEN 7 90 #define RINGSIZE_POS 23 91 #define RINGSIZE_LEN 3 92 #define RINGTYPE_POS 19 93 #define RINGTYPE_LEN 2 94 #define RINGMODE_POS 20 95 #define RINGMODE_LEN 3 96 #define RECOMTIMEOUTL_POS 28 97 #define RECOMTIMEOUTL_LEN 4 98 #define RECOMTIMEOUTH_POS 0 99 #define RECOMTIMEOUTH_LEN 3 100 #define NUMMSGSINQ_POS 1 101 #define NUMMSGSINQ_LEN 16 102 #define ACCEPTLERR BIT(19) 103 #define QCOHERENT BIT(4) 104 #define RECOMBBUF BIT(27) 105 106 #define MAC_OFFSET 0x30 107 #define OFFSET_4 0x04 108 #define OFFSET_8 0x08 109 110 #define BLOCK_ETH_CSR_OFFSET 0x2000 111 #define BLOCK_ETH_CLE_CSR_OFFSET 0x6000 112 #define BLOCK_ETH_RING_IF_OFFSET 0x9000 113 #define BLOCK_ETH_CLKRST_CSR_OFFSET 0xc000 114 #define BLOCK_ETH_DIAG_CSR_OFFSET 0xD000 115 #define BLOCK_ETH_MAC_OFFSET 0x0000 116 #define BLOCK_ETH_MAC_CSR_OFFSET 0x2800 117 118 #define CLKEN_ADDR 0xc208 119 #define SRST_ADDR 0xc200 120 121 #define MAC_ADDR_REG_OFFSET 0x00 122 #define MAC_COMMAND_REG_OFFSET 0x04 123 #define MAC_WRITE_REG_OFFSET 0x08 124 #define MAC_READ_REG_OFFSET 0x0c 125 #define MAC_COMMAND_DONE_REG_OFFSET 0x10 126 127 #define MII_MGMT_CONFIG_ADDR 0x20 128 #define MII_MGMT_COMMAND_ADDR 0x24 129 #define MII_MGMT_ADDRESS_ADDR 0x28 130 #define MII_MGMT_CONTROL_ADDR 0x2c 131 #define MII_MGMT_STATUS_ADDR 0x30 132 #define MII_MGMT_INDICATORS_ADDR 0x34 133 134 #define BUSY_MASK BIT(0) 135 #define READ_CYCLE_MASK BIT(0) 136 #define PHY_CONTROL_SET(dst, val) xgene_set_bits(dst, val, 0, 16) 137 138 #define ENET_SPARE_CFG_REG_ADDR 0x0750 139 #define RSIF_CONFIG_REG_ADDR 0x0010 140 #define RSIF_RAM_DBG_REG0_ADDR 0x0048 141 #define RGMII_REG_0_ADDR 0x07e0 142 #define CFG_LINK_AGGR_RESUME_0_ADDR 0x07c8 143 #define DEBUG_REG_ADDR 0x0700 144 #define CFG_BYPASS_ADDR 0x0294 145 #define CLE_BYPASS_REG0_0_ADDR 0x0490 146 #define CLE_BYPASS_REG1_0_ADDR 0x0494 147 #define CFG_RSIF_FPBUFF_TIMEOUT_EN BIT(31) 148 #define RESUME_TX BIT(0) 149 #define CFG_SPEED_1250 BIT(24) 150 #define TX_PORT0 BIT(0) 151 #define CFG_BYPASS_UNISEC_TX BIT(2) 152 #define CFG_BYPASS_UNISEC_RX BIT(1) 153 #define CFG_CLE_BYPASS_EN0 BIT(31) 154 #define CFG_TXCLK_MUXSEL0_SET(dst, val) xgene_set_bits(dst, val, 29, 3) 155 #define CFG_RXCLK_MUXSEL0_SET(dst, val) xgene_set_bits(dst, val, 26, 3) 156 157 #define CFG_CLE_IP_PROTOCOL0_SET(dst, val) xgene_set_bits(dst, val, 16, 2) 158 #define CFG_CLE_DSTQID0_SET(dst, val) xgene_set_bits(dst, val, 0, 12) 159 #define CFG_CLE_FPSEL0_SET(dst, val) xgene_set_bits(dst, val, 16, 4) 160 #define CFG_MACMODE_SET(dst, val) xgene_set_bits(dst, val, 18, 2) 161 #define CFG_WAITASYNCRD_SET(dst, val) xgene_set_bits(dst, val, 0, 16) 162 #define CFG_CLE_DSTQID0(val) (val & GENMASK(11, 0)) 163 #define CFG_CLE_FPSEL0(val) ((val << 16) & GENMASK(19, 16)) 164 #define ICM_CONFIG0_REG_0_ADDR 0x0400 165 #define ICM_CONFIG2_REG_0_ADDR 0x0410 166 #define RX_DV_GATE_REG_0_ADDR 0x05fc 167 #define TX_DV_GATE_EN0 BIT(2) 168 #define RX_DV_GATE_EN0 BIT(1) 169 #define RESUME_RX0 BIT(0) 170 #define ENET_CFGSSQMIFPRESET_ADDR 0x14 171 #define ENET_CFGSSQMIWQRESET_ADDR 0x1c 172 #define ENET_CFGSSQMIWQASSOC_ADDR 0xe0 173 #define ENET_CFGSSQMIFPQASSOC_ADDR 0xdc 174 #define ENET_CFGSSQMIQMLITEFPQASSOC_ADDR 0xf0 175 #define ENET_CFGSSQMIQMLITEWQASSOC_ADDR 0xf4 176 #define ENET_CFG_MEM_RAM_SHUTDOWN_ADDR 0x70 177 #define ENET_BLOCK_MEM_RDY_ADDR 0x74 178 #define MAC_CONFIG_1_ADDR 0x00 179 #define MAC_CONFIG_2_ADDR 0x04 180 #define MAX_FRAME_LEN_ADDR 0x10 181 #define INTERFACE_CONTROL_ADDR 0x38 182 #define STATION_ADDR0_ADDR 0x40 183 #define STATION_ADDR1_ADDR 0x44 184 #define PHY_ADDR_SET(dst, val) xgene_set_bits(dst, val, 8, 5) 185 #define REG_ADDR_SET(dst, val) xgene_set_bits(dst, val, 0, 5) 186 #define ENET_INTERFACE_MODE2_SET(dst, val) xgene_set_bits(dst, val, 8, 2) 187 #define MGMT_CLOCK_SEL_SET(dst, val) xgene_set_bits(dst, val, 0, 3) 188 #define SOFT_RESET1 BIT(31) 189 #define TX_EN BIT(0) 190 #define RX_EN BIT(2) 191 #define ENET_LHD_MODE BIT(25) 192 #define ENET_GHD_MODE BIT(26) 193 #define FULL_DUPLEX2 BIT(0) 194 #define PAD_CRC BIT(2) 195 #define SCAN_AUTO_INCR BIT(5) 196 #define TBYT_ADDR 0x38 197 #define TPKT_ADDR 0x39 198 #define TDRP_ADDR 0x45 199 #define TFCS_ADDR 0x47 200 #define TUND_ADDR 0x4a 201 202 #define TSO_IPPROTO_TCP 1 203 204 #define USERINFO_POS 0 205 #define USERINFO_LEN 32 206 #define FPQNUM_POS 32 207 #define FPQNUM_LEN 12 208 #define ELERR_POS 46 209 #define ELERR_LEN 2 210 #define NV_POS 50 211 #define NV_LEN 1 212 #define LL_POS 51 213 #define LL_LEN 1 214 #define LERR_POS 60 215 #define LERR_LEN 3 216 #define STASH_POS 52 217 #define STASH_LEN 2 218 #define BUFDATALEN_POS 48 219 #define BUFDATALEN_LEN 15 220 #define DATAADDR_POS 0 221 #define DATAADDR_LEN 42 222 #define COHERENT_POS 63 223 #define HENQNUM_POS 48 224 #define HENQNUM_LEN 12 225 #define TYPESEL_POS 44 226 #define TYPESEL_LEN 4 227 #define ETHHDR_POS 12 228 #define ETHHDR_LEN 8 229 #define IC_POS 35 /* Insert CRC */ 230 #define TCPHDR_POS 0 231 #define TCPHDR_LEN 6 232 #define IPHDR_POS 6 233 #define IPHDR_LEN 6 234 #define EC_POS 22 /* Enable checksum */ 235 #define EC_LEN 1 236 #define ET_POS 23 /* Enable TSO */ 237 #define IS_POS 24 /* IP protocol select */ 238 #define IS_LEN 1 239 #define TYPE_ETH_WORK_MESSAGE_POS 44 240 #define LL_BYTES_MSB_POS 56 241 #define LL_BYTES_MSB_LEN 8 242 #define LL_BYTES_LSB_POS 48 243 #define LL_BYTES_LSB_LEN 12 244 #define LL_LEN_POS 48 245 #define LL_LEN_LEN 8 246 #define DATALEN_MASK GENMASK(11, 0) 247 248 #define LAST_BUFFER (0x7800ULL << BUFDATALEN_POS) 249 250 struct xgene_enet_raw_desc { 251 __le64 m0; 252 __le64 m1; 253 __le64 m2; 254 __le64 m3; 255 }; 256 257 struct xgene_enet_raw_desc16 { 258 __le64 m0; 259 __le64 m1; 260 }; 261 262 static inline void xgene_enet_mark_desc_slot_empty(void *desc_slot_ptr) 263 { 264 __le64 *desc_slot = desc_slot_ptr; 265 266 desc_slot[EMPTY_SLOT_INDEX] = cpu_to_le64(EMPTY_SLOT); 267 } 268 269 static inline bool xgene_enet_is_desc_slot_empty(void *desc_slot_ptr) 270 { 271 __le64 *desc_slot = desc_slot_ptr; 272 273 return (desc_slot[EMPTY_SLOT_INDEX] == cpu_to_le64(EMPTY_SLOT)); 274 } 275 276 enum xgene_enet_ring_cfgsize { 277 RING_CFGSIZE_512B, 278 RING_CFGSIZE_2KB, 279 RING_CFGSIZE_16KB, 280 RING_CFGSIZE_64KB, 281 RING_CFGSIZE_512KB, 282 RING_CFGSIZE_INVALID 283 }; 284 285 enum xgene_enet_ring_type { 286 RING_DISABLED, 287 RING_REGULAR, 288 RING_BUFPOOL 289 }; 290 291 enum xgene_ring_owner { 292 RING_OWNER_ETH0, 293 RING_OWNER_ETH1, 294 RING_OWNER_CPU = 15, 295 RING_OWNER_INVALID 296 }; 297 298 enum xgene_enet_ring_bufnum { 299 RING_BUFNUM_REGULAR = 0x0, 300 RING_BUFNUM_BUFPOOL = 0x20, 301 RING_BUFNUM_INVALID 302 }; 303 304 enum xgene_enet_err_code { 305 HBF_READ_DATA = 3, 306 HBF_LL_READ = 4, 307 BAD_WORK_MSG = 6, 308 BUFPOOL_TIMEOUT = 15, 309 INGRESS_CRC = 16, 310 INGRESS_CHECKSUM = 17, 311 INGRESS_TRUNC_FRAME = 18, 312 INGRESS_PKT_LEN = 19, 313 INGRESS_PKT_UNDER = 20, 314 INGRESS_FIFO_OVERRUN = 21, 315 INGRESS_CHECKSUM_COMPUTE = 26, 316 ERR_CODE_INVALID 317 }; 318 319 static inline enum xgene_ring_owner xgene_enet_ring_owner(u16 id) 320 { 321 return (id & RING_OWNER_MASK) >> 6; 322 } 323 324 static inline u8 xgene_enet_ring_bufnum(u16 id) 325 { 326 return id & RING_BUFNUM_MASK; 327 } 328 329 static inline bool xgene_enet_is_bufpool(u16 id) 330 { 331 return ((id & RING_BUFNUM_MASK) >= 0x20) ? true : false; 332 } 333 334 static inline u16 xgene_enet_get_numslots(u16 id, u32 size) 335 { 336 bool is_bufpool = xgene_enet_is_bufpool(id); 337 338 return (is_bufpool) ? size / BUFPOOL_DESC_SIZE : 339 size / WORK_DESC_SIZE; 340 } 341 342 void xgene_enet_parse_error(struct xgene_enet_desc_ring *ring, 343 struct xgene_enet_pdata *pdata, 344 enum xgene_enet_err_code status); 345 346 int xgene_enet_mdio_config(struct xgene_enet_pdata *pdata); 347 void xgene_enet_mdio_remove(struct xgene_enet_pdata *pdata); 348 bool xgene_ring_mgr_init(struct xgene_enet_pdata *p); 349 int xgene_enet_phy_connect(struct net_device *ndev); 350 void xgene_enet_phy_disconnect(struct xgene_enet_pdata *pdata); 351 352 extern const struct xgene_mac_ops xgene_gmac_ops; 353 extern const struct xgene_port_ops xgene_gport_ops; 354 extern struct xgene_ring_ops xgene_ring1_ops; 355 356 #endif /* __XGENE_ENET_HW_H__ */ 357