1 /* Applied Micro X-Gene SoC Ethernet Driver 2 * 3 * Copyright (c) 2014, Applied Micro Circuits Corporation 4 * Authors: Iyappan Subramanian <isubramanian@apm.com> 5 * Ravi Patel <rapatel@apm.com> 6 * Keyur Chudgar <kchudgar@apm.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program. If not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #ifndef __XGENE_ENET_HW_H__ 23 #define __XGENE_ENET_HW_H__ 24 25 #include "xgene_enet_main.h" 26 27 struct xgene_enet_pdata; 28 struct xgene_enet_stats; 29 struct xgene_enet_desc_ring; 30 31 /* clears and then set bits */ 32 static inline void xgene_set_bits(u32 *dst, u32 val, u32 start, u32 len) 33 { 34 u32 end = start + len - 1; 35 u32 mask = GENMASK(end, start); 36 37 *dst &= ~mask; 38 *dst |= (val << start) & mask; 39 } 40 41 static inline u32 xgene_get_bits(u32 val, u32 start, u32 end) 42 { 43 return (val & GENMASK(end, start)) >> start; 44 } 45 46 enum xgene_enet_rm { 47 RM0, 48 RM1, 49 RM3 = 3 50 }; 51 52 #define CSR_RING_ID 0x0008 53 #define OVERWRITE BIT(31) 54 #define IS_BUFFER_POOL BIT(20) 55 #define PREFETCH_BUF_EN BIT(21) 56 #define CSR_RING_ID_BUF 0x000c 57 #define CSR_RING_NE_INT_MODE 0x017c 58 #define CSR_RING_CONFIG 0x006c 59 #define CSR_RING_WR_BASE 0x0070 60 #define NUM_RING_CONFIG 5 61 #define BUFPOOL_MODE 3 62 #define INC_DEC_CMD_ADDR 0x002c 63 #define UDP_HDR_SIZE 2 64 #define BUF_LEN_CODE_2K 0x5000 65 66 #define CREATE_MASK(pos, len) GENMASK((pos)+(len)-1, (pos)) 67 #define CREATE_MASK_ULL(pos, len) GENMASK_ULL((pos)+(len)-1, (pos)) 68 69 /* Empty slot soft signature */ 70 #define EMPTY_SLOT_INDEX 1 71 #define EMPTY_SLOT ~0ULL 72 73 #define WORK_DESC_SIZE 32 74 #define BUFPOOL_DESC_SIZE 16 75 76 #define RING_OWNER_MASK GENMASK(9, 6) 77 #define RING_BUFNUM_MASK GENMASK(5, 0) 78 79 #define SELTHRSH_POS 3 80 #define SELTHRSH_LEN 3 81 #define RINGADDRL_POS 5 82 #define RINGADDRL_LEN 27 83 #define RINGADDRH_POS 0 84 #define RINGADDRH_LEN 6 85 #define RINGSIZE_POS 23 86 #define RINGSIZE_LEN 3 87 #define RINGTYPE_POS 19 88 #define RINGTYPE_LEN 2 89 #define RINGMODE_POS 20 90 #define RINGMODE_LEN 3 91 #define RECOMTIMEOUTL_POS 28 92 #define RECOMTIMEOUTL_LEN 3 93 #define RECOMTIMEOUTH_POS 0 94 #define RECOMTIMEOUTH_LEN 2 95 #define NUMMSGSINQ_POS 1 96 #define NUMMSGSINQ_LEN 16 97 #define ACCEPTLERR BIT(19) 98 #define QCOHERENT BIT(4) 99 #define RECOMBBUF BIT(27) 100 101 #define MAC_OFFSET 0x30 102 103 #define BLOCK_ETH_CSR_OFFSET 0x2000 104 #define BLOCK_ETH_RING_IF_OFFSET 0x9000 105 #define BLOCK_ETH_CLKRST_CSR_OFFSET 0xc000 106 #define BLOCK_ETH_DIAG_CSR_OFFSET 0xD000 107 #define BLOCK_ETH_MAC_OFFSET 0x0000 108 #define BLOCK_ETH_MAC_CSR_OFFSET 0x2800 109 110 #define CLKEN_ADDR 0xc208 111 #define SRST_ADDR 0xc200 112 113 #define MAC_ADDR_REG_OFFSET 0x00 114 #define MAC_COMMAND_REG_OFFSET 0x04 115 #define MAC_WRITE_REG_OFFSET 0x08 116 #define MAC_READ_REG_OFFSET 0x0c 117 #define MAC_COMMAND_DONE_REG_OFFSET 0x10 118 119 #define MII_MGMT_CONFIG_ADDR 0x20 120 #define MII_MGMT_COMMAND_ADDR 0x24 121 #define MII_MGMT_ADDRESS_ADDR 0x28 122 #define MII_MGMT_CONTROL_ADDR 0x2c 123 #define MII_MGMT_STATUS_ADDR 0x30 124 #define MII_MGMT_INDICATORS_ADDR 0x34 125 126 #define BUSY_MASK BIT(0) 127 #define READ_CYCLE_MASK BIT(0) 128 #define PHY_CONTROL_SET(dst, val) xgene_set_bits(dst, val, 0, 16) 129 130 #define ENET_SPARE_CFG_REG_ADDR 0x0750 131 #define RSIF_CONFIG_REG_ADDR 0x0010 132 #define RSIF_RAM_DBG_REG0_ADDR 0x0048 133 #define RGMII_REG_0_ADDR 0x07e0 134 #define CFG_LINK_AGGR_RESUME_0_ADDR 0x07c8 135 #define DEBUG_REG_ADDR 0x0700 136 #define CFG_BYPASS_ADDR 0x0294 137 #define CLE_BYPASS_REG0_0_ADDR 0x0490 138 #define CLE_BYPASS_REG1_0_ADDR 0x0494 139 #define CFG_RSIF_FPBUFF_TIMEOUT_EN BIT(31) 140 #define RESUME_TX BIT(0) 141 #define CFG_SPEED_1250 BIT(24) 142 #define TX_PORT0 BIT(0) 143 #define CFG_BYPASS_UNISEC_TX BIT(2) 144 #define CFG_BYPASS_UNISEC_RX BIT(1) 145 #define CFG_CLE_BYPASS_EN0 BIT(31) 146 #define CFG_TXCLK_MUXSEL0_SET(dst, val) xgene_set_bits(dst, val, 29, 3) 147 148 #define CFG_CLE_IP_PROTOCOL0_SET(dst, val) xgene_set_bits(dst, val, 16, 2) 149 #define CFG_CLE_DSTQID0_SET(dst, val) xgene_set_bits(dst, val, 0, 12) 150 #define CFG_CLE_FPSEL0_SET(dst, val) xgene_set_bits(dst, val, 16, 4) 151 #define CFG_MACMODE_SET(dst, val) xgene_set_bits(dst, val, 18, 2) 152 #define CFG_WAITASYNCRD_SET(dst, val) xgene_set_bits(dst, val, 0, 16) 153 #define CFG_CLE_DSTQID0(val) (val & GENMASK(11, 0)) 154 #define CFG_CLE_FPSEL0(val) ((val << 16) & GENMASK(19, 16)) 155 #define ICM_CONFIG0_REG_0_ADDR 0x0400 156 #define ICM_CONFIG2_REG_0_ADDR 0x0410 157 #define RX_DV_GATE_REG_0_ADDR 0x05fc 158 #define TX_DV_GATE_EN0 BIT(2) 159 #define RX_DV_GATE_EN0 BIT(1) 160 #define RESUME_RX0 BIT(0) 161 #define ENET_CFGSSQMIWQASSOC_ADDR 0xe0 162 #define ENET_CFGSSQMIFPQASSOC_ADDR 0xdc 163 #define ENET_CFGSSQMIQMLITEFPQASSOC_ADDR 0xf0 164 #define ENET_CFGSSQMIQMLITEWQASSOC_ADDR 0xf4 165 #define ENET_CFG_MEM_RAM_SHUTDOWN_ADDR 0x70 166 #define ENET_BLOCK_MEM_RDY_ADDR 0x74 167 #define MAC_CONFIG_1_ADDR 0x00 168 #define MAC_CONFIG_2_ADDR 0x04 169 #define MAX_FRAME_LEN_ADDR 0x10 170 #define INTERFACE_CONTROL_ADDR 0x38 171 #define STATION_ADDR0_ADDR 0x40 172 #define STATION_ADDR1_ADDR 0x44 173 #define PHY_ADDR_SET(dst, val) xgene_set_bits(dst, val, 8, 5) 174 #define REG_ADDR_SET(dst, val) xgene_set_bits(dst, val, 0, 5) 175 #define ENET_INTERFACE_MODE2_SET(dst, val) xgene_set_bits(dst, val, 8, 2) 176 #define MGMT_CLOCK_SEL_SET(dst, val) xgene_set_bits(dst, val, 0, 3) 177 #define SOFT_RESET1 BIT(31) 178 #define TX_EN BIT(0) 179 #define RX_EN BIT(2) 180 #define ENET_LHD_MODE BIT(25) 181 #define ENET_GHD_MODE BIT(26) 182 #define FULL_DUPLEX2 BIT(0) 183 #define SCAN_AUTO_INCR BIT(5) 184 #define TBYT_ADDR 0x38 185 #define TPKT_ADDR 0x39 186 #define TDRP_ADDR 0x45 187 #define TFCS_ADDR 0x47 188 #define TUND_ADDR 0x4a 189 190 #define TSO_IPPROTO_TCP 1 191 192 #define USERINFO_POS 0 193 #define USERINFO_LEN 32 194 #define FPQNUM_POS 32 195 #define FPQNUM_LEN 12 196 #define LERR_POS 60 197 #define LERR_LEN 3 198 #define STASH_POS 52 199 #define STASH_LEN 2 200 #define BUFDATALEN_POS 48 201 #define BUFDATALEN_LEN 12 202 #define DATAADDR_POS 0 203 #define DATAADDR_LEN 42 204 #define COHERENT_POS 63 205 #define HENQNUM_POS 48 206 #define HENQNUM_LEN 12 207 #define TYPESEL_POS 44 208 #define TYPESEL_LEN 4 209 #define ETHHDR_POS 12 210 #define ETHHDR_LEN 8 211 #define IC_POS 35 /* Insert CRC */ 212 #define TCPHDR_POS 0 213 #define TCPHDR_LEN 6 214 #define IPHDR_POS 6 215 #define IPHDR_LEN 6 216 #define EC_POS 22 /* Enable checksum */ 217 #define EC_LEN 1 218 #define IS_POS 24 /* IP protocol select */ 219 #define IS_LEN 1 220 #define TYPE_ETH_WORK_MESSAGE_POS 44 221 222 struct xgene_enet_raw_desc { 223 __le64 m0; 224 __le64 m1; 225 __le64 m2; 226 __le64 m3; 227 }; 228 229 struct xgene_enet_raw_desc16 { 230 __le64 m0; 231 __le64 m1; 232 }; 233 234 static inline void xgene_enet_mark_desc_slot_empty(void *desc_slot_ptr) 235 { 236 __le64 *desc_slot = desc_slot_ptr; 237 238 desc_slot[EMPTY_SLOT_INDEX] = cpu_to_le64(EMPTY_SLOT); 239 } 240 241 static inline bool xgene_enet_is_desc_slot_empty(void *desc_slot_ptr) 242 { 243 __le64 *desc_slot = desc_slot_ptr; 244 245 return (desc_slot[EMPTY_SLOT_INDEX] == cpu_to_le64(EMPTY_SLOT)); 246 } 247 248 enum xgene_enet_ring_cfgsize { 249 RING_CFGSIZE_512B, 250 RING_CFGSIZE_2KB, 251 RING_CFGSIZE_16KB, 252 RING_CFGSIZE_64KB, 253 RING_CFGSIZE_512KB, 254 RING_CFGSIZE_INVALID 255 }; 256 257 enum xgene_enet_ring_type { 258 RING_DISABLED, 259 RING_REGULAR, 260 RING_BUFPOOL 261 }; 262 263 enum xgene_ring_owner { 264 RING_OWNER_ETH0, 265 RING_OWNER_ETH1, 266 RING_OWNER_CPU = 15, 267 RING_OWNER_INVALID 268 }; 269 270 enum xgene_enet_ring_bufnum { 271 RING_BUFNUM_REGULAR = 0x0, 272 RING_BUFNUM_BUFPOOL = 0x20, 273 RING_BUFNUM_INVALID 274 }; 275 276 enum xgene_enet_cmd { 277 XGENE_ENET_WR_CMD = BIT(31), 278 XGENE_ENET_RD_CMD = BIT(30) 279 }; 280 281 enum xgene_enet_err_code { 282 HBF_READ_DATA = 3, 283 HBF_LL_READ = 4, 284 BAD_WORK_MSG = 6, 285 BUFPOOL_TIMEOUT = 15, 286 INGRESS_CRC = 16, 287 INGRESS_CHECKSUM = 17, 288 INGRESS_TRUNC_FRAME = 18, 289 INGRESS_PKT_LEN = 19, 290 INGRESS_PKT_UNDER = 20, 291 INGRESS_FIFO_OVERRUN = 21, 292 INGRESS_CHECKSUM_COMPUTE = 26, 293 ERR_CODE_INVALID 294 }; 295 296 static inline enum xgene_ring_owner xgene_enet_ring_owner(u16 id) 297 { 298 return (id & RING_OWNER_MASK) >> 6; 299 } 300 301 static inline u8 xgene_enet_ring_bufnum(u16 id) 302 { 303 return id & RING_BUFNUM_MASK; 304 } 305 306 static inline bool xgene_enet_is_bufpool(u16 id) 307 { 308 return ((id & RING_BUFNUM_MASK) >= 0x20) ? true : false; 309 } 310 311 static inline u16 xgene_enet_get_numslots(u16 id, u32 size) 312 { 313 bool is_bufpool = xgene_enet_is_bufpool(id); 314 315 return (is_bufpool) ? size / BUFPOOL_DESC_SIZE : 316 size / WORK_DESC_SIZE; 317 } 318 319 void xgene_enet_parse_error(struct xgene_enet_desc_ring *ring, 320 struct xgene_enet_pdata *pdata, 321 enum xgene_enet_err_code status); 322 323 int xgene_enet_mdio_config(struct xgene_enet_pdata *pdata); 324 void xgene_enet_mdio_remove(struct xgene_enet_pdata *pdata); 325 bool xgene_ring_mgr_init(struct xgene_enet_pdata *p); 326 327 extern struct xgene_mac_ops xgene_gmac_ops; 328 extern struct xgene_port_ops xgene_gport_ops; 329 extern struct xgene_ring_ops xgene_ring1_ops; 330 331 #endif /* __XGENE_ENET_HW_H__ */ 332