1 /* Applied Micro X-Gene SoC Ethernet Driver 2 * 3 * Copyright (c) 2014, Applied Micro Circuits Corporation 4 * Authors: Iyappan Subramanian <isubramanian@apm.com> 5 * Ravi Patel <rapatel@apm.com> 6 * Keyur Chudgar <kchudgar@apm.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program. If not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #ifndef __XGENE_ENET_HW_H__ 23 #define __XGENE_ENET_HW_H__ 24 25 #include "xgene_enet_main.h" 26 27 struct xgene_enet_pdata; 28 struct xgene_enet_stats; 29 struct xgene_enet_desc_ring; 30 31 /* clears and then set bits */ 32 static inline void xgene_set_bits(u32 *dst, u32 val, u32 start, u32 len) 33 { 34 u32 end = start + len - 1; 35 u32 mask = GENMASK(end, start); 36 37 *dst &= ~mask; 38 *dst |= (val << start) & mask; 39 } 40 41 static inline u32 xgene_get_bits(u32 val, u32 start, u32 end) 42 { 43 return (val & GENMASK(end, start)) >> start; 44 } 45 46 enum xgene_enet_rm { 47 RM0, 48 RM1, 49 RM3 = 3 50 }; 51 52 #define CSR_RING_ID 0x0008 53 #define OVERWRITE BIT(31) 54 #define IS_BUFFER_POOL BIT(20) 55 #define PREFETCH_BUF_EN BIT(21) 56 #define CSR_RING_ID_BUF 0x000c 57 #define CSR_PBM_COAL 0x0014 58 #define CSR_PBM_CTICK0 0x0018 59 #define CSR_PBM_CTICK1 0x001c 60 #define CSR_PBM_CTICK2 0x0020 61 #define CSR_PBM_CTICK3 0x0024 62 #define CSR_THRESHOLD0_SET1 0x0030 63 #define CSR_THRESHOLD1_SET1 0x0034 64 #define CSR_RING_NE_INT_MODE 0x017c 65 #define CSR_RING_CONFIG 0x006c 66 #define CSR_RING_WR_BASE 0x0070 67 #define NUM_RING_CONFIG 5 68 #define BUFPOOL_MODE 3 69 #define INC_DEC_CMD_ADDR 0x002c 70 #define UDP_HDR_SIZE 2 71 #define BUF_LEN_CODE_2K 0x5000 72 73 #define CREATE_MASK(pos, len) GENMASK((pos)+(len)-1, (pos)) 74 #define CREATE_MASK_ULL(pos, len) GENMASK_ULL((pos)+(len)-1, (pos)) 75 76 /* Empty slot soft signature */ 77 #define EMPTY_SLOT_INDEX 1 78 #define EMPTY_SLOT ~0ULL 79 80 #define WORK_DESC_SIZE 32 81 #define BUFPOOL_DESC_SIZE 16 82 83 #define RING_OWNER_MASK GENMASK(9, 6) 84 #define RING_BUFNUM_MASK GENMASK(5, 0) 85 86 #define SELTHRSH_POS 3 87 #define SELTHRSH_LEN 3 88 #define RINGADDRL_POS 5 89 #define RINGADDRL_LEN 27 90 #define RINGADDRH_POS 0 91 #define RINGADDRH_LEN 7 92 #define RINGSIZE_POS 23 93 #define RINGSIZE_LEN 3 94 #define RINGTYPE_POS 19 95 #define RINGTYPE_LEN 2 96 #define RINGMODE_POS 20 97 #define RINGMODE_LEN 3 98 #define RECOMTIMEOUTL_POS 28 99 #define RECOMTIMEOUTL_LEN 4 100 #define RECOMTIMEOUTH_POS 0 101 #define RECOMTIMEOUTH_LEN 3 102 #define NUMMSGSINQ_POS 1 103 #define NUMMSGSINQ_LEN 16 104 #define ACCEPTLERR BIT(19) 105 #define QCOHERENT BIT(4) 106 #define RECOMBBUF BIT(27) 107 108 #define MAC_OFFSET 0x30 109 #define OFFSET_4 0x04 110 #define OFFSET_8 0x08 111 112 #define BLOCK_ETH_CSR_OFFSET 0x2000 113 #define BLOCK_ETH_CLE_CSR_OFFSET 0x6000 114 #define BLOCK_ETH_RING_IF_OFFSET 0x9000 115 #define BLOCK_ETH_CLKRST_CSR_OFFSET 0xc000 116 #define BLOCK_ETH_DIAG_CSR_OFFSET 0xD000 117 #define BLOCK_ETH_MAC_OFFSET 0x0000 118 #define BLOCK_ETH_STATS_OFFSET 0x0000 119 #define BLOCK_ETH_MAC_CSR_OFFSET 0x2800 120 121 #define CLKEN_ADDR 0xc208 122 #define SRST_ADDR 0xc200 123 124 #define MAC_ADDR_REG_OFFSET 0x00 125 #define MAC_COMMAND_REG_OFFSET 0x04 126 #define MAC_WRITE_REG_OFFSET 0x08 127 #define MAC_READ_REG_OFFSET 0x0c 128 #define MAC_COMMAND_DONE_REG_OFFSET 0x10 129 130 #define STAT_ADDR_REG_OFFSET 0x14 131 #define STAT_COMMAND_REG_OFFSET 0x18 132 #define STAT_WRITE_REG_OFFSET 0x1c 133 #define STAT_READ_REG_OFFSET 0x20 134 #define STAT_COMMAND_DONE_REG_OFFSET 0x24 135 136 #define PCS_ADDR_REG_OFFSET 0x00 137 #define PCS_COMMAND_REG_OFFSET 0x04 138 #define PCS_WRITE_REG_OFFSET 0x08 139 #define PCS_READ_REG_OFFSET 0x0c 140 #define PCS_COMMAND_DONE_REG_OFFSET 0x10 141 142 #define MII_MGMT_CONFIG_ADDR 0x20 143 #define MII_MGMT_COMMAND_ADDR 0x24 144 #define MII_MGMT_ADDRESS_ADDR 0x28 145 #define MII_MGMT_CONTROL_ADDR 0x2c 146 #define MII_MGMT_STATUS_ADDR 0x30 147 #define MII_MGMT_INDICATORS_ADDR 0x34 148 149 #define BUSY_MASK BIT(0) 150 #define READ_CYCLE_MASK BIT(0) 151 #define PHY_CONTROL_SET(dst, val) xgene_set_bits(dst, val, 0, 16) 152 153 #define ENET_SPARE_CFG_REG_ADDR 0x0750 154 #define RSIF_CONFIG_REG_ADDR 0x0010 155 #define RSIF_RAM_DBG_REG0_ADDR 0x0048 156 #define RGMII_REG_0_ADDR 0x07e0 157 #define CFG_LINK_AGGR_RESUME_0_ADDR 0x07c8 158 #define DEBUG_REG_ADDR 0x0700 159 #define CFG_BYPASS_ADDR 0x0294 160 #define CLE_BYPASS_REG0_0_ADDR 0x0490 161 #define CLE_BYPASS_REG1_0_ADDR 0x0494 162 #define CFG_RSIF_FPBUFF_TIMEOUT_EN BIT(31) 163 #define RESUME_TX BIT(0) 164 #define CFG_SPEED_1250 BIT(24) 165 #define TX_PORT0 BIT(0) 166 #define CFG_BYPASS_UNISEC_TX BIT(2) 167 #define CFG_BYPASS_UNISEC_RX BIT(1) 168 #define CFG_CLE_BYPASS_EN0 BIT(31) 169 #define CFG_TXCLK_MUXSEL0_SET(dst, val) xgene_set_bits(dst, val, 29, 3) 170 #define CFG_RXCLK_MUXSEL0_SET(dst, val) xgene_set_bits(dst, val, 26, 3) 171 172 #define CFG_CLE_IP_PROTOCOL0_SET(dst, val) xgene_set_bits(dst, val, 16, 2) 173 #define CFG_CLE_IP_HDR_LEN_SET(dst, val) xgene_set_bits(dst, val, 8, 5) 174 #define CFG_CLE_DSTQID0_SET(dst, val) xgene_set_bits(dst, val, 0, 12) 175 #define CFG_CLE_FPSEL0_SET(dst, val) xgene_set_bits(dst, val, 16, 4) 176 #define CFG_CLE_NXTFPSEL0_SET(dst, val) xgene_set_bits(dst, val, 20, 4) 177 #define CFG_MACMODE_SET(dst, val) xgene_set_bits(dst, val, 18, 2) 178 #define CFG_WAITASYNCRD_SET(dst, val) xgene_set_bits(dst, val, 0, 16) 179 #define CFG_CLE_DSTQID0(val) ((val) & GENMASK(11, 0)) 180 #define CFG_CLE_FPSEL0(val) (((val) << 16) & GENMASK(19, 16)) 181 #define CSR_ECM_CFG_0_ADDR 0x0220 182 #define CSR_ECM_CFG_1_ADDR 0x0224 183 #define CSR_MULTI_DPF0_ADDR 0x0230 184 #define RXBUF_PAUSE_THRESH 0x0534 185 #define RXBUF_PAUSE_OFF_THRESH 0x0540 186 #define DEF_PAUSE_THRES 0x7d 187 #define DEF_PAUSE_OFF_THRES 0x6d 188 #define DEF_QUANTA 0x8000 189 #define NORM_PAUSE_OPCODE 0x0001 190 #define PAUSE_XON_EN BIT(30) 191 #define MULTI_DPF_AUTOCTRL BIT(28) 192 #define CFG_CLE_NXTFPSEL0(val) (((val) << 20) & GENMASK(23, 20)) 193 #define ICM_CONFIG0_REG_0_ADDR 0x0400 194 #define ICM_CONFIG2_REG_0_ADDR 0x0410 195 #define ECM_CONFIG0_REG_0_ADDR 0x0500 196 #define ECM_CONFIG0_REG_1_ADDR 0x0504 197 #define ICM_ECM_DROP_COUNT_REG0_ADDR 0x0508 198 #define ICM_ECM_DROP_COUNT_REG1_ADDR 0x050c 199 #define RX_DV_GATE_REG_0_ADDR 0x05fc 200 #define TX_DV_GATE_EN0 BIT(2) 201 #define RX_DV_GATE_EN0 BIT(1) 202 #define RESUME_RX0 BIT(0) 203 #define ENET_CFGSSQMIFPRESET_ADDR 0x14 204 #define ENET_CFGSSQMIWQRESET_ADDR 0x1c 205 #define ENET_CFGSSQMIWQASSOC_ADDR 0xe0 206 #define ENET_CFGSSQMIFPQASSOC_ADDR 0xdc 207 #define ENET_CFGSSQMIQMLITEFPQASSOC_ADDR 0xf0 208 #define ENET_CFGSSQMIQMLITEWQASSOC_ADDR 0xf4 209 #define ENET_CFG_MEM_RAM_SHUTDOWN_ADDR 0x70 210 #define ENET_BLOCK_MEM_RDY_ADDR 0x74 211 #define MAC_CONFIG_1_ADDR 0x00 212 #define MAC_CONFIG_2_ADDR 0x04 213 #define MAX_FRAME_LEN_ADDR 0x10 214 #define INTERFACE_CONTROL_ADDR 0x38 215 #define STATION_ADDR0_ADDR 0x40 216 #define STATION_ADDR1_ADDR 0x44 217 #define PHY_ADDR_SET(dst, val) xgene_set_bits(dst, val, 8, 5) 218 #define REG_ADDR_SET(dst, val) xgene_set_bits(dst, val, 0, 5) 219 #define ENET_INTERFACE_MODE2_SET(dst, val) xgene_set_bits(dst, val, 8, 2) 220 #define MGMT_CLOCK_SEL_SET(dst, val) xgene_set_bits(dst, val, 0, 3) 221 #define SOFT_RESET1 BIT(31) 222 #define TX_EN BIT(0) 223 #define RX_EN BIT(2) 224 #define TX_FLOW_EN BIT(4) 225 #define RX_FLOW_EN BIT(5) 226 #define ENET_LHD_MODE BIT(25) 227 #define ENET_GHD_MODE BIT(26) 228 #define FULL_DUPLEX2 BIT(0) 229 #define PAD_CRC BIT(2) 230 #define LENGTH_CHK BIT(4) 231 232 #define TR64_ADDR 0x20 233 #define TR127_ADDR 0x21 234 #define TR255_ADDR 0x22 235 #define TR511_ADDR 0x23 236 #define TR1K_ADDR 0x24 237 #define TRMAX_ADDR 0x25 238 #define TRMGV_ADDR 0x26 239 240 #define RFCS_ADDR 0x29 241 #define RMCA_ADDR 0x2a 242 #define RBCA_ADDR 0x2b 243 #define RXCF_ADDR 0x2c 244 #define RXPF_ADDR 0x2d 245 #define RXUO_ADDR 0x2e 246 #define RALN_ADDR 0x2f 247 #define RFLR_ADDR 0x30 248 #define RCDE_ADDR 0x31 249 #define RCSE_ADDR 0x32 250 #define RUND_ADDR 0x33 251 #define ROVR_ADDR 0x34 252 #define RFRG_ADDR 0x35 253 #define RJBR_ADDR 0x36 254 #define RDRP_ADDR 0x37 255 256 #define TMCA_ADDR 0x3a 257 #define TBCA_ADDR 0x3b 258 #define TXPF_ADDR 0x3c 259 #define TDFR_ADDR 0x3d 260 #define TEDF_ADDR 0x3e 261 #define TSCL_ADDR 0x3f 262 #define TMCL_ADDR 0x40 263 #define TLCL_ADDR 0x41 264 #define TXCL_ADDR 0x42 265 #define TNCL_ADDR 0x43 266 #define TPFH_ADDR 0x44 267 #define TDRP_ADDR 0x45 268 #define TJBR_ADDR 0x46 269 #define TFCS_ADDR 0x47 270 #define TXCF_ADDR 0x48 271 #define TOVR_ADDR 0x49 272 #define TUND_ADDR 0x4a 273 #define TFRG_ADDR 0x4b 274 #define DUMP_ADDR 0x27 275 276 #define ECM_DROP_COUNT(src) xgene_get_bits(src, 0, 15) 277 #define ICM_DROP_COUNT(src) xgene_get_bits(src, 16, 31) 278 279 #define TSO_IPPROTO_TCP 1 280 281 #define USERINFO_POS 0 282 #define USERINFO_LEN 32 283 #define FPQNUM_POS 32 284 #define FPQNUM_LEN 12 285 #define ELERR_POS 46 286 #define ELERR_LEN 2 287 #define NV_POS 50 288 #define NV_LEN 1 289 #define LL_POS 51 290 #define LL_LEN 1 291 #define LERR_POS 60 292 #define LERR_LEN 3 293 #define STASH_POS 52 294 #define STASH_LEN 2 295 #define BUFDATALEN_POS 48 296 #define BUFDATALEN_LEN 15 297 #define DATAADDR_POS 0 298 #define DATAADDR_LEN 42 299 #define COHERENT_POS 63 300 #define HENQNUM_POS 48 301 #define HENQNUM_LEN 12 302 #define TYPESEL_POS 44 303 #define TYPESEL_LEN 4 304 #define ETHHDR_POS 12 305 #define ETHHDR_LEN 8 306 #define IC_POS 35 /* Insert CRC */ 307 #define TCPHDR_POS 0 308 #define TCPHDR_LEN 6 309 #define IPHDR_POS 6 310 #define IPHDR_LEN 6 311 #define MSS_POS 20 312 #define MSS_LEN 2 313 #define EC_POS 22 /* Enable checksum */ 314 #define EC_LEN 1 315 #define ET_POS 23 /* Enable TSO */ 316 #define IS_POS 24 /* IP protocol select */ 317 #define IS_LEN 1 318 #define TYPE_ETH_WORK_MESSAGE_POS 44 319 #define LL_BYTES_MSB_POS 56 320 #define LL_BYTES_MSB_LEN 8 321 #define LL_BYTES_LSB_POS 48 322 #define LL_BYTES_LSB_LEN 12 323 #define LL_LEN_POS 48 324 #define LL_LEN_LEN 8 325 #define DATALEN_MASK GENMASK(11, 0) 326 327 #define LAST_BUFFER (0x7800ULL << BUFDATALEN_POS) 328 329 #define TSO_MSS0_POS 0 330 #define TSO_MSS0_LEN 14 331 #define TSO_MSS1_POS 16 332 #define TSO_MSS1_LEN 14 333 334 struct xgene_enet_raw_desc { 335 __le64 m0; 336 __le64 m1; 337 __le64 m2; 338 __le64 m3; 339 }; 340 341 struct xgene_enet_raw_desc16 { 342 __le64 m0; 343 __le64 m1; 344 }; 345 346 static inline void xgene_enet_mark_desc_slot_empty(void *desc_slot_ptr) 347 { 348 __le64 *desc_slot = desc_slot_ptr; 349 350 desc_slot[EMPTY_SLOT_INDEX] = cpu_to_le64(EMPTY_SLOT); 351 } 352 353 static inline bool xgene_enet_is_desc_slot_empty(void *desc_slot_ptr) 354 { 355 __le64 *desc_slot = desc_slot_ptr; 356 357 return (desc_slot[EMPTY_SLOT_INDEX] == cpu_to_le64(EMPTY_SLOT)); 358 } 359 360 enum xgene_enet_ring_cfgsize { 361 RING_CFGSIZE_512B, 362 RING_CFGSIZE_2KB, 363 RING_CFGSIZE_16KB, 364 RING_CFGSIZE_64KB, 365 RING_CFGSIZE_512KB, 366 RING_CFGSIZE_INVALID 367 }; 368 369 enum xgene_enet_ring_type { 370 RING_DISABLED, 371 RING_REGULAR, 372 RING_BUFPOOL 373 }; 374 375 enum xgene_ring_owner { 376 RING_OWNER_ETH0, 377 RING_OWNER_ETH1, 378 RING_OWNER_CPU = 15, 379 RING_OWNER_INVALID 380 }; 381 382 enum xgene_enet_ring_bufnum { 383 RING_BUFNUM_REGULAR = 0x0, 384 RING_BUFNUM_BUFPOOL = 0x20, 385 RING_BUFNUM_INVALID 386 }; 387 388 enum xgene_enet_err_code { 389 HBF_READ_DATA = 3, 390 HBF_LL_READ = 4, 391 BAD_WORK_MSG = 6, 392 BUFPOOL_TIMEOUT = 15, 393 INGRESS_CRC = 16, 394 INGRESS_CHECKSUM = 17, 395 INGRESS_TRUNC_FRAME = 18, 396 INGRESS_PKT_LEN = 19, 397 INGRESS_PKT_UNDER = 20, 398 INGRESS_FIFO_OVERRUN = 21, 399 INGRESS_CHECKSUM_COMPUTE = 26, 400 ERR_CODE_INVALID 401 }; 402 403 static inline enum xgene_ring_owner xgene_enet_ring_owner(u16 id) 404 { 405 return (id & RING_OWNER_MASK) >> 6; 406 } 407 408 static inline u8 xgene_enet_ring_bufnum(u16 id) 409 { 410 return id & RING_BUFNUM_MASK; 411 } 412 413 static inline bool xgene_enet_is_bufpool(u16 id) 414 { 415 return ((id & RING_BUFNUM_MASK) >= 0x20) ? true : false; 416 } 417 418 static inline u8 xgene_enet_get_fpsel(u16 id) 419 { 420 if (xgene_enet_is_bufpool(id)) 421 return xgene_enet_ring_bufnum(id) - RING_BUFNUM_BUFPOOL; 422 423 return 0; 424 } 425 426 static inline u16 xgene_enet_get_numslots(u16 id, u32 size) 427 { 428 bool is_bufpool = xgene_enet_is_bufpool(id); 429 430 return (is_bufpool) ? size / BUFPOOL_DESC_SIZE : 431 size / WORK_DESC_SIZE; 432 } 433 434 void xgene_enet_parse_error(struct xgene_enet_desc_ring *ring, 435 enum xgene_enet_err_code status); 436 int xgene_enet_mdio_config(struct xgene_enet_pdata *pdata); 437 void xgene_enet_mdio_remove(struct xgene_enet_pdata *pdata); 438 bool xgene_ring_mgr_init(struct xgene_enet_pdata *p); 439 int xgene_enet_phy_connect(struct net_device *ndev); 440 void xgene_enet_phy_disconnect(struct xgene_enet_pdata *pdata); 441 u32 xgene_enet_rd_mac(struct xgene_enet_pdata *pdata, u32 rd_addr); 442 void xgene_enet_wr_mac(struct xgene_enet_pdata *pdata, u32 wr_addr, 443 u32 wr_data); 444 u32 xgene_enet_rd_stat(struct xgene_enet_pdata *pdata, u32 rd_addr); 445 446 extern const struct xgene_mac_ops xgene_gmac_ops; 447 extern const struct xgene_port_ops xgene_gport_ops; 448 extern struct xgene_ring_ops xgene_ring1_ops; 449 450 #endif /* __XGENE_ENET_HW_H__ */ 451