1 /* Applied Micro X-Gene SoC Ethernet Classifier structures 2 * 3 * Copyright (c) 2016, Applied Micro Circuits Corporation 4 * Authors: Khuong Dinh <kdinh@apm.com> 5 * Tanmay Inamdar <tinamdar@apm.com> 6 * Iyappan Subramanian <isubramanian@apm.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program. If not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #ifndef __XGENE_ENET_CLE_H__ 23 #define __XGENE_ENET_CLE_H__ 24 25 #include <linux/io.h> 26 #include <linux/random.h> 27 28 /* Register offsets */ 29 #define INDADDR 0x04 30 #define INDCMD 0x08 31 #define INDCMD_STATUS 0x0c 32 #define DATA_RAM0 0x10 33 #define SNPTR0 0x0100 34 #define SPPTR0 0x0104 35 #define DFCLSRESDBPTR0 0x0108 36 #define DFCLSRESDB00 0x010c 37 #define RSS_CTRL0 0x0000013c 38 39 #define CLE_CMD_TO 10 /* ms */ 40 #define CLE_PKTRAM_SIZE 256 /* bytes */ 41 #define CLE_PORT_OFFSET 0x200 42 #define CLE_DRAM_REGS 17 43 44 #define CLE_DN_TYPE_LEN 2 45 #define CLE_DN_TYPE_POS 0 46 #define CLE_DN_LASTN_LEN 1 47 #define CLE_DN_LASTN_POS 2 48 #define CLE_DN_HLS_LEN 1 49 #define CLE_DN_HLS_POS 3 50 #define CLE_DN_EXT_LEN 2 51 #define CLE_DN_EXT_POS 4 52 #define CLE_DN_BSTOR_LEN 2 53 #define CLE_DN_BSTOR_POS 6 54 #define CLE_DN_SBSTOR_LEN 2 55 #define CLE_DN_SBSTOR_POS 8 56 #define CLE_DN_RPTR_LEN 12 57 #define CLE_DN_RPTR_POS 12 58 59 #define CLE_BR_VALID_LEN 1 60 #define CLE_BR_VALID_POS 0 61 #define CLE_BR_NPPTR_LEN 9 62 #define CLE_BR_NPPTR_POS 1 63 #define CLE_BR_JB_LEN 1 64 #define CLE_BR_JB_POS 10 65 #define CLE_BR_JR_LEN 1 66 #define CLE_BR_JR_POS 11 67 #define CLE_BR_OP_LEN 3 68 #define CLE_BR_OP_POS 12 69 #define CLE_BR_NNODE_LEN 9 70 #define CLE_BR_NNODE_POS 15 71 #define CLE_BR_NBR_LEN 5 72 #define CLE_BR_NBR_POS 24 73 74 #define CLE_BR_DATA_LEN 16 75 #define CLE_BR_DATA_POS 0 76 #define CLE_BR_MASK_LEN 16 77 #define CLE_BR_MASK_POS 16 78 79 #define CLE_KN_PRIO_POS 0 80 #define CLE_KN_PRIO_LEN 3 81 #define CLE_KN_RPTR_POS 3 82 #define CLE_KN_RPTR_LEN 10 83 #define CLE_TYPE_POS 0 84 #define CLE_TYPE_LEN 2 85 86 #define CLE_DROP_POS 28 87 #define CLE_DROP_LEN 1 88 #define CLE_DSTQIDL_POS 25 89 #define CLE_DSTQIDL_LEN 7 90 #define CLE_DSTQIDH_POS 0 91 #define CLE_DSTQIDH_LEN 5 92 #define CLE_FPSEL_POS 21 93 #define CLE_FPSEL_LEN 4 94 #define CLE_NFPSEL_POS 17 95 #define CLE_NFPSEL_LEN 4 96 #define CLE_PRIORITY_POS 5 97 #define CLE_PRIORITY_LEN 3 98 99 #define JMP_ABS 0 100 #define JMP_REL 1 101 #define JMP_FW 0 102 #define JMP_BW 1 103 104 enum xgene_cle_ptree_nodes { 105 PKT_TYPE_NODE, 106 PKT_PROT_NODE, 107 RSS_IPV4_TCP_NODE, 108 RSS_IPV4_UDP_NODE, 109 RSS_IPV4_OTHERS_NODE, 110 LAST_NODE, 111 MAX_NODES 112 }; 113 114 enum xgene_cle_byte_store { 115 NO_BYTE, 116 FIRST_BYTE, 117 SECOND_BYTE, 118 BOTH_BYTES 119 }; 120 121 /* Preclassification operation types */ 122 enum xgene_cle_node_type { 123 INV, 124 KN, 125 EWDN, 126 RES_NODE 127 }; 128 129 /* Preclassification operation types */ 130 enum xgene_cle_op_type { 131 EQT, 132 NEQT, 133 LTEQT, 134 GTEQT, 135 AND, 136 NAND 137 }; 138 139 enum xgene_cle_parser { 140 PARSER0, 141 PARSER1, 142 PARSER2, 143 PARSER_ALL 144 }; 145 146 #define XGENE_CLE_DRAM(type) (((type) & 0xf) << 28) 147 enum xgene_cle_dram_type { 148 PKT_RAM, 149 RSS_IDT, 150 RSS_IPV4_HASH_SKEY, 151 PTREE_RAM = 0xc, 152 AVL_RAM, 153 DB_RAM 154 }; 155 156 enum xgene_cle_cmd_type { 157 CLE_CMD_WR = 1, 158 CLE_CMD_RD = 2, 159 CLE_CMD_AVL_ADD = 8, 160 CLE_CMD_AVL_DEL = 16, 161 CLE_CMD_AVL_SRCH = 32 162 }; 163 164 enum xgene_cle_ipv4_rss_hashtype { 165 RSS_IPV4_8B, 166 RSS_IPV4_12B, 167 }; 168 169 enum xgene_cle_prot_type { 170 XGENE_CLE_TCP, 171 XGENE_CLE_UDP, 172 XGENE_CLE_ESP, 173 XGENE_CLE_OTHER 174 }; 175 176 enum xgene_cle_prot_version { 177 XGENE_CLE_IPV4, 178 }; 179 180 enum xgene_cle_ptree_dbptrs { 181 DB_RES_DROP, 182 DB_RES_DEF, 183 DB_RES_ACCEPT, 184 DB_MAX_PTRS 185 }; 186 187 /* RSS sideband signal info */ 188 #define SB_IPFRAG_POS 0 189 #define SB_IPFRAG_LEN 1 190 #define SB_IPPROT_POS 1 191 #define SB_IPPROT_LEN 2 192 #define SB_IPVER_POS 3 193 #define SB_IPVER_LEN 1 194 #define SB_HDRLEN_POS 4 195 #define SB_HDRLEN_LEN 12 196 197 /* RSS indirection table */ 198 #define XGENE_CLE_IDT_ENTRIES 128 199 #define IDT_DSTQID_POS 0 200 #define IDT_DSTQID_LEN 12 201 #define IDT_FPSEL_POS 12 202 #define IDT_FPSEL_LEN 5 203 #define IDT_NFPSEL_POS 17 204 #define IDT_NFPSEL_LEN 5 205 #define IDT_FPSEL1_POS 12 206 #define IDT_FPSEL1_LEN 4 207 #define IDT_NFPSEL1_POS 16 208 #define IDT_NFPSEL1_LEN 4 209 210 struct xgene_cle_ptree_branch { 211 bool valid; 212 u16 next_packet_pointer; 213 bool jump_bw; 214 bool jump_rel; 215 u8 operation; 216 u16 next_node; 217 u8 next_branch; 218 u16 data; 219 u16 mask; 220 }; 221 222 struct xgene_cle_ptree_ewdn { 223 u8 node_type; 224 bool last_node; 225 bool hdr_len_store; 226 u8 hdr_extn; 227 u8 byte_store; 228 u8 search_byte_store; 229 u16 result_pointer; 230 u8 num_branches; 231 struct xgene_cle_ptree_branch branch[6]; 232 }; 233 234 struct xgene_cle_ptree_key { 235 u8 priority; 236 u16 result_pointer; 237 }; 238 239 struct xgene_cle_ptree_kn { 240 u8 node_type; 241 u8 num_keys; 242 struct xgene_cle_ptree_key key[32]; 243 }; 244 245 struct xgene_cle_dbptr { 246 u8 split_boundary; 247 u8 mirror_nxtfpsel; 248 u8 mirror_fpsel; 249 u16 mirror_dstqid; 250 u8 drop; 251 u8 mirror; 252 u8 hdr_data_split; 253 u64 hopinfomsbs; 254 u8 DR; 255 u8 HR; 256 u64 hopinfomlsbs; 257 u16 h0enq_num; 258 u8 h0fpsel; 259 u8 nxtfpsel; 260 u8 fpsel; 261 u16 dstqid; 262 u8 cle_priority; 263 u8 cle_flowgroup; 264 u8 cle_perflow; 265 u8 cle_insert_timestamp; 266 u8 stash; 267 u8 in; 268 u8 perprioen; 269 u8 perflowgroupen; 270 u8 perflowen; 271 u8 selhash; 272 u8 selhdrext; 273 u8 mirror_nxtfpsel_msb; 274 u8 mirror_fpsel_msb; 275 u8 hfpsel_msb; 276 u8 nxtfpsel_msb; 277 u8 fpsel_msb; 278 }; 279 280 struct xgene_cle_ptree { 281 struct xgene_cle_ptree_kn *kn; 282 struct xgene_cle_dbptr *dbptr; 283 u32 num_kn; 284 u32 num_dbptr; 285 u32 start_node; 286 u32 start_pkt; 287 u32 start_dbptr; 288 }; 289 290 struct xgene_enet_cle { 291 void __iomem *base; 292 struct xgene_cle_ptree ptree; 293 enum xgene_cle_parser active_parser; 294 u32 parsers; 295 u32 max_nodes; 296 u32 max_dbptrs; 297 u32 jump_bytes; 298 }; 299 300 extern const struct xgene_cle_ops xgene_cle3in_ops; 301 302 #endif /* __XGENE_ENET_CLE_H__ */ 303