11ccea77eSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later
2384fe7a4SIyappan Subramanian /*
3384fe7a4SIyappan Subramanian  * Applied Micro X-Gene SoC Ethernet v2 Driver
4384fe7a4SIyappan Subramanian  *
5384fe7a4SIyappan Subramanian  * Copyright (c) 2017, Applied Micro Circuits Corporation
6384fe7a4SIyappan Subramanian  * Author(s): Iyappan Subramanian <isubramanian@apm.com>
7384fe7a4SIyappan Subramanian  *	      Keyur Chudgar <kchudgar@apm.com>
8384fe7a4SIyappan Subramanian  */
9384fe7a4SIyappan Subramanian 
10384fe7a4SIyappan Subramanian #include "main.h"
11384fe7a4SIyappan Subramanian 
12384fe7a4SIyappan Subramanian /* create circular linked list of descriptors */
xge_setup_desc(struct xge_desc_ring * ring)13384fe7a4SIyappan Subramanian void xge_setup_desc(struct xge_desc_ring *ring)
14384fe7a4SIyappan Subramanian {
15384fe7a4SIyappan Subramanian 	struct xge_raw_desc *raw_desc;
16384fe7a4SIyappan Subramanian 	dma_addr_t dma_h, next_dma;
17384fe7a4SIyappan Subramanian 	u16 offset;
18384fe7a4SIyappan Subramanian 	int i;
19384fe7a4SIyappan Subramanian 
20384fe7a4SIyappan Subramanian 	for (i = 0; i < XGENE_ENET_NUM_DESC; i++) {
21384fe7a4SIyappan Subramanian 		raw_desc = &ring->raw_desc[i];
22384fe7a4SIyappan Subramanian 
23384fe7a4SIyappan Subramanian 		offset = (i + 1) & (XGENE_ENET_NUM_DESC - 1);
24384fe7a4SIyappan Subramanian 		next_dma = ring->dma_addr + (offset * XGENE_ENET_DESC_SIZE);
25384fe7a4SIyappan Subramanian 
26384fe7a4SIyappan Subramanian 		raw_desc->m0 = cpu_to_le64(SET_BITS(E, 1) |
27384fe7a4SIyappan Subramanian 					   SET_BITS(PKT_SIZE, SLOT_EMPTY));
28384fe7a4SIyappan Subramanian 		dma_h = upper_32_bits(next_dma);
29384fe7a4SIyappan Subramanian 		raw_desc->m1 = cpu_to_le64(SET_BITS(NEXT_DESC_ADDRL, next_dma) |
30384fe7a4SIyappan Subramanian 					   SET_BITS(NEXT_DESC_ADDRH, dma_h));
31384fe7a4SIyappan Subramanian 	}
32384fe7a4SIyappan Subramanian }
33384fe7a4SIyappan Subramanian 
xge_update_tx_desc_addr(struct xge_pdata * pdata)34384fe7a4SIyappan Subramanian void xge_update_tx_desc_addr(struct xge_pdata *pdata)
35384fe7a4SIyappan Subramanian {
36384fe7a4SIyappan Subramanian 	struct xge_desc_ring *ring = pdata->tx_ring;
37384fe7a4SIyappan Subramanian 	dma_addr_t dma_addr = ring->dma_addr;
38384fe7a4SIyappan Subramanian 
39384fe7a4SIyappan Subramanian 	xge_wr_csr(pdata, DMATXDESCL, dma_addr);
40384fe7a4SIyappan Subramanian 	xge_wr_csr(pdata, DMATXDESCH, upper_32_bits(dma_addr));
41384fe7a4SIyappan Subramanian 
42384fe7a4SIyappan Subramanian 	ring->head = 0;
43384fe7a4SIyappan Subramanian 	ring->tail = 0;
44384fe7a4SIyappan Subramanian }
45384fe7a4SIyappan Subramanian 
xge_update_rx_desc_addr(struct xge_pdata * pdata)46384fe7a4SIyappan Subramanian void xge_update_rx_desc_addr(struct xge_pdata *pdata)
47384fe7a4SIyappan Subramanian {
48384fe7a4SIyappan Subramanian 	struct xge_desc_ring *ring = pdata->rx_ring;
49384fe7a4SIyappan Subramanian 	dma_addr_t dma_addr = ring->dma_addr;
50384fe7a4SIyappan Subramanian 
51384fe7a4SIyappan Subramanian 	xge_wr_csr(pdata, DMARXDESCL, dma_addr);
52384fe7a4SIyappan Subramanian 	xge_wr_csr(pdata, DMARXDESCH, upper_32_bits(dma_addr));
53384fe7a4SIyappan Subramanian 
54384fe7a4SIyappan Subramanian 	ring->head = 0;
55384fe7a4SIyappan Subramanian 	ring->tail = 0;
56384fe7a4SIyappan Subramanian }
57384fe7a4SIyappan Subramanian 
xge_intr_enable(struct xge_pdata * pdata)58384fe7a4SIyappan Subramanian void xge_intr_enable(struct xge_pdata *pdata)
59384fe7a4SIyappan Subramanian {
60384fe7a4SIyappan Subramanian 	u32 data;
61384fe7a4SIyappan Subramanian 
62384fe7a4SIyappan Subramanian 	data = RX_PKT_RCVD | TX_PKT_SENT;
63384fe7a4SIyappan Subramanian 	xge_wr_csr(pdata, DMAINTRMASK, data);
64384fe7a4SIyappan Subramanian }
65384fe7a4SIyappan Subramanian 
xge_intr_disable(struct xge_pdata * pdata)66384fe7a4SIyappan Subramanian void xge_intr_disable(struct xge_pdata *pdata)
67384fe7a4SIyappan Subramanian {
68384fe7a4SIyappan Subramanian 	xge_wr_csr(pdata, DMAINTRMASK, 0);
69384fe7a4SIyappan Subramanian }
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