1 /* 2 * AMD 10Gb Ethernet driver 3 * 4 * This file is available to you under your choice of the following two 5 * licenses: 6 * 7 * License 1: GPLv2 8 * 9 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc. 10 * 11 * This file is free software; you may copy, redistribute and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation, either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program. If not, see <http://www.gnu.org/licenses/>. 23 * 24 * This file incorporates work covered by the following copyright and 25 * permission notice: 26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 28 * Inc. unless otherwise expressly agreed to in writing between Synopsys 29 * and you. 30 * 31 * The Software IS NOT an item of Licensed Software or Licensed Product 32 * under any End User Software License Agreement or Agreement for Licensed 33 * Product with Synopsys or any supplement thereto. Permission is hereby 34 * granted, free of charge, to any person obtaining a copy of this software 35 * annotated with this license and the Software, to deal in the Software 36 * without restriction, including without limitation the rights to use, 37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 38 * of the Software, and to permit persons to whom the Software is furnished 39 * to do so, subject to the following conditions: 40 * 41 * The above copyright notice and this permission notice shall be included 42 * in all copies or substantial portions of the Software. 43 * 44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 54 * THE POSSIBILITY OF SUCH DAMAGE. 55 * 56 * 57 * License 2: Modified BSD 58 * 59 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc. 60 * All rights reserved. 61 * 62 * Redistribution and use in source and binary forms, with or without 63 * modification, are permitted provided that the following conditions are met: 64 * * Redistributions of source code must retain the above copyright 65 * notice, this list of conditions and the following disclaimer. 66 * * Redistributions in binary form must reproduce the above copyright 67 * notice, this list of conditions and the following disclaimer in the 68 * documentation and/or other materials provided with the distribution. 69 * * Neither the name of Advanced Micro Devices, Inc. nor the 70 * names of its contributors may be used to endorse or promote products 71 * derived from this software without specific prior written permission. 72 * 73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY 77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 83 * 84 * This file incorporates work covered by the following copyright and 85 * permission notice: 86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 88 * Inc. unless otherwise expressly agreed to in writing between Synopsys 89 * and you. 90 * 91 * The Software IS NOT an item of Licensed Software or Licensed Product 92 * under any End User Software License Agreement or Agreement for Licensed 93 * Product with Synopsys or any supplement thereto. Permission is hereby 94 * granted, free of charge, to any person obtaining a copy of this software 95 * annotated with this license and the Software, to deal in the Software 96 * without restriction, including without limitation the rights to use, 97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 98 * of the Software, and to permit persons to whom the Software is furnished 99 * to do so, subject to the following conditions: 100 * 101 * The above copyright notice and this permission notice shall be included 102 * in all copies or substantial portions of the Software. 103 * 104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 114 * THE POSSIBILITY OF SUCH DAMAGE. 115 */ 116 117 #ifndef __XGBE_H__ 118 #define __XGBE_H__ 119 120 #include <linux/dma-mapping.h> 121 #include <linux/netdevice.h> 122 #include <linux/workqueue.h> 123 #include <linux/phy.h> 124 #include <linux/if_vlan.h> 125 #include <linux/bitops.h> 126 #include <linux/ptp_clock_kernel.h> 127 #include <linux/timecounter.h> 128 #include <linux/net_tstamp.h> 129 #include <net/dcbnl.h> 130 #include <linux/completion.h> 131 #include <linux/cpumask.h> 132 #include <linux/interrupt.h> 133 #include <linux/dcache.h> 134 #include <linux/ethtool.h> 135 #include <linux/list.h> 136 137 #define XGBE_DRV_NAME "amd-xgbe" 138 #define XGBE_DRV_DESC "AMD 10 Gigabit Ethernet Driver" 139 140 /* Descriptor related defines */ 141 #define XGBE_TX_DESC_CNT 512 142 #define XGBE_TX_DESC_MIN_FREE (XGBE_TX_DESC_CNT >> 3) 143 #define XGBE_TX_DESC_MAX_PROC (XGBE_TX_DESC_CNT >> 1) 144 #define XGBE_RX_DESC_CNT 512 145 146 #define XGBE_TX_DESC_CNT_MIN 64 147 #define XGBE_TX_DESC_CNT_MAX 4096 148 #define XGBE_RX_DESC_CNT_MIN 64 149 #define XGBE_RX_DESC_CNT_MAX 4096 150 151 #define XGBE_TX_MAX_BUF_SIZE (0x3fff & ~(64 - 1)) 152 153 /* Descriptors required for maximum contiguous TSO/GSO packet */ 154 #define XGBE_TX_MAX_SPLIT ((GSO_MAX_SIZE / XGBE_TX_MAX_BUF_SIZE) + 1) 155 156 /* Maximum possible descriptors needed for an SKB: 157 * - Maximum number of SKB frags 158 * - Maximum descriptors for contiguous TSO/GSO packet 159 * - Possible context descriptor 160 * - Possible TSO header descriptor 161 */ 162 #define XGBE_TX_MAX_DESCS (MAX_SKB_FRAGS + XGBE_TX_MAX_SPLIT + 2) 163 164 #define XGBE_RX_MIN_BUF_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN) 165 #define XGBE_RX_BUF_ALIGN 64 166 #define XGBE_SKB_ALLOC_SIZE 256 167 #define XGBE_SPH_HDSMS_SIZE 2 /* Keep in sync with SKB_ALLOC_SIZE */ 168 169 #define XGBE_MAX_DMA_CHANNELS 16 170 #define XGBE_MAX_QUEUES 16 171 #define XGBE_PRIORITY_QUEUES 8 172 #define XGBE_DMA_STOP_TIMEOUT 1 173 174 /* DMA cache settings - Outer sharable, write-back, write-allocate */ 175 #define XGBE_DMA_OS_ARCR 0x002b2b2b 176 #define XGBE_DMA_OS_AWCR 0x2f2f2f2f 177 178 /* DMA cache settings - System, no caches used */ 179 #define XGBE_DMA_SYS_ARCR 0x00303030 180 #define XGBE_DMA_SYS_AWCR 0x30303030 181 182 /* DMA cache settings - PCI device */ 183 #define XGBE_DMA_PCI_ARCR 0x000f0f0f 184 #define XGBE_DMA_PCI_AWCR 0x0f0f0f0f 185 #define XGBE_DMA_PCI_AWARCR 0x00000f0f 186 187 /* DMA channel interrupt modes */ 188 #define XGBE_IRQ_MODE_EDGE 0 189 #define XGBE_IRQ_MODE_LEVEL 1 190 191 #define XGMAC_MIN_PACKET 60 192 #define XGMAC_STD_PACKET_MTU 1500 193 #define XGMAC_MAX_STD_PACKET 1518 194 #define XGMAC_JUMBO_PACKET_MTU 9000 195 #define XGMAC_MAX_JUMBO_PACKET 9018 196 #define XGMAC_ETH_PREAMBLE (12 + 8) /* Inter-frame gap + preamble */ 197 198 #define XGMAC_PFC_DATA_LEN 46 199 #define XGMAC_PFC_DELAYS 14000 200 201 #define XGMAC_PRIO_QUEUES(_cnt) \ 202 min_t(unsigned int, IEEE_8021QAZ_MAX_TCS, (_cnt)) 203 204 /* Common property names */ 205 #define XGBE_MAC_ADDR_PROPERTY "mac-address" 206 #define XGBE_PHY_MODE_PROPERTY "phy-mode" 207 #define XGBE_DMA_IRQS_PROPERTY "amd,per-channel-interrupt" 208 #define XGBE_SPEEDSET_PROPERTY "amd,speed-set" 209 210 /* Device-tree clock names */ 211 #define XGBE_DMA_CLOCK "dma_clk" 212 #define XGBE_PTP_CLOCK "ptp_clk" 213 214 /* ACPI property names */ 215 #define XGBE_ACPI_DMA_FREQ "amd,dma-freq" 216 #define XGBE_ACPI_PTP_FREQ "amd,ptp-freq" 217 218 /* PCI BAR mapping */ 219 #define XGBE_XGMAC_BAR 0 220 #define XGBE_XPCS_BAR 1 221 #define XGBE_MAC_PROP_OFFSET 0x1d000 222 #define XGBE_I2C_CTRL_OFFSET 0x1e000 223 224 /* PCI MSI/MSIx support */ 225 #define XGBE_MSI_BASE_COUNT 4 226 #define XGBE_MSI_MIN_COUNT (XGBE_MSI_BASE_COUNT + 1) 227 228 /* PCI clock frequencies */ 229 #define XGBE_V2_DMA_CLOCK_FREQ 500000000 /* 500 MHz */ 230 #define XGBE_V2_PTP_CLOCK_FREQ 125000000 /* 125 MHz */ 231 232 /* Timestamp support - values based on 50MHz PTP clock 233 * 50MHz => 20 nsec 234 */ 235 #define XGBE_TSTAMP_SSINC 20 236 #define XGBE_TSTAMP_SNSINC 0 237 238 /* Driver PMT macros */ 239 #define XGMAC_DRIVER_CONTEXT 1 240 #define XGMAC_IOCTL_CONTEXT 2 241 242 #define XGMAC_FIFO_MIN_ALLOC 2048 243 #define XGMAC_FIFO_UNIT 256 244 #define XGMAC_FIFO_ALIGN(_x) \ 245 (((_x) + XGMAC_FIFO_UNIT - 1) & ~(XGMAC_FIFO_UNIT - 1)) 246 #define XGMAC_FIFO_FC_OFF 2048 247 #define XGMAC_FIFO_FC_MIN 4096 248 249 #define XGBE_TC_MIN_QUANTUM 10 250 251 /* Helper macro for descriptor handling 252 * Always use XGBE_GET_DESC_DATA to access the descriptor data 253 * since the index is free-running and needs to be and-ed 254 * with the descriptor count value of the ring to index to 255 * the proper descriptor data. 256 */ 257 #define XGBE_GET_DESC_DATA(_ring, _idx) \ 258 ((_ring)->rdata + \ 259 ((_idx) & ((_ring)->rdesc_count - 1))) 260 261 /* Default coalescing parameters */ 262 #define XGMAC_INIT_DMA_TX_USECS 1000 263 #define XGMAC_INIT_DMA_TX_FRAMES 25 264 265 #define XGMAC_MAX_DMA_RIWT 0xff 266 #define XGMAC_INIT_DMA_RX_USECS 30 267 #define XGMAC_INIT_DMA_RX_FRAMES 25 268 269 /* Flow control queue count */ 270 #define XGMAC_MAX_FLOW_CONTROL_QUEUES 8 271 272 /* Flow control threshold units */ 273 #define XGMAC_FLOW_CONTROL_UNIT 512 274 #define XGMAC_FLOW_CONTROL_ALIGN(_x) \ 275 (((_x) + XGMAC_FLOW_CONTROL_UNIT - 1) & ~(XGMAC_FLOW_CONTROL_UNIT - 1)) 276 #define XGMAC_FLOW_CONTROL_VALUE(_x) \ 277 (((_x) < 1024) ? 0 : ((_x) / XGMAC_FLOW_CONTROL_UNIT) - 2) 278 #define XGMAC_FLOW_CONTROL_MAX 33280 279 280 /* Maximum MAC address hash table size (256 bits = 8 bytes) */ 281 #define XGBE_MAC_HASH_TABLE_SIZE 8 282 283 /* Receive Side Scaling */ 284 #define XGBE_RSS_HASH_KEY_SIZE 40 285 #define XGBE_RSS_MAX_TABLE_SIZE 256 286 #define XGBE_RSS_LOOKUP_TABLE_TYPE 0 287 #define XGBE_RSS_HASH_KEY_TYPE 1 288 289 /* Auto-negotiation */ 290 #define XGBE_AN_MS_TIMEOUT 500 291 #define XGBE_LINK_TIMEOUT 5 292 293 #define XGBE_SGMII_AN_LINK_STATUS BIT(1) 294 #define XGBE_SGMII_AN_LINK_SPEED (BIT(2) | BIT(3)) 295 #define XGBE_SGMII_AN_LINK_SPEED_100 0x04 296 #define XGBE_SGMII_AN_LINK_SPEED_1000 0x08 297 #define XGBE_SGMII_AN_LINK_DUPLEX BIT(4) 298 299 /* ECC correctable error notification window (seconds) */ 300 #define XGBE_ECC_LIMIT 60 301 302 /* MDIO port types */ 303 #define XGMAC_MAX_C22_PORT 3 304 305 /* Link mode bit operations */ 306 #define XGBE_ZERO_SUP(_ls) \ 307 ethtool_link_ksettings_zero_link_mode((_ls), supported) 308 309 #define XGBE_SET_SUP(_ls, _mode) \ 310 ethtool_link_ksettings_add_link_mode((_ls), supported, _mode) 311 312 #define XGBE_CLR_SUP(_ls, _mode) \ 313 ethtool_link_ksettings_del_link_mode((_ls), supported, _mode) 314 315 #define XGBE_IS_SUP(_ls, _mode) \ 316 ethtool_link_ksettings_test_link_mode((_ls), supported, _mode) 317 318 #define XGBE_ZERO_ADV(_ls) \ 319 ethtool_link_ksettings_zero_link_mode((_ls), advertising) 320 321 #define XGBE_SET_ADV(_ls, _mode) \ 322 ethtool_link_ksettings_add_link_mode((_ls), advertising, _mode) 323 324 #define XGBE_CLR_ADV(_ls, _mode) \ 325 ethtool_link_ksettings_del_link_mode((_ls), advertising, _mode) 326 327 #define XGBE_ADV(_ls, _mode) \ 328 ethtool_link_ksettings_test_link_mode((_ls), advertising, _mode) 329 330 #define XGBE_ZERO_LP_ADV(_ls) \ 331 ethtool_link_ksettings_zero_link_mode((_ls), lp_advertising) 332 333 #define XGBE_SET_LP_ADV(_ls, _mode) \ 334 ethtool_link_ksettings_add_link_mode((_ls), lp_advertising, _mode) 335 336 #define XGBE_CLR_LP_ADV(_ls, _mode) \ 337 ethtool_link_ksettings_del_link_mode((_ls), lp_advertising, _mode) 338 339 #define XGBE_LP_ADV(_ls, _mode) \ 340 ethtool_link_ksettings_test_link_mode((_ls), lp_advertising, _mode) 341 342 #define XGBE_LM_COPY(_dst, _dname, _src, _sname) \ 343 bitmap_copy((_dst)->link_modes._dname, \ 344 (_src)->link_modes._sname, \ 345 __ETHTOOL_LINK_MODE_MASK_NBITS) 346 347 struct xgbe_prv_data; 348 349 struct xgbe_packet_data { 350 struct sk_buff *skb; 351 352 unsigned int attributes; 353 354 unsigned int errors; 355 356 unsigned int rdesc_count; 357 unsigned int length; 358 359 unsigned int header_len; 360 unsigned int tcp_header_len; 361 unsigned int tcp_payload_len; 362 unsigned short mss; 363 364 unsigned short vlan_ctag; 365 366 u64 rx_tstamp; 367 368 u32 rss_hash; 369 enum pkt_hash_types rss_hash_type; 370 371 unsigned int tx_packets; 372 unsigned int tx_bytes; 373 }; 374 375 /* Common Rx and Tx descriptor mapping */ 376 struct xgbe_ring_desc { 377 __le32 desc0; 378 __le32 desc1; 379 __le32 desc2; 380 __le32 desc3; 381 }; 382 383 /* Page allocation related values */ 384 struct xgbe_page_alloc { 385 struct page *pages; 386 unsigned int pages_len; 387 unsigned int pages_offset; 388 389 dma_addr_t pages_dma; 390 }; 391 392 /* Ring entry buffer data */ 393 struct xgbe_buffer_data { 394 struct xgbe_page_alloc pa; 395 struct xgbe_page_alloc pa_unmap; 396 397 dma_addr_t dma_base; 398 unsigned long dma_off; 399 unsigned int dma_len; 400 }; 401 402 /* Tx-related ring data */ 403 struct xgbe_tx_ring_data { 404 unsigned int packets; /* BQL packet count */ 405 unsigned int bytes; /* BQL byte count */ 406 }; 407 408 /* Rx-related ring data */ 409 struct xgbe_rx_ring_data { 410 struct xgbe_buffer_data hdr; /* Header locations */ 411 struct xgbe_buffer_data buf; /* Payload locations */ 412 413 unsigned short hdr_len; /* Length of received header */ 414 unsigned short len; /* Length of received packet */ 415 }; 416 417 /* Structure used to hold information related to the descriptor 418 * and the packet associated with the descriptor (always use 419 * use the XGBE_GET_DESC_DATA macro to access this data from the ring) 420 */ 421 struct xgbe_ring_data { 422 struct xgbe_ring_desc *rdesc; /* Virtual address of descriptor */ 423 dma_addr_t rdesc_dma; /* DMA address of descriptor */ 424 425 struct sk_buff *skb; /* Virtual address of SKB */ 426 dma_addr_t skb_dma; /* DMA address of SKB data */ 427 unsigned int skb_dma_len; /* Length of SKB DMA area */ 428 429 struct xgbe_tx_ring_data tx; /* Tx-related data */ 430 struct xgbe_rx_ring_data rx; /* Rx-related data */ 431 432 unsigned int mapped_as_page; 433 434 /* Incomplete receive save location. If the budget is exhausted 435 * or the last descriptor (last normal descriptor or a following 436 * context descriptor) has not been DMA'd yet the current state 437 * of the receive processing needs to be saved. 438 */ 439 unsigned int state_saved; 440 struct { 441 struct sk_buff *skb; 442 unsigned int len; 443 unsigned int error; 444 } state; 445 }; 446 447 struct xgbe_ring { 448 /* Ring lock - used just for TX rings at the moment */ 449 spinlock_t lock; 450 451 /* Per packet related information */ 452 struct xgbe_packet_data packet_data; 453 454 /* Virtual/DMA addresses and count of allocated descriptor memory */ 455 struct xgbe_ring_desc *rdesc; 456 dma_addr_t rdesc_dma; 457 unsigned int rdesc_count; 458 459 /* Array of descriptor data corresponding the descriptor memory 460 * (always use the XGBE_GET_DESC_DATA macro to access this data) 461 */ 462 struct xgbe_ring_data *rdata; 463 464 /* Page allocation for RX buffers */ 465 struct xgbe_page_alloc rx_hdr_pa; 466 struct xgbe_page_alloc rx_buf_pa; 467 int node; 468 469 /* Ring index values 470 * cur - Tx: index of descriptor to be used for current transfer 471 * Rx: index of descriptor to check for packet availability 472 * dirty - Tx: index of descriptor to check for transfer complete 473 * Rx: index of descriptor to check for buffer reallocation 474 */ 475 unsigned int cur; 476 unsigned int dirty; 477 478 /* Coalesce frame count used for interrupt bit setting */ 479 unsigned int coalesce_count; 480 481 union { 482 struct { 483 unsigned int queue_stopped; 484 unsigned int xmit_more; 485 unsigned short cur_mss; 486 unsigned short cur_vlan_ctag; 487 } tx; 488 }; 489 } ____cacheline_aligned; 490 491 /* Structure used to describe the descriptor rings associated with 492 * a DMA channel. 493 */ 494 struct xgbe_channel { 495 char name[16]; 496 497 /* Address of private data area for device */ 498 struct xgbe_prv_data *pdata; 499 500 /* Queue index and base address of queue's DMA registers */ 501 unsigned int queue_index; 502 void __iomem *dma_regs; 503 504 /* Per channel interrupt irq number */ 505 int dma_irq; 506 char dma_irq_name[IFNAMSIZ + 32]; 507 508 /* Netdev related settings */ 509 struct napi_struct napi; 510 511 /* Per channel interrupt enablement tracker */ 512 unsigned int curr_ier; 513 unsigned int saved_ier; 514 515 unsigned int tx_timer_active; 516 struct timer_list tx_timer; 517 518 struct xgbe_ring *tx_ring; 519 struct xgbe_ring *rx_ring; 520 521 int node; 522 cpumask_t affinity_mask; 523 } ____cacheline_aligned; 524 525 enum xgbe_state { 526 XGBE_DOWN, 527 XGBE_LINK_INIT, 528 XGBE_LINK_ERR, 529 XGBE_STOPPED, 530 }; 531 532 enum xgbe_int { 533 XGMAC_INT_DMA_CH_SR_TI, 534 XGMAC_INT_DMA_CH_SR_TPS, 535 XGMAC_INT_DMA_CH_SR_TBU, 536 XGMAC_INT_DMA_CH_SR_RI, 537 XGMAC_INT_DMA_CH_SR_RBU, 538 XGMAC_INT_DMA_CH_SR_RPS, 539 XGMAC_INT_DMA_CH_SR_TI_RI, 540 XGMAC_INT_DMA_CH_SR_FBE, 541 XGMAC_INT_DMA_ALL, 542 }; 543 544 enum xgbe_int_state { 545 XGMAC_INT_STATE_SAVE, 546 XGMAC_INT_STATE_RESTORE, 547 }; 548 549 enum xgbe_ecc_sec { 550 XGBE_ECC_SEC_TX, 551 XGBE_ECC_SEC_RX, 552 XGBE_ECC_SEC_DESC, 553 }; 554 555 enum xgbe_speed { 556 XGBE_SPEED_1000 = 0, 557 XGBE_SPEED_2500, 558 XGBE_SPEED_10000, 559 XGBE_SPEEDS, 560 }; 561 562 enum xgbe_xpcs_access { 563 XGBE_XPCS_ACCESS_V1 = 0, 564 XGBE_XPCS_ACCESS_V2, 565 }; 566 567 enum xgbe_an_mode { 568 XGBE_AN_MODE_CL73 = 0, 569 XGBE_AN_MODE_CL73_REDRV, 570 XGBE_AN_MODE_CL37, 571 XGBE_AN_MODE_CL37_SGMII, 572 XGBE_AN_MODE_NONE, 573 }; 574 575 enum xgbe_an { 576 XGBE_AN_READY = 0, 577 XGBE_AN_PAGE_RECEIVED, 578 XGBE_AN_INCOMPAT_LINK, 579 XGBE_AN_COMPLETE, 580 XGBE_AN_NO_LINK, 581 XGBE_AN_ERROR, 582 }; 583 584 enum xgbe_rx { 585 XGBE_RX_BPA = 0, 586 XGBE_RX_XNP, 587 XGBE_RX_COMPLETE, 588 XGBE_RX_ERROR, 589 }; 590 591 enum xgbe_mode { 592 XGBE_MODE_KX_1000 = 0, 593 XGBE_MODE_KX_2500, 594 XGBE_MODE_KR, 595 XGBE_MODE_X, 596 XGBE_MODE_SGMII_100, 597 XGBE_MODE_SGMII_1000, 598 XGBE_MODE_SFI, 599 XGBE_MODE_UNKNOWN, 600 }; 601 602 enum xgbe_speedset { 603 XGBE_SPEEDSET_1000_10000 = 0, 604 XGBE_SPEEDSET_2500_10000, 605 }; 606 607 enum xgbe_mdio_mode { 608 XGBE_MDIO_MODE_NONE = 0, 609 XGBE_MDIO_MODE_CL22, 610 XGBE_MDIO_MODE_CL45, 611 }; 612 613 struct xgbe_phy { 614 struct ethtool_link_ksettings lks; 615 616 int address; 617 618 int autoneg; 619 int speed; 620 int duplex; 621 622 int link; 623 624 int pause_autoneg; 625 int tx_pause; 626 int rx_pause; 627 }; 628 629 enum xgbe_i2c_cmd { 630 XGBE_I2C_CMD_READ = 0, 631 XGBE_I2C_CMD_WRITE, 632 }; 633 634 struct xgbe_i2c_op { 635 enum xgbe_i2c_cmd cmd; 636 637 unsigned int target; 638 639 void *buf; 640 unsigned int len; 641 }; 642 643 struct xgbe_i2c_op_state { 644 struct xgbe_i2c_op *op; 645 646 unsigned int tx_len; 647 unsigned char *tx_buf; 648 649 unsigned int rx_len; 650 unsigned char *rx_buf; 651 652 unsigned int tx_abort_source; 653 654 int ret; 655 }; 656 657 struct xgbe_i2c { 658 unsigned int started; 659 unsigned int max_speed_mode; 660 unsigned int rx_fifo_size; 661 unsigned int tx_fifo_size; 662 663 struct xgbe_i2c_op_state op_state; 664 }; 665 666 struct xgbe_mmc_stats { 667 /* Tx Stats */ 668 u64 txoctetcount_gb; 669 u64 txframecount_gb; 670 u64 txbroadcastframes_g; 671 u64 txmulticastframes_g; 672 u64 tx64octets_gb; 673 u64 tx65to127octets_gb; 674 u64 tx128to255octets_gb; 675 u64 tx256to511octets_gb; 676 u64 tx512to1023octets_gb; 677 u64 tx1024tomaxoctets_gb; 678 u64 txunicastframes_gb; 679 u64 txmulticastframes_gb; 680 u64 txbroadcastframes_gb; 681 u64 txunderflowerror; 682 u64 txoctetcount_g; 683 u64 txframecount_g; 684 u64 txpauseframes; 685 u64 txvlanframes_g; 686 687 /* Rx Stats */ 688 u64 rxframecount_gb; 689 u64 rxoctetcount_gb; 690 u64 rxoctetcount_g; 691 u64 rxbroadcastframes_g; 692 u64 rxmulticastframes_g; 693 u64 rxcrcerror; 694 u64 rxrunterror; 695 u64 rxjabbererror; 696 u64 rxundersize_g; 697 u64 rxoversize_g; 698 u64 rx64octets_gb; 699 u64 rx65to127octets_gb; 700 u64 rx128to255octets_gb; 701 u64 rx256to511octets_gb; 702 u64 rx512to1023octets_gb; 703 u64 rx1024tomaxoctets_gb; 704 u64 rxunicastframes_g; 705 u64 rxlengtherror; 706 u64 rxoutofrangetype; 707 u64 rxpauseframes; 708 u64 rxfifooverflow; 709 u64 rxvlanframes_gb; 710 u64 rxwatchdogerror; 711 }; 712 713 struct xgbe_ext_stats { 714 u64 tx_tso_packets; 715 u64 rx_split_header_packets; 716 u64 rx_buffer_unavailable; 717 718 u64 txq_packets[XGBE_MAX_DMA_CHANNELS]; 719 u64 txq_bytes[XGBE_MAX_DMA_CHANNELS]; 720 u64 rxq_packets[XGBE_MAX_DMA_CHANNELS]; 721 u64 rxq_bytes[XGBE_MAX_DMA_CHANNELS]; 722 723 u64 tx_vxlan_packets; 724 u64 rx_vxlan_packets; 725 u64 rx_csum_errors; 726 u64 rx_vxlan_csum_errors; 727 }; 728 729 struct xgbe_hw_if { 730 int (*tx_complete)(struct xgbe_ring_desc *); 731 732 int (*set_mac_address)(struct xgbe_prv_data *, u8 *addr); 733 int (*config_rx_mode)(struct xgbe_prv_data *); 734 735 int (*enable_rx_csum)(struct xgbe_prv_data *); 736 int (*disable_rx_csum)(struct xgbe_prv_data *); 737 738 int (*enable_rx_vlan_stripping)(struct xgbe_prv_data *); 739 int (*disable_rx_vlan_stripping)(struct xgbe_prv_data *); 740 int (*enable_rx_vlan_filtering)(struct xgbe_prv_data *); 741 int (*disable_rx_vlan_filtering)(struct xgbe_prv_data *); 742 int (*update_vlan_hash_table)(struct xgbe_prv_data *); 743 744 int (*read_mmd_regs)(struct xgbe_prv_data *, int, int); 745 void (*write_mmd_regs)(struct xgbe_prv_data *, int, int, int); 746 int (*set_speed)(struct xgbe_prv_data *, int); 747 748 int (*set_ext_mii_mode)(struct xgbe_prv_data *, unsigned int, 749 enum xgbe_mdio_mode); 750 int (*read_ext_mii_regs)(struct xgbe_prv_data *, int, int); 751 int (*write_ext_mii_regs)(struct xgbe_prv_data *, int, int, u16); 752 753 int (*set_gpio)(struct xgbe_prv_data *, unsigned int); 754 int (*clr_gpio)(struct xgbe_prv_data *, unsigned int); 755 756 void (*enable_tx)(struct xgbe_prv_data *); 757 void (*disable_tx)(struct xgbe_prv_data *); 758 void (*enable_rx)(struct xgbe_prv_data *); 759 void (*disable_rx)(struct xgbe_prv_data *); 760 761 void (*powerup_tx)(struct xgbe_prv_data *); 762 void (*powerdown_tx)(struct xgbe_prv_data *); 763 void (*powerup_rx)(struct xgbe_prv_data *); 764 void (*powerdown_rx)(struct xgbe_prv_data *); 765 766 int (*init)(struct xgbe_prv_data *); 767 int (*exit)(struct xgbe_prv_data *); 768 769 int (*enable_int)(struct xgbe_channel *, enum xgbe_int); 770 int (*disable_int)(struct xgbe_channel *, enum xgbe_int); 771 void (*dev_xmit)(struct xgbe_channel *); 772 int (*dev_read)(struct xgbe_channel *); 773 void (*tx_desc_init)(struct xgbe_channel *); 774 void (*rx_desc_init)(struct xgbe_channel *); 775 void (*tx_desc_reset)(struct xgbe_ring_data *); 776 void (*rx_desc_reset)(struct xgbe_prv_data *, struct xgbe_ring_data *, 777 unsigned int); 778 int (*is_last_desc)(struct xgbe_ring_desc *); 779 int (*is_context_desc)(struct xgbe_ring_desc *); 780 void (*tx_start_xmit)(struct xgbe_channel *, struct xgbe_ring *); 781 782 /* For FLOW ctrl */ 783 int (*config_tx_flow_control)(struct xgbe_prv_data *); 784 int (*config_rx_flow_control)(struct xgbe_prv_data *); 785 786 /* For RX coalescing */ 787 int (*config_rx_coalesce)(struct xgbe_prv_data *); 788 int (*config_tx_coalesce)(struct xgbe_prv_data *); 789 unsigned int (*usec_to_riwt)(struct xgbe_prv_data *, unsigned int); 790 unsigned int (*riwt_to_usec)(struct xgbe_prv_data *, unsigned int); 791 792 /* For RX and TX threshold config */ 793 int (*config_rx_threshold)(struct xgbe_prv_data *, unsigned int); 794 int (*config_tx_threshold)(struct xgbe_prv_data *, unsigned int); 795 796 /* For RX and TX Store and Forward Mode config */ 797 int (*config_rsf_mode)(struct xgbe_prv_data *, unsigned int); 798 int (*config_tsf_mode)(struct xgbe_prv_data *, unsigned int); 799 800 /* For TX DMA Operate on Second Frame config */ 801 int (*config_osp_mode)(struct xgbe_prv_data *); 802 803 /* For MMC statistics */ 804 void (*rx_mmc_int)(struct xgbe_prv_data *); 805 void (*tx_mmc_int)(struct xgbe_prv_data *); 806 void (*read_mmc_stats)(struct xgbe_prv_data *); 807 808 /* For Timestamp config */ 809 int (*config_tstamp)(struct xgbe_prv_data *, unsigned int); 810 void (*update_tstamp_addend)(struct xgbe_prv_data *, unsigned int); 811 void (*set_tstamp_time)(struct xgbe_prv_data *, unsigned int sec, 812 unsigned int nsec); 813 u64 (*get_tstamp_time)(struct xgbe_prv_data *); 814 u64 (*get_tx_tstamp)(struct xgbe_prv_data *); 815 816 /* For Data Center Bridging config */ 817 void (*config_tc)(struct xgbe_prv_data *); 818 void (*config_dcb_tc)(struct xgbe_prv_data *); 819 void (*config_dcb_pfc)(struct xgbe_prv_data *); 820 821 /* For Receive Side Scaling */ 822 int (*enable_rss)(struct xgbe_prv_data *); 823 int (*disable_rss)(struct xgbe_prv_data *); 824 int (*set_rss_hash_key)(struct xgbe_prv_data *, const u8 *); 825 int (*set_rss_lookup_table)(struct xgbe_prv_data *, const u32 *); 826 827 /* For ECC */ 828 void (*disable_ecc_ded)(struct xgbe_prv_data *); 829 void (*disable_ecc_sec)(struct xgbe_prv_data *, enum xgbe_ecc_sec); 830 831 /* For VXLAN */ 832 void (*enable_vxlan)(struct xgbe_prv_data *); 833 void (*disable_vxlan)(struct xgbe_prv_data *); 834 void (*set_vxlan_id)(struct xgbe_prv_data *); 835 }; 836 837 /* This structure represents implementation specific routines for an 838 * implementation of a PHY. All routines are required unless noted below. 839 * Optional routines: 840 * an_pre, an_post 841 * kr_training_pre, kr_training_post 842 * module_info, module_eeprom 843 */ 844 struct xgbe_phy_impl_if { 845 /* Perform Setup/teardown actions */ 846 int (*init)(struct xgbe_prv_data *); 847 void (*exit)(struct xgbe_prv_data *); 848 849 /* Perform start/stop specific actions */ 850 int (*reset)(struct xgbe_prv_data *); 851 int (*start)(struct xgbe_prv_data *); 852 void (*stop)(struct xgbe_prv_data *); 853 854 /* Return the link status */ 855 int (*link_status)(struct xgbe_prv_data *, int *); 856 857 /* Indicate if a particular speed is valid */ 858 bool (*valid_speed)(struct xgbe_prv_data *, int); 859 860 /* Check if the specified mode can/should be used */ 861 bool (*use_mode)(struct xgbe_prv_data *, enum xgbe_mode); 862 /* Switch the PHY into various modes */ 863 void (*set_mode)(struct xgbe_prv_data *, enum xgbe_mode); 864 /* Retrieve mode needed for a specific speed */ 865 enum xgbe_mode (*get_mode)(struct xgbe_prv_data *, int); 866 /* Retrieve new/next mode when trying to auto-negotiate */ 867 enum xgbe_mode (*switch_mode)(struct xgbe_prv_data *); 868 /* Retrieve current mode */ 869 enum xgbe_mode (*cur_mode)(struct xgbe_prv_data *); 870 871 /* Retrieve current auto-negotiation mode */ 872 enum xgbe_an_mode (*an_mode)(struct xgbe_prv_data *); 873 874 /* Configure auto-negotiation settings */ 875 int (*an_config)(struct xgbe_prv_data *); 876 877 /* Set/override auto-negotiation advertisement settings */ 878 void (*an_advertising)(struct xgbe_prv_data *, 879 struct ethtool_link_ksettings *); 880 881 /* Process results of auto-negotiation */ 882 enum xgbe_mode (*an_outcome)(struct xgbe_prv_data *); 883 884 /* Pre/Post auto-negotiation support */ 885 void (*an_pre)(struct xgbe_prv_data *); 886 void (*an_post)(struct xgbe_prv_data *); 887 888 /* Pre/Post KR training enablement support */ 889 void (*kr_training_pre)(struct xgbe_prv_data *); 890 void (*kr_training_post)(struct xgbe_prv_data *); 891 892 /* SFP module related info */ 893 int (*module_info)(struct xgbe_prv_data *pdata, 894 struct ethtool_modinfo *modinfo); 895 int (*module_eeprom)(struct xgbe_prv_data *pdata, 896 struct ethtool_eeprom *eeprom, u8 *data); 897 }; 898 899 struct xgbe_phy_if { 900 /* For PHY setup/teardown */ 901 int (*phy_init)(struct xgbe_prv_data *); 902 void (*phy_exit)(struct xgbe_prv_data *); 903 904 /* For PHY support when setting device up/down */ 905 int (*phy_reset)(struct xgbe_prv_data *); 906 int (*phy_start)(struct xgbe_prv_data *); 907 void (*phy_stop)(struct xgbe_prv_data *); 908 909 /* For PHY support while device is up */ 910 void (*phy_status)(struct xgbe_prv_data *); 911 int (*phy_config_aneg)(struct xgbe_prv_data *); 912 913 /* For PHY settings validation */ 914 bool (*phy_valid_speed)(struct xgbe_prv_data *, int); 915 916 /* For single interrupt support */ 917 irqreturn_t (*an_isr)(struct xgbe_prv_data *); 918 919 /* For ethtool PHY support */ 920 int (*module_info)(struct xgbe_prv_data *pdata, 921 struct ethtool_modinfo *modinfo); 922 int (*module_eeprom)(struct xgbe_prv_data *pdata, 923 struct ethtool_eeprom *eeprom, u8 *data); 924 925 /* PHY implementation specific services */ 926 struct xgbe_phy_impl_if phy_impl; 927 }; 928 929 struct xgbe_i2c_if { 930 /* For initial I2C setup */ 931 int (*i2c_init)(struct xgbe_prv_data *); 932 933 /* For I2C support when setting device up/down */ 934 int (*i2c_start)(struct xgbe_prv_data *); 935 void (*i2c_stop)(struct xgbe_prv_data *); 936 937 /* For performing I2C operations */ 938 int (*i2c_xfer)(struct xgbe_prv_data *, struct xgbe_i2c_op *); 939 940 /* For single interrupt support */ 941 irqreturn_t (*i2c_isr)(struct xgbe_prv_data *); 942 }; 943 944 struct xgbe_desc_if { 945 int (*alloc_ring_resources)(struct xgbe_prv_data *); 946 void (*free_ring_resources)(struct xgbe_prv_data *); 947 int (*map_tx_skb)(struct xgbe_channel *, struct sk_buff *); 948 int (*map_rx_buffer)(struct xgbe_prv_data *, struct xgbe_ring *, 949 struct xgbe_ring_data *); 950 void (*unmap_rdata)(struct xgbe_prv_data *, struct xgbe_ring_data *); 951 void (*wrapper_tx_desc_init)(struct xgbe_prv_data *); 952 void (*wrapper_rx_desc_init)(struct xgbe_prv_data *); 953 }; 954 955 /* This structure contains flags that indicate what hardware features 956 * or configurations are present in the device. 957 */ 958 struct xgbe_hw_features { 959 /* HW Version */ 960 unsigned int version; 961 962 /* HW Feature Register0 */ 963 unsigned int gmii; /* 1000 Mbps support */ 964 unsigned int vlhash; /* VLAN Hash Filter */ 965 unsigned int sma; /* SMA(MDIO) Interface */ 966 unsigned int rwk; /* PMT remote wake-up packet */ 967 unsigned int mgk; /* PMT magic packet */ 968 unsigned int mmc; /* RMON module */ 969 unsigned int aoe; /* ARP Offload */ 970 unsigned int ts; /* IEEE 1588-2008 Advanced Timestamp */ 971 unsigned int eee; /* Energy Efficient Ethernet */ 972 unsigned int tx_coe; /* Tx Checksum Offload */ 973 unsigned int rx_coe; /* Rx Checksum Offload */ 974 unsigned int addn_mac; /* Additional MAC Addresses */ 975 unsigned int ts_src; /* Timestamp Source */ 976 unsigned int sa_vlan_ins; /* Source Address or VLAN Insertion */ 977 unsigned int vxn; /* VXLAN/NVGRE */ 978 979 /* HW Feature Register1 */ 980 unsigned int rx_fifo_size; /* MTL Receive FIFO Size */ 981 unsigned int tx_fifo_size; /* MTL Transmit FIFO Size */ 982 unsigned int adv_ts_hi; /* Advance Timestamping High Word */ 983 unsigned int dma_width; /* DMA width */ 984 unsigned int dcb; /* DCB Feature */ 985 unsigned int sph; /* Split Header Feature */ 986 unsigned int tso; /* TCP Segmentation Offload */ 987 unsigned int dma_debug; /* DMA Debug Registers */ 988 unsigned int rss; /* Receive Side Scaling */ 989 unsigned int tc_cnt; /* Number of Traffic Classes */ 990 unsigned int hash_table_size; /* Hash Table Size */ 991 unsigned int l3l4_filter_num; /* Number of L3-L4 Filters */ 992 993 /* HW Feature Register2 */ 994 unsigned int rx_q_cnt; /* Number of MTL Receive Queues */ 995 unsigned int tx_q_cnt; /* Number of MTL Transmit Queues */ 996 unsigned int rx_ch_cnt; /* Number of DMA Receive Channels */ 997 unsigned int tx_ch_cnt; /* Number of DMA Transmit Channels */ 998 unsigned int pps_out_num; /* Number of PPS outputs */ 999 unsigned int aux_snap_num; /* Number of Aux snapshot inputs */ 1000 }; 1001 1002 struct xgbe_version_data { 1003 void (*init_function_ptrs_phy_impl)(struct xgbe_phy_if *); 1004 enum xgbe_xpcs_access xpcs_access; 1005 unsigned int mmc_64bit; 1006 unsigned int tx_max_fifo_size; 1007 unsigned int rx_max_fifo_size; 1008 unsigned int tx_tstamp_workaround; 1009 unsigned int ecc_support; 1010 unsigned int i2c_support; 1011 unsigned int irq_reissue_support; 1012 unsigned int tx_desc_prefetch; 1013 unsigned int rx_desc_prefetch; 1014 unsigned int an_cdr_workaround; 1015 }; 1016 1017 struct xgbe_prv_data { 1018 struct net_device *netdev; 1019 struct pci_dev *pcidev; 1020 struct platform_device *platdev; 1021 struct acpi_device *adev; 1022 struct device *dev; 1023 struct platform_device *phy_platdev; 1024 struct device *phy_dev; 1025 1026 /* Version related data */ 1027 struct xgbe_version_data *vdata; 1028 1029 /* ACPI or DT flag */ 1030 unsigned int use_acpi; 1031 1032 /* XGMAC/XPCS related mmio registers */ 1033 void __iomem *xgmac_regs; /* XGMAC CSRs */ 1034 void __iomem *xpcs_regs; /* XPCS MMD registers */ 1035 void __iomem *rxtx_regs; /* SerDes Rx/Tx CSRs */ 1036 void __iomem *sir0_regs; /* SerDes integration registers (1/2) */ 1037 void __iomem *sir1_regs; /* SerDes integration registers (2/2) */ 1038 void __iomem *xprop_regs; /* XGBE property registers */ 1039 void __iomem *xi2c_regs; /* XGBE I2C CSRs */ 1040 1041 /* Port property registers */ 1042 unsigned int pp0; 1043 unsigned int pp1; 1044 unsigned int pp2; 1045 unsigned int pp3; 1046 unsigned int pp4; 1047 1048 /* Overall device lock */ 1049 spinlock_t lock; 1050 1051 /* XPCS indirect addressing lock */ 1052 spinlock_t xpcs_lock; 1053 unsigned int xpcs_window_def_reg; 1054 unsigned int xpcs_window_sel_reg; 1055 unsigned int xpcs_window; 1056 unsigned int xpcs_window_size; 1057 unsigned int xpcs_window_mask; 1058 1059 /* RSS addressing mutex */ 1060 struct mutex rss_mutex; 1061 1062 /* Flags representing xgbe_state */ 1063 unsigned long dev_state; 1064 1065 /* ECC support */ 1066 unsigned long tx_sec_period; 1067 unsigned long tx_ded_period; 1068 unsigned long rx_sec_period; 1069 unsigned long rx_ded_period; 1070 unsigned long desc_sec_period; 1071 unsigned long desc_ded_period; 1072 1073 unsigned int tx_sec_count; 1074 unsigned int tx_ded_count; 1075 unsigned int rx_sec_count; 1076 unsigned int rx_ded_count; 1077 unsigned int desc_ded_count; 1078 unsigned int desc_sec_count; 1079 1080 int dev_irq; 1081 int ecc_irq; 1082 int i2c_irq; 1083 int channel_irq[XGBE_MAX_DMA_CHANNELS]; 1084 1085 unsigned int per_channel_irq; 1086 unsigned int irq_count; 1087 unsigned int channel_irq_count; 1088 unsigned int channel_irq_mode; 1089 1090 char ecc_name[IFNAMSIZ + 32]; 1091 1092 struct xgbe_hw_if hw_if; 1093 struct xgbe_phy_if phy_if; 1094 struct xgbe_desc_if desc_if; 1095 struct xgbe_i2c_if i2c_if; 1096 1097 /* AXI DMA settings */ 1098 unsigned int coherent; 1099 unsigned int arcr; 1100 unsigned int awcr; 1101 unsigned int awarcr; 1102 1103 /* Service routine support */ 1104 struct workqueue_struct *dev_workqueue; 1105 struct work_struct service_work; 1106 struct timer_list service_timer; 1107 1108 /* Rings for Tx/Rx on a DMA channel */ 1109 struct xgbe_channel *channel[XGBE_MAX_DMA_CHANNELS]; 1110 unsigned int tx_max_channel_count; 1111 unsigned int rx_max_channel_count; 1112 unsigned int channel_count; 1113 unsigned int tx_ring_count; 1114 unsigned int tx_desc_count; 1115 unsigned int rx_ring_count; 1116 unsigned int rx_desc_count; 1117 1118 unsigned int new_tx_ring_count; 1119 unsigned int new_rx_ring_count; 1120 1121 unsigned int tx_max_q_count; 1122 unsigned int rx_max_q_count; 1123 unsigned int tx_q_count; 1124 unsigned int rx_q_count; 1125 1126 /* Tx/Rx common settings */ 1127 unsigned int blen; 1128 unsigned int pbl; 1129 unsigned int aal; 1130 unsigned int rd_osr_limit; 1131 unsigned int wr_osr_limit; 1132 1133 /* Tx settings */ 1134 unsigned int tx_sf_mode; 1135 unsigned int tx_threshold; 1136 unsigned int tx_osp_mode; 1137 unsigned int tx_max_fifo_size; 1138 1139 /* Rx settings */ 1140 unsigned int rx_sf_mode; 1141 unsigned int rx_threshold; 1142 unsigned int rx_max_fifo_size; 1143 1144 /* Tx coalescing settings */ 1145 unsigned int tx_usecs; 1146 unsigned int tx_frames; 1147 1148 /* Rx coalescing settings */ 1149 unsigned int rx_riwt; 1150 unsigned int rx_usecs; 1151 unsigned int rx_frames; 1152 1153 /* Current Rx buffer size */ 1154 unsigned int rx_buf_size; 1155 1156 /* Flow control settings */ 1157 unsigned int pause_autoneg; 1158 unsigned int tx_pause; 1159 unsigned int rx_pause; 1160 unsigned int rx_rfa[XGBE_MAX_QUEUES]; 1161 unsigned int rx_rfd[XGBE_MAX_QUEUES]; 1162 1163 /* Receive Side Scaling settings */ 1164 u8 rss_key[XGBE_RSS_HASH_KEY_SIZE]; 1165 u32 rss_table[XGBE_RSS_MAX_TABLE_SIZE]; 1166 u32 rss_options; 1167 1168 /* VXLAN settings */ 1169 u16 vxlan_port; 1170 1171 /* Netdev related settings */ 1172 unsigned char mac_addr[ETH_ALEN]; 1173 netdev_features_t netdev_features; 1174 struct napi_struct napi; 1175 struct xgbe_mmc_stats mmc_stats; 1176 struct xgbe_ext_stats ext_stats; 1177 1178 /* Filtering support */ 1179 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 1180 1181 /* Device clocks */ 1182 struct clk *sysclk; 1183 unsigned long sysclk_rate; 1184 struct clk *ptpclk; 1185 unsigned long ptpclk_rate; 1186 1187 /* Timestamp support */ 1188 spinlock_t tstamp_lock; 1189 struct ptp_clock_info ptp_clock_info; 1190 struct ptp_clock *ptp_clock; 1191 struct hwtstamp_config tstamp_config; 1192 struct cyclecounter tstamp_cc; 1193 struct timecounter tstamp_tc; 1194 unsigned int tstamp_addend; 1195 struct work_struct tx_tstamp_work; 1196 struct sk_buff *tx_tstamp_skb; 1197 u64 tx_tstamp; 1198 1199 /* DCB support */ 1200 struct ieee_ets *ets; 1201 struct ieee_pfc *pfc; 1202 unsigned int q2tc_map[XGBE_MAX_QUEUES]; 1203 unsigned int prio2q_map[IEEE_8021QAZ_MAX_TCS]; 1204 unsigned int pfcq[XGBE_MAX_QUEUES]; 1205 unsigned int pfc_rfa; 1206 u8 num_tcs; 1207 1208 /* Hardware features of the device */ 1209 struct xgbe_hw_features hw_feat; 1210 1211 /* Device work structures */ 1212 struct work_struct restart_work; 1213 struct work_struct stopdev_work; 1214 1215 /* Keeps track of power mode */ 1216 unsigned int power_down; 1217 1218 /* Network interface message level setting */ 1219 u32 msg_enable; 1220 1221 /* Current PHY settings */ 1222 phy_interface_t phy_mode; 1223 int phy_link; 1224 int phy_speed; 1225 1226 /* MDIO/PHY related settings */ 1227 unsigned int phy_started; 1228 void *phy_data; 1229 struct xgbe_phy phy; 1230 int mdio_mmd; 1231 unsigned long link_check; 1232 struct completion mdio_complete; 1233 1234 unsigned int kr_redrv; 1235 1236 char an_name[IFNAMSIZ + 32]; 1237 struct workqueue_struct *an_workqueue; 1238 1239 int an_irq; 1240 struct work_struct an_irq_work; 1241 1242 /* Auto-negotiation state machine support */ 1243 unsigned int an_int; 1244 unsigned int an_status; 1245 struct mutex an_mutex; 1246 enum xgbe_an an_result; 1247 enum xgbe_an an_state; 1248 enum xgbe_rx kr_state; 1249 enum xgbe_rx kx_state; 1250 struct work_struct an_work; 1251 unsigned int an_again; 1252 unsigned int an_supported; 1253 unsigned int parallel_detect; 1254 unsigned int fec_ability; 1255 unsigned long an_start; 1256 enum xgbe_an_mode an_mode; 1257 1258 /* I2C support */ 1259 struct xgbe_i2c i2c; 1260 struct mutex i2c_mutex; 1261 struct completion i2c_complete; 1262 char i2c_name[IFNAMSIZ + 32]; 1263 1264 unsigned int lpm_ctrl; /* CTRL1 for resume */ 1265 1266 unsigned int isr_as_tasklet; 1267 struct tasklet_struct tasklet_dev; 1268 struct tasklet_struct tasklet_ecc; 1269 struct tasklet_struct tasklet_i2c; 1270 struct tasklet_struct tasklet_an; 1271 1272 struct dentry *xgbe_debugfs; 1273 1274 unsigned int debugfs_xgmac_reg; 1275 1276 unsigned int debugfs_xpcs_mmd; 1277 unsigned int debugfs_xpcs_reg; 1278 1279 unsigned int debugfs_xprop_reg; 1280 1281 unsigned int debugfs_xi2c_reg; 1282 1283 bool debugfs_an_cdr_workaround; 1284 bool debugfs_an_cdr_track_early; 1285 }; 1286 1287 /* Function prototypes*/ 1288 struct xgbe_prv_data *xgbe_alloc_pdata(struct device *); 1289 void xgbe_free_pdata(struct xgbe_prv_data *); 1290 void xgbe_set_counts(struct xgbe_prv_data *); 1291 int xgbe_config_netdev(struct xgbe_prv_data *); 1292 void xgbe_deconfig_netdev(struct xgbe_prv_data *); 1293 1294 int xgbe_platform_init(void); 1295 void xgbe_platform_exit(void); 1296 #ifdef CONFIG_PCI 1297 int xgbe_pci_init(void); 1298 void xgbe_pci_exit(void); 1299 #else 1300 static inline int xgbe_pci_init(void) { return 0; } 1301 static inline void xgbe_pci_exit(void) { } 1302 #endif 1303 1304 void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *); 1305 void xgbe_init_function_ptrs_phy(struct xgbe_phy_if *); 1306 void xgbe_init_function_ptrs_phy_v1(struct xgbe_phy_if *); 1307 void xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if *); 1308 void xgbe_init_function_ptrs_desc(struct xgbe_desc_if *); 1309 void xgbe_init_function_ptrs_i2c(struct xgbe_i2c_if *); 1310 const struct net_device_ops *xgbe_get_netdev_ops(void); 1311 const struct ethtool_ops *xgbe_get_ethtool_ops(void); 1312 const struct udp_tunnel_nic_info *xgbe_get_udp_tunnel_info(void); 1313 1314 #ifdef CONFIG_AMD_XGBE_DCB 1315 const struct dcbnl_rtnl_ops *xgbe_get_dcbnl_ops(void); 1316 #endif 1317 1318 void xgbe_ptp_register(struct xgbe_prv_data *); 1319 void xgbe_ptp_unregister(struct xgbe_prv_data *); 1320 void xgbe_dump_tx_desc(struct xgbe_prv_data *, struct xgbe_ring *, 1321 unsigned int, unsigned int, unsigned int); 1322 void xgbe_dump_rx_desc(struct xgbe_prv_data *, struct xgbe_ring *, 1323 unsigned int); 1324 void xgbe_print_pkt(struct net_device *, struct sk_buff *, bool); 1325 void xgbe_get_all_hw_features(struct xgbe_prv_data *); 1326 int xgbe_powerup(struct net_device *, unsigned int); 1327 int xgbe_powerdown(struct net_device *, unsigned int); 1328 void xgbe_init_rx_coalesce(struct xgbe_prv_data *); 1329 void xgbe_init_tx_coalesce(struct xgbe_prv_data *); 1330 void xgbe_restart_dev(struct xgbe_prv_data *pdata); 1331 void xgbe_full_restart_dev(struct xgbe_prv_data *pdata); 1332 1333 #ifdef CONFIG_DEBUG_FS 1334 void xgbe_debugfs_init(struct xgbe_prv_data *); 1335 void xgbe_debugfs_exit(struct xgbe_prv_data *); 1336 void xgbe_debugfs_rename(struct xgbe_prv_data *pdata); 1337 #else 1338 static inline void xgbe_debugfs_init(struct xgbe_prv_data *pdata) {} 1339 static inline void xgbe_debugfs_exit(struct xgbe_prv_data *pdata) {} 1340 static inline void xgbe_debugfs_rename(struct xgbe_prv_data *pdata) {} 1341 #endif /* CONFIG_DEBUG_FS */ 1342 1343 /* NOTE: Uncomment for function trace log messages in KERNEL LOG */ 1344 #if 0 1345 #define YDEBUG 1346 #define YDEBUG_MDIO 1347 #endif 1348 1349 /* For debug prints */ 1350 #ifdef YDEBUG 1351 #define DBGPR(x...) pr_alert(x) 1352 #else 1353 #define DBGPR(x...) do { } while (0) 1354 #endif 1355 1356 #ifdef YDEBUG_MDIO 1357 #define DBGPR_MDIO(x...) pr_alert(x) 1358 #else 1359 #define DBGPR_MDIO(x...) do { } while (0) 1360 #endif 1361 1362 #endif 1363