1 /* 2 * AMD 10Gb Ethernet driver 3 * 4 * This file is available to you under your choice of the following two 5 * licenses: 6 * 7 * License 1: GPLv2 8 * 9 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc. 10 * 11 * This file is free software; you may copy, redistribute and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation, either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program. If not, see <http://www.gnu.org/licenses/>. 23 * 24 * This file incorporates work covered by the following copyright and 25 * permission notice: 26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 28 * Inc. unless otherwise expressly agreed to in writing between Synopsys 29 * and you. 30 * 31 * The Software IS NOT an item of Licensed Software or Licensed Product 32 * under any End User Software License Agreement or Agreement for Licensed 33 * Product with Synopsys or any supplement thereto. Permission is hereby 34 * granted, free of charge, to any person obtaining a copy of this software 35 * annotated with this license and the Software, to deal in the Software 36 * without restriction, including without limitation the rights to use, 37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 38 * of the Software, and to permit persons to whom the Software is furnished 39 * to do so, subject to the following conditions: 40 * 41 * The above copyright notice and this permission notice shall be included 42 * in all copies or substantial portions of the Software. 43 * 44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 54 * THE POSSIBILITY OF SUCH DAMAGE. 55 * 56 * 57 * License 2: Modified BSD 58 * 59 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc. 60 * All rights reserved. 61 * 62 * Redistribution and use in source and binary forms, with or without 63 * modification, are permitted provided that the following conditions are met: 64 * * Redistributions of source code must retain the above copyright 65 * notice, this list of conditions and the following disclaimer. 66 * * Redistributions in binary form must reproduce the above copyright 67 * notice, this list of conditions and the following disclaimer in the 68 * documentation and/or other materials provided with the distribution. 69 * * Neither the name of Advanced Micro Devices, Inc. nor the 70 * names of its contributors may be used to endorse or promote products 71 * derived from this software without specific prior written permission. 72 * 73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY 77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 83 * 84 * This file incorporates work covered by the following copyright and 85 * permission notice: 86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 88 * Inc. unless otherwise expressly agreed to in writing between Synopsys 89 * and you. 90 * 91 * The Software IS NOT an item of Licensed Software or Licensed Product 92 * under any End User Software License Agreement or Agreement for Licensed 93 * Product with Synopsys or any supplement thereto. Permission is hereby 94 * granted, free of charge, to any person obtaining a copy of this software 95 * annotated with this license and the Software, to deal in the Software 96 * without restriction, including without limitation the rights to use, 97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 98 * of the Software, and to permit persons to whom the Software is furnished 99 * to do so, subject to the following conditions: 100 * 101 * The above copyright notice and this permission notice shall be included 102 * in all copies or substantial portions of the Software. 103 * 104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 114 * THE POSSIBILITY OF SUCH DAMAGE. 115 */ 116 117 #ifndef __XGBE_H__ 118 #define __XGBE_H__ 119 120 #include <linux/dma-mapping.h> 121 #include <linux/netdevice.h> 122 #include <linux/workqueue.h> 123 #include <linux/phy.h> 124 #include <linux/if_vlan.h> 125 #include <linux/bitops.h> 126 #include <linux/ptp_clock_kernel.h> 127 #include <linux/timecounter.h> 128 #include <linux/net_tstamp.h> 129 #include <net/dcbnl.h> 130 #include <linux/completion.h> 131 #include <linux/cpumask.h> 132 #include <linux/interrupt.h> 133 #include <linux/dcache.h> 134 #include <linux/ethtool.h> 135 #include <linux/list.h> 136 137 #define XGBE_DRV_NAME "amd-xgbe" 138 #define XGBE_DRV_DESC "AMD 10 Gigabit Ethernet Driver" 139 140 /* Descriptor related defines */ 141 #define XGBE_TX_DESC_CNT 512 142 #define XGBE_TX_DESC_MIN_FREE (XGBE_TX_DESC_CNT >> 3) 143 #define XGBE_TX_DESC_MAX_PROC (XGBE_TX_DESC_CNT >> 1) 144 #define XGBE_RX_DESC_CNT 512 145 146 #define XGBE_TX_DESC_CNT_MIN 64 147 #define XGBE_TX_DESC_CNT_MAX 4096 148 #define XGBE_RX_DESC_CNT_MIN 64 149 #define XGBE_RX_DESC_CNT_MAX 4096 150 151 #define XGBE_TX_MAX_BUF_SIZE (0x3fff & ~(64 - 1)) 152 153 /* Descriptors required for maximum contiguous TSO/GSO packet */ 154 #define XGBE_TX_MAX_SPLIT \ 155 ((GSO_LEGACY_MAX_SIZE / XGBE_TX_MAX_BUF_SIZE) + 1) 156 157 /* Maximum possible descriptors needed for an SKB: 158 * - Maximum number of SKB frags 159 * - Maximum descriptors for contiguous TSO/GSO packet 160 * - Possible context descriptor 161 * - Possible TSO header descriptor 162 */ 163 #define XGBE_TX_MAX_DESCS (MAX_SKB_FRAGS + XGBE_TX_MAX_SPLIT + 2) 164 165 #define XGBE_RX_MIN_BUF_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN) 166 #define XGBE_RX_BUF_ALIGN 64 167 #define XGBE_SKB_ALLOC_SIZE 256 168 #define XGBE_SPH_HDSMS_SIZE 2 /* Keep in sync with SKB_ALLOC_SIZE */ 169 170 #define XGBE_MAX_DMA_CHANNELS 16 171 #define XGBE_MAX_QUEUES 16 172 #define XGBE_PRIORITY_QUEUES 8 173 #define XGBE_DMA_STOP_TIMEOUT 1 174 175 /* DMA cache settings - Outer sharable, write-back, write-allocate */ 176 #define XGBE_DMA_OS_ARCR 0x002b2b2b 177 #define XGBE_DMA_OS_AWCR 0x2f2f2f2f 178 179 /* DMA cache settings - System, no caches used */ 180 #define XGBE_DMA_SYS_ARCR 0x00303030 181 #define XGBE_DMA_SYS_AWCR 0x30303030 182 183 /* DMA cache settings - PCI device */ 184 #define XGBE_DMA_PCI_ARCR 0x000f0f0f 185 #define XGBE_DMA_PCI_AWCR 0x0f0f0f0f 186 #define XGBE_DMA_PCI_AWARCR 0x00000f0f 187 188 /* DMA channel interrupt modes */ 189 #define XGBE_IRQ_MODE_EDGE 0 190 #define XGBE_IRQ_MODE_LEVEL 1 191 192 #define XGMAC_MIN_PACKET 60 193 #define XGMAC_STD_PACKET_MTU 1500 194 #define XGMAC_MAX_STD_PACKET 1518 195 #define XGMAC_JUMBO_PACKET_MTU 9000 196 #define XGMAC_MAX_JUMBO_PACKET 9018 197 #define XGMAC_ETH_PREAMBLE (12 + 8) /* Inter-frame gap + preamble */ 198 199 #define XGMAC_PFC_DATA_LEN 46 200 #define XGMAC_PFC_DELAYS 14000 201 202 #define XGMAC_PRIO_QUEUES(_cnt) \ 203 min_t(unsigned int, IEEE_8021QAZ_MAX_TCS, (_cnt)) 204 205 /* Common property names */ 206 #define XGBE_MAC_ADDR_PROPERTY "mac-address" 207 #define XGBE_PHY_MODE_PROPERTY "phy-mode" 208 #define XGBE_DMA_IRQS_PROPERTY "amd,per-channel-interrupt" 209 #define XGBE_SPEEDSET_PROPERTY "amd,speed-set" 210 211 /* Device-tree clock names */ 212 #define XGBE_DMA_CLOCK "dma_clk" 213 #define XGBE_PTP_CLOCK "ptp_clk" 214 215 /* ACPI property names */ 216 #define XGBE_ACPI_DMA_FREQ "amd,dma-freq" 217 #define XGBE_ACPI_PTP_FREQ "amd,ptp-freq" 218 219 /* PCI BAR mapping */ 220 #define XGBE_XGMAC_BAR 0 221 #define XGBE_XPCS_BAR 1 222 #define XGBE_MAC_PROP_OFFSET 0x1d000 223 #define XGBE_I2C_CTRL_OFFSET 0x1e000 224 225 /* PCI MSI/MSIx support */ 226 #define XGBE_MSI_BASE_COUNT 4 227 #define XGBE_MSI_MIN_COUNT (XGBE_MSI_BASE_COUNT + 1) 228 229 /* PCI clock frequencies */ 230 #define XGBE_V2_DMA_CLOCK_FREQ 500000000 /* 500 MHz */ 231 #define XGBE_V2_PTP_CLOCK_FREQ 125000000 /* 125 MHz */ 232 233 /* Timestamp support - values based on 50MHz PTP clock 234 * 50MHz => 20 nsec 235 */ 236 #define XGBE_TSTAMP_SSINC 20 237 #define XGBE_TSTAMP_SNSINC 0 238 239 /* Driver PMT macros */ 240 #define XGMAC_DRIVER_CONTEXT 1 241 #define XGMAC_IOCTL_CONTEXT 2 242 243 #define XGMAC_FIFO_MIN_ALLOC 2048 244 #define XGMAC_FIFO_UNIT 256 245 #define XGMAC_FIFO_ALIGN(_x) \ 246 (((_x) + XGMAC_FIFO_UNIT - 1) & ~(XGMAC_FIFO_UNIT - 1)) 247 #define XGMAC_FIFO_FC_OFF 2048 248 #define XGMAC_FIFO_FC_MIN 4096 249 250 #define XGBE_TC_MIN_QUANTUM 10 251 252 /* Helper macro for descriptor handling 253 * Always use XGBE_GET_DESC_DATA to access the descriptor data 254 * since the index is free-running and needs to be and-ed 255 * with the descriptor count value of the ring to index to 256 * the proper descriptor data. 257 */ 258 #define XGBE_GET_DESC_DATA(_ring, _idx) \ 259 ((_ring)->rdata + \ 260 ((_idx) & ((_ring)->rdesc_count - 1))) 261 262 /* Default coalescing parameters */ 263 #define XGMAC_INIT_DMA_TX_USECS 1000 264 #define XGMAC_INIT_DMA_TX_FRAMES 25 265 266 #define XGMAC_MAX_DMA_RIWT 0xff 267 #define XGMAC_INIT_DMA_RX_USECS 30 268 #define XGMAC_INIT_DMA_RX_FRAMES 25 269 270 /* Flow control queue count */ 271 #define XGMAC_MAX_FLOW_CONTROL_QUEUES 8 272 273 /* Flow control threshold units */ 274 #define XGMAC_FLOW_CONTROL_UNIT 512 275 #define XGMAC_FLOW_CONTROL_ALIGN(_x) \ 276 (((_x) + XGMAC_FLOW_CONTROL_UNIT - 1) & ~(XGMAC_FLOW_CONTROL_UNIT - 1)) 277 #define XGMAC_FLOW_CONTROL_VALUE(_x) \ 278 (((_x) < 1024) ? 0 : ((_x) / XGMAC_FLOW_CONTROL_UNIT) - 2) 279 #define XGMAC_FLOW_CONTROL_MAX 33280 280 281 /* Maximum MAC address hash table size (256 bits = 8 bytes) */ 282 #define XGBE_MAC_HASH_TABLE_SIZE 8 283 284 /* Receive Side Scaling */ 285 #define XGBE_RSS_HASH_KEY_SIZE 40 286 #define XGBE_RSS_MAX_TABLE_SIZE 256 287 #define XGBE_RSS_LOOKUP_TABLE_TYPE 0 288 #define XGBE_RSS_HASH_KEY_TYPE 1 289 290 /* Auto-negotiation */ 291 #define XGBE_AN_MS_TIMEOUT 500 292 #define XGBE_LINK_TIMEOUT 5 293 294 #define XGBE_SGMII_AN_LINK_STATUS BIT(1) 295 #define XGBE_SGMII_AN_LINK_SPEED (BIT(2) | BIT(3)) 296 #define XGBE_SGMII_AN_LINK_SPEED_100 0x04 297 #define XGBE_SGMII_AN_LINK_SPEED_1000 0x08 298 #define XGBE_SGMII_AN_LINK_DUPLEX BIT(4) 299 300 /* ECC correctable error notification window (seconds) */ 301 #define XGBE_ECC_LIMIT 60 302 303 /* MDIO port types */ 304 #define XGMAC_MAX_C22_PORT 3 305 306 /* Link mode bit operations */ 307 #define XGBE_ZERO_SUP(_ls) \ 308 ethtool_link_ksettings_zero_link_mode((_ls), supported) 309 310 #define XGBE_SET_SUP(_ls, _mode) \ 311 ethtool_link_ksettings_add_link_mode((_ls), supported, _mode) 312 313 #define XGBE_CLR_SUP(_ls, _mode) \ 314 ethtool_link_ksettings_del_link_mode((_ls), supported, _mode) 315 316 #define XGBE_IS_SUP(_ls, _mode) \ 317 ethtool_link_ksettings_test_link_mode((_ls), supported, _mode) 318 319 #define XGBE_ZERO_ADV(_ls) \ 320 ethtool_link_ksettings_zero_link_mode((_ls), advertising) 321 322 #define XGBE_SET_ADV(_ls, _mode) \ 323 ethtool_link_ksettings_add_link_mode((_ls), advertising, _mode) 324 325 #define XGBE_CLR_ADV(_ls, _mode) \ 326 ethtool_link_ksettings_del_link_mode((_ls), advertising, _mode) 327 328 #define XGBE_ADV(_ls, _mode) \ 329 ethtool_link_ksettings_test_link_mode((_ls), advertising, _mode) 330 331 #define XGBE_ZERO_LP_ADV(_ls) \ 332 ethtool_link_ksettings_zero_link_mode((_ls), lp_advertising) 333 334 #define XGBE_SET_LP_ADV(_ls, _mode) \ 335 ethtool_link_ksettings_add_link_mode((_ls), lp_advertising, _mode) 336 337 #define XGBE_CLR_LP_ADV(_ls, _mode) \ 338 ethtool_link_ksettings_del_link_mode((_ls), lp_advertising, _mode) 339 340 #define XGBE_LP_ADV(_ls, _mode) \ 341 ethtool_link_ksettings_test_link_mode((_ls), lp_advertising, _mode) 342 343 #define XGBE_LM_COPY(_dst, _dname, _src, _sname) \ 344 bitmap_copy((_dst)->link_modes._dname, \ 345 (_src)->link_modes._sname, \ 346 __ETHTOOL_LINK_MODE_MASK_NBITS) 347 348 struct xgbe_prv_data; 349 350 struct xgbe_packet_data { 351 struct sk_buff *skb; 352 353 unsigned int attributes; 354 355 unsigned int errors; 356 357 unsigned int rdesc_count; 358 unsigned int length; 359 360 unsigned int header_len; 361 unsigned int tcp_header_len; 362 unsigned int tcp_payload_len; 363 unsigned short mss; 364 365 unsigned short vlan_ctag; 366 367 u64 rx_tstamp; 368 369 u32 rss_hash; 370 enum pkt_hash_types rss_hash_type; 371 372 unsigned int tx_packets; 373 unsigned int tx_bytes; 374 }; 375 376 /* Common Rx and Tx descriptor mapping */ 377 struct xgbe_ring_desc { 378 __le32 desc0; 379 __le32 desc1; 380 __le32 desc2; 381 __le32 desc3; 382 }; 383 384 /* Page allocation related values */ 385 struct xgbe_page_alloc { 386 struct page *pages; 387 unsigned int pages_len; 388 unsigned int pages_offset; 389 390 dma_addr_t pages_dma; 391 }; 392 393 /* Ring entry buffer data */ 394 struct xgbe_buffer_data { 395 struct xgbe_page_alloc pa; 396 struct xgbe_page_alloc pa_unmap; 397 398 dma_addr_t dma_base; 399 unsigned long dma_off; 400 unsigned int dma_len; 401 }; 402 403 /* Tx-related ring data */ 404 struct xgbe_tx_ring_data { 405 unsigned int packets; /* BQL packet count */ 406 unsigned int bytes; /* BQL byte count */ 407 }; 408 409 /* Rx-related ring data */ 410 struct xgbe_rx_ring_data { 411 struct xgbe_buffer_data hdr; /* Header locations */ 412 struct xgbe_buffer_data buf; /* Payload locations */ 413 414 unsigned short hdr_len; /* Length of received header */ 415 unsigned short len; /* Length of received packet */ 416 }; 417 418 /* Structure used to hold information related to the descriptor 419 * and the packet associated with the descriptor (always use 420 * the XGBE_GET_DESC_DATA macro to access this data from the ring) 421 */ 422 struct xgbe_ring_data { 423 struct xgbe_ring_desc *rdesc; /* Virtual address of descriptor */ 424 dma_addr_t rdesc_dma; /* DMA address of descriptor */ 425 426 struct sk_buff *skb; /* Virtual address of SKB */ 427 dma_addr_t skb_dma; /* DMA address of SKB data */ 428 unsigned int skb_dma_len; /* Length of SKB DMA area */ 429 430 struct xgbe_tx_ring_data tx; /* Tx-related data */ 431 struct xgbe_rx_ring_data rx; /* Rx-related data */ 432 433 unsigned int mapped_as_page; 434 435 /* Incomplete receive save location. If the budget is exhausted 436 * or the last descriptor (last normal descriptor or a following 437 * context descriptor) has not been DMA'd yet the current state 438 * of the receive processing needs to be saved. 439 */ 440 unsigned int state_saved; 441 struct { 442 struct sk_buff *skb; 443 unsigned int len; 444 unsigned int error; 445 } state; 446 }; 447 448 struct xgbe_ring { 449 /* Ring lock - used just for TX rings at the moment */ 450 spinlock_t lock; 451 452 /* Per packet related information */ 453 struct xgbe_packet_data packet_data; 454 455 /* Virtual/DMA addresses and count of allocated descriptor memory */ 456 struct xgbe_ring_desc *rdesc; 457 dma_addr_t rdesc_dma; 458 unsigned int rdesc_count; 459 460 /* Array of descriptor data corresponding the descriptor memory 461 * (always use the XGBE_GET_DESC_DATA macro to access this data) 462 */ 463 struct xgbe_ring_data *rdata; 464 465 /* Page allocation for RX buffers */ 466 struct xgbe_page_alloc rx_hdr_pa; 467 struct xgbe_page_alloc rx_buf_pa; 468 int node; 469 470 /* Ring index values 471 * cur - Tx: index of descriptor to be used for current transfer 472 * Rx: index of descriptor to check for packet availability 473 * dirty - Tx: index of descriptor to check for transfer complete 474 * Rx: index of descriptor to check for buffer reallocation 475 */ 476 unsigned int cur; 477 unsigned int dirty; 478 479 /* Coalesce frame count used for interrupt bit setting */ 480 unsigned int coalesce_count; 481 482 union { 483 struct { 484 unsigned int queue_stopped; 485 unsigned int xmit_more; 486 unsigned short cur_mss; 487 unsigned short cur_vlan_ctag; 488 } tx; 489 }; 490 } ____cacheline_aligned; 491 492 /* Structure used to describe the descriptor rings associated with 493 * a DMA channel. 494 */ 495 struct xgbe_channel { 496 char name[16]; 497 498 /* Address of private data area for device */ 499 struct xgbe_prv_data *pdata; 500 501 /* Queue index and base address of queue's DMA registers */ 502 unsigned int queue_index; 503 void __iomem *dma_regs; 504 505 /* Per channel interrupt irq number */ 506 int dma_irq; 507 char dma_irq_name[IFNAMSIZ + 32]; 508 509 /* Netdev related settings */ 510 struct napi_struct napi; 511 512 /* Per channel interrupt enablement tracker */ 513 unsigned int curr_ier; 514 unsigned int saved_ier; 515 516 unsigned int tx_timer_active; 517 struct timer_list tx_timer; 518 519 struct xgbe_ring *tx_ring; 520 struct xgbe_ring *rx_ring; 521 522 int node; 523 cpumask_t affinity_mask; 524 } ____cacheline_aligned; 525 526 enum xgbe_state { 527 XGBE_DOWN, 528 XGBE_LINK_INIT, 529 XGBE_LINK_ERR, 530 XGBE_STOPPED, 531 }; 532 533 enum xgbe_int { 534 XGMAC_INT_DMA_CH_SR_TI, 535 XGMAC_INT_DMA_CH_SR_TPS, 536 XGMAC_INT_DMA_CH_SR_TBU, 537 XGMAC_INT_DMA_CH_SR_RI, 538 XGMAC_INT_DMA_CH_SR_RBU, 539 XGMAC_INT_DMA_CH_SR_RPS, 540 XGMAC_INT_DMA_CH_SR_TI_RI, 541 XGMAC_INT_DMA_CH_SR_FBE, 542 XGMAC_INT_DMA_ALL, 543 }; 544 545 enum xgbe_int_state { 546 XGMAC_INT_STATE_SAVE, 547 XGMAC_INT_STATE_RESTORE, 548 }; 549 550 enum xgbe_ecc_sec { 551 XGBE_ECC_SEC_TX, 552 XGBE_ECC_SEC_RX, 553 XGBE_ECC_SEC_DESC, 554 }; 555 556 enum xgbe_speed { 557 XGBE_SPEED_1000 = 0, 558 XGBE_SPEED_2500, 559 XGBE_SPEED_10000, 560 XGBE_SPEEDS, 561 }; 562 563 enum xgbe_xpcs_access { 564 XGBE_XPCS_ACCESS_V1 = 0, 565 XGBE_XPCS_ACCESS_V2, 566 }; 567 568 enum xgbe_an_mode { 569 XGBE_AN_MODE_CL73 = 0, 570 XGBE_AN_MODE_CL73_REDRV, 571 XGBE_AN_MODE_CL37, 572 XGBE_AN_MODE_CL37_SGMII, 573 XGBE_AN_MODE_NONE, 574 }; 575 576 enum xgbe_an { 577 XGBE_AN_READY = 0, 578 XGBE_AN_PAGE_RECEIVED, 579 XGBE_AN_INCOMPAT_LINK, 580 XGBE_AN_COMPLETE, 581 XGBE_AN_NO_LINK, 582 XGBE_AN_ERROR, 583 }; 584 585 enum xgbe_rx { 586 XGBE_RX_BPA = 0, 587 XGBE_RX_XNP, 588 XGBE_RX_COMPLETE, 589 XGBE_RX_ERROR, 590 }; 591 592 enum xgbe_mode { 593 XGBE_MODE_KX_1000 = 0, 594 XGBE_MODE_KX_2500, 595 XGBE_MODE_KR, 596 XGBE_MODE_X, 597 XGBE_MODE_SGMII_100, 598 XGBE_MODE_SGMII_1000, 599 XGBE_MODE_SFI, 600 XGBE_MODE_UNKNOWN, 601 }; 602 603 enum xgbe_speedset { 604 XGBE_SPEEDSET_1000_10000 = 0, 605 XGBE_SPEEDSET_2500_10000, 606 }; 607 608 enum xgbe_mdio_mode { 609 XGBE_MDIO_MODE_NONE = 0, 610 XGBE_MDIO_MODE_CL22, 611 XGBE_MDIO_MODE_CL45, 612 }; 613 614 enum xgbe_mb_cmd { 615 XGBE_MB_CMD_POWER_OFF = 0, 616 XGBE_MB_CMD_SET_1G, 617 XGBE_MB_CMD_SET_2_5G, 618 XGBE_MB_CMD_SET_10G_SFI, 619 XGBE_MB_CMD_SET_10G_KR, 620 XGBE_MB_CMD_RRC 621 }; 622 623 enum xgbe_mb_subcmd { 624 XGBE_MB_SUBCMD_NONE = 0, 625 626 /* 10GbE SFP subcommands */ 627 XGBE_MB_SUBCMD_ACTIVE = 0, 628 XGBE_MB_SUBCMD_PASSIVE_1M, 629 XGBE_MB_SUBCMD_PASSIVE_3M, 630 XGBE_MB_SUBCMD_PASSIVE_OTHER, 631 632 /* 1GbE Mode subcommands */ 633 XGBE_MB_SUBCMD_10MBITS = 0, 634 XGBE_MB_SUBCMD_100MBITS, 635 XGBE_MB_SUBCMD_1G_SGMII, 636 XGBE_MB_SUBCMD_1G_KX 637 }; 638 639 struct xgbe_phy { 640 struct ethtool_link_ksettings lks; 641 642 int address; 643 644 int autoneg; 645 int speed; 646 int duplex; 647 648 int link; 649 650 int pause_autoneg; 651 int tx_pause; 652 int rx_pause; 653 }; 654 655 enum xgbe_i2c_cmd { 656 XGBE_I2C_CMD_READ = 0, 657 XGBE_I2C_CMD_WRITE, 658 }; 659 660 struct xgbe_i2c_op { 661 enum xgbe_i2c_cmd cmd; 662 663 unsigned int target; 664 665 void *buf; 666 unsigned int len; 667 }; 668 669 struct xgbe_i2c_op_state { 670 struct xgbe_i2c_op *op; 671 672 unsigned int tx_len; 673 unsigned char *tx_buf; 674 675 unsigned int rx_len; 676 unsigned char *rx_buf; 677 678 unsigned int tx_abort_source; 679 680 int ret; 681 }; 682 683 struct xgbe_i2c { 684 unsigned int started; 685 unsigned int max_speed_mode; 686 unsigned int rx_fifo_size; 687 unsigned int tx_fifo_size; 688 689 struct xgbe_i2c_op_state op_state; 690 }; 691 692 struct xgbe_mmc_stats { 693 /* Tx Stats */ 694 u64 txoctetcount_gb; 695 u64 txframecount_gb; 696 u64 txbroadcastframes_g; 697 u64 txmulticastframes_g; 698 u64 tx64octets_gb; 699 u64 tx65to127octets_gb; 700 u64 tx128to255octets_gb; 701 u64 tx256to511octets_gb; 702 u64 tx512to1023octets_gb; 703 u64 tx1024tomaxoctets_gb; 704 u64 txunicastframes_gb; 705 u64 txmulticastframes_gb; 706 u64 txbroadcastframes_gb; 707 u64 txunderflowerror; 708 u64 txoctetcount_g; 709 u64 txframecount_g; 710 u64 txpauseframes; 711 u64 txvlanframes_g; 712 713 /* Rx Stats */ 714 u64 rxframecount_gb; 715 u64 rxoctetcount_gb; 716 u64 rxoctetcount_g; 717 u64 rxbroadcastframes_g; 718 u64 rxmulticastframes_g; 719 u64 rxcrcerror; 720 u64 rxrunterror; 721 u64 rxjabbererror; 722 u64 rxundersize_g; 723 u64 rxoversize_g; 724 u64 rx64octets_gb; 725 u64 rx65to127octets_gb; 726 u64 rx128to255octets_gb; 727 u64 rx256to511octets_gb; 728 u64 rx512to1023octets_gb; 729 u64 rx1024tomaxoctets_gb; 730 u64 rxunicastframes_g; 731 u64 rxlengtherror; 732 u64 rxoutofrangetype; 733 u64 rxpauseframes; 734 u64 rxfifooverflow; 735 u64 rxvlanframes_gb; 736 u64 rxwatchdogerror; 737 }; 738 739 struct xgbe_ext_stats { 740 u64 tx_tso_packets; 741 u64 rx_split_header_packets; 742 u64 rx_buffer_unavailable; 743 744 u64 txq_packets[XGBE_MAX_DMA_CHANNELS]; 745 u64 txq_bytes[XGBE_MAX_DMA_CHANNELS]; 746 u64 rxq_packets[XGBE_MAX_DMA_CHANNELS]; 747 u64 rxq_bytes[XGBE_MAX_DMA_CHANNELS]; 748 749 u64 tx_vxlan_packets; 750 u64 rx_vxlan_packets; 751 u64 rx_csum_errors; 752 u64 rx_vxlan_csum_errors; 753 }; 754 755 struct xgbe_hw_if { 756 int (*tx_complete)(struct xgbe_ring_desc *); 757 758 int (*set_mac_address)(struct xgbe_prv_data *, const u8 *addr); 759 int (*config_rx_mode)(struct xgbe_prv_data *); 760 761 int (*enable_rx_csum)(struct xgbe_prv_data *); 762 int (*disable_rx_csum)(struct xgbe_prv_data *); 763 764 int (*enable_rx_vlan_stripping)(struct xgbe_prv_data *); 765 int (*disable_rx_vlan_stripping)(struct xgbe_prv_data *); 766 int (*enable_rx_vlan_filtering)(struct xgbe_prv_data *); 767 int (*disable_rx_vlan_filtering)(struct xgbe_prv_data *); 768 int (*update_vlan_hash_table)(struct xgbe_prv_data *); 769 770 int (*read_mmd_regs)(struct xgbe_prv_data *, int, int); 771 void (*write_mmd_regs)(struct xgbe_prv_data *, int, int, int); 772 int (*set_speed)(struct xgbe_prv_data *, int); 773 774 int (*set_ext_mii_mode)(struct xgbe_prv_data *, unsigned int, 775 enum xgbe_mdio_mode); 776 int (*read_ext_mii_regs)(struct xgbe_prv_data *, int, int); 777 int (*write_ext_mii_regs)(struct xgbe_prv_data *, int, int, u16); 778 779 int (*set_gpio)(struct xgbe_prv_data *, unsigned int); 780 int (*clr_gpio)(struct xgbe_prv_data *, unsigned int); 781 782 void (*enable_tx)(struct xgbe_prv_data *); 783 void (*disable_tx)(struct xgbe_prv_data *); 784 void (*enable_rx)(struct xgbe_prv_data *); 785 void (*disable_rx)(struct xgbe_prv_data *); 786 787 void (*powerup_tx)(struct xgbe_prv_data *); 788 void (*powerdown_tx)(struct xgbe_prv_data *); 789 void (*powerup_rx)(struct xgbe_prv_data *); 790 void (*powerdown_rx)(struct xgbe_prv_data *); 791 792 int (*init)(struct xgbe_prv_data *); 793 int (*exit)(struct xgbe_prv_data *); 794 795 int (*enable_int)(struct xgbe_channel *, enum xgbe_int); 796 int (*disable_int)(struct xgbe_channel *, enum xgbe_int); 797 void (*dev_xmit)(struct xgbe_channel *); 798 int (*dev_read)(struct xgbe_channel *); 799 void (*tx_desc_init)(struct xgbe_channel *); 800 void (*rx_desc_init)(struct xgbe_channel *); 801 void (*tx_desc_reset)(struct xgbe_ring_data *); 802 void (*rx_desc_reset)(struct xgbe_prv_data *, struct xgbe_ring_data *, 803 unsigned int); 804 int (*is_last_desc)(struct xgbe_ring_desc *); 805 int (*is_context_desc)(struct xgbe_ring_desc *); 806 void (*tx_start_xmit)(struct xgbe_channel *, struct xgbe_ring *); 807 808 /* For FLOW ctrl */ 809 int (*config_tx_flow_control)(struct xgbe_prv_data *); 810 int (*config_rx_flow_control)(struct xgbe_prv_data *); 811 812 /* For RX coalescing */ 813 int (*config_rx_coalesce)(struct xgbe_prv_data *); 814 int (*config_tx_coalesce)(struct xgbe_prv_data *); 815 unsigned int (*usec_to_riwt)(struct xgbe_prv_data *, unsigned int); 816 unsigned int (*riwt_to_usec)(struct xgbe_prv_data *, unsigned int); 817 818 /* For RX and TX threshold config */ 819 int (*config_rx_threshold)(struct xgbe_prv_data *, unsigned int); 820 int (*config_tx_threshold)(struct xgbe_prv_data *, unsigned int); 821 822 /* For RX and TX Store and Forward Mode config */ 823 int (*config_rsf_mode)(struct xgbe_prv_data *, unsigned int); 824 int (*config_tsf_mode)(struct xgbe_prv_data *, unsigned int); 825 826 /* For TX DMA Operate on Second Frame config */ 827 int (*config_osp_mode)(struct xgbe_prv_data *); 828 829 /* For MMC statistics */ 830 void (*rx_mmc_int)(struct xgbe_prv_data *); 831 void (*tx_mmc_int)(struct xgbe_prv_data *); 832 void (*read_mmc_stats)(struct xgbe_prv_data *); 833 834 /* For Timestamp config */ 835 int (*config_tstamp)(struct xgbe_prv_data *, unsigned int); 836 void (*update_tstamp_addend)(struct xgbe_prv_data *, unsigned int); 837 void (*set_tstamp_time)(struct xgbe_prv_data *, unsigned int sec, 838 unsigned int nsec); 839 u64 (*get_tstamp_time)(struct xgbe_prv_data *); 840 u64 (*get_tx_tstamp)(struct xgbe_prv_data *); 841 842 /* For Data Center Bridging config */ 843 void (*config_tc)(struct xgbe_prv_data *); 844 void (*config_dcb_tc)(struct xgbe_prv_data *); 845 void (*config_dcb_pfc)(struct xgbe_prv_data *); 846 847 /* For Receive Side Scaling */ 848 int (*enable_rss)(struct xgbe_prv_data *); 849 int (*disable_rss)(struct xgbe_prv_data *); 850 int (*set_rss_hash_key)(struct xgbe_prv_data *, const u8 *); 851 int (*set_rss_lookup_table)(struct xgbe_prv_data *, const u32 *); 852 853 /* For ECC */ 854 void (*disable_ecc_ded)(struct xgbe_prv_data *); 855 void (*disable_ecc_sec)(struct xgbe_prv_data *, enum xgbe_ecc_sec); 856 857 /* For VXLAN */ 858 void (*enable_vxlan)(struct xgbe_prv_data *); 859 void (*disable_vxlan)(struct xgbe_prv_data *); 860 void (*set_vxlan_id)(struct xgbe_prv_data *); 861 }; 862 863 /* This structure represents implementation specific routines for an 864 * implementation of a PHY. All routines are required unless noted below. 865 * Optional routines: 866 * an_pre, an_post 867 * kr_training_pre, kr_training_post 868 * module_info, module_eeprom 869 */ 870 struct xgbe_phy_impl_if { 871 /* Perform Setup/teardown actions */ 872 int (*init)(struct xgbe_prv_data *); 873 void (*exit)(struct xgbe_prv_data *); 874 875 /* Perform start/stop specific actions */ 876 int (*reset)(struct xgbe_prv_data *); 877 int (*start)(struct xgbe_prv_data *); 878 void (*stop)(struct xgbe_prv_data *); 879 880 /* Return the link status */ 881 int (*link_status)(struct xgbe_prv_data *, int *); 882 883 /* Indicate if a particular speed is valid */ 884 bool (*valid_speed)(struct xgbe_prv_data *, int); 885 886 /* Check if the specified mode can/should be used */ 887 bool (*use_mode)(struct xgbe_prv_data *, enum xgbe_mode); 888 /* Switch the PHY into various modes */ 889 void (*set_mode)(struct xgbe_prv_data *, enum xgbe_mode); 890 /* Retrieve mode needed for a specific speed */ 891 enum xgbe_mode (*get_mode)(struct xgbe_prv_data *, int); 892 /* Retrieve new/next mode when trying to auto-negotiate */ 893 enum xgbe_mode (*switch_mode)(struct xgbe_prv_data *); 894 /* Retrieve current mode */ 895 enum xgbe_mode (*cur_mode)(struct xgbe_prv_data *); 896 897 /* Retrieve current auto-negotiation mode */ 898 enum xgbe_an_mode (*an_mode)(struct xgbe_prv_data *); 899 900 /* Configure auto-negotiation settings */ 901 int (*an_config)(struct xgbe_prv_data *); 902 903 /* Set/override auto-negotiation advertisement settings */ 904 void (*an_advertising)(struct xgbe_prv_data *, 905 struct ethtool_link_ksettings *); 906 907 /* Process results of auto-negotiation */ 908 enum xgbe_mode (*an_outcome)(struct xgbe_prv_data *); 909 910 /* Pre/Post auto-negotiation support */ 911 void (*an_pre)(struct xgbe_prv_data *); 912 void (*an_post)(struct xgbe_prv_data *); 913 914 /* Pre/Post KR training enablement support */ 915 void (*kr_training_pre)(struct xgbe_prv_data *); 916 void (*kr_training_post)(struct xgbe_prv_data *); 917 918 /* SFP module related info */ 919 int (*module_info)(struct xgbe_prv_data *pdata, 920 struct ethtool_modinfo *modinfo); 921 int (*module_eeprom)(struct xgbe_prv_data *pdata, 922 struct ethtool_eeprom *eeprom, u8 *data); 923 }; 924 925 struct xgbe_phy_if { 926 /* For PHY setup/teardown */ 927 int (*phy_init)(struct xgbe_prv_data *); 928 void (*phy_exit)(struct xgbe_prv_data *); 929 930 /* For PHY support when setting device up/down */ 931 int (*phy_reset)(struct xgbe_prv_data *); 932 int (*phy_start)(struct xgbe_prv_data *); 933 void (*phy_stop)(struct xgbe_prv_data *); 934 935 /* For PHY support while device is up */ 936 void (*phy_status)(struct xgbe_prv_data *); 937 int (*phy_config_aneg)(struct xgbe_prv_data *); 938 939 /* For PHY settings validation */ 940 bool (*phy_valid_speed)(struct xgbe_prv_data *, int); 941 942 /* For single interrupt support */ 943 irqreturn_t (*an_isr)(struct xgbe_prv_data *); 944 945 /* For ethtool PHY support */ 946 int (*module_info)(struct xgbe_prv_data *pdata, 947 struct ethtool_modinfo *modinfo); 948 int (*module_eeprom)(struct xgbe_prv_data *pdata, 949 struct ethtool_eeprom *eeprom, u8 *data); 950 951 /* PHY implementation specific services */ 952 struct xgbe_phy_impl_if phy_impl; 953 }; 954 955 struct xgbe_i2c_if { 956 /* For initial I2C setup */ 957 int (*i2c_init)(struct xgbe_prv_data *); 958 959 /* For I2C support when setting device up/down */ 960 int (*i2c_start)(struct xgbe_prv_data *); 961 void (*i2c_stop)(struct xgbe_prv_data *); 962 963 /* For performing I2C operations */ 964 int (*i2c_xfer)(struct xgbe_prv_data *, struct xgbe_i2c_op *); 965 966 /* For single interrupt support */ 967 irqreturn_t (*i2c_isr)(struct xgbe_prv_data *); 968 }; 969 970 struct xgbe_desc_if { 971 int (*alloc_ring_resources)(struct xgbe_prv_data *); 972 void (*free_ring_resources)(struct xgbe_prv_data *); 973 int (*map_tx_skb)(struct xgbe_channel *, struct sk_buff *); 974 int (*map_rx_buffer)(struct xgbe_prv_data *, struct xgbe_ring *, 975 struct xgbe_ring_data *); 976 void (*unmap_rdata)(struct xgbe_prv_data *, struct xgbe_ring_data *); 977 void (*wrapper_tx_desc_init)(struct xgbe_prv_data *); 978 void (*wrapper_rx_desc_init)(struct xgbe_prv_data *); 979 }; 980 981 /* This structure contains flags that indicate what hardware features 982 * or configurations are present in the device. 983 */ 984 struct xgbe_hw_features { 985 /* HW Version */ 986 unsigned int version; 987 988 /* HW Feature Register0 */ 989 unsigned int gmii; /* 1000 Mbps support */ 990 unsigned int vlhash; /* VLAN Hash Filter */ 991 unsigned int sma; /* SMA(MDIO) Interface */ 992 unsigned int rwk; /* PMT remote wake-up packet */ 993 unsigned int mgk; /* PMT magic packet */ 994 unsigned int mmc; /* RMON module */ 995 unsigned int aoe; /* ARP Offload */ 996 unsigned int ts; /* IEEE 1588-2008 Advanced Timestamp */ 997 unsigned int eee; /* Energy Efficient Ethernet */ 998 unsigned int tx_coe; /* Tx Checksum Offload */ 999 unsigned int rx_coe; /* Rx Checksum Offload */ 1000 unsigned int addn_mac; /* Additional MAC Addresses */ 1001 unsigned int ts_src; /* Timestamp Source */ 1002 unsigned int sa_vlan_ins; /* Source Address or VLAN Insertion */ 1003 unsigned int vxn; /* VXLAN/NVGRE */ 1004 1005 /* HW Feature Register1 */ 1006 unsigned int rx_fifo_size; /* MTL Receive FIFO Size */ 1007 unsigned int tx_fifo_size; /* MTL Transmit FIFO Size */ 1008 unsigned int adv_ts_hi; /* Advance Timestamping High Word */ 1009 unsigned int dma_width; /* DMA width */ 1010 unsigned int dcb; /* DCB Feature */ 1011 unsigned int sph; /* Split Header Feature */ 1012 unsigned int tso; /* TCP Segmentation Offload */ 1013 unsigned int dma_debug; /* DMA Debug Registers */ 1014 unsigned int rss; /* Receive Side Scaling */ 1015 unsigned int tc_cnt; /* Number of Traffic Classes */ 1016 unsigned int hash_table_size; /* Hash Table Size */ 1017 unsigned int l3l4_filter_num; /* Number of L3-L4 Filters */ 1018 1019 /* HW Feature Register2 */ 1020 unsigned int rx_q_cnt; /* Number of MTL Receive Queues */ 1021 unsigned int tx_q_cnt; /* Number of MTL Transmit Queues */ 1022 unsigned int rx_ch_cnt; /* Number of DMA Receive Channels */ 1023 unsigned int tx_ch_cnt; /* Number of DMA Transmit Channels */ 1024 unsigned int pps_out_num; /* Number of PPS outputs */ 1025 unsigned int aux_snap_num; /* Number of Aux snapshot inputs */ 1026 }; 1027 1028 struct xgbe_version_data { 1029 void (*init_function_ptrs_phy_impl)(struct xgbe_phy_if *); 1030 enum xgbe_xpcs_access xpcs_access; 1031 unsigned int mmc_64bit; 1032 unsigned int tx_max_fifo_size; 1033 unsigned int rx_max_fifo_size; 1034 unsigned int tx_tstamp_workaround; 1035 unsigned int ecc_support; 1036 unsigned int i2c_support; 1037 unsigned int irq_reissue_support; 1038 unsigned int tx_desc_prefetch; 1039 unsigned int rx_desc_prefetch; 1040 unsigned int an_cdr_workaround; 1041 unsigned int enable_rrc; 1042 }; 1043 1044 struct xgbe_prv_data { 1045 struct net_device *netdev; 1046 struct pci_dev *pcidev; 1047 struct platform_device *platdev; 1048 struct acpi_device *adev; 1049 struct device *dev; 1050 struct platform_device *phy_platdev; 1051 struct device *phy_dev; 1052 1053 /* Version related data */ 1054 struct xgbe_version_data *vdata; 1055 1056 /* ACPI or DT flag */ 1057 unsigned int use_acpi; 1058 1059 /* XGMAC/XPCS related mmio registers */ 1060 void __iomem *xgmac_regs; /* XGMAC CSRs */ 1061 void __iomem *xpcs_regs; /* XPCS MMD registers */ 1062 void __iomem *rxtx_regs; /* SerDes Rx/Tx CSRs */ 1063 void __iomem *sir0_regs; /* SerDes integration registers (1/2) */ 1064 void __iomem *sir1_regs; /* SerDes integration registers (2/2) */ 1065 void __iomem *xprop_regs; /* XGBE property registers */ 1066 void __iomem *xi2c_regs; /* XGBE I2C CSRs */ 1067 1068 /* Port property registers */ 1069 unsigned int pp0; 1070 unsigned int pp1; 1071 unsigned int pp2; 1072 unsigned int pp3; 1073 unsigned int pp4; 1074 1075 /* Overall device lock */ 1076 spinlock_t lock; 1077 1078 /* XPCS indirect addressing lock */ 1079 spinlock_t xpcs_lock; 1080 unsigned int xpcs_window_def_reg; 1081 unsigned int xpcs_window_sel_reg; 1082 unsigned int xpcs_window; 1083 unsigned int xpcs_window_size; 1084 unsigned int xpcs_window_mask; 1085 1086 /* RSS addressing mutex */ 1087 struct mutex rss_mutex; 1088 1089 /* Flags representing xgbe_state */ 1090 unsigned long dev_state; 1091 1092 /* ECC support */ 1093 unsigned long tx_sec_period; 1094 unsigned long tx_ded_period; 1095 unsigned long rx_sec_period; 1096 unsigned long rx_ded_period; 1097 unsigned long desc_sec_period; 1098 unsigned long desc_ded_period; 1099 1100 unsigned int tx_sec_count; 1101 unsigned int tx_ded_count; 1102 unsigned int rx_sec_count; 1103 unsigned int rx_ded_count; 1104 unsigned int desc_ded_count; 1105 unsigned int desc_sec_count; 1106 1107 int dev_irq; 1108 int ecc_irq; 1109 int i2c_irq; 1110 int channel_irq[XGBE_MAX_DMA_CHANNELS]; 1111 1112 unsigned int per_channel_irq; 1113 unsigned int irq_count; 1114 unsigned int channel_irq_count; 1115 unsigned int channel_irq_mode; 1116 1117 char ecc_name[IFNAMSIZ + 32]; 1118 1119 struct xgbe_hw_if hw_if; 1120 struct xgbe_phy_if phy_if; 1121 struct xgbe_desc_if desc_if; 1122 struct xgbe_i2c_if i2c_if; 1123 1124 /* AXI DMA settings */ 1125 unsigned int coherent; 1126 unsigned int arcr; 1127 unsigned int awcr; 1128 unsigned int awarcr; 1129 1130 /* Service routine support */ 1131 struct workqueue_struct *dev_workqueue; 1132 struct work_struct service_work; 1133 struct timer_list service_timer; 1134 1135 /* Rings for Tx/Rx on a DMA channel */ 1136 struct xgbe_channel *channel[XGBE_MAX_DMA_CHANNELS]; 1137 unsigned int tx_max_channel_count; 1138 unsigned int rx_max_channel_count; 1139 unsigned int channel_count; 1140 unsigned int tx_ring_count; 1141 unsigned int tx_desc_count; 1142 unsigned int rx_ring_count; 1143 unsigned int rx_desc_count; 1144 1145 unsigned int new_tx_ring_count; 1146 unsigned int new_rx_ring_count; 1147 1148 unsigned int tx_max_q_count; 1149 unsigned int rx_max_q_count; 1150 unsigned int tx_q_count; 1151 unsigned int rx_q_count; 1152 1153 /* Tx/Rx common settings */ 1154 unsigned int blen; 1155 unsigned int pbl; 1156 unsigned int aal; 1157 unsigned int rd_osr_limit; 1158 unsigned int wr_osr_limit; 1159 1160 /* Tx settings */ 1161 unsigned int tx_sf_mode; 1162 unsigned int tx_threshold; 1163 unsigned int tx_osp_mode; 1164 unsigned int tx_max_fifo_size; 1165 1166 /* Rx settings */ 1167 unsigned int rx_sf_mode; 1168 unsigned int rx_threshold; 1169 unsigned int rx_max_fifo_size; 1170 1171 /* Tx coalescing settings */ 1172 unsigned int tx_usecs; 1173 unsigned int tx_frames; 1174 1175 /* Rx coalescing settings */ 1176 unsigned int rx_riwt; 1177 unsigned int rx_usecs; 1178 unsigned int rx_frames; 1179 1180 /* Current Rx buffer size */ 1181 unsigned int rx_buf_size; 1182 1183 /* Flow control settings */ 1184 unsigned int pause_autoneg; 1185 unsigned int tx_pause; 1186 unsigned int rx_pause; 1187 unsigned int rx_rfa[XGBE_MAX_QUEUES]; 1188 unsigned int rx_rfd[XGBE_MAX_QUEUES]; 1189 1190 /* Receive Side Scaling settings */ 1191 u8 rss_key[XGBE_RSS_HASH_KEY_SIZE]; 1192 u32 rss_table[XGBE_RSS_MAX_TABLE_SIZE]; 1193 u32 rss_options; 1194 1195 /* VXLAN settings */ 1196 u16 vxlan_port; 1197 1198 /* Netdev related settings */ 1199 unsigned char mac_addr[ETH_ALEN]; 1200 netdev_features_t netdev_features; 1201 struct napi_struct napi; 1202 struct xgbe_mmc_stats mmc_stats; 1203 struct xgbe_ext_stats ext_stats; 1204 1205 /* Filtering support */ 1206 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 1207 1208 /* Device clocks */ 1209 struct clk *sysclk; 1210 unsigned long sysclk_rate; 1211 struct clk *ptpclk; 1212 unsigned long ptpclk_rate; 1213 1214 /* Timestamp support */ 1215 spinlock_t tstamp_lock; 1216 struct ptp_clock_info ptp_clock_info; 1217 struct ptp_clock *ptp_clock; 1218 struct hwtstamp_config tstamp_config; 1219 struct cyclecounter tstamp_cc; 1220 struct timecounter tstamp_tc; 1221 unsigned int tstamp_addend; 1222 struct work_struct tx_tstamp_work; 1223 struct sk_buff *tx_tstamp_skb; 1224 u64 tx_tstamp; 1225 1226 /* DCB support */ 1227 struct ieee_ets *ets; 1228 struct ieee_pfc *pfc; 1229 unsigned int q2tc_map[XGBE_MAX_QUEUES]; 1230 unsigned int prio2q_map[IEEE_8021QAZ_MAX_TCS]; 1231 unsigned int pfcq[XGBE_MAX_QUEUES]; 1232 unsigned int pfc_rfa; 1233 u8 num_tcs; 1234 1235 /* Hardware features of the device */ 1236 struct xgbe_hw_features hw_feat; 1237 1238 /* Device work structures */ 1239 struct work_struct restart_work; 1240 struct work_struct stopdev_work; 1241 1242 /* Keeps track of power mode */ 1243 unsigned int power_down; 1244 1245 /* Network interface message level setting */ 1246 u32 msg_enable; 1247 1248 /* Current PHY settings */ 1249 phy_interface_t phy_mode; 1250 int phy_link; 1251 int phy_speed; 1252 1253 /* MDIO/PHY related settings */ 1254 unsigned int phy_started; 1255 void *phy_data; 1256 struct xgbe_phy phy; 1257 int mdio_mmd; 1258 unsigned long link_check; 1259 struct completion mdio_complete; 1260 1261 unsigned int kr_redrv; 1262 1263 char an_name[IFNAMSIZ + 32]; 1264 struct workqueue_struct *an_workqueue; 1265 1266 int an_irq; 1267 struct work_struct an_irq_work; 1268 1269 /* Auto-negotiation state machine support */ 1270 unsigned int an_int; 1271 unsigned int an_status; 1272 struct mutex an_mutex; 1273 enum xgbe_an an_result; 1274 enum xgbe_an an_state; 1275 enum xgbe_rx kr_state; 1276 enum xgbe_rx kx_state; 1277 struct work_struct an_work; 1278 unsigned int an_again; 1279 unsigned int an_supported; 1280 unsigned int parallel_detect; 1281 unsigned int fec_ability; 1282 unsigned long an_start; 1283 enum xgbe_an_mode an_mode; 1284 1285 /* I2C support */ 1286 struct xgbe_i2c i2c; 1287 struct mutex i2c_mutex; 1288 struct completion i2c_complete; 1289 char i2c_name[IFNAMSIZ + 32]; 1290 1291 unsigned int lpm_ctrl; /* CTRL1 for resume */ 1292 1293 unsigned int isr_as_tasklet; 1294 struct tasklet_struct tasklet_dev; 1295 struct tasklet_struct tasklet_ecc; 1296 struct tasklet_struct tasklet_i2c; 1297 struct tasklet_struct tasklet_an; 1298 1299 struct dentry *xgbe_debugfs; 1300 1301 unsigned int debugfs_xgmac_reg; 1302 1303 unsigned int debugfs_xpcs_mmd; 1304 unsigned int debugfs_xpcs_reg; 1305 1306 unsigned int debugfs_xprop_reg; 1307 1308 unsigned int debugfs_xi2c_reg; 1309 1310 bool debugfs_an_cdr_workaround; 1311 bool debugfs_an_cdr_track_early; 1312 }; 1313 1314 /* Function prototypes*/ 1315 struct xgbe_prv_data *xgbe_alloc_pdata(struct device *); 1316 void xgbe_free_pdata(struct xgbe_prv_data *); 1317 void xgbe_set_counts(struct xgbe_prv_data *); 1318 int xgbe_config_netdev(struct xgbe_prv_data *); 1319 void xgbe_deconfig_netdev(struct xgbe_prv_data *); 1320 1321 int xgbe_platform_init(void); 1322 void xgbe_platform_exit(void); 1323 #ifdef CONFIG_PCI 1324 int xgbe_pci_init(void); 1325 void xgbe_pci_exit(void); 1326 #else 1327 static inline int xgbe_pci_init(void) { return 0; } 1328 static inline void xgbe_pci_exit(void) { } 1329 #endif 1330 1331 void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *); 1332 void xgbe_init_function_ptrs_phy(struct xgbe_phy_if *); 1333 void xgbe_init_function_ptrs_phy_v1(struct xgbe_phy_if *); 1334 void xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if *); 1335 void xgbe_init_function_ptrs_desc(struct xgbe_desc_if *); 1336 void xgbe_init_function_ptrs_i2c(struct xgbe_i2c_if *); 1337 const struct net_device_ops *xgbe_get_netdev_ops(void); 1338 const struct ethtool_ops *xgbe_get_ethtool_ops(void); 1339 const struct udp_tunnel_nic_info *xgbe_get_udp_tunnel_info(void); 1340 1341 #ifdef CONFIG_AMD_XGBE_DCB 1342 const struct dcbnl_rtnl_ops *xgbe_get_dcbnl_ops(void); 1343 #endif 1344 1345 void xgbe_ptp_register(struct xgbe_prv_data *); 1346 void xgbe_ptp_unregister(struct xgbe_prv_data *); 1347 void xgbe_dump_tx_desc(struct xgbe_prv_data *, struct xgbe_ring *, 1348 unsigned int, unsigned int, unsigned int); 1349 void xgbe_dump_rx_desc(struct xgbe_prv_data *, struct xgbe_ring *, 1350 unsigned int); 1351 void xgbe_print_pkt(struct net_device *, struct sk_buff *, bool); 1352 void xgbe_get_all_hw_features(struct xgbe_prv_data *); 1353 int xgbe_powerup(struct net_device *, unsigned int); 1354 int xgbe_powerdown(struct net_device *, unsigned int); 1355 void xgbe_init_rx_coalesce(struct xgbe_prv_data *); 1356 void xgbe_init_tx_coalesce(struct xgbe_prv_data *); 1357 void xgbe_restart_dev(struct xgbe_prv_data *pdata); 1358 void xgbe_full_restart_dev(struct xgbe_prv_data *pdata); 1359 1360 #ifdef CONFIG_DEBUG_FS 1361 void xgbe_debugfs_init(struct xgbe_prv_data *); 1362 void xgbe_debugfs_exit(struct xgbe_prv_data *); 1363 void xgbe_debugfs_rename(struct xgbe_prv_data *pdata); 1364 #else 1365 static inline void xgbe_debugfs_init(struct xgbe_prv_data *pdata) {} 1366 static inline void xgbe_debugfs_exit(struct xgbe_prv_data *pdata) {} 1367 static inline void xgbe_debugfs_rename(struct xgbe_prv_data *pdata) {} 1368 #endif /* CONFIG_DEBUG_FS */ 1369 1370 /* NOTE: Uncomment for function trace log messages in KERNEL LOG */ 1371 #if 0 1372 #define YDEBUG 1373 #define YDEBUG_MDIO 1374 #endif 1375 1376 /* For debug prints */ 1377 #ifdef YDEBUG 1378 #define DBGPR(x...) pr_alert(x) 1379 #else 1380 #define DBGPR(x...) do { } while (0) 1381 #endif 1382 1383 #ifdef YDEBUG_MDIO 1384 #define DBGPR_MDIO(x...) pr_alert(x) 1385 #else 1386 #define DBGPR_MDIO(x...) do { } while (0) 1387 #endif 1388 1389 #endif 1390