1 /* 2 * AMD 10Gb Ethernet driver 3 * 4 * This file is available to you under your choice of the following two 5 * licenses: 6 * 7 * License 1: GPLv2 8 * 9 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc. 10 * 11 * This file is free software; you may copy, redistribute and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation, either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program. If not, see <http://www.gnu.org/licenses/>. 23 * 24 * This file incorporates work covered by the following copyright and 25 * permission notice: 26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 28 * Inc. unless otherwise expressly agreed to in writing between Synopsys 29 * and you. 30 * 31 * The Software IS NOT an item of Licensed Software or Licensed Product 32 * under any End User Software License Agreement or Agreement for Licensed 33 * Product with Synopsys or any supplement thereto. Permission is hereby 34 * granted, free of charge, to any person obtaining a copy of this software 35 * annotated with this license and the Software, to deal in the Software 36 * without restriction, including without limitation the rights to use, 37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 38 * of the Software, and to permit persons to whom the Software is furnished 39 * to do so, subject to the following conditions: 40 * 41 * The above copyright notice and this permission notice shall be included 42 * in all copies or substantial portions of the Software. 43 * 44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 54 * THE POSSIBILITY OF SUCH DAMAGE. 55 * 56 * 57 * License 2: Modified BSD 58 * 59 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc. 60 * All rights reserved. 61 * 62 * Redistribution and use in source and binary forms, with or without 63 * modification, are permitted provided that the following conditions are met: 64 * * Redistributions of source code must retain the above copyright 65 * notice, this list of conditions and the following disclaimer. 66 * * Redistributions in binary form must reproduce the above copyright 67 * notice, this list of conditions and the following disclaimer in the 68 * documentation and/or other materials provided with the distribution. 69 * * Neither the name of Advanced Micro Devices, Inc. nor the 70 * names of its contributors may be used to endorse or promote products 71 * derived from this software without specific prior written permission. 72 * 73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY 77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 83 * 84 * This file incorporates work covered by the following copyright and 85 * permission notice: 86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 88 * Inc. unless otherwise expressly agreed to in writing between Synopsys 89 * and you. 90 * 91 * The Software IS NOT an item of Licensed Software or Licensed Product 92 * under any End User Software License Agreement or Agreement for Licensed 93 * Product with Synopsys or any supplement thereto. Permission is hereby 94 * granted, free of charge, to any person obtaining a copy of this software 95 * annotated with this license and the Software, to deal in the Software 96 * without restriction, including without limitation the rights to use, 97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 98 * of the Software, and to permit persons to whom the Software is furnished 99 * to do so, subject to the following conditions: 100 * 101 * The above copyright notice and this permission notice shall be included 102 * in all copies or substantial portions of the Software. 103 * 104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 114 * THE POSSIBILITY OF SUCH DAMAGE. 115 */ 116 117 #ifndef __XGBE_H__ 118 #define __XGBE_H__ 119 120 #include <linux/dma-mapping.h> 121 #include <linux/netdevice.h> 122 #include <linux/workqueue.h> 123 #include <linux/phy.h> 124 #include <linux/if_vlan.h> 125 #include <linux/bitops.h> 126 #include <linux/ptp_clock_kernel.h> 127 #include <linux/timecounter.h> 128 #include <linux/net_tstamp.h> 129 #include <net/dcbnl.h> 130 #include <linux/completion.h> 131 #include <linux/cpumask.h> 132 #include <linux/interrupt.h> 133 #include <linux/dcache.h> 134 #include <linux/ethtool.h> 135 #include <linux/list.h> 136 137 #define XGBE_DRV_NAME "amd-xgbe" 138 #define XGBE_DRV_VERSION "1.0.3" 139 #define XGBE_DRV_DESC "AMD 10 Gigabit Ethernet Driver" 140 141 /* Descriptor related defines */ 142 #define XGBE_TX_DESC_CNT 512 143 #define XGBE_TX_DESC_MIN_FREE (XGBE_TX_DESC_CNT >> 3) 144 #define XGBE_TX_DESC_MAX_PROC (XGBE_TX_DESC_CNT >> 1) 145 #define XGBE_RX_DESC_CNT 512 146 147 #define XGBE_TX_MAX_BUF_SIZE (0x3fff & ~(64 - 1)) 148 149 /* Descriptors required for maximum contiguous TSO/GSO packet */ 150 #define XGBE_TX_MAX_SPLIT ((GSO_MAX_SIZE / XGBE_TX_MAX_BUF_SIZE) + 1) 151 152 /* Maximum possible descriptors needed for an SKB: 153 * - Maximum number of SKB frags 154 * - Maximum descriptors for contiguous TSO/GSO packet 155 * - Possible context descriptor 156 * - Possible TSO header descriptor 157 */ 158 #define XGBE_TX_MAX_DESCS (MAX_SKB_FRAGS + XGBE_TX_MAX_SPLIT + 2) 159 160 #define XGBE_RX_MIN_BUF_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN) 161 #define XGBE_RX_BUF_ALIGN 64 162 #define XGBE_SKB_ALLOC_SIZE 256 163 #define XGBE_SPH_HDSMS_SIZE 2 /* Keep in sync with SKB_ALLOC_SIZE */ 164 165 #define XGBE_MAX_DMA_CHANNELS 16 166 #define XGBE_MAX_QUEUES 16 167 #define XGBE_PRIORITY_QUEUES 8 168 #define XGBE_DMA_STOP_TIMEOUT 1 169 170 /* DMA cache settings - Outer sharable, write-back, write-allocate */ 171 #define XGBE_DMA_OS_ARCR 0x002b2b2b 172 #define XGBE_DMA_OS_AWCR 0x2f2f2f2f 173 174 /* DMA cache settings - System, no caches used */ 175 #define XGBE_DMA_SYS_ARCR 0x00303030 176 #define XGBE_DMA_SYS_AWCR 0x30303030 177 178 /* DMA cache settings - PCI device */ 179 #define XGBE_DMA_PCI_ARCR 0x00000003 180 #define XGBE_DMA_PCI_AWCR 0x13131313 181 #define XGBE_DMA_PCI_AWARCR 0x00000313 182 183 /* DMA channel interrupt modes */ 184 #define XGBE_IRQ_MODE_EDGE 0 185 #define XGBE_IRQ_MODE_LEVEL 1 186 187 #define XGMAC_MIN_PACKET 60 188 #define XGMAC_STD_PACKET_MTU 1500 189 #define XGMAC_MAX_STD_PACKET 1518 190 #define XGMAC_JUMBO_PACKET_MTU 9000 191 #define XGMAC_MAX_JUMBO_PACKET 9018 192 #define XGMAC_ETH_PREAMBLE (12 + 8) /* Inter-frame gap + preamble */ 193 194 #define XGMAC_PFC_DATA_LEN 46 195 #define XGMAC_PFC_DELAYS 14000 196 197 #define XGMAC_PRIO_QUEUES(_cnt) \ 198 min_t(unsigned int, IEEE_8021QAZ_MAX_TCS, (_cnt)) 199 200 /* Common property names */ 201 #define XGBE_MAC_ADDR_PROPERTY "mac-address" 202 #define XGBE_PHY_MODE_PROPERTY "phy-mode" 203 #define XGBE_DMA_IRQS_PROPERTY "amd,per-channel-interrupt" 204 #define XGBE_SPEEDSET_PROPERTY "amd,speed-set" 205 206 /* Device-tree clock names */ 207 #define XGBE_DMA_CLOCK "dma_clk" 208 #define XGBE_PTP_CLOCK "ptp_clk" 209 210 /* ACPI property names */ 211 #define XGBE_ACPI_DMA_FREQ "amd,dma-freq" 212 #define XGBE_ACPI_PTP_FREQ "amd,ptp-freq" 213 214 /* PCI BAR mapping */ 215 #define XGBE_XGMAC_BAR 0 216 #define XGBE_XPCS_BAR 1 217 #define XGBE_MAC_PROP_OFFSET 0x1d000 218 #define XGBE_I2C_CTRL_OFFSET 0x1e000 219 220 /* PCI MSI/MSIx support */ 221 #define XGBE_MSI_BASE_COUNT 4 222 #define XGBE_MSI_MIN_COUNT (XGBE_MSI_BASE_COUNT + 1) 223 224 /* PCI clock frequencies */ 225 #define XGBE_V2_DMA_CLOCK_FREQ 500000000 /* 500 MHz */ 226 #define XGBE_V2_PTP_CLOCK_FREQ 125000000 /* 125 MHz */ 227 228 /* Timestamp support - values based on 50MHz PTP clock 229 * 50MHz => 20 nsec 230 */ 231 #define XGBE_TSTAMP_SSINC 20 232 #define XGBE_TSTAMP_SNSINC 0 233 234 /* Driver PMT macros */ 235 #define XGMAC_DRIVER_CONTEXT 1 236 #define XGMAC_IOCTL_CONTEXT 2 237 238 #define XGMAC_FIFO_MIN_ALLOC 2048 239 #define XGMAC_FIFO_UNIT 256 240 #define XGMAC_FIFO_ALIGN(_x) \ 241 (((_x) + XGMAC_FIFO_UNIT - 1) & ~(XGMAC_FIFO_UNIT - 1)) 242 #define XGMAC_FIFO_FC_OFF 2048 243 #define XGMAC_FIFO_FC_MIN 4096 244 245 #define XGBE_TC_MIN_QUANTUM 10 246 247 /* Helper macro for descriptor handling 248 * Always use XGBE_GET_DESC_DATA to access the descriptor data 249 * since the index is free-running and needs to be and-ed 250 * with the descriptor count value of the ring to index to 251 * the proper descriptor data. 252 */ 253 #define XGBE_GET_DESC_DATA(_ring, _idx) \ 254 ((_ring)->rdata + \ 255 ((_idx) & ((_ring)->rdesc_count - 1))) 256 257 /* Default coalescing parameters */ 258 #define XGMAC_INIT_DMA_TX_USECS 1000 259 #define XGMAC_INIT_DMA_TX_FRAMES 25 260 261 #define XGMAC_MAX_DMA_RIWT 0xff 262 #define XGMAC_INIT_DMA_RX_USECS 30 263 #define XGMAC_INIT_DMA_RX_FRAMES 25 264 265 /* Flow control queue count */ 266 #define XGMAC_MAX_FLOW_CONTROL_QUEUES 8 267 268 /* Flow control threshold units */ 269 #define XGMAC_FLOW_CONTROL_UNIT 512 270 #define XGMAC_FLOW_CONTROL_ALIGN(_x) \ 271 (((_x) + XGMAC_FLOW_CONTROL_UNIT - 1) & ~(XGMAC_FLOW_CONTROL_UNIT - 1)) 272 #define XGMAC_FLOW_CONTROL_VALUE(_x) \ 273 (((_x) < 1024) ? 0 : ((_x) / XGMAC_FLOW_CONTROL_UNIT) - 2) 274 #define XGMAC_FLOW_CONTROL_MAX 33280 275 276 /* Maximum MAC address hash table size (256 bits = 8 bytes) */ 277 #define XGBE_MAC_HASH_TABLE_SIZE 8 278 279 /* Receive Side Scaling */ 280 #define XGBE_RSS_HASH_KEY_SIZE 40 281 #define XGBE_RSS_MAX_TABLE_SIZE 256 282 #define XGBE_RSS_LOOKUP_TABLE_TYPE 0 283 #define XGBE_RSS_HASH_KEY_TYPE 1 284 285 /* Auto-negotiation */ 286 #define XGBE_AN_MS_TIMEOUT 500 287 #define XGBE_LINK_TIMEOUT 5 288 289 #define XGBE_SGMII_AN_LINK_STATUS BIT(1) 290 #define XGBE_SGMII_AN_LINK_SPEED (BIT(2) | BIT(3)) 291 #define XGBE_SGMII_AN_LINK_SPEED_100 0x04 292 #define XGBE_SGMII_AN_LINK_SPEED_1000 0x08 293 #define XGBE_SGMII_AN_LINK_DUPLEX BIT(4) 294 295 /* ECC correctable error notification window (seconds) */ 296 #define XGBE_ECC_LIMIT 60 297 298 /* MDIO port types */ 299 #define XGMAC_MAX_C22_PORT 3 300 301 /* Link mode bit operations */ 302 #define XGBE_ZERO_SUP(_ls) \ 303 ethtool_link_ksettings_zero_link_mode((_ls), supported) 304 305 #define XGBE_SET_SUP(_ls, _mode) \ 306 ethtool_link_ksettings_add_link_mode((_ls), supported, _mode) 307 308 #define XGBE_CLR_SUP(_ls, _mode) \ 309 ethtool_link_ksettings_del_link_mode((_ls), supported, _mode) 310 311 #define XGBE_IS_SUP(_ls, _mode) \ 312 ethtool_link_ksettings_test_link_mode((_ls), supported, _mode) 313 314 #define XGBE_ZERO_ADV(_ls) \ 315 ethtool_link_ksettings_zero_link_mode((_ls), advertising) 316 317 #define XGBE_SET_ADV(_ls, _mode) \ 318 ethtool_link_ksettings_add_link_mode((_ls), advertising, _mode) 319 320 #define XGBE_CLR_ADV(_ls, _mode) \ 321 ethtool_link_ksettings_del_link_mode((_ls), advertising, _mode) 322 323 #define XGBE_ADV(_ls, _mode) \ 324 ethtool_link_ksettings_test_link_mode((_ls), advertising, _mode) 325 326 #define XGBE_ZERO_LP_ADV(_ls) \ 327 ethtool_link_ksettings_zero_link_mode((_ls), lp_advertising) 328 329 #define XGBE_SET_LP_ADV(_ls, _mode) \ 330 ethtool_link_ksettings_add_link_mode((_ls), lp_advertising, _mode) 331 332 #define XGBE_CLR_LP_ADV(_ls, _mode) \ 333 ethtool_link_ksettings_del_link_mode((_ls), lp_advertising, _mode) 334 335 #define XGBE_LP_ADV(_ls, _mode) \ 336 ethtool_link_ksettings_test_link_mode((_ls), lp_advertising, _mode) 337 338 #define XGBE_LM_COPY(_dst, _dname, _src, _sname) \ 339 bitmap_copy((_dst)->link_modes._dname, \ 340 (_src)->link_modes._sname, \ 341 __ETHTOOL_LINK_MODE_MASK_NBITS) 342 343 struct xgbe_prv_data; 344 345 struct xgbe_packet_data { 346 struct sk_buff *skb; 347 348 unsigned int attributes; 349 350 unsigned int errors; 351 352 unsigned int rdesc_count; 353 unsigned int length; 354 355 unsigned int header_len; 356 unsigned int tcp_header_len; 357 unsigned int tcp_payload_len; 358 unsigned short mss; 359 360 unsigned short vlan_ctag; 361 362 u64 rx_tstamp; 363 364 u32 rss_hash; 365 enum pkt_hash_types rss_hash_type; 366 367 unsigned int tx_packets; 368 unsigned int tx_bytes; 369 }; 370 371 /* Common Rx and Tx descriptor mapping */ 372 struct xgbe_ring_desc { 373 __le32 desc0; 374 __le32 desc1; 375 __le32 desc2; 376 __le32 desc3; 377 }; 378 379 /* Page allocation related values */ 380 struct xgbe_page_alloc { 381 struct page *pages; 382 unsigned int pages_len; 383 unsigned int pages_offset; 384 385 dma_addr_t pages_dma; 386 }; 387 388 /* Ring entry buffer data */ 389 struct xgbe_buffer_data { 390 struct xgbe_page_alloc pa; 391 struct xgbe_page_alloc pa_unmap; 392 393 dma_addr_t dma_base; 394 unsigned long dma_off; 395 unsigned int dma_len; 396 }; 397 398 /* Tx-related ring data */ 399 struct xgbe_tx_ring_data { 400 unsigned int packets; /* BQL packet count */ 401 unsigned int bytes; /* BQL byte count */ 402 }; 403 404 /* Rx-related ring data */ 405 struct xgbe_rx_ring_data { 406 struct xgbe_buffer_data hdr; /* Header locations */ 407 struct xgbe_buffer_data buf; /* Payload locations */ 408 409 unsigned short hdr_len; /* Length of received header */ 410 unsigned short len; /* Length of received packet */ 411 }; 412 413 /* Structure used to hold information related to the descriptor 414 * and the packet associated with the descriptor (always use 415 * use the XGBE_GET_DESC_DATA macro to access this data from the ring) 416 */ 417 struct xgbe_ring_data { 418 struct xgbe_ring_desc *rdesc; /* Virtual address of descriptor */ 419 dma_addr_t rdesc_dma; /* DMA address of descriptor */ 420 421 struct sk_buff *skb; /* Virtual address of SKB */ 422 dma_addr_t skb_dma; /* DMA address of SKB data */ 423 unsigned int skb_dma_len; /* Length of SKB DMA area */ 424 425 struct xgbe_tx_ring_data tx; /* Tx-related data */ 426 struct xgbe_rx_ring_data rx; /* Rx-related data */ 427 428 unsigned int mapped_as_page; 429 430 /* Incomplete receive save location. If the budget is exhausted 431 * or the last descriptor (last normal descriptor or a following 432 * context descriptor) has not been DMA'd yet the current state 433 * of the receive processing needs to be saved. 434 */ 435 unsigned int state_saved; 436 struct { 437 struct sk_buff *skb; 438 unsigned int len; 439 unsigned int error; 440 } state; 441 }; 442 443 struct xgbe_ring { 444 /* Ring lock - used just for TX rings at the moment */ 445 spinlock_t lock; 446 447 /* Per packet related information */ 448 struct xgbe_packet_data packet_data; 449 450 /* Virtual/DMA addresses and count of allocated descriptor memory */ 451 struct xgbe_ring_desc *rdesc; 452 dma_addr_t rdesc_dma; 453 unsigned int rdesc_count; 454 455 /* Array of descriptor data corresponding the descriptor memory 456 * (always use the XGBE_GET_DESC_DATA macro to access this data) 457 */ 458 struct xgbe_ring_data *rdata; 459 460 /* Page allocation for RX buffers */ 461 struct xgbe_page_alloc rx_hdr_pa; 462 struct xgbe_page_alloc rx_buf_pa; 463 int node; 464 465 /* Ring index values 466 * cur - Tx: index of descriptor to be used for current transfer 467 * Rx: index of descriptor to check for packet availability 468 * dirty - Tx: index of descriptor to check for transfer complete 469 * Rx: index of descriptor to check for buffer reallocation 470 */ 471 unsigned int cur; 472 unsigned int dirty; 473 474 /* Coalesce frame count used for interrupt bit setting */ 475 unsigned int coalesce_count; 476 477 union { 478 struct { 479 unsigned int queue_stopped; 480 unsigned int xmit_more; 481 unsigned short cur_mss; 482 unsigned short cur_vlan_ctag; 483 } tx; 484 }; 485 } ____cacheline_aligned; 486 487 /* Structure used to describe the descriptor rings associated with 488 * a DMA channel. 489 */ 490 struct xgbe_channel { 491 char name[16]; 492 493 /* Address of private data area for device */ 494 struct xgbe_prv_data *pdata; 495 496 /* Queue index and base address of queue's DMA registers */ 497 unsigned int queue_index; 498 void __iomem *dma_regs; 499 500 /* Per channel interrupt irq number */ 501 int dma_irq; 502 char dma_irq_name[IFNAMSIZ + 32]; 503 504 /* Netdev related settings */ 505 struct napi_struct napi; 506 507 /* Per channel interrupt enablement tracker */ 508 unsigned int curr_ier; 509 unsigned int saved_ier; 510 511 unsigned int tx_timer_active; 512 struct timer_list tx_timer; 513 514 struct xgbe_ring *tx_ring; 515 struct xgbe_ring *rx_ring; 516 517 int node; 518 cpumask_t affinity_mask; 519 } ____cacheline_aligned; 520 521 enum xgbe_state { 522 XGBE_DOWN, 523 XGBE_LINK_INIT, 524 XGBE_LINK_ERR, 525 XGBE_STOPPED, 526 }; 527 528 enum xgbe_int { 529 XGMAC_INT_DMA_CH_SR_TI, 530 XGMAC_INT_DMA_CH_SR_TPS, 531 XGMAC_INT_DMA_CH_SR_TBU, 532 XGMAC_INT_DMA_CH_SR_RI, 533 XGMAC_INT_DMA_CH_SR_RBU, 534 XGMAC_INT_DMA_CH_SR_RPS, 535 XGMAC_INT_DMA_CH_SR_TI_RI, 536 XGMAC_INT_DMA_CH_SR_FBE, 537 XGMAC_INT_DMA_ALL, 538 }; 539 540 enum xgbe_int_state { 541 XGMAC_INT_STATE_SAVE, 542 XGMAC_INT_STATE_RESTORE, 543 }; 544 545 enum xgbe_ecc_sec { 546 XGBE_ECC_SEC_TX, 547 XGBE_ECC_SEC_RX, 548 XGBE_ECC_SEC_DESC, 549 }; 550 551 enum xgbe_speed { 552 XGBE_SPEED_1000 = 0, 553 XGBE_SPEED_2500, 554 XGBE_SPEED_10000, 555 XGBE_SPEEDS, 556 }; 557 558 enum xgbe_xpcs_access { 559 XGBE_XPCS_ACCESS_V1 = 0, 560 XGBE_XPCS_ACCESS_V2, 561 }; 562 563 enum xgbe_an_mode { 564 XGBE_AN_MODE_CL73 = 0, 565 XGBE_AN_MODE_CL73_REDRV, 566 XGBE_AN_MODE_CL37, 567 XGBE_AN_MODE_CL37_SGMII, 568 XGBE_AN_MODE_NONE, 569 }; 570 571 enum xgbe_an { 572 XGBE_AN_READY = 0, 573 XGBE_AN_PAGE_RECEIVED, 574 XGBE_AN_INCOMPAT_LINK, 575 XGBE_AN_COMPLETE, 576 XGBE_AN_NO_LINK, 577 XGBE_AN_ERROR, 578 }; 579 580 enum xgbe_rx { 581 XGBE_RX_BPA = 0, 582 XGBE_RX_XNP, 583 XGBE_RX_COMPLETE, 584 XGBE_RX_ERROR, 585 }; 586 587 enum xgbe_mode { 588 XGBE_MODE_KX_1000 = 0, 589 XGBE_MODE_KX_2500, 590 XGBE_MODE_KR, 591 XGBE_MODE_X, 592 XGBE_MODE_SGMII_100, 593 XGBE_MODE_SGMII_1000, 594 XGBE_MODE_SFI, 595 XGBE_MODE_UNKNOWN, 596 }; 597 598 enum xgbe_speedset { 599 XGBE_SPEEDSET_1000_10000 = 0, 600 XGBE_SPEEDSET_2500_10000, 601 }; 602 603 enum xgbe_mdio_mode { 604 XGBE_MDIO_MODE_NONE = 0, 605 XGBE_MDIO_MODE_CL22, 606 XGBE_MDIO_MODE_CL45, 607 }; 608 609 struct xgbe_phy { 610 struct ethtool_link_ksettings lks; 611 612 int address; 613 614 int autoneg; 615 int speed; 616 int duplex; 617 618 int link; 619 620 int pause_autoneg; 621 int tx_pause; 622 int rx_pause; 623 }; 624 625 enum xgbe_i2c_cmd { 626 XGBE_I2C_CMD_READ = 0, 627 XGBE_I2C_CMD_WRITE, 628 }; 629 630 struct xgbe_i2c_op { 631 enum xgbe_i2c_cmd cmd; 632 633 unsigned int target; 634 635 void *buf; 636 unsigned int len; 637 }; 638 639 struct xgbe_i2c_op_state { 640 struct xgbe_i2c_op *op; 641 642 unsigned int tx_len; 643 unsigned char *tx_buf; 644 645 unsigned int rx_len; 646 unsigned char *rx_buf; 647 648 unsigned int tx_abort_source; 649 650 int ret; 651 }; 652 653 struct xgbe_i2c { 654 unsigned int started; 655 unsigned int max_speed_mode; 656 unsigned int rx_fifo_size; 657 unsigned int tx_fifo_size; 658 659 struct xgbe_i2c_op_state op_state; 660 }; 661 662 struct xgbe_mmc_stats { 663 /* Tx Stats */ 664 u64 txoctetcount_gb; 665 u64 txframecount_gb; 666 u64 txbroadcastframes_g; 667 u64 txmulticastframes_g; 668 u64 tx64octets_gb; 669 u64 tx65to127octets_gb; 670 u64 tx128to255octets_gb; 671 u64 tx256to511octets_gb; 672 u64 tx512to1023octets_gb; 673 u64 tx1024tomaxoctets_gb; 674 u64 txunicastframes_gb; 675 u64 txmulticastframes_gb; 676 u64 txbroadcastframes_gb; 677 u64 txunderflowerror; 678 u64 txoctetcount_g; 679 u64 txframecount_g; 680 u64 txpauseframes; 681 u64 txvlanframes_g; 682 683 /* Rx Stats */ 684 u64 rxframecount_gb; 685 u64 rxoctetcount_gb; 686 u64 rxoctetcount_g; 687 u64 rxbroadcastframes_g; 688 u64 rxmulticastframes_g; 689 u64 rxcrcerror; 690 u64 rxrunterror; 691 u64 rxjabbererror; 692 u64 rxundersize_g; 693 u64 rxoversize_g; 694 u64 rx64octets_gb; 695 u64 rx65to127octets_gb; 696 u64 rx128to255octets_gb; 697 u64 rx256to511octets_gb; 698 u64 rx512to1023octets_gb; 699 u64 rx1024tomaxoctets_gb; 700 u64 rxunicastframes_g; 701 u64 rxlengtherror; 702 u64 rxoutofrangetype; 703 u64 rxpauseframes; 704 u64 rxfifooverflow; 705 u64 rxvlanframes_gb; 706 u64 rxwatchdogerror; 707 }; 708 709 struct xgbe_ext_stats { 710 u64 tx_tso_packets; 711 u64 rx_split_header_packets; 712 u64 rx_buffer_unavailable; 713 714 u64 txq_packets[XGBE_MAX_DMA_CHANNELS]; 715 u64 txq_bytes[XGBE_MAX_DMA_CHANNELS]; 716 u64 rxq_packets[XGBE_MAX_DMA_CHANNELS]; 717 u64 rxq_bytes[XGBE_MAX_DMA_CHANNELS]; 718 719 u64 tx_vxlan_packets; 720 u64 rx_vxlan_packets; 721 u64 rx_csum_errors; 722 u64 rx_vxlan_csum_errors; 723 }; 724 725 struct xgbe_hw_if { 726 int (*tx_complete)(struct xgbe_ring_desc *); 727 728 int (*set_mac_address)(struct xgbe_prv_data *, u8 *addr); 729 int (*config_rx_mode)(struct xgbe_prv_data *); 730 731 int (*enable_rx_csum)(struct xgbe_prv_data *); 732 int (*disable_rx_csum)(struct xgbe_prv_data *); 733 734 int (*enable_rx_vlan_stripping)(struct xgbe_prv_data *); 735 int (*disable_rx_vlan_stripping)(struct xgbe_prv_data *); 736 int (*enable_rx_vlan_filtering)(struct xgbe_prv_data *); 737 int (*disable_rx_vlan_filtering)(struct xgbe_prv_data *); 738 int (*update_vlan_hash_table)(struct xgbe_prv_data *); 739 740 int (*read_mmd_regs)(struct xgbe_prv_data *, int, int); 741 void (*write_mmd_regs)(struct xgbe_prv_data *, int, int, int); 742 int (*set_speed)(struct xgbe_prv_data *, int); 743 744 int (*set_ext_mii_mode)(struct xgbe_prv_data *, unsigned int, 745 enum xgbe_mdio_mode); 746 int (*read_ext_mii_regs)(struct xgbe_prv_data *, int, int); 747 int (*write_ext_mii_regs)(struct xgbe_prv_data *, int, int, u16); 748 749 int (*set_gpio)(struct xgbe_prv_data *, unsigned int); 750 int (*clr_gpio)(struct xgbe_prv_data *, unsigned int); 751 752 void (*enable_tx)(struct xgbe_prv_data *); 753 void (*disable_tx)(struct xgbe_prv_data *); 754 void (*enable_rx)(struct xgbe_prv_data *); 755 void (*disable_rx)(struct xgbe_prv_data *); 756 757 void (*powerup_tx)(struct xgbe_prv_data *); 758 void (*powerdown_tx)(struct xgbe_prv_data *); 759 void (*powerup_rx)(struct xgbe_prv_data *); 760 void (*powerdown_rx)(struct xgbe_prv_data *); 761 762 int (*init)(struct xgbe_prv_data *); 763 int (*exit)(struct xgbe_prv_data *); 764 765 int (*enable_int)(struct xgbe_channel *, enum xgbe_int); 766 int (*disable_int)(struct xgbe_channel *, enum xgbe_int); 767 void (*dev_xmit)(struct xgbe_channel *); 768 int (*dev_read)(struct xgbe_channel *); 769 void (*tx_desc_init)(struct xgbe_channel *); 770 void (*rx_desc_init)(struct xgbe_channel *); 771 void (*tx_desc_reset)(struct xgbe_ring_data *); 772 void (*rx_desc_reset)(struct xgbe_prv_data *, struct xgbe_ring_data *, 773 unsigned int); 774 int (*is_last_desc)(struct xgbe_ring_desc *); 775 int (*is_context_desc)(struct xgbe_ring_desc *); 776 void (*tx_start_xmit)(struct xgbe_channel *, struct xgbe_ring *); 777 778 /* For FLOW ctrl */ 779 int (*config_tx_flow_control)(struct xgbe_prv_data *); 780 int (*config_rx_flow_control)(struct xgbe_prv_data *); 781 782 /* For RX coalescing */ 783 int (*config_rx_coalesce)(struct xgbe_prv_data *); 784 int (*config_tx_coalesce)(struct xgbe_prv_data *); 785 unsigned int (*usec_to_riwt)(struct xgbe_prv_data *, unsigned int); 786 unsigned int (*riwt_to_usec)(struct xgbe_prv_data *, unsigned int); 787 788 /* For RX and TX threshold config */ 789 int (*config_rx_threshold)(struct xgbe_prv_data *, unsigned int); 790 int (*config_tx_threshold)(struct xgbe_prv_data *, unsigned int); 791 792 /* For RX and TX Store and Forward Mode config */ 793 int (*config_rsf_mode)(struct xgbe_prv_data *, unsigned int); 794 int (*config_tsf_mode)(struct xgbe_prv_data *, unsigned int); 795 796 /* For TX DMA Operate on Second Frame config */ 797 int (*config_osp_mode)(struct xgbe_prv_data *); 798 799 /* For MMC statistics */ 800 void (*rx_mmc_int)(struct xgbe_prv_data *); 801 void (*tx_mmc_int)(struct xgbe_prv_data *); 802 void (*read_mmc_stats)(struct xgbe_prv_data *); 803 804 /* For Timestamp config */ 805 int (*config_tstamp)(struct xgbe_prv_data *, unsigned int); 806 void (*update_tstamp_addend)(struct xgbe_prv_data *, unsigned int); 807 void (*set_tstamp_time)(struct xgbe_prv_data *, unsigned int sec, 808 unsigned int nsec); 809 u64 (*get_tstamp_time)(struct xgbe_prv_data *); 810 u64 (*get_tx_tstamp)(struct xgbe_prv_data *); 811 812 /* For Data Center Bridging config */ 813 void (*config_tc)(struct xgbe_prv_data *); 814 void (*config_dcb_tc)(struct xgbe_prv_data *); 815 void (*config_dcb_pfc)(struct xgbe_prv_data *); 816 817 /* For Receive Side Scaling */ 818 int (*enable_rss)(struct xgbe_prv_data *); 819 int (*disable_rss)(struct xgbe_prv_data *); 820 int (*set_rss_hash_key)(struct xgbe_prv_data *, const u8 *); 821 int (*set_rss_lookup_table)(struct xgbe_prv_data *, const u32 *); 822 823 /* For ECC */ 824 void (*disable_ecc_ded)(struct xgbe_prv_data *); 825 void (*disable_ecc_sec)(struct xgbe_prv_data *, enum xgbe_ecc_sec); 826 827 /* For VXLAN */ 828 void (*enable_vxlan)(struct xgbe_prv_data *); 829 void (*disable_vxlan)(struct xgbe_prv_data *); 830 void (*set_vxlan_id)(struct xgbe_prv_data *); 831 }; 832 833 /* This structure represents implementation specific routines for an 834 * implementation of a PHY. All routines are required unless noted below. 835 * Optional routines: 836 * kr_training_pre, kr_training_post 837 */ 838 struct xgbe_phy_impl_if { 839 /* Perform Setup/teardown actions */ 840 int (*init)(struct xgbe_prv_data *); 841 void (*exit)(struct xgbe_prv_data *); 842 843 /* Perform start/stop specific actions */ 844 int (*reset)(struct xgbe_prv_data *); 845 int (*start)(struct xgbe_prv_data *); 846 void (*stop)(struct xgbe_prv_data *); 847 848 /* Return the link status */ 849 int (*link_status)(struct xgbe_prv_data *, int *); 850 851 /* Indicate if a particular speed is valid */ 852 bool (*valid_speed)(struct xgbe_prv_data *, int); 853 854 /* Check if the specified mode can/should be used */ 855 bool (*use_mode)(struct xgbe_prv_data *, enum xgbe_mode); 856 /* Switch the PHY into various modes */ 857 void (*set_mode)(struct xgbe_prv_data *, enum xgbe_mode); 858 /* Retrieve mode needed for a specific speed */ 859 enum xgbe_mode (*get_mode)(struct xgbe_prv_data *, int); 860 /* Retrieve new/next mode when trying to auto-negotiate */ 861 enum xgbe_mode (*switch_mode)(struct xgbe_prv_data *); 862 /* Retrieve current mode */ 863 enum xgbe_mode (*cur_mode)(struct xgbe_prv_data *); 864 865 /* Retrieve current auto-negotiation mode */ 866 enum xgbe_an_mode (*an_mode)(struct xgbe_prv_data *); 867 868 /* Configure auto-negotiation settings */ 869 int (*an_config)(struct xgbe_prv_data *); 870 871 /* Set/override auto-negotiation advertisement settings */ 872 void (*an_advertising)(struct xgbe_prv_data *, 873 struct ethtool_link_ksettings *); 874 875 /* Process results of auto-negotiation */ 876 enum xgbe_mode (*an_outcome)(struct xgbe_prv_data *); 877 878 /* Pre/Post KR training enablement support */ 879 void (*kr_training_pre)(struct xgbe_prv_data *); 880 void (*kr_training_post)(struct xgbe_prv_data *); 881 }; 882 883 struct xgbe_phy_if { 884 /* For PHY setup/teardown */ 885 int (*phy_init)(struct xgbe_prv_data *); 886 void (*phy_exit)(struct xgbe_prv_data *); 887 888 /* For PHY support when setting device up/down */ 889 int (*phy_reset)(struct xgbe_prv_data *); 890 int (*phy_start)(struct xgbe_prv_data *); 891 void (*phy_stop)(struct xgbe_prv_data *); 892 893 /* For PHY support while device is up */ 894 void (*phy_status)(struct xgbe_prv_data *); 895 int (*phy_config_aneg)(struct xgbe_prv_data *); 896 897 /* For PHY settings validation */ 898 bool (*phy_valid_speed)(struct xgbe_prv_data *, int); 899 900 /* For single interrupt support */ 901 irqreturn_t (*an_isr)(struct xgbe_prv_data *); 902 903 /* PHY implementation specific services */ 904 struct xgbe_phy_impl_if phy_impl; 905 }; 906 907 struct xgbe_i2c_if { 908 /* For initial I2C setup */ 909 int (*i2c_init)(struct xgbe_prv_data *); 910 911 /* For I2C support when setting device up/down */ 912 int (*i2c_start)(struct xgbe_prv_data *); 913 void (*i2c_stop)(struct xgbe_prv_data *); 914 915 /* For performing I2C operations */ 916 int (*i2c_xfer)(struct xgbe_prv_data *, struct xgbe_i2c_op *); 917 918 /* For single interrupt support */ 919 irqreturn_t (*i2c_isr)(struct xgbe_prv_data *); 920 }; 921 922 struct xgbe_desc_if { 923 int (*alloc_ring_resources)(struct xgbe_prv_data *); 924 void (*free_ring_resources)(struct xgbe_prv_data *); 925 int (*map_tx_skb)(struct xgbe_channel *, struct sk_buff *); 926 int (*map_rx_buffer)(struct xgbe_prv_data *, struct xgbe_ring *, 927 struct xgbe_ring_data *); 928 void (*unmap_rdata)(struct xgbe_prv_data *, struct xgbe_ring_data *); 929 void (*wrapper_tx_desc_init)(struct xgbe_prv_data *); 930 void (*wrapper_rx_desc_init)(struct xgbe_prv_data *); 931 }; 932 933 /* This structure contains flags that indicate what hardware features 934 * or configurations are present in the device. 935 */ 936 struct xgbe_hw_features { 937 /* HW Version */ 938 unsigned int version; 939 940 /* HW Feature Register0 */ 941 unsigned int gmii; /* 1000 Mbps support */ 942 unsigned int vlhash; /* VLAN Hash Filter */ 943 unsigned int sma; /* SMA(MDIO) Interface */ 944 unsigned int rwk; /* PMT remote wake-up packet */ 945 unsigned int mgk; /* PMT magic packet */ 946 unsigned int mmc; /* RMON module */ 947 unsigned int aoe; /* ARP Offload */ 948 unsigned int ts; /* IEEE 1588-2008 Advanced Timestamp */ 949 unsigned int eee; /* Energy Efficient Ethernet */ 950 unsigned int tx_coe; /* Tx Checksum Offload */ 951 unsigned int rx_coe; /* Rx Checksum Offload */ 952 unsigned int addn_mac; /* Additional MAC Addresses */ 953 unsigned int ts_src; /* Timestamp Source */ 954 unsigned int sa_vlan_ins; /* Source Address or VLAN Insertion */ 955 unsigned int vxn; /* VXLAN/NVGRE */ 956 957 /* HW Feature Register1 */ 958 unsigned int rx_fifo_size; /* MTL Receive FIFO Size */ 959 unsigned int tx_fifo_size; /* MTL Transmit FIFO Size */ 960 unsigned int adv_ts_hi; /* Advance Timestamping High Word */ 961 unsigned int dma_width; /* DMA width */ 962 unsigned int dcb; /* DCB Feature */ 963 unsigned int sph; /* Split Header Feature */ 964 unsigned int tso; /* TCP Segmentation Offload */ 965 unsigned int dma_debug; /* DMA Debug Registers */ 966 unsigned int rss; /* Receive Side Scaling */ 967 unsigned int tc_cnt; /* Number of Traffic Classes */ 968 unsigned int hash_table_size; /* Hash Table Size */ 969 unsigned int l3l4_filter_num; /* Number of L3-L4 Filters */ 970 971 /* HW Feature Register2 */ 972 unsigned int rx_q_cnt; /* Number of MTL Receive Queues */ 973 unsigned int tx_q_cnt; /* Number of MTL Transmit Queues */ 974 unsigned int rx_ch_cnt; /* Number of DMA Receive Channels */ 975 unsigned int tx_ch_cnt; /* Number of DMA Transmit Channels */ 976 unsigned int pps_out_num; /* Number of PPS outputs */ 977 unsigned int aux_snap_num; /* Number of Aux snapshot inputs */ 978 }; 979 980 struct xgbe_version_data { 981 void (*init_function_ptrs_phy_impl)(struct xgbe_phy_if *); 982 enum xgbe_xpcs_access xpcs_access; 983 unsigned int mmc_64bit; 984 unsigned int tx_max_fifo_size; 985 unsigned int rx_max_fifo_size; 986 unsigned int tx_tstamp_workaround; 987 unsigned int ecc_support; 988 unsigned int i2c_support; 989 unsigned int irq_reissue_support; 990 unsigned int tx_desc_prefetch; 991 unsigned int rx_desc_prefetch; 992 }; 993 994 struct xgbe_vxlan_data { 995 struct list_head list; 996 sa_family_t sa_family; 997 __be16 port; 998 }; 999 1000 struct xgbe_prv_data { 1001 struct net_device *netdev; 1002 struct pci_dev *pcidev; 1003 struct platform_device *platdev; 1004 struct acpi_device *adev; 1005 struct device *dev; 1006 struct platform_device *phy_platdev; 1007 struct device *phy_dev; 1008 1009 /* Version related data */ 1010 struct xgbe_version_data *vdata; 1011 1012 /* ACPI or DT flag */ 1013 unsigned int use_acpi; 1014 1015 /* XGMAC/XPCS related mmio registers */ 1016 void __iomem *xgmac_regs; /* XGMAC CSRs */ 1017 void __iomem *xpcs_regs; /* XPCS MMD registers */ 1018 void __iomem *rxtx_regs; /* SerDes Rx/Tx CSRs */ 1019 void __iomem *sir0_regs; /* SerDes integration registers (1/2) */ 1020 void __iomem *sir1_regs; /* SerDes integration registers (2/2) */ 1021 void __iomem *xprop_regs; /* XGBE property registers */ 1022 void __iomem *xi2c_regs; /* XGBE I2C CSRs */ 1023 1024 /* Overall device lock */ 1025 spinlock_t lock; 1026 1027 /* XPCS indirect addressing lock */ 1028 spinlock_t xpcs_lock; 1029 unsigned int xpcs_window_def_reg; 1030 unsigned int xpcs_window_sel_reg; 1031 unsigned int xpcs_window; 1032 unsigned int xpcs_window_size; 1033 unsigned int xpcs_window_mask; 1034 1035 /* RSS addressing mutex */ 1036 struct mutex rss_mutex; 1037 1038 /* Flags representing xgbe_state */ 1039 unsigned long dev_state; 1040 1041 /* ECC support */ 1042 unsigned long tx_sec_period; 1043 unsigned long tx_ded_period; 1044 unsigned long rx_sec_period; 1045 unsigned long rx_ded_period; 1046 unsigned long desc_sec_period; 1047 unsigned long desc_ded_period; 1048 1049 unsigned int tx_sec_count; 1050 unsigned int tx_ded_count; 1051 unsigned int rx_sec_count; 1052 unsigned int rx_ded_count; 1053 unsigned int desc_ded_count; 1054 unsigned int desc_sec_count; 1055 1056 int dev_irq; 1057 int ecc_irq; 1058 int i2c_irq; 1059 int channel_irq[XGBE_MAX_DMA_CHANNELS]; 1060 1061 unsigned int per_channel_irq; 1062 unsigned int irq_count; 1063 unsigned int channel_irq_count; 1064 unsigned int channel_irq_mode; 1065 1066 char ecc_name[IFNAMSIZ + 32]; 1067 1068 struct xgbe_hw_if hw_if; 1069 struct xgbe_phy_if phy_if; 1070 struct xgbe_desc_if desc_if; 1071 struct xgbe_i2c_if i2c_if; 1072 1073 /* AXI DMA settings */ 1074 unsigned int coherent; 1075 unsigned int arcr; 1076 unsigned int awcr; 1077 unsigned int awarcr; 1078 1079 /* Service routine support */ 1080 struct workqueue_struct *dev_workqueue; 1081 struct work_struct service_work; 1082 struct timer_list service_timer; 1083 1084 /* Rings for Tx/Rx on a DMA channel */ 1085 struct xgbe_channel *channel[XGBE_MAX_DMA_CHANNELS]; 1086 unsigned int tx_max_channel_count; 1087 unsigned int rx_max_channel_count; 1088 unsigned int channel_count; 1089 unsigned int tx_ring_count; 1090 unsigned int tx_desc_count; 1091 unsigned int rx_ring_count; 1092 unsigned int rx_desc_count; 1093 1094 unsigned int tx_max_q_count; 1095 unsigned int rx_max_q_count; 1096 unsigned int tx_q_count; 1097 unsigned int rx_q_count; 1098 1099 /* Tx/Rx common settings */ 1100 unsigned int blen; 1101 unsigned int pbl; 1102 unsigned int aal; 1103 unsigned int rd_osr_limit; 1104 unsigned int wr_osr_limit; 1105 1106 /* Tx settings */ 1107 unsigned int tx_sf_mode; 1108 unsigned int tx_threshold; 1109 unsigned int tx_osp_mode; 1110 unsigned int tx_max_fifo_size; 1111 1112 /* Rx settings */ 1113 unsigned int rx_sf_mode; 1114 unsigned int rx_threshold; 1115 unsigned int rx_max_fifo_size; 1116 1117 /* Tx coalescing settings */ 1118 unsigned int tx_usecs; 1119 unsigned int tx_frames; 1120 1121 /* Rx coalescing settings */ 1122 unsigned int rx_riwt; 1123 unsigned int rx_usecs; 1124 unsigned int rx_frames; 1125 1126 /* Current Rx buffer size */ 1127 unsigned int rx_buf_size; 1128 1129 /* Flow control settings */ 1130 unsigned int pause_autoneg; 1131 unsigned int tx_pause; 1132 unsigned int rx_pause; 1133 unsigned int rx_rfa[XGBE_MAX_QUEUES]; 1134 unsigned int rx_rfd[XGBE_MAX_QUEUES]; 1135 1136 /* Receive Side Scaling settings */ 1137 u8 rss_key[XGBE_RSS_HASH_KEY_SIZE]; 1138 u32 rss_table[XGBE_RSS_MAX_TABLE_SIZE]; 1139 u32 rss_options; 1140 1141 /* VXLAN settings */ 1142 unsigned int vxlan_port_set; 1143 unsigned int vxlan_offloads_set; 1144 unsigned int vxlan_force_disable; 1145 unsigned int vxlan_port_count; 1146 struct list_head vxlan_ports; 1147 u16 vxlan_port; 1148 netdev_features_t vxlan_features; 1149 1150 /* Netdev related settings */ 1151 unsigned char mac_addr[ETH_ALEN]; 1152 netdev_features_t netdev_features; 1153 struct napi_struct napi; 1154 struct xgbe_mmc_stats mmc_stats; 1155 struct xgbe_ext_stats ext_stats; 1156 1157 /* Filtering support */ 1158 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 1159 1160 /* Device clocks */ 1161 struct clk *sysclk; 1162 unsigned long sysclk_rate; 1163 struct clk *ptpclk; 1164 unsigned long ptpclk_rate; 1165 1166 /* Timestamp support */ 1167 spinlock_t tstamp_lock; 1168 struct ptp_clock_info ptp_clock_info; 1169 struct ptp_clock *ptp_clock; 1170 struct hwtstamp_config tstamp_config; 1171 struct cyclecounter tstamp_cc; 1172 struct timecounter tstamp_tc; 1173 unsigned int tstamp_addend; 1174 struct work_struct tx_tstamp_work; 1175 struct sk_buff *tx_tstamp_skb; 1176 u64 tx_tstamp; 1177 1178 /* DCB support */ 1179 struct ieee_ets *ets; 1180 struct ieee_pfc *pfc; 1181 unsigned int q2tc_map[XGBE_MAX_QUEUES]; 1182 unsigned int prio2q_map[IEEE_8021QAZ_MAX_TCS]; 1183 unsigned int pfcq[XGBE_MAX_QUEUES]; 1184 unsigned int pfc_rfa; 1185 u8 num_tcs; 1186 1187 /* Hardware features of the device */ 1188 struct xgbe_hw_features hw_feat; 1189 1190 /* Device work structures */ 1191 struct work_struct restart_work; 1192 struct work_struct stopdev_work; 1193 1194 /* Keeps track of power mode */ 1195 unsigned int power_down; 1196 1197 /* Network interface message level setting */ 1198 u32 msg_enable; 1199 1200 /* Current PHY settings */ 1201 phy_interface_t phy_mode; 1202 int phy_link; 1203 int phy_speed; 1204 1205 /* MDIO/PHY related settings */ 1206 unsigned int phy_started; 1207 void *phy_data; 1208 struct xgbe_phy phy; 1209 int mdio_mmd; 1210 unsigned long link_check; 1211 struct completion mdio_complete; 1212 1213 unsigned int kr_redrv; 1214 1215 char an_name[IFNAMSIZ + 32]; 1216 struct workqueue_struct *an_workqueue; 1217 1218 int an_irq; 1219 struct work_struct an_irq_work; 1220 1221 /* Auto-negotiation state machine support */ 1222 unsigned int an_int; 1223 unsigned int an_status; 1224 struct mutex an_mutex; 1225 enum xgbe_an an_result; 1226 enum xgbe_an an_state; 1227 enum xgbe_rx kr_state; 1228 enum xgbe_rx kx_state; 1229 struct work_struct an_work; 1230 unsigned int an_supported; 1231 unsigned int parallel_detect; 1232 unsigned int fec_ability; 1233 unsigned long an_start; 1234 enum xgbe_an_mode an_mode; 1235 1236 /* I2C support */ 1237 struct xgbe_i2c i2c; 1238 struct mutex i2c_mutex; 1239 struct completion i2c_complete; 1240 char i2c_name[IFNAMSIZ + 32]; 1241 1242 unsigned int lpm_ctrl; /* CTRL1 for resume */ 1243 1244 unsigned int isr_as_tasklet; 1245 struct tasklet_struct tasklet_dev; 1246 struct tasklet_struct tasklet_ecc; 1247 struct tasklet_struct tasklet_i2c; 1248 struct tasklet_struct tasklet_an; 1249 1250 struct dentry *xgbe_debugfs; 1251 1252 unsigned int debugfs_xgmac_reg; 1253 1254 unsigned int debugfs_xpcs_mmd; 1255 unsigned int debugfs_xpcs_reg; 1256 1257 unsigned int debugfs_xprop_reg; 1258 1259 unsigned int debugfs_xi2c_reg; 1260 }; 1261 1262 /* Function prototypes*/ 1263 struct xgbe_prv_data *xgbe_alloc_pdata(struct device *); 1264 void xgbe_free_pdata(struct xgbe_prv_data *); 1265 void xgbe_set_counts(struct xgbe_prv_data *); 1266 int xgbe_config_netdev(struct xgbe_prv_data *); 1267 void xgbe_deconfig_netdev(struct xgbe_prv_data *); 1268 1269 int xgbe_platform_init(void); 1270 void xgbe_platform_exit(void); 1271 #ifdef CONFIG_PCI 1272 int xgbe_pci_init(void); 1273 void xgbe_pci_exit(void); 1274 #else 1275 static inline int xgbe_pci_init(void) { return 0; } 1276 static inline void xgbe_pci_exit(void) { } 1277 #endif 1278 1279 void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *); 1280 void xgbe_init_function_ptrs_phy(struct xgbe_phy_if *); 1281 void xgbe_init_function_ptrs_phy_v1(struct xgbe_phy_if *); 1282 void xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if *); 1283 void xgbe_init_function_ptrs_desc(struct xgbe_desc_if *); 1284 void xgbe_init_function_ptrs_i2c(struct xgbe_i2c_if *); 1285 const struct net_device_ops *xgbe_get_netdev_ops(void); 1286 const struct ethtool_ops *xgbe_get_ethtool_ops(void); 1287 1288 #ifdef CONFIG_AMD_XGBE_DCB 1289 const struct dcbnl_rtnl_ops *xgbe_get_dcbnl_ops(void); 1290 #endif 1291 1292 void xgbe_ptp_register(struct xgbe_prv_data *); 1293 void xgbe_ptp_unregister(struct xgbe_prv_data *); 1294 void xgbe_dump_tx_desc(struct xgbe_prv_data *, struct xgbe_ring *, 1295 unsigned int, unsigned int, unsigned int); 1296 void xgbe_dump_rx_desc(struct xgbe_prv_data *, struct xgbe_ring *, 1297 unsigned int); 1298 void xgbe_print_pkt(struct net_device *, struct sk_buff *, bool); 1299 void xgbe_get_all_hw_features(struct xgbe_prv_data *); 1300 int xgbe_powerup(struct net_device *, unsigned int); 1301 int xgbe_powerdown(struct net_device *, unsigned int); 1302 void xgbe_init_rx_coalesce(struct xgbe_prv_data *); 1303 void xgbe_init_tx_coalesce(struct xgbe_prv_data *); 1304 1305 #ifdef CONFIG_DEBUG_FS 1306 void xgbe_debugfs_init(struct xgbe_prv_data *); 1307 void xgbe_debugfs_exit(struct xgbe_prv_data *); 1308 void xgbe_debugfs_rename(struct xgbe_prv_data *pdata); 1309 #else 1310 static inline void xgbe_debugfs_init(struct xgbe_prv_data *pdata) {} 1311 static inline void xgbe_debugfs_exit(struct xgbe_prv_data *pdata) {} 1312 static inline void xgbe_debugfs_rename(struct xgbe_prv_data *pdata) {} 1313 #endif /* CONFIG_DEBUG_FS */ 1314 1315 /* NOTE: Uncomment for function trace log messages in KERNEL LOG */ 1316 #if 0 1317 #define YDEBUG 1318 #define YDEBUG_MDIO 1319 #endif 1320 1321 /* For debug prints */ 1322 #ifdef YDEBUG 1323 #define DBGPR(x...) pr_alert(x) 1324 #else 1325 #define DBGPR(x...) do { } while (0) 1326 #endif 1327 1328 #ifdef YDEBUG_MDIO 1329 #define DBGPR_MDIO(x...) pr_alert(x) 1330 #else 1331 #define DBGPR_MDIO(x...) do { } while (0) 1332 #endif 1333 1334 #endif 1335