1 /* 2 * AMD 10Gb Ethernet driver 3 * 4 * This file is available to you under your choice of the following two 5 * licenses: 6 * 7 * License 1: GPLv2 8 * 9 * Copyright (c) 2014 Advanced Micro Devices, Inc. 10 * 11 * This file is free software; you may copy, redistribute and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation, either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program. If not, see <http://www.gnu.org/licenses/>. 23 * 24 * This file incorporates work covered by the following copyright and 25 * permission notice: 26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 28 * Inc. unless otherwise expressly agreed to in writing between Synopsys 29 * and you. 30 * 31 * The Software IS NOT an item of Licensed Software or Licensed Product 32 * under any End User Software License Agreement or Agreement for Licensed 33 * Product with Synopsys or any supplement thereto. Permission is hereby 34 * granted, free of charge, to any person obtaining a copy of this software 35 * annotated with this license and the Software, to deal in the Software 36 * without restriction, including without limitation the rights to use, 37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 38 * of the Software, and to permit persons to whom the Software is furnished 39 * to do so, subject to the following conditions: 40 * 41 * The above copyright notice and this permission notice shall be included 42 * in all copies or substantial portions of the Software. 43 * 44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 54 * THE POSSIBILITY OF SUCH DAMAGE. 55 * 56 * 57 * License 2: Modified BSD 58 * 59 * Copyright (c) 2014 Advanced Micro Devices, Inc. 60 * All rights reserved. 61 * 62 * Redistribution and use in source and binary forms, with or without 63 * modification, are permitted provided that the following conditions are met: 64 * * Redistributions of source code must retain the above copyright 65 * notice, this list of conditions and the following disclaimer. 66 * * Redistributions in binary form must reproduce the above copyright 67 * notice, this list of conditions and the following disclaimer in the 68 * documentation and/or other materials provided with the distribution. 69 * * Neither the name of Advanced Micro Devices, Inc. nor the 70 * names of its contributors may be used to endorse or promote products 71 * derived from this software without specific prior written permission. 72 * 73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY 77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 83 * 84 * This file incorporates work covered by the following copyright and 85 * permission notice: 86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 88 * Inc. unless otherwise expressly agreed to in writing between Synopsys 89 * and you. 90 * 91 * The Software IS NOT an item of Licensed Software or Licensed Product 92 * under any End User Software License Agreement or Agreement for Licensed 93 * Product with Synopsys or any supplement thereto. Permission is hereby 94 * granted, free of charge, to any person obtaining a copy of this software 95 * annotated with this license and the Software, to deal in the Software 96 * without restriction, including without limitation the rights to use, 97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 98 * of the Software, and to permit persons to whom the Software is furnished 99 * to do so, subject to the following conditions: 100 * 101 * The above copyright notice and this permission notice shall be included 102 * in all copies or substantial portions of the Software. 103 * 104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 114 * THE POSSIBILITY OF SUCH DAMAGE. 115 */ 116 117 #ifndef __XGBE_H__ 118 #define __XGBE_H__ 119 120 #include <linux/dma-mapping.h> 121 #include <linux/netdevice.h> 122 #include <linux/workqueue.h> 123 #include <linux/phy.h> 124 #include <linux/if_vlan.h> 125 #include <linux/bitops.h> 126 #include <linux/ptp_clock_kernel.h> 127 #include <linux/timecounter.h> 128 #include <linux/net_tstamp.h> 129 #include <net/dcbnl.h> 130 131 #define XGBE_DRV_NAME "amd-xgbe" 132 #define XGBE_DRV_VERSION "1.0.0-a" 133 #define XGBE_DRV_DESC "AMD 10 Gigabit Ethernet Driver" 134 135 /* Descriptor related defines */ 136 #define XGBE_TX_DESC_CNT 512 137 #define XGBE_TX_DESC_MIN_FREE (XGBE_TX_DESC_CNT >> 3) 138 #define XGBE_TX_DESC_MAX_PROC (XGBE_TX_DESC_CNT >> 1) 139 #define XGBE_RX_DESC_CNT 512 140 141 #define XGBE_TX_MAX_BUF_SIZE (0x3fff & ~(64 - 1)) 142 143 /* Descriptors required for maximum contigous TSO/GSO packet */ 144 #define XGBE_TX_MAX_SPLIT ((GSO_MAX_SIZE / XGBE_TX_MAX_BUF_SIZE) + 1) 145 146 /* Maximum possible descriptors needed for an SKB: 147 * - Maximum number of SKB frags 148 * - Maximum descriptors for contiguous TSO/GSO packet 149 * - Possible context descriptor 150 * - Possible TSO header descriptor 151 */ 152 #define XGBE_TX_MAX_DESCS (MAX_SKB_FRAGS + XGBE_TX_MAX_SPLIT + 2) 153 154 #define XGBE_RX_MIN_BUF_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN) 155 #define XGBE_RX_BUF_ALIGN 64 156 #define XGBE_SKB_ALLOC_SIZE 256 157 #define XGBE_SPH_HDSMS_SIZE 2 /* Keep in sync with SKB_ALLOC_SIZE */ 158 159 #define XGBE_MAX_DMA_CHANNELS 16 160 #define XGBE_MAX_QUEUES 16 161 #define XGBE_DMA_STOP_TIMEOUT 5 162 163 /* DMA cache settings - Outer sharable, write-back, write-allocate */ 164 #define XGBE_DMA_OS_AXDOMAIN 0x2 165 #define XGBE_DMA_OS_ARCACHE 0xb 166 #define XGBE_DMA_OS_AWCACHE 0xf 167 168 /* DMA cache settings - System, no caches used */ 169 #define XGBE_DMA_SYS_AXDOMAIN 0x3 170 #define XGBE_DMA_SYS_ARCACHE 0x0 171 #define XGBE_DMA_SYS_AWCACHE 0x0 172 173 #define XGBE_DMA_INTERRUPT_MASK 0x31c7 174 175 #define XGMAC_MIN_PACKET 60 176 #define XGMAC_STD_PACKET_MTU 1500 177 #define XGMAC_MAX_STD_PACKET 1518 178 #define XGMAC_JUMBO_PACKET_MTU 9000 179 #define XGMAC_MAX_JUMBO_PACKET 9018 180 181 /* MDIO bus phy name */ 182 #define XGBE_PHY_NAME "amd_xgbe_phy" 183 #define XGBE_PRTAD 0 184 185 /* Common property names */ 186 #define XGBE_MAC_ADDR_PROPERTY "mac-address" 187 #define XGBE_PHY_MODE_PROPERTY "phy-mode" 188 #define XGBE_DMA_IRQS_PROPERTY "amd,per-channel-interrupt" 189 190 /* Device-tree clock names */ 191 #define XGBE_DMA_CLOCK "dma_clk" 192 #define XGBE_PTP_CLOCK "ptp_clk" 193 194 /* ACPI property names */ 195 #define XGBE_ACPI_DMA_FREQ "amd,dma-freq" 196 #define XGBE_ACPI_PTP_FREQ "amd,ptp-freq" 197 198 /* Timestamp support - values based on 50MHz PTP clock 199 * 50MHz => 20 nsec 200 */ 201 #define XGBE_TSTAMP_SSINC 20 202 #define XGBE_TSTAMP_SNSINC 0 203 204 /* Driver PMT macros */ 205 #define XGMAC_DRIVER_CONTEXT 1 206 #define XGMAC_IOCTL_CONTEXT 2 207 208 #define XGBE_FIFO_MAX 81920 209 #define XGBE_FIFO_SIZE_B(x) (x) 210 #define XGBE_FIFO_SIZE_KB(x) (x * 1024) 211 212 #define XGBE_TC_MIN_QUANTUM 10 213 214 /* Helper macro for descriptor handling 215 * Always use XGBE_GET_DESC_DATA to access the descriptor data 216 * since the index is free-running and needs to be and-ed 217 * with the descriptor count value of the ring to index to 218 * the proper descriptor data. 219 */ 220 #define XGBE_GET_DESC_DATA(_ring, _idx) \ 221 ((_ring)->rdata + \ 222 ((_idx) & ((_ring)->rdesc_count - 1))) 223 224 /* Default coalescing parameters */ 225 #define XGMAC_INIT_DMA_TX_USECS 50 226 #define XGMAC_INIT_DMA_TX_FRAMES 25 227 228 #define XGMAC_MAX_DMA_RIWT 0xff 229 #define XGMAC_INIT_DMA_RX_USECS 30 230 #define XGMAC_INIT_DMA_RX_FRAMES 25 231 232 /* Flow control queue count */ 233 #define XGMAC_MAX_FLOW_CONTROL_QUEUES 8 234 235 /* Maximum MAC address hash table size (256 bits = 8 bytes) */ 236 #define XGBE_MAC_HASH_TABLE_SIZE 8 237 238 /* Receive Side Scaling */ 239 #define XGBE_RSS_HASH_KEY_SIZE 40 240 #define XGBE_RSS_MAX_TABLE_SIZE 256 241 #define XGBE_RSS_LOOKUP_TABLE_TYPE 0 242 #define XGBE_RSS_HASH_KEY_TYPE 1 243 244 struct xgbe_prv_data; 245 246 struct xgbe_packet_data { 247 struct sk_buff *skb; 248 249 unsigned int attributes; 250 251 unsigned int errors; 252 253 unsigned int rdesc_count; 254 unsigned int length; 255 256 unsigned int header_len; 257 unsigned int tcp_header_len; 258 unsigned int tcp_payload_len; 259 unsigned short mss; 260 261 unsigned short vlan_ctag; 262 263 u64 rx_tstamp; 264 265 u32 rss_hash; 266 enum pkt_hash_types rss_hash_type; 267 268 unsigned int tx_packets; 269 unsigned int tx_bytes; 270 }; 271 272 /* Common Rx and Tx descriptor mapping */ 273 struct xgbe_ring_desc { 274 __le32 desc0; 275 __le32 desc1; 276 __le32 desc2; 277 __le32 desc3; 278 }; 279 280 /* Page allocation related values */ 281 struct xgbe_page_alloc { 282 struct page *pages; 283 unsigned int pages_len; 284 unsigned int pages_offset; 285 286 dma_addr_t pages_dma; 287 }; 288 289 /* Ring entry buffer data */ 290 struct xgbe_buffer_data { 291 struct xgbe_page_alloc pa; 292 struct xgbe_page_alloc pa_unmap; 293 294 dma_addr_t dma; 295 unsigned int dma_len; 296 }; 297 298 /* Tx-related ring data */ 299 struct xgbe_tx_ring_data { 300 unsigned int packets; /* BQL packet count */ 301 unsigned int bytes; /* BQL byte count */ 302 }; 303 304 /* Rx-related ring data */ 305 struct xgbe_rx_ring_data { 306 struct xgbe_buffer_data hdr; /* Header locations */ 307 struct xgbe_buffer_data buf; /* Payload locations */ 308 309 unsigned short hdr_len; /* Length of received header */ 310 unsigned short len; /* Length of received packet */ 311 }; 312 313 /* Structure used to hold information related to the descriptor 314 * and the packet associated with the descriptor (always use 315 * use the XGBE_GET_DESC_DATA macro to access this data from the ring) 316 */ 317 struct xgbe_ring_data { 318 struct xgbe_ring_desc *rdesc; /* Virtual address of descriptor */ 319 dma_addr_t rdesc_dma; /* DMA address of descriptor */ 320 321 struct sk_buff *skb; /* Virtual address of SKB */ 322 dma_addr_t skb_dma; /* DMA address of SKB data */ 323 unsigned int skb_dma_len; /* Length of SKB DMA area */ 324 325 struct xgbe_tx_ring_data tx; /* Tx-related data */ 326 struct xgbe_rx_ring_data rx; /* Rx-related data */ 327 328 unsigned int interrupt; /* Interrupt indicator */ 329 330 unsigned int mapped_as_page; 331 332 /* Incomplete receive save location. If the budget is exhausted 333 * or the last descriptor (last normal descriptor or a following 334 * context descriptor) has not been DMA'd yet the current state 335 * of the receive processing needs to be saved. 336 */ 337 unsigned int state_saved; 338 struct { 339 unsigned int incomplete; 340 unsigned int context_next; 341 struct sk_buff *skb; 342 unsigned int len; 343 unsigned int error; 344 } state; 345 }; 346 347 struct xgbe_ring { 348 /* Ring lock - used just for TX rings at the moment */ 349 spinlock_t lock; 350 351 /* Per packet related information */ 352 struct xgbe_packet_data packet_data; 353 354 /* Virtual/DMA addresses and count of allocated descriptor memory */ 355 struct xgbe_ring_desc *rdesc; 356 dma_addr_t rdesc_dma; 357 unsigned int rdesc_count; 358 359 /* Array of descriptor data corresponding the descriptor memory 360 * (always use the XGBE_GET_DESC_DATA macro to access this data) 361 */ 362 struct xgbe_ring_data *rdata; 363 364 /* Page allocation for RX buffers */ 365 struct xgbe_page_alloc rx_hdr_pa; 366 struct xgbe_page_alloc rx_buf_pa; 367 368 /* Ring index values 369 * cur - Tx: index of descriptor to be used for current transfer 370 * Rx: index of descriptor to check for packet availability 371 * dirty - Tx: index of descriptor to check for transfer complete 372 * Rx: index of descriptor to check for buffer reallocation 373 */ 374 unsigned int cur; 375 unsigned int dirty; 376 377 /* Coalesce frame count used for interrupt bit setting */ 378 unsigned int coalesce_count; 379 380 union { 381 struct { 382 unsigned int queue_stopped; 383 unsigned int xmit_more; 384 unsigned short cur_mss; 385 unsigned short cur_vlan_ctag; 386 } tx; 387 }; 388 } ____cacheline_aligned; 389 390 /* Structure used to describe the descriptor rings associated with 391 * a DMA channel. 392 */ 393 struct xgbe_channel { 394 char name[16]; 395 396 /* Address of private data area for device */ 397 struct xgbe_prv_data *pdata; 398 399 /* Queue index and base address of queue's DMA registers */ 400 unsigned int queue_index; 401 void __iomem *dma_regs; 402 403 /* Per channel interrupt irq number */ 404 int dma_irq; 405 char dma_irq_name[IFNAMSIZ + 32]; 406 407 /* Netdev related settings */ 408 struct napi_struct napi; 409 410 unsigned int saved_ier; 411 412 unsigned int tx_timer_active; 413 struct hrtimer tx_timer; 414 415 struct xgbe_ring *tx_ring; 416 struct xgbe_ring *rx_ring; 417 } ____cacheline_aligned; 418 419 enum xgbe_int { 420 XGMAC_INT_DMA_CH_SR_TI, 421 XGMAC_INT_DMA_CH_SR_TPS, 422 XGMAC_INT_DMA_CH_SR_TBU, 423 XGMAC_INT_DMA_CH_SR_RI, 424 XGMAC_INT_DMA_CH_SR_RBU, 425 XGMAC_INT_DMA_CH_SR_RPS, 426 XGMAC_INT_DMA_CH_SR_TI_RI, 427 XGMAC_INT_DMA_CH_SR_FBE, 428 XGMAC_INT_DMA_ALL, 429 }; 430 431 enum xgbe_int_state { 432 XGMAC_INT_STATE_SAVE, 433 XGMAC_INT_STATE_RESTORE, 434 }; 435 436 enum xgbe_mtl_fifo_size { 437 XGMAC_MTL_FIFO_SIZE_256 = 0x00, 438 XGMAC_MTL_FIFO_SIZE_512 = 0x01, 439 XGMAC_MTL_FIFO_SIZE_1K = 0x03, 440 XGMAC_MTL_FIFO_SIZE_2K = 0x07, 441 XGMAC_MTL_FIFO_SIZE_4K = 0x0f, 442 XGMAC_MTL_FIFO_SIZE_8K = 0x1f, 443 XGMAC_MTL_FIFO_SIZE_16K = 0x3f, 444 XGMAC_MTL_FIFO_SIZE_32K = 0x7f, 445 XGMAC_MTL_FIFO_SIZE_64K = 0xff, 446 XGMAC_MTL_FIFO_SIZE_128K = 0x1ff, 447 XGMAC_MTL_FIFO_SIZE_256K = 0x3ff, 448 }; 449 450 struct xgbe_mmc_stats { 451 /* Tx Stats */ 452 u64 txoctetcount_gb; 453 u64 txframecount_gb; 454 u64 txbroadcastframes_g; 455 u64 txmulticastframes_g; 456 u64 tx64octets_gb; 457 u64 tx65to127octets_gb; 458 u64 tx128to255octets_gb; 459 u64 tx256to511octets_gb; 460 u64 tx512to1023octets_gb; 461 u64 tx1024tomaxoctets_gb; 462 u64 txunicastframes_gb; 463 u64 txmulticastframes_gb; 464 u64 txbroadcastframes_gb; 465 u64 txunderflowerror; 466 u64 txoctetcount_g; 467 u64 txframecount_g; 468 u64 txpauseframes; 469 u64 txvlanframes_g; 470 471 /* Rx Stats */ 472 u64 rxframecount_gb; 473 u64 rxoctetcount_gb; 474 u64 rxoctetcount_g; 475 u64 rxbroadcastframes_g; 476 u64 rxmulticastframes_g; 477 u64 rxcrcerror; 478 u64 rxrunterror; 479 u64 rxjabbererror; 480 u64 rxundersize_g; 481 u64 rxoversize_g; 482 u64 rx64octets_gb; 483 u64 rx65to127octets_gb; 484 u64 rx128to255octets_gb; 485 u64 rx256to511octets_gb; 486 u64 rx512to1023octets_gb; 487 u64 rx1024tomaxoctets_gb; 488 u64 rxunicastframes_g; 489 u64 rxlengtherror; 490 u64 rxoutofrangetype; 491 u64 rxpauseframes; 492 u64 rxfifooverflow; 493 u64 rxvlanframes_gb; 494 u64 rxwatchdogerror; 495 }; 496 497 struct xgbe_hw_if { 498 int (*tx_complete)(struct xgbe_ring_desc *); 499 500 int (*set_promiscuous_mode)(struct xgbe_prv_data *, unsigned int); 501 int (*set_all_multicast_mode)(struct xgbe_prv_data *, unsigned int); 502 int (*add_mac_addresses)(struct xgbe_prv_data *); 503 int (*set_mac_address)(struct xgbe_prv_data *, u8 *addr); 504 505 int (*enable_rx_csum)(struct xgbe_prv_data *); 506 int (*disable_rx_csum)(struct xgbe_prv_data *); 507 508 int (*enable_rx_vlan_stripping)(struct xgbe_prv_data *); 509 int (*disable_rx_vlan_stripping)(struct xgbe_prv_data *); 510 int (*enable_rx_vlan_filtering)(struct xgbe_prv_data *); 511 int (*disable_rx_vlan_filtering)(struct xgbe_prv_data *); 512 int (*update_vlan_hash_table)(struct xgbe_prv_data *); 513 514 int (*read_mmd_regs)(struct xgbe_prv_data *, int, int); 515 void (*write_mmd_regs)(struct xgbe_prv_data *, int, int, int); 516 int (*set_gmii_speed)(struct xgbe_prv_data *); 517 int (*set_gmii_2500_speed)(struct xgbe_prv_data *); 518 int (*set_xgmii_speed)(struct xgbe_prv_data *); 519 520 void (*enable_tx)(struct xgbe_prv_data *); 521 void (*disable_tx)(struct xgbe_prv_data *); 522 void (*enable_rx)(struct xgbe_prv_data *); 523 void (*disable_rx)(struct xgbe_prv_data *); 524 525 void (*powerup_tx)(struct xgbe_prv_data *); 526 void (*powerdown_tx)(struct xgbe_prv_data *); 527 void (*powerup_rx)(struct xgbe_prv_data *); 528 void (*powerdown_rx)(struct xgbe_prv_data *); 529 530 int (*init)(struct xgbe_prv_data *); 531 int (*exit)(struct xgbe_prv_data *); 532 533 int (*enable_int)(struct xgbe_channel *, enum xgbe_int); 534 int (*disable_int)(struct xgbe_channel *, enum xgbe_int); 535 void (*dev_xmit)(struct xgbe_channel *); 536 int (*dev_read)(struct xgbe_channel *); 537 void (*tx_desc_init)(struct xgbe_channel *); 538 void (*rx_desc_init)(struct xgbe_channel *); 539 void (*rx_desc_reset)(struct xgbe_ring_data *); 540 void (*tx_desc_reset)(struct xgbe_ring_data *); 541 int (*is_last_desc)(struct xgbe_ring_desc *); 542 int (*is_context_desc)(struct xgbe_ring_desc *); 543 void (*tx_start_xmit)(struct xgbe_channel *, struct xgbe_ring *); 544 545 /* For FLOW ctrl */ 546 int (*config_tx_flow_control)(struct xgbe_prv_data *); 547 int (*config_rx_flow_control)(struct xgbe_prv_data *); 548 549 /* For RX coalescing */ 550 int (*config_rx_coalesce)(struct xgbe_prv_data *); 551 int (*config_tx_coalesce)(struct xgbe_prv_data *); 552 unsigned int (*usec_to_riwt)(struct xgbe_prv_data *, unsigned int); 553 unsigned int (*riwt_to_usec)(struct xgbe_prv_data *, unsigned int); 554 555 /* For RX and TX threshold config */ 556 int (*config_rx_threshold)(struct xgbe_prv_data *, unsigned int); 557 int (*config_tx_threshold)(struct xgbe_prv_data *, unsigned int); 558 559 /* For RX and TX Store and Forward Mode config */ 560 int (*config_rsf_mode)(struct xgbe_prv_data *, unsigned int); 561 int (*config_tsf_mode)(struct xgbe_prv_data *, unsigned int); 562 563 /* For TX DMA Operate on Second Frame config */ 564 int (*config_osp_mode)(struct xgbe_prv_data *); 565 566 /* For RX and TX PBL config */ 567 int (*config_rx_pbl_val)(struct xgbe_prv_data *); 568 int (*get_rx_pbl_val)(struct xgbe_prv_data *); 569 int (*config_tx_pbl_val)(struct xgbe_prv_data *); 570 int (*get_tx_pbl_val)(struct xgbe_prv_data *); 571 int (*config_pblx8)(struct xgbe_prv_data *); 572 573 /* For MMC statistics */ 574 void (*rx_mmc_int)(struct xgbe_prv_data *); 575 void (*tx_mmc_int)(struct xgbe_prv_data *); 576 void (*read_mmc_stats)(struct xgbe_prv_data *); 577 578 /* For Timestamp config */ 579 int (*config_tstamp)(struct xgbe_prv_data *, unsigned int); 580 void (*update_tstamp_addend)(struct xgbe_prv_data *, unsigned int); 581 void (*set_tstamp_time)(struct xgbe_prv_data *, unsigned int sec, 582 unsigned int nsec); 583 u64 (*get_tstamp_time)(struct xgbe_prv_data *); 584 u64 (*get_tx_tstamp)(struct xgbe_prv_data *); 585 586 /* For Data Center Bridging config */ 587 void (*config_dcb_tc)(struct xgbe_prv_data *); 588 void (*config_dcb_pfc)(struct xgbe_prv_data *); 589 590 /* For Receive Side Scaling */ 591 int (*enable_rss)(struct xgbe_prv_data *); 592 int (*disable_rss)(struct xgbe_prv_data *); 593 int (*set_rss_hash_key)(struct xgbe_prv_data *, const u8 *); 594 int (*set_rss_lookup_table)(struct xgbe_prv_data *, const u32 *); 595 }; 596 597 struct xgbe_desc_if { 598 int (*alloc_ring_resources)(struct xgbe_prv_data *); 599 void (*free_ring_resources)(struct xgbe_prv_data *); 600 int (*map_tx_skb)(struct xgbe_channel *, struct sk_buff *); 601 int (*map_rx_buffer)(struct xgbe_prv_data *, struct xgbe_ring *, 602 struct xgbe_ring_data *); 603 void (*unmap_rdata)(struct xgbe_prv_data *, struct xgbe_ring_data *); 604 void (*wrapper_tx_desc_init)(struct xgbe_prv_data *); 605 void (*wrapper_rx_desc_init)(struct xgbe_prv_data *); 606 }; 607 608 /* This structure contains flags that indicate what hardware features 609 * or configurations are present in the device. 610 */ 611 struct xgbe_hw_features { 612 /* HW Version */ 613 unsigned int version; 614 615 /* HW Feature Register0 */ 616 unsigned int gmii; /* 1000 Mbps support */ 617 unsigned int vlhash; /* VLAN Hash Filter */ 618 unsigned int sma; /* SMA(MDIO) Interface */ 619 unsigned int rwk; /* PMT remote wake-up packet */ 620 unsigned int mgk; /* PMT magic packet */ 621 unsigned int mmc; /* RMON module */ 622 unsigned int aoe; /* ARP Offload */ 623 unsigned int ts; /* IEEE 1588-2008 Adavanced Timestamp */ 624 unsigned int eee; /* Energy Efficient Ethernet */ 625 unsigned int tx_coe; /* Tx Checksum Offload */ 626 unsigned int rx_coe; /* Rx Checksum Offload */ 627 unsigned int addn_mac; /* Additional MAC Addresses */ 628 unsigned int ts_src; /* Timestamp Source */ 629 unsigned int sa_vlan_ins; /* Source Address or VLAN Insertion */ 630 631 /* HW Feature Register1 */ 632 unsigned int rx_fifo_size; /* MTL Receive FIFO Size */ 633 unsigned int tx_fifo_size; /* MTL Transmit FIFO Size */ 634 unsigned int adv_ts_hi; /* Advance Timestamping High Word */ 635 unsigned int dcb; /* DCB Feature */ 636 unsigned int sph; /* Split Header Feature */ 637 unsigned int tso; /* TCP Segmentation Offload */ 638 unsigned int dma_debug; /* DMA Debug Registers */ 639 unsigned int rss; /* Receive Side Scaling */ 640 unsigned int tc_cnt; /* Number of Traffic Classes */ 641 unsigned int hash_table_size; /* Hash Table Size */ 642 unsigned int l3l4_filter_num; /* Number of L3-L4 Filters */ 643 644 /* HW Feature Register2 */ 645 unsigned int rx_q_cnt; /* Number of MTL Receive Queues */ 646 unsigned int tx_q_cnt; /* Number of MTL Transmit Queues */ 647 unsigned int rx_ch_cnt; /* Number of DMA Receive Channels */ 648 unsigned int tx_ch_cnt; /* Number of DMA Transmit Channels */ 649 unsigned int pps_out_num; /* Number of PPS outputs */ 650 unsigned int aux_snap_num; /* Number of Aux snapshot inputs */ 651 }; 652 653 struct xgbe_prv_data { 654 struct net_device *netdev; 655 struct platform_device *pdev; 656 struct acpi_device *adev; 657 struct device *dev; 658 659 /* ACPI or DT flag */ 660 unsigned int use_acpi; 661 662 /* XGMAC/XPCS related mmio registers */ 663 void __iomem *xgmac_regs; /* XGMAC CSRs */ 664 void __iomem *xpcs_regs; /* XPCS MMD registers */ 665 666 /* Overall device lock */ 667 spinlock_t lock; 668 669 /* XPCS indirect addressing mutex */ 670 struct mutex xpcs_mutex; 671 672 /* RSS addressing mutex */ 673 struct mutex rss_mutex; 674 675 int dev_irq; 676 unsigned int per_channel_irq; 677 678 struct xgbe_hw_if hw_if; 679 struct xgbe_desc_if desc_if; 680 681 /* AXI DMA settings */ 682 unsigned int coherent; 683 unsigned int axdomain; 684 unsigned int arcache; 685 unsigned int awcache; 686 687 /* Rings for Tx/Rx on a DMA channel */ 688 struct xgbe_channel *channel; 689 unsigned int channel_count; 690 unsigned int tx_ring_count; 691 unsigned int tx_desc_count; 692 unsigned int rx_ring_count; 693 unsigned int rx_desc_count; 694 695 unsigned int tx_q_count; 696 unsigned int rx_q_count; 697 698 /* Tx/Rx common settings */ 699 unsigned int pblx8; 700 701 /* Tx settings */ 702 unsigned int tx_sf_mode; 703 unsigned int tx_threshold; 704 unsigned int tx_pbl; 705 unsigned int tx_osp_mode; 706 707 /* Rx settings */ 708 unsigned int rx_sf_mode; 709 unsigned int rx_threshold; 710 unsigned int rx_pbl; 711 712 /* Tx coalescing settings */ 713 unsigned int tx_usecs; 714 unsigned int tx_frames; 715 716 /* Rx coalescing settings */ 717 unsigned int rx_riwt; 718 unsigned int rx_frames; 719 720 /* Current Rx buffer size */ 721 unsigned int rx_buf_size; 722 723 /* Flow control settings */ 724 unsigned int pause_autoneg; 725 unsigned int tx_pause; 726 unsigned int rx_pause; 727 728 /* Receive Side Scaling settings */ 729 u8 rss_key[XGBE_RSS_HASH_KEY_SIZE]; 730 u32 rss_table[XGBE_RSS_MAX_TABLE_SIZE]; 731 u32 rss_options; 732 733 /* MDIO settings */ 734 struct module *phy_module; 735 char *mii_bus_id; 736 struct mii_bus *mii; 737 int mdio_mmd; 738 struct phy_device *phydev; 739 int default_autoneg; 740 int default_speed; 741 742 /* Current PHY settings */ 743 phy_interface_t phy_mode; 744 int phy_link; 745 int phy_speed; 746 unsigned int phy_tx_pause; 747 unsigned int phy_rx_pause; 748 749 /* Netdev related settings */ 750 unsigned char mac_addr[ETH_ALEN]; 751 netdev_features_t netdev_features; 752 struct napi_struct napi; 753 struct xgbe_mmc_stats mmc_stats; 754 755 /* Filtering support */ 756 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 757 758 /* Device clocks */ 759 struct clk *sysclk; 760 unsigned long sysclk_rate; 761 struct clk *ptpclk; 762 unsigned long ptpclk_rate; 763 764 /* Timestamp support */ 765 spinlock_t tstamp_lock; 766 struct ptp_clock_info ptp_clock_info; 767 struct ptp_clock *ptp_clock; 768 struct hwtstamp_config tstamp_config; 769 struct cyclecounter tstamp_cc; 770 struct timecounter tstamp_tc; 771 unsigned int tstamp_addend; 772 struct work_struct tx_tstamp_work; 773 struct sk_buff *tx_tstamp_skb; 774 u64 tx_tstamp; 775 776 /* DCB support */ 777 struct ieee_ets *ets; 778 struct ieee_pfc *pfc; 779 unsigned int q2tc_map[XGBE_MAX_QUEUES]; 780 unsigned int prio2q_map[IEEE_8021QAZ_MAX_TCS]; 781 782 /* Hardware features of the device */ 783 struct xgbe_hw_features hw_feat; 784 785 /* Device restart work structure */ 786 struct work_struct restart_work; 787 788 /* Keeps track of power mode */ 789 unsigned int power_down; 790 791 #ifdef CONFIG_DEBUG_FS 792 struct dentry *xgbe_debugfs; 793 794 unsigned int debugfs_xgmac_reg; 795 796 unsigned int debugfs_xpcs_mmd; 797 unsigned int debugfs_xpcs_reg; 798 #endif 799 }; 800 801 /* Function prototypes*/ 802 803 void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *); 804 void xgbe_init_function_ptrs_desc(struct xgbe_desc_if *); 805 struct net_device_ops *xgbe_get_netdev_ops(void); 806 struct ethtool_ops *xgbe_get_ethtool_ops(void); 807 #ifdef CONFIG_AMD_XGBE_DCB 808 const struct dcbnl_rtnl_ops *xgbe_get_dcbnl_ops(void); 809 #endif 810 811 int xgbe_mdio_register(struct xgbe_prv_data *); 812 void xgbe_mdio_unregister(struct xgbe_prv_data *); 813 void xgbe_dump_phy_registers(struct xgbe_prv_data *); 814 void xgbe_ptp_register(struct xgbe_prv_data *); 815 void xgbe_ptp_unregister(struct xgbe_prv_data *); 816 void xgbe_dump_tx_desc(struct xgbe_ring *, unsigned int, unsigned int, 817 unsigned int); 818 void xgbe_dump_rx_desc(struct xgbe_ring *, struct xgbe_ring_desc *, 819 unsigned int); 820 void xgbe_print_pkt(struct net_device *, struct sk_buff *, bool); 821 void xgbe_get_all_hw_features(struct xgbe_prv_data *); 822 int xgbe_powerup(struct net_device *, unsigned int); 823 int xgbe_powerdown(struct net_device *, unsigned int); 824 void xgbe_init_rx_coalesce(struct xgbe_prv_data *); 825 void xgbe_init_tx_coalesce(struct xgbe_prv_data *); 826 827 #ifdef CONFIG_DEBUG_FS 828 void xgbe_debugfs_init(struct xgbe_prv_data *); 829 void xgbe_debugfs_exit(struct xgbe_prv_data *); 830 #else 831 static inline void xgbe_debugfs_init(struct xgbe_prv_data *pdata) {} 832 static inline void xgbe_debugfs_exit(struct xgbe_prv_data *pdata) {} 833 #endif /* CONFIG_DEBUG_FS */ 834 835 /* NOTE: Uncomment for TX and RX DESCRIPTOR DUMP in KERNEL LOG */ 836 #if 0 837 #define XGMAC_ENABLE_TX_DESC_DUMP 838 #define XGMAC_ENABLE_RX_DESC_DUMP 839 #endif 840 841 /* NOTE: Uncomment for TX and RX PACKET DUMP in KERNEL LOG */ 842 #if 0 843 #define XGMAC_ENABLE_TX_PKT_DUMP 844 #define XGMAC_ENABLE_RX_PKT_DUMP 845 #endif 846 847 /* NOTE: Uncomment for function trace log messages in KERNEL LOG */ 848 #if 0 849 #define YDEBUG 850 #define YDEBUG_MDIO 851 #endif 852 853 /* For debug prints */ 854 #ifdef YDEBUG 855 #define DBGPR(x...) pr_alert(x) 856 #define DBGPHY_REGS(x...) xgbe_dump_phy_registers(x) 857 #else 858 #define DBGPR(x...) do { } while (0) 859 #define DBGPHY_REGS(x...) do { } while (0) 860 #endif 861 862 #ifdef YDEBUG_MDIO 863 #define DBGPR_MDIO(x...) pr_alert(x) 864 #else 865 #define DBGPR_MDIO(x...) do { } while (0) 866 #endif 867 868 #endif 869