1 /* 2 * AMD 10Gb Ethernet driver 3 * 4 * This file is available to you under your choice of the following two 5 * licenses: 6 * 7 * License 1: GPLv2 8 * 9 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc. 10 * 11 * This file is free software; you may copy, redistribute and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation, either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program. If not, see <http://www.gnu.org/licenses/>. 23 * 24 * This file incorporates work covered by the following copyright and 25 * permission notice: 26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 28 * Inc. unless otherwise expressly agreed to in writing between Synopsys 29 * and you. 30 * 31 * The Software IS NOT an item of Licensed Software or Licensed Product 32 * under any End User Software License Agreement or Agreement for Licensed 33 * Product with Synopsys or any supplement thereto. Permission is hereby 34 * granted, free of charge, to any person obtaining a copy of this software 35 * annotated with this license and the Software, to deal in the Software 36 * without restriction, including without limitation the rights to use, 37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 38 * of the Software, and to permit persons to whom the Software is furnished 39 * to do so, subject to the following conditions: 40 * 41 * The above copyright notice and this permission notice shall be included 42 * in all copies or substantial portions of the Software. 43 * 44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 54 * THE POSSIBILITY OF SUCH DAMAGE. 55 * 56 * 57 * License 2: Modified BSD 58 * 59 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc. 60 * All rights reserved. 61 * 62 * Redistribution and use in source and binary forms, with or without 63 * modification, are permitted provided that the following conditions are met: 64 * * Redistributions of source code must retain the above copyright 65 * notice, this list of conditions and the following disclaimer. 66 * * Redistributions in binary form must reproduce the above copyright 67 * notice, this list of conditions and the following disclaimer in the 68 * documentation and/or other materials provided with the distribution. 69 * * Neither the name of Advanced Micro Devices, Inc. nor the 70 * names of its contributors may be used to endorse or promote products 71 * derived from this software without specific prior written permission. 72 * 73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY 77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 83 * 84 * This file incorporates work covered by the following copyright and 85 * permission notice: 86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 88 * Inc. unless otherwise expressly agreed to in writing between Synopsys 89 * and you. 90 * 91 * The Software IS NOT an item of Licensed Software or Licensed Product 92 * under any End User Software License Agreement or Agreement for Licensed 93 * Product with Synopsys or any supplement thereto. Permission is hereby 94 * granted, free of charge, to any person obtaining a copy of this software 95 * annotated with this license and the Software, to deal in the Software 96 * without restriction, including without limitation the rights to use, 97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 98 * of the Software, and to permit persons to whom the Software is furnished 99 * to do so, subject to the following conditions: 100 * 101 * The above copyright notice and this permission notice shall be included 102 * in all copies or substantial portions of the Software. 103 * 104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 114 * THE POSSIBILITY OF SUCH DAMAGE. 115 */ 116 117 #ifndef __XGBE_H__ 118 #define __XGBE_H__ 119 120 #include <linux/dma-mapping.h> 121 #include <linux/netdevice.h> 122 #include <linux/workqueue.h> 123 #include <linux/phy.h> 124 #include <linux/if_vlan.h> 125 #include <linux/bitops.h> 126 #include <linux/ptp_clock_kernel.h> 127 #include <linux/timecounter.h> 128 #include <linux/net_tstamp.h> 129 #include <net/dcbnl.h> 130 #include <linux/completion.h> 131 #include <linux/cpumask.h> 132 133 #define XGBE_DRV_NAME "amd-xgbe" 134 #define XGBE_DRV_VERSION "1.0.3" 135 #define XGBE_DRV_DESC "AMD 10 Gigabit Ethernet Driver" 136 137 /* Descriptor related defines */ 138 #define XGBE_TX_DESC_CNT 512 139 #define XGBE_TX_DESC_MIN_FREE (XGBE_TX_DESC_CNT >> 3) 140 #define XGBE_TX_DESC_MAX_PROC (XGBE_TX_DESC_CNT >> 1) 141 #define XGBE_RX_DESC_CNT 512 142 143 #define XGBE_TX_MAX_BUF_SIZE (0x3fff & ~(64 - 1)) 144 145 /* Descriptors required for maximum contiguous TSO/GSO packet */ 146 #define XGBE_TX_MAX_SPLIT ((GSO_MAX_SIZE / XGBE_TX_MAX_BUF_SIZE) + 1) 147 148 /* Maximum possible descriptors needed for an SKB: 149 * - Maximum number of SKB frags 150 * - Maximum descriptors for contiguous TSO/GSO packet 151 * - Possible context descriptor 152 * - Possible TSO header descriptor 153 */ 154 #define XGBE_TX_MAX_DESCS (MAX_SKB_FRAGS + XGBE_TX_MAX_SPLIT + 2) 155 156 #define XGBE_RX_MIN_BUF_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN) 157 #define XGBE_RX_BUF_ALIGN 64 158 #define XGBE_SKB_ALLOC_SIZE 256 159 #define XGBE_SPH_HDSMS_SIZE 2 /* Keep in sync with SKB_ALLOC_SIZE */ 160 161 #define XGBE_MAX_DMA_CHANNELS 16 162 #define XGBE_MAX_QUEUES 16 163 #define XGBE_PRIORITY_QUEUES 8 164 #define XGBE_DMA_STOP_TIMEOUT 1 165 166 /* DMA cache settings - Outer sharable, write-back, write-allocate */ 167 #define XGBE_DMA_OS_ARCR 0x002b2b2b 168 #define XGBE_DMA_OS_AWCR 0x2f2f2f2f 169 170 /* DMA cache settings - System, no caches used */ 171 #define XGBE_DMA_SYS_ARCR 0x00303030 172 #define XGBE_DMA_SYS_AWCR 0x30303030 173 174 /* DMA cache settings - PCI device */ 175 #define XGBE_DMA_PCI_ARCR 0x00000003 176 #define XGBE_DMA_PCI_AWCR 0x13131313 177 #define XGBE_DMA_PCI_AWARCR 0x00000313 178 179 /* DMA channel interrupt modes */ 180 #define XGBE_IRQ_MODE_EDGE 0 181 #define XGBE_IRQ_MODE_LEVEL 1 182 183 #define XGBE_DMA_INTERRUPT_MASK 0x31c7 184 185 #define XGMAC_MIN_PACKET 60 186 #define XGMAC_STD_PACKET_MTU 1500 187 #define XGMAC_MAX_STD_PACKET 1518 188 #define XGMAC_JUMBO_PACKET_MTU 9000 189 #define XGMAC_MAX_JUMBO_PACKET 9018 190 #define XGMAC_ETH_PREAMBLE (12 + 8) /* Inter-frame gap + preamble */ 191 192 #define XGMAC_PFC_DATA_LEN 46 193 #define XGMAC_PFC_DELAYS 14000 194 195 #define XGMAC_PRIO_QUEUES(_cnt) \ 196 min_t(unsigned int, IEEE_8021QAZ_MAX_TCS, (_cnt)) 197 198 /* Common property names */ 199 #define XGBE_MAC_ADDR_PROPERTY "mac-address" 200 #define XGBE_PHY_MODE_PROPERTY "phy-mode" 201 #define XGBE_DMA_IRQS_PROPERTY "amd,per-channel-interrupt" 202 #define XGBE_SPEEDSET_PROPERTY "amd,speed-set" 203 204 /* Device-tree clock names */ 205 #define XGBE_DMA_CLOCK "dma_clk" 206 #define XGBE_PTP_CLOCK "ptp_clk" 207 208 /* ACPI property names */ 209 #define XGBE_ACPI_DMA_FREQ "amd,dma-freq" 210 #define XGBE_ACPI_PTP_FREQ "amd,ptp-freq" 211 212 /* PCI BAR mapping */ 213 #define XGBE_XGMAC_BAR 0 214 #define XGBE_XPCS_BAR 1 215 #define XGBE_MAC_PROP_OFFSET 0x1d000 216 #define XGBE_I2C_CTRL_OFFSET 0x1e000 217 218 /* PCI MSI/MSIx support */ 219 #define XGBE_MSI_BASE_COUNT 4 220 #define XGBE_MSI_MIN_COUNT (XGBE_MSI_BASE_COUNT + 1) 221 222 /* PCI clock frequencies */ 223 #define XGBE_V2_DMA_CLOCK_FREQ 500000000 /* 500 MHz */ 224 #define XGBE_V2_PTP_CLOCK_FREQ 125000000 /* 125 MHz */ 225 226 /* Timestamp support - values based on 50MHz PTP clock 227 * 50MHz => 20 nsec 228 */ 229 #define XGBE_TSTAMP_SSINC 20 230 #define XGBE_TSTAMP_SNSINC 0 231 232 /* Driver PMT macros */ 233 #define XGMAC_DRIVER_CONTEXT 1 234 #define XGMAC_IOCTL_CONTEXT 2 235 236 #define XGMAC_FIFO_MIN_ALLOC 2048 237 #define XGMAC_FIFO_UNIT 256 238 #define XGMAC_FIFO_ALIGN(_x) \ 239 (((_x) + XGMAC_FIFO_UNIT - 1) & ~(XGMAC_FIFO_UNIT - 1)) 240 #define XGMAC_FIFO_FC_OFF 2048 241 #define XGMAC_FIFO_FC_MIN 4096 242 243 #define XGBE_TC_MIN_QUANTUM 10 244 245 /* Helper macro for descriptor handling 246 * Always use XGBE_GET_DESC_DATA to access the descriptor data 247 * since the index is free-running and needs to be and-ed 248 * with the descriptor count value of the ring to index to 249 * the proper descriptor data. 250 */ 251 #define XGBE_GET_DESC_DATA(_ring, _idx) \ 252 ((_ring)->rdata + \ 253 ((_idx) & ((_ring)->rdesc_count - 1))) 254 255 /* Default coalescing parameters */ 256 #define XGMAC_INIT_DMA_TX_USECS 1000 257 #define XGMAC_INIT_DMA_TX_FRAMES 25 258 259 #define XGMAC_MAX_DMA_RIWT 0xff 260 #define XGMAC_INIT_DMA_RX_USECS 30 261 #define XGMAC_INIT_DMA_RX_FRAMES 25 262 263 /* Flow control queue count */ 264 #define XGMAC_MAX_FLOW_CONTROL_QUEUES 8 265 266 /* Flow control threshold units */ 267 #define XGMAC_FLOW_CONTROL_UNIT 512 268 #define XGMAC_FLOW_CONTROL_ALIGN(_x) \ 269 (((_x) + XGMAC_FLOW_CONTROL_UNIT - 1) & ~(XGMAC_FLOW_CONTROL_UNIT - 1)) 270 #define XGMAC_FLOW_CONTROL_VALUE(_x) \ 271 (((_x) < 1024) ? 0 : ((_x) / XGMAC_FLOW_CONTROL_UNIT) - 2) 272 #define XGMAC_FLOW_CONTROL_MAX 33280 273 274 /* Maximum MAC address hash table size (256 bits = 8 bytes) */ 275 #define XGBE_MAC_HASH_TABLE_SIZE 8 276 277 /* Receive Side Scaling */ 278 #define XGBE_RSS_HASH_KEY_SIZE 40 279 #define XGBE_RSS_MAX_TABLE_SIZE 256 280 #define XGBE_RSS_LOOKUP_TABLE_TYPE 0 281 #define XGBE_RSS_HASH_KEY_TYPE 1 282 283 /* Auto-negotiation */ 284 #define XGBE_AN_MS_TIMEOUT 500 285 #define XGBE_LINK_TIMEOUT 5 286 287 #define XGBE_SGMII_AN_LINK_STATUS BIT(1) 288 #define XGBE_SGMII_AN_LINK_SPEED (BIT(2) | BIT(3)) 289 #define XGBE_SGMII_AN_LINK_SPEED_100 0x04 290 #define XGBE_SGMII_AN_LINK_SPEED_1000 0x08 291 #define XGBE_SGMII_AN_LINK_DUPLEX BIT(4) 292 293 /* ECC correctable error notification window (seconds) */ 294 #define XGBE_ECC_LIMIT 60 295 296 /* MDIO port types */ 297 #define XGMAC_MAX_C22_PORT 3 298 299 struct xgbe_prv_data; 300 301 struct xgbe_packet_data { 302 struct sk_buff *skb; 303 304 unsigned int attributes; 305 306 unsigned int errors; 307 308 unsigned int rdesc_count; 309 unsigned int length; 310 311 unsigned int header_len; 312 unsigned int tcp_header_len; 313 unsigned int tcp_payload_len; 314 unsigned short mss; 315 316 unsigned short vlan_ctag; 317 318 u64 rx_tstamp; 319 320 u32 rss_hash; 321 enum pkt_hash_types rss_hash_type; 322 323 unsigned int tx_packets; 324 unsigned int tx_bytes; 325 }; 326 327 /* Common Rx and Tx descriptor mapping */ 328 struct xgbe_ring_desc { 329 __le32 desc0; 330 __le32 desc1; 331 __le32 desc2; 332 __le32 desc3; 333 }; 334 335 /* Page allocation related values */ 336 struct xgbe_page_alloc { 337 struct page *pages; 338 unsigned int pages_len; 339 unsigned int pages_offset; 340 341 dma_addr_t pages_dma; 342 }; 343 344 /* Ring entry buffer data */ 345 struct xgbe_buffer_data { 346 struct xgbe_page_alloc pa; 347 struct xgbe_page_alloc pa_unmap; 348 349 dma_addr_t dma_base; 350 unsigned long dma_off; 351 unsigned int dma_len; 352 }; 353 354 /* Tx-related ring data */ 355 struct xgbe_tx_ring_data { 356 unsigned int packets; /* BQL packet count */ 357 unsigned int bytes; /* BQL byte count */ 358 }; 359 360 /* Rx-related ring data */ 361 struct xgbe_rx_ring_data { 362 struct xgbe_buffer_data hdr; /* Header locations */ 363 struct xgbe_buffer_data buf; /* Payload locations */ 364 365 unsigned short hdr_len; /* Length of received header */ 366 unsigned short len; /* Length of received packet */ 367 }; 368 369 /* Structure used to hold information related to the descriptor 370 * and the packet associated with the descriptor (always use 371 * use the XGBE_GET_DESC_DATA macro to access this data from the ring) 372 */ 373 struct xgbe_ring_data { 374 struct xgbe_ring_desc *rdesc; /* Virtual address of descriptor */ 375 dma_addr_t rdesc_dma; /* DMA address of descriptor */ 376 377 struct sk_buff *skb; /* Virtual address of SKB */ 378 dma_addr_t skb_dma; /* DMA address of SKB data */ 379 unsigned int skb_dma_len; /* Length of SKB DMA area */ 380 381 struct xgbe_tx_ring_data tx; /* Tx-related data */ 382 struct xgbe_rx_ring_data rx; /* Rx-related data */ 383 384 unsigned int mapped_as_page; 385 386 /* Incomplete receive save location. If the budget is exhausted 387 * or the last descriptor (last normal descriptor or a following 388 * context descriptor) has not been DMA'd yet the current state 389 * of the receive processing needs to be saved. 390 */ 391 unsigned int state_saved; 392 struct { 393 struct sk_buff *skb; 394 unsigned int len; 395 unsigned int error; 396 } state; 397 }; 398 399 struct xgbe_ring { 400 /* Ring lock - used just for TX rings at the moment */ 401 spinlock_t lock; 402 403 /* Per packet related information */ 404 struct xgbe_packet_data packet_data; 405 406 /* Virtual/DMA addresses and count of allocated descriptor memory */ 407 struct xgbe_ring_desc *rdesc; 408 dma_addr_t rdesc_dma; 409 unsigned int rdesc_count; 410 411 /* Array of descriptor data corresponding the descriptor memory 412 * (always use the XGBE_GET_DESC_DATA macro to access this data) 413 */ 414 struct xgbe_ring_data *rdata; 415 416 /* Page allocation for RX buffers */ 417 struct xgbe_page_alloc rx_hdr_pa; 418 struct xgbe_page_alloc rx_buf_pa; 419 int node; 420 421 /* Ring index values 422 * cur - Tx: index of descriptor to be used for current transfer 423 * Rx: index of descriptor to check for packet availability 424 * dirty - Tx: index of descriptor to check for transfer complete 425 * Rx: index of descriptor to check for buffer reallocation 426 */ 427 unsigned int cur; 428 unsigned int dirty; 429 430 /* Coalesce frame count used for interrupt bit setting */ 431 unsigned int coalesce_count; 432 433 union { 434 struct { 435 unsigned int queue_stopped; 436 unsigned int xmit_more; 437 unsigned short cur_mss; 438 unsigned short cur_vlan_ctag; 439 } tx; 440 }; 441 } ____cacheline_aligned; 442 443 /* Structure used to describe the descriptor rings associated with 444 * a DMA channel. 445 */ 446 struct xgbe_channel { 447 char name[16]; 448 449 /* Address of private data area for device */ 450 struct xgbe_prv_data *pdata; 451 452 /* Queue index and base address of queue's DMA registers */ 453 unsigned int queue_index; 454 void __iomem *dma_regs; 455 456 /* Per channel interrupt irq number */ 457 int dma_irq; 458 char dma_irq_name[IFNAMSIZ + 32]; 459 460 /* Netdev related settings */ 461 struct napi_struct napi; 462 463 unsigned int saved_ier; 464 465 unsigned int tx_timer_active; 466 struct timer_list tx_timer; 467 468 struct xgbe_ring *tx_ring; 469 struct xgbe_ring *rx_ring; 470 471 int node; 472 cpumask_t affinity_mask; 473 } ____cacheline_aligned; 474 475 enum xgbe_state { 476 XGBE_DOWN, 477 XGBE_LINK_INIT, 478 XGBE_LINK_ERR, 479 XGBE_STOPPED, 480 }; 481 482 enum xgbe_int { 483 XGMAC_INT_DMA_CH_SR_TI, 484 XGMAC_INT_DMA_CH_SR_TPS, 485 XGMAC_INT_DMA_CH_SR_TBU, 486 XGMAC_INT_DMA_CH_SR_RI, 487 XGMAC_INT_DMA_CH_SR_RBU, 488 XGMAC_INT_DMA_CH_SR_RPS, 489 XGMAC_INT_DMA_CH_SR_TI_RI, 490 XGMAC_INT_DMA_CH_SR_FBE, 491 XGMAC_INT_DMA_ALL, 492 }; 493 494 enum xgbe_int_state { 495 XGMAC_INT_STATE_SAVE, 496 XGMAC_INT_STATE_RESTORE, 497 }; 498 499 enum xgbe_ecc_sec { 500 XGBE_ECC_SEC_TX, 501 XGBE_ECC_SEC_RX, 502 XGBE_ECC_SEC_DESC, 503 }; 504 505 enum xgbe_speed { 506 XGBE_SPEED_1000 = 0, 507 XGBE_SPEED_2500, 508 XGBE_SPEED_10000, 509 XGBE_SPEEDS, 510 }; 511 512 enum xgbe_xpcs_access { 513 XGBE_XPCS_ACCESS_V1 = 0, 514 XGBE_XPCS_ACCESS_V2, 515 }; 516 517 enum xgbe_an_mode { 518 XGBE_AN_MODE_CL73 = 0, 519 XGBE_AN_MODE_CL73_REDRV, 520 XGBE_AN_MODE_CL37, 521 XGBE_AN_MODE_CL37_SGMII, 522 XGBE_AN_MODE_NONE, 523 }; 524 525 enum xgbe_an { 526 XGBE_AN_READY = 0, 527 XGBE_AN_PAGE_RECEIVED, 528 XGBE_AN_INCOMPAT_LINK, 529 XGBE_AN_COMPLETE, 530 XGBE_AN_NO_LINK, 531 XGBE_AN_ERROR, 532 }; 533 534 enum xgbe_rx { 535 XGBE_RX_BPA = 0, 536 XGBE_RX_XNP, 537 XGBE_RX_COMPLETE, 538 XGBE_RX_ERROR, 539 }; 540 541 enum xgbe_mode { 542 XGBE_MODE_KX_1000 = 0, 543 XGBE_MODE_KX_2500, 544 XGBE_MODE_KR, 545 XGBE_MODE_X, 546 XGBE_MODE_SGMII_100, 547 XGBE_MODE_SGMII_1000, 548 XGBE_MODE_SFI, 549 XGBE_MODE_UNKNOWN, 550 }; 551 552 enum xgbe_speedset { 553 XGBE_SPEEDSET_1000_10000 = 0, 554 XGBE_SPEEDSET_2500_10000, 555 }; 556 557 enum xgbe_mdio_mode { 558 XGBE_MDIO_MODE_NONE = 0, 559 XGBE_MDIO_MODE_CL22, 560 XGBE_MDIO_MODE_CL45, 561 }; 562 563 struct xgbe_phy { 564 u32 supported; 565 u32 advertising; 566 u32 lp_advertising; 567 568 int address; 569 570 int autoneg; 571 int speed; 572 int duplex; 573 574 int link; 575 576 int pause_autoneg; 577 int tx_pause; 578 int rx_pause; 579 }; 580 581 enum xgbe_i2c_cmd { 582 XGBE_I2C_CMD_READ = 0, 583 XGBE_I2C_CMD_WRITE, 584 }; 585 586 struct xgbe_i2c_op { 587 enum xgbe_i2c_cmd cmd; 588 589 unsigned int target; 590 591 void *buf; 592 unsigned int len; 593 }; 594 595 struct xgbe_i2c_op_state { 596 struct xgbe_i2c_op *op; 597 598 unsigned int tx_len; 599 unsigned char *tx_buf; 600 601 unsigned int rx_len; 602 unsigned char *rx_buf; 603 604 unsigned int tx_abort_source; 605 606 int ret; 607 }; 608 609 struct xgbe_i2c { 610 unsigned int started; 611 unsigned int max_speed_mode; 612 unsigned int rx_fifo_size; 613 unsigned int tx_fifo_size; 614 615 struct xgbe_i2c_op_state op_state; 616 }; 617 618 struct xgbe_mmc_stats { 619 /* Tx Stats */ 620 u64 txoctetcount_gb; 621 u64 txframecount_gb; 622 u64 txbroadcastframes_g; 623 u64 txmulticastframes_g; 624 u64 tx64octets_gb; 625 u64 tx65to127octets_gb; 626 u64 tx128to255octets_gb; 627 u64 tx256to511octets_gb; 628 u64 tx512to1023octets_gb; 629 u64 tx1024tomaxoctets_gb; 630 u64 txunicastframes_gb; 631 u64 txmulticastframes_gb; 632 u64 txbroadcastframes_gb; 633 u64 txunderflowerror; 634 u64 txoctetcount_g; 635 u64 txframecount_g; 636 u64 txpauseframes; 637 u64 txvlanframes_g; 638 639 /* Rx Stats */ 640 u64 rxframecount_gb; 641 u64 rxoctetcount_gb; 642 u64 rxoctetcount_g; 643 u64 rxbroadcastframes_g; 644 u64 rxmulticastframes_g; 645 u64 rxcrcerror; 646 u64 rxrunterror; 647 u64 rxjabbererror; 648 u64 rxundersize_g; 649 u64 rxoversize_g; 650 u64 rx64octets_gb; 651 u64 rx65to127octets_gb; 652 u64 rx128to255octets_gb; 653 u64 rx256to511octets_gb; 654 u64 rx512to1023octets_gb; 655 u64 rx1024tomaxoctets_gb; 656 u64 rxunicastframes_g; 657 u64 rxlengtherror; 658 u64 rxoutofrangetype; 659 u64 rxpauseframes; 660 u64 rxfifooverflow; 661 u64 rxvlanframes_gb; 662 u64 rxwatchdogerror; 663 }; 664 665 struct xgbe_ext_stats { 666 u64 tx_tso_packets; 667 u64 rx_split_header_packets; 668 u64 rx_buffer_unavailable; 669 }; 670 671 struct xgbe_hw_if { 672 int (*tx_complete)(struct xgbe_ring_desc *); 673 674 int (*set_mac_address)(struct xgbe_prv_data *, u8 *addr); 675 int (*config_rx_mode)(struct xgbe_prv_data *); 676 677 int (*enable_rx_csum)(struct xgbe_prv_data *); 678 int (*disable_rx_csum)(struct xgbe_prv_data *); 679 680 int (*enable_rx_vlan_stripping)(struct xgbe_prv_data *); 681 int (*disable_rx_vlan_stripping)(struct xgbe_prv_data *); 682 int (*enable_rx_vlan_filtering)(struct xgbe_prv_data *); 683 int (*disable_rx_vlan_filtering)(struct xgbe_prv_data *); 684 int (*update_vlan_hash_table)(struct xgbe_prv_data *); 685 686 int (*read_mmd_regs)(struct xgbe_prv_data *, int, int); 687 void (*write_mmd_regs)(struct xgbe_prv_data *, int, int, int); 688 int (*set_speed)(struct xgbe_prv_data *, int); 689 690 int (*set_ext_mii_mode)(struct xgbe_prv_data *, unsigned int, 691 enum xgbe_mdio_mode); 692 int (*read_ext_mii_regs)(struct xgbe_prv_data *, int, int); 693 int (*write_ext_mii_regs)(struct xgbe_prv_data *, int, int, u16); 694 695 int (*set_gpio)(struct xgbe_prv_data *, unsigned int); 696 int (*clr_gpio)(struct xgbe_prv_data *, unsigned int); 697 698 void (*enable_tx)(struct xgbe_prv_data *); 699 void (*disable_tx)(struct xgbe_prv_data *); 700 void (*enable_rx)(struct xgbe_prv_data *); 701 void (*disable_rx)(struct xgbe_prv_data *); 702 703 void (*powerup_tx)(struct xgbe_prv_data *); 704 void (*powerdown_tx)(struct xgbe_prv_data *); 705 void (*powerup_rx)(struct xgbe_prv_data *); 706 void (*powerdown_rx)(struct xgbe_prv_data *); 707 708 int (*init)(struct xgbe_prv_data *); 709 int (*exit)(struct xgbe_prv_data *); 710 711 int (*enable_int)(struct xgbe_channel *, enum xgbe_int); 712 int (*disable_int)(struct xgbe_channel *, enum xgbe_int); 713 void (*dev_xmit)(struct xgbe_channel *); 714 int (*dev_read)(struct xgbe_channel *); 715 void (*tx_desc_init)(struct xgbe_channel *); 716 void (*rx_desc_init)(struct xgbe_channel *); 717 void (*tx_desc_reset)(struct xgbe_ring_data *); 718 void (*rx_desc_reset)(struct xgbe_prv_data *, struct xgbe_ring_data *, 719 unsigned int); 720 int (*is_last_desc)(struct xgbe_ring_desc *); 721 int (*is_context_desc)(struct xgbe_ring_desc *); 722 void (*tx_start_xmit)(struct xgbe_channel *, struct xgbe_ring *); 723 724 /* For FLOW ctrl */ 725 int (*config_tx_flow_control)(struct xgbe_prv_data *); 726 int (*config_rx_flow_control)(struct xgbe_prv_data *); 727 728 /* For RX coalescing */ 729 int (*config_rx_coalesce)(struct xgbe_prv_data *); 730 int (*config_tx_coalesce)(struct xgbe_prv_data *); 731 unsigned int (*usec_to_riwt)(struct xgbe_prv_data *, unsigned int); 732 unsigned int (*riwt_to_usec)(struct xgbe_prv_data *, unsigned int); 733 734 /* For RX and TX threshold config */ 735 int (*config_rx_threshold)(struct xgbe_prv_data *, unsigned int); 736 int (*config_tx_threshold)(struct xgbe_prv_data *, unsigned int); 737 738 /* For RX and TX Store and Forward Mode config */ 739 int (*config_rsf_mode)(struct xgbe_prv_data *, unsigned int); 740 int (*config_tsf_mode)(struct xgbe_prv_data *, unsigned int); 741 742 /* For TX DMA Operate on Second Frame config */ 743 int (*config_osp_mode)(struct xgbe_prv_data *); 744 745 /* For MMC statistics */ 746 void (*rx_mmc_int)(struct xgbe_prv_data *); 747 void (*tx_mmc_int)(struct xgbe_prv_data *); 748 void (*read_mmc_stats)(struct xgbe_prv_data *); 749 750 /* For Timestamp config */ 751 int (*config_tstamp)(struct xgbe_prv_data *, unsigned int); 752 void (*update_tstamp_addend)(struct xgbe_prv_data *, unsigned int); 753 void (*set_tstamp_time)(struct xgbe_prv_data *, unsigned int sec, 754 unsigned int nsec); 755 u64 (*get_tstamp_time)(struct xgbe_prv_data *); 756 u64 (*get_tx_tstamp)(struct xgbe_prv_data *); 757 758 /* For Data Center Bridging config */ 759 void (*config_tc)(struct xgbe_prv_data *); 760 void (*config_dcb_tc)(struct xgbe_prv_data *); 761 void (*config_dcb_pfc)(struct xgbe_prv_data *); 762 763 /* For Receive Side Scaling */ 764 int (*enable_rss)(struct xgbe_prv_data *); 765 int (*disable_rss)(struct xgbe_prv_data *); 766 int (*set_rss_hash_key)(struct xgbe_prv_data *, const u8 *); 767 int (*set_rss_lookup_table)(struct xgbe_prv_data *, const u32 *); 768 769 /* For ECC */ 770 void (*disable_ecc_ded)(struct xgbe_prv_data *); 771 void (*disable_ecc_sec)(struct xgbe_prv_data *, enum xgbe_ecc_sec); 772 }; 773 774 /* This structure represents implementation specific routines for an 775 * implementation of a PHY. All routines are required unless noted below. 776 * Optional routines: 777 * kr_training_pre, kr_training_post 778 */ 779 struct xgbe_phy_impl_if { 780 /* Perform Setup/teardown actions */ 781 int (*init)(struct xgbe_prv_data *); 782 void (*exit)(struct xgbe_prv_data *); 783 784 /* Perform start/stop specific actions */ 785 int (*reset)(struct xgbe_prv_data *); 786 int (*start)(struct xgbe_prv_data *); 787 void (*stop)(struct xgbe_prv_data *); 788 789 /* Return the link status */ 790 int (*link_status)(struct xgbe_prv_data *, int *); 791 792 /* Indicate if a particular speed is valid */ 793 bool (*valid_speed)(struct xgbe_prv_data *, int); 794 795 /* Check if the specified mode can/should be used */ 796 bool (*use_mode)(struct xgbe_prv_data *, enum xgbe_mode); 797 /* Switch the PHY into various modes */ 798 void (*set_mode)(struct xgbe_prv_data *, enum xgbe_mode); 799 /* Retrieve mode needed for a specific speed */ 800 enum xgbe_mode (*get_mode)(struct xgbe_prv_data *, int); 801 /* Retrieve new/next mode when trying to auto-negotiate */ 802 enum xgbe_mode (*switch_mode)(struct xgbe_prv_data *); 803 /* Retrieve current mode */ 804 enum xgbe_mode (*cur_mode)(struct xgbe_prv_data *); 805 806 /* Retrieve current auto-negotiation mode */ 807 enum xgbe_an_mode (*an_mode)(struct xgbe_prv_data *); 808 809 /* Configure auto-negotiation settings */ 810 int (*an_config)(struct xgbe_prv_data *); 811 812 /* Set/override auto-negotiation advertisement settings */ 813 unsigned int (*an_advertising)(struct xgbe_prv_data *); 814 815 /* Process results of auto-negotiation */ 816 enum xgbe_mode (*an_outcome)(struct xgbe_prv_data *); 817 818 /* Pre/Post KR training enablement support */ 819 void (*kr_training_pre)(struct xgbe_prv_data *); 820 void (*kr_training_post)(struct xgbe_prv_data *); 821 }; 822 823 struct xgbe_phy_if { 824 /* For PHY setup/teardown */ 825 int (*phy_init)(struct xgbe_prv_data *); 826 void (*phy_exit)(struct xgbe_prv_data *); 827 828 /* For PHY support when setting device up/down */ 829 int (*phy_reset)(struct xgbe_prv_data *); 830 int (*phy_start)(struct xgbe_prv_data *); 831 void (*phy_stop)(struct xgbe_prv_data *); 832 833 /* For PHY support while device is up */ 834 void (*phy_status)(struct xgbe_prv_data *); 835 int (*phy_config_aneg)(struct xgbe_prv_data *); 836 837 /* For PHY settings validation */ 838 bool (*phy_valid_speed)(struct xgbe_prv_data *, int); 839 840 /* For single interrupt support */ 841 irqreturn_t (*an_isr)(struct xgbe_prv_data *); 842 843 /* PHY implementation specific services */ 844 struct xgbe_phy_impl_if phy_impl; 845 }; 846 847 struct xgbe_i2c_if { 848 /* For initial I2C setup */ 849 int (*i2c_init)(struct xgbe_prv_data *); 850 851 /* For I2C support when setting device up/down */ 852 int (*i2c_start)(struct xgbe_prv_data *); 853 void (*i2c_stop)(struct xgbe_prv_data *); 854 855 /* For performing I2C operations */ 856 int (*i2c_xfer)(struct xgbe_prv_data *, struct xgbe_i2c_op *); 857 858 /* For single interrupt support */ 859 irqreturn_t (*i2c_isr)(struct xgbe_prv_data *); 860 }; 861 862 struct xgbe_desc_if { 863 int (*alloc_ring_resources)(struct xgbe_prv_data *); 864 void (*free_ring_resources)(struct xgbe_prv_data *); 865 int (*map_tx_skb)(struct xgbe_channel *, struct sk_buff *); 866 int (*map_rx_buffer)(struct xgbe_prv_data *, struct xgbe_ring *, 867 struct xgbe_ring_data *); 868 void (*unmap_rdata)(struct xgbe_prv_data *, struct xgbe_ring_data *); 869 void (*wrapper_tx_desc_init)(struct xgbe_prv_data *); 870 void (*wrapper_rx_desc_init)(struct xgbe_prv_data *); 871 }; 872 873 /* This structure contains flags that indicate what hardware features 874 * or configurations are present in the device. 875 */ 876 struct xgbe_hw_features { 877 /* HW Version */ 878 unsigned int version; 879 880 /* HW Feature Register0 */ 881 unsigned int gmii; /* 1000 Mbps support */ 882 unsigned int vlhash; /* VLAN Hash Filter */ 883 unsigned int sma; /* SMA(MDIO) Interface */ 884 unsigned int rwk; /* PMT remote wake-up packet */ 885 unsigned int mgk; /* PMT magic packet */ 886 unsigned int mmc; /* RMON module */ 887 unsigned int aoe; /* ARP Offload */ 888 unsigned int ts; /* IEEE 1588-2008 Advanced Timestamp */ 889 unsigned int eee; /* Energy Efficient Ethernet */ 890 unsigned int tx_coe; /* Tx Checksum Offload */ 891 unsigned int rx_coe; /* Rx Checksum Offload */ 892 unsigned int addn_mac; /* Additional MAC Addresses */ 893 unsigned int ts_src; /* Timestamp Source */ 894 unsigned int sa_vlan_ins; /* Source Address or VLAN Insertion */ 895 896 /* HW Feature Register1 */ 897 unsigned int rx_fifo_size; /* MTL Receive FIFO Size */ 898 unsigned int tx_fifo_size; /* MTL Transmit FIFO Size */ 899 unsigned int adv_ts_hi; /* Advance Timestamping High Word */ 900 unsigned int dma_width; /* DMA width */ 901 unsigned int dcb; /* DCB Feature */ 902 unsigned int sph; /* Split Header Feature */ 903 unsigned int tso; /* TCP Segmentation Offload */ 904 unsigned int dma_debug; /* DMA Debug Registers */ 905 unsigned int rss; /* Receive Side Scaling */ 906 unsigned int tc_cnt; /* Number of Traffic Classes */ 907 unsigned int hash_table_size; /* Hash Table Size */ 908 unsigned int l3l4_filter_num; /* Number of L3-L4 Filters */ 909 910 /* HW Feature Register2 */ 911 unsigned int rx_q_cnt; /* Number of MTL Receive Queues */ 912 unsigned int tx_q_cnt; /* Number of MTL Transmit Queues */ 913 unsigned int rx_ch_cnt; /* Number of DMA Receive Channels */ 914 unsigned int tx_ch_cnt; /* Number of DMA Transmit Channels */ 915 unsigned int pps_out_num; /* Number of PPS outputs */ 916 unsigned int aux_snap_num; /* Number of Aux snapshot inputs */ 917 }; 918 919 struct xgbe_version_data { 920 void (*init_function_ptrs_phy_impl)(struct xgbe_phy_if *); 921 enum xgbe_xpcs_access xpcs_access; 922 unsigned int mmc_64bit; 923 unsigned int tx_max_fifo_size; 924 unsigned int rx_max_fifo_size; 925 unsigned int tx_tstamp_workaround; 926 unsigned int ecc_support; 927 unsigned int i2c_support; 928 unsigned int irq_reissue_support; 929 unsigned int tx_desc_prefetch; 930 unsigned int rx_desc_prefetch; 931 }; 932 933 struct xgbe_prv_data { 934 struct net_device *netdev; 935 struct pci_dev *pcidev; 936 struct platform_device *platdev; 937 struct acpi_device *adev; 938 struct device *dev; 939 struct platform_device *phy_platdev; 940 struct device *phy_dev; 941 942 /* Version related data */ 943 struct xgbe_version_data *vdata; 944 945 /* ACPI or DT flag */ 946 unsigned int use_acpi; 947 948 /* XGMAC/XPCS related mmio registers */ 949 void __iomem *xgmac_regs; /* XGMAC CSRs */ 950 void __iomem *xpcs_regs; /* XPCS MMD registers */ 951 void __iomem *rxtx_regs; /* SerDes Rx/Tx CSRs */ 952 void __iomem *sir0_regs; /* SerDes integration registers (1/2) */ 953 void __iomem *sir1_regs; /* SerDes integration registers (2/2) */ 954 void __iomem *xprop_regs; /* XGBE property registers */ 955 void __iomem *xi2c_regs; /* XGBE I2C CSRs */ 956 957 /* Overall device lock */ 958 spinlock_t lock; 959 960 /* XPCS indirect addressing lock */ 961 spinlock_t xpcs_lock; 962 unsigned int xpcs_window_def_reg; 963 unsigned int xpcs_window_sel_reg; 964 unsigned int xpcs_window; 965 unsigned int xpcs_window_size; 966 unsigned int xpcs_window_mask; 967 968 /* RSS addressing mutex */ 969 struct mutex rss_mutex; 970 971 /* Flags representing xgbe_state */ 972 unsigned long dev_state; 973 974 /* ECC support */ 975 unsigned long tx_sec_period; 976 unsigned long tx_ded_period; 977 unsigned long rx_sec_period; 978 unsigned long rx_ded_period; 979 unsigned long desc_sec_period; 980 unsigned long desc_ded_period; 981 982 unsigned int tx_sec_count; 983 unsigned int tx_ded_count; 984 unsigned int rx_sec_count; 985 unsigned int rx_ded_count; 986 unsigned int desc_ded_count; 987 unsigned int desc_sec_count; 988 989 int dev_irq; 990 int ecc_irq; 991 int i2c_irq; 992 int channel_irq[XGBE_MAX_DMA_CHANNELS]; 993 994 unsigned int per_channel_irq; 995 unsigned int irq_count; 996 unsigned int channel_irq_count; 997 unsigned int channel_irq_mode; 998 999 char ecc_name[IFNAMSIZ + 32]; 1000 1001 struct xgbe_hw_if hw_if; 1002 struct xgbe_phy_if phy_if; 1003 struct xgbe_desc_if desc_if; 1004 struct xgbe_i2c_if i2c_if; 1005 1006 /* AXI DMA settings */ 1007 unsigned int coherent; 1008 unsigned int arcr; 1009 unsigned int awcr; 1010 unsigned int awarcr; 1011 1012 /* Service routine support */ 1013 struct workqueue_struct *dev_workqueue; 1014 struct work_struct service_work; 1015 struct timer_list service_timer; 1016 1017 /* Rings for Tx/Rx on a DMA channel */ 1018 struct xgbe_channel *channel[XGBE_MAX_DMA_CHANNELS]; 1019 unsigned int tx_max_channel_count; 1020 unsigned int rx_max_channel_count; 1021 unsigned int channel_count; 1022 unsigned int tx_ring_count; 1023 unsigned int tx_desc_count; 1024 unsigned int rx_ring_count; 1025 unsigned int rx_desc_count; 1026 1027 unsigned int tx_max_q_count; 1028 unsigned int rx_max_q_count; 1029 unsigned int tx_q_count; 1030 unsigned int rx_q_count; 1031 1032 /* Tx/Rx common settings */ 1033 unsigned int blen; 1034 unsigned int pbl; 1035 unsigned int aal; 1036 unsigned int rd_osr_limit; 1037 unsigned int wr_osr_limit; 1038 1039 /* Tx settings */ 1040 unsigned int tx_sf_mode; 1041 unsigned int tx_threshold; 1042 unsigned int tx_osp_mode; 1043 unsigned int tx_max_fifo_size; 1044 1045 /* Rx settings */ 1046 unsigned int rx_sf_mode; 1047 unsigned int rx_threshold; 1048 unsigned int rx_max_fifo_size; 1049 1050 /* Tx coalescing settings */ 1051 unsigned int tx_usecs; 1052 unsigned int tx_frames; 1053 1054 /* Rx coalescing settings */ 1055 unsigned int rx_riwt; 1056 unsigned int rx_usecs; 1057 unsigned int rx_frames; 1058 1059 /* Current Rx buffer size */ 1060 unsigned int rx_buf_size; 1061 1062 /* Flow control settings */ 1063 unsigned int pause_autoneg; 1064 unsigned int tx_pause; 1065 unsigned int rx_pause; 1066 unsigned int rx_rfa[XGBE_MAX_QUEUES]; 1067 unsigned int rx_rfd[XGBE_MAX_QUEUES]; 1068 1069 /* Receive Side Scaling settings */ 1070 u8 rss_key[XGBE_RSS_HASH_KEY_SIZE]; 1071 u32 rss_table[XGBE_RSS_MAX_TABLE_SIZE]; 1072 u32 rss_options; 1073 1074 /* Netdev related settings */ 1075 unsigned char mac_addr[ETH_ALEN]; 1076 netdev_features_t netdev_features; 1077 struct napi_struct napi; 1078 struct xgbe_mmc_stats mmc_stats; 1079 struct xgbe_ext_stats ext_stats; 1080 1081 /* Filtering support */ 1082 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 1083 1084 /* Device clocks */ 1085 struct clk *sysclk; 1086 unsigned long sysclk_rate; 1087 struct clk *ptpclk; 1088 unsigned long ptpclk_rate; 1089 1090 /* Timestamp support */ 1091 spinlock_t tstamp_lock; 1092 struct ptp_clock_info ptp_clock_info; 1093 struct ptp_clock *ptp_clock; 1094 struct hwtstamp_config tstamp_config; 1095 struct cyclecounter tstamp_cc; 1096 struct timecounter tstamp_tc; 1097 unsigned int tstamp_addend; 1098 struct work_struct tx_tstamp_work; 1099 struct sk_buff *tx_tstamp_skb; 1100 u64 tx_tstamp; 1101 1102 /* DCB support */ 1103 struct ieee_ets *ets; 1104 struct ieee_pfc *pfc; 1105 unsigned int q2tc_map[XGBE_MAX_QUEUES]; 1106 unsigned int prio2q_map[IEEE_8021QAZ_MAX_TCS]; 1107 unsigned int pfcq[XGBE_MAX_QUEUES]; 1108 unsigned int pfc_rfa; 1109 u8 num_tcs; 1110 1111 /* Hardware features of the device */ 1112 struct xgbe_hw_features hw_feat; 1113 1114 /* Device work structures */ 1115 struct work_struct restart_work; 1116 struct work_struct stopdev_work; 1117 1118 /* Keeps track of power mode */ 1119 unsigned int power_down; 1120 1121 /* Network interface message level setting */ 1122 u32 msg_enable; 1123 1124 /* Current PHY settings */ 1125 phy_interface_t phy_mode; 1126 int phy_link; 1127 int phy_speed; 1128 1129 /* MDIO/PHY related settings */ 1130 unsigned int phy_started; 1131 void *phy_data; 1132 struct xgbe_phy phy; 1133 int mdio_mmd; 1134 unsigned long link_check; 1135 struct completion mdio_complete; 1136 1137 unsigned int kr_redrv; 1138 1139 char an_name[IFNAMSIZ + 32]; 1140 struct workqueue_struct *an_workqueue; 1141 1142 int an_irq; 1143 struct work_struct an_irq_work; 1144 1145 /* Auto-negotiation state machine support */ 1146 unsigned int an_int; 1147 unsigned int an_status; 1148 struct mutex an_mutex; 1149 enum xgbe_an an_result; 1150 enum xgbe_an an_state; 1151 enum xgbe_rx kr_state; 1152 enum xgbe_rx kx_state; 1153 struct work_struct an_work; 1154 unsigned int an_supported; 1155 unsigned int parallel_detect; 1156 unsigned int fec_ability; 1157 unsigned long an_start; 1158 enum xgbe_an_mode an_mode; 1159 1160 /* I2C support */ 1161 struct xgbe_i2c i2c; 1162 struct mutex i2c_mutex; 1163 struct completion i2c_complete; 1164 char i2c_name[IFNAMSIZ + 32]; 1165 1166 unsigned int lpm_ctrl; /* CTRL1 for resume */ 1167 1168 unsigned int isr_as_tasklet; 1169 struct tasklet_struct tasklet_dev; 1170 struct tasklet_struct tasklet_ecc; 1171 struct tasklet_struct tasklet_i2c; 1172 struct tasklet_struct tasklet_an; 1173 1174 #ifdef CONFIG_DEBUG_FS 1175 struct dentry *xgbe_debugfs; 1176 1177 unsigned int debugfs_xgmac_reg; 1178 1179 unsigned int debugfs_xpcs_mmd; 1180 unsigned int debugfs_xpcs_reg; 1181 1182 unsigned int debugfs_xprop_reg; 1183 1184 unsigned int debugfs_xi2c_reg; 1185 #endif 1186 }; 1187 1188 /* Function prototypes*/ 1189 struct xgbe_prv_data *xgbe_alloc_pdata(struct device *); 1190 void xgbe_free_pdata(struct xgbe_prv_data *); 1191 void xgbe_set_counts(struct xgbe_prv_data *); 1192 int xgbe_config_netdev(struct xgbe_prv_data *); 1193 void xgbe_deconfig_netdev(struct xgbe_prv_data *); 1194 1195 int xgbe_platform_init(void); 1196 void xgbe_platform_exit(void); 1197 #ifdef CONFIG_PCI 1198 int xgbe_pci_init(void); 1199 void xgbe_pci_exit(void); 1200 #else 1201 static inline int xgbe_pci_init(void) { return 0; } 1202 static inline void xgbe_pci_exit(void) { } 1203 #endif 1204 1205 void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *); 1206 void xgbe_init_function_ptrs_phy(struct xgbe_phy_if *); 1207 void xgbe_init_function_ptrs_phy_v1(struct xgbe_phy_if *); 1208 void xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if *); 1209 void xgbe_init_function_ptrs_desc(struct xgbe_desc_if *); 1210 void xgbe_init_function_ptrs_i2c(struct xgbe_i2c_if *); 1211 const struct net_device_ops *xgbe_get_netdev_ops(void); 1212 const struct ethtool_ops *xgbe_get_ethtool_ops(void); 1213 1214 #ifdef CONFIG_AMD_XGBE_DCB 1215 const struct dcbnl_rtnl_ops *xgbe_get_dcbnl_ops(void); 1216 #endif 1217 1218 void xgbe_ptp_register(struct xgbe_prv_data *); 1219 void xgbe_ptp_unregister(struct xgbe_prv_data *); 1220 void xgbe_dump_tx_desc(struct xgbe_prv_data *, struct xgbe_ring *, 1221 unsigned int, unsigned int, unsigned int); 1222 void xgbe_dump_rx_desc(struct xgbe_prv_data *, struct xgbe_ring *, 1223 unsigned int); 1224 void xgbe_print_pkt(struct net_device *, struct sk_buff *, bool); 1225 void xgbe_get_all_hw_features(struct xgbe_prv_data *); 1226 int xgbe_powerup(struct net_device *, unsigned int); 1227 int xgbe_powerdown(struct net_device *, unsigned int); 1228 void xgbe_init_rx_coalesce(struct xgbe_prv_data *); 1229 void xgbe_init_tx_coalesce(struct xgbe_prv_data *); 1230 1231 #ifdef CONFIG_DEBUG_FS 1232 void xgbe_debugfs_init(struct xgbe_prv_data *); 1233 void xgbe_debugfs_exit(struct xgbe_prv_data *); 1234 #else 1235 static inline void xgbe_debugfs_init(struct xgbe_prv_data *pdata) {} 1236 static inline void xgbe_debugfs_exit(struct xgbe_prv_data *pdata) {} 1237 #endif /* CONFIG_DEBUG_FS */ 1238 1239 /* NOTE: Uncomment for function trace log messages in KERNEL LOG */ 1240 #if 0 1241 #define YDEBUG 1242 #define YDEBUG_MDIO 1243 #endif 1244 1245 /* For debug prints */ 1246 #ifdef YDEBUG 1247 #define DBGPR(x...) pr_alert(x) 1248 #else 1249 #define DBGPR(x...) do { } while (0) 1250 #endif 1251 1252 #ifdef YDEBUG_MDIO 1253 #define DBGPR_MDIO(x...) pr_alert(x) 1254 #else 1255 #define DBGPR_MDIO(x...) do { } while (0) 1256 #endif 1257 1258 #endif 1259