xref: /openbmc/linux/drivers/net/ethernet/amd/xgbe/xgbe.h (revision c819e2cf)
1 /*
2  * AMD 10Gb Ethernet driver
3  *
4  * This file is available to you under your choice of the following two
5  * licenses:
6  *
7  * License 1: GPLv2
8  *
9  * Copyright (c) 2014 Advanced Micro Devices, Inc.
10  *
11  * This file is free software; you may copy, redistribute and/or modify
12  * it under the terms of the GNU General Public License as published by
13  * the Free Software Foundation, either version 2 of the License, or (at
14  * your option) any later version.
15  *
16  * This file is distributed in the hope that it will be useful, but
17  * WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19  * General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
23  *
24  * This file incorporates work covered by the following copyright and
25  * permission notice:
26  *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
27  *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28  *     Inc. unless otherwise expressly agreed to in writing between Synopsys
29  *     and you.
30  *
31  *     The Software IS NOT an item of Licensed Software or Licensed Product
32  *     under any End User Software License Agreement or Agreement for Licensed
33  *     Product with Synopsys or any supplement thereto.  Permission is hereby
34  *     granted, free of charge, to any person obtaining a copy of this software
35  *     annotated with this license and the Software, to deal in the Software
36  *     without restriction, including without limitation the rights to use,
37  *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38  *     of the Software, and to permit persons to whom the Software is furnished
39  *     to do so, subject to the following conditions:
40  *
41  *     The above copyright notice and this permission notice shall be included
42  *     in all copies or substantial portions of the Software.
43  *
44  *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45  *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46  *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47  *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48  *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49  *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50  *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51  *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52  *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53  *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54  *     THE POSSIBILITY OF SUCH DAMAGE.
55  *
56  *
57  * License 2: Modified BSD
58  *
59  * Copyright (c) 2014 Advanced Micro Devices, Inc.
60  * All rights reserved.
61  *
62  * Redistribution and use in source and binary forms, with or without
63  * modification, are permitted provided that the following conditions are met:
64  *     * Redistributions of source code must retain the above copyright
65  *       notice, this list of conditions and the following disclaimer.
66  *     * Redistributions in binary form must reproduce the above copyright
67  *       notice, this list of conditions and the following disclaimer in the
68  *       documentation and/or other materials provided with the distribution.
69  *     * Neither the name of Advanced Micro Devices, Inc. nor the
70  *       names of its contributors may be used to endorse or promote products
71  *       derived from this software without specific prior written permission.
72  *
73  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76  * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
83  *
84  * This file incorporates work covered by the following copyright and
85  * permission notice:
86  *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
87  *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88  *     Inc. unless otherwise expressly agreed to in writing between Synopsys
89  *     and you.
90  *
91  *     The Software IS NOT an item of Licensed Software or Licensed Product
92  *     under any End User Software License Agreement or Agreement for Licensed
93  *     Product with Synopsys or any supplement thereto.  Permission is hereby
94  *     granted, free of charge, to any person obtaining a copy of this software
95  *     annotated with this license and the Software, to deal in the Software
96  *     without restriction, including without limitation the rights to use,
97  *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98  *     of the Software, and to permit persons to whom the Software is furnished
99  *     to do so, subject to the following conditions:
100  *
101  *     The above copyright notice and this permission notice shall be included
102  *     in all copies or substantial portions of the Software.
103  *
104  *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105  *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106  *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107  *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108  *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109  *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110  *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111  *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112  *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113  *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114  *     THE POSSIBILITY OF SUCH DAMAGE.
115  */
116 
117 #ifndef __XGBE_H__
118 #define __XGBE_H__
119 
120 #include <linux/dma-mapping.h>
121 #include <linux/netdevice.h>
122 #include <linux/workqueue.h>
123 #include <linux/phy.h>
124 #include <linux/if_vlan.h>
125 #include <linux/bitops.h>
126 #include <linux/ptp_clock_kernel.h>
127 #include <linux/clocksource.h>
128 #include <linux/net_tstamp.h>
129 #include <net/dcbnl.h>
130 
131 #define XGBE_DRV_NAME		"amd-xgbe"
132 #define XGBE_DRV_VERSION	"1.0.0-a"
133 #define XGBE_DRV_DESC		"AMD 10 Gigabit Ethernet Driver"
134 
135 /* Descriptor related defines */
136 #define XGBE_TX_DESC_CNT	512
137 #define XGBE_TX_DESC_MIN_FREE	(XGBE_TX_DESC_CNT >> 3)
138 #define XGBE_TX_DESC_MAX_PROC	(XGBE_TX_DESC_CNT >> 1)
139 #define XGBE_RX_DESC_CNT	512
140 
141 #define XGBE_TX_MAX_BUF_SIZE	(0x3fff & ~(64 - 1))
142 
143 /* Descriptors required for maximum contigous TSO/GSO packet */
144 #define XGBE_TX_MAX_SPLIT	((GSO_MAX_SIZE / XGBE_TX_MAX_BUF_SIZE) + 1)
145 
146 /* Maximum possible descriptors needed for an SKB:
147  * - Maximum number of SKB frags
148  * - Maximum descriptors for contiguous TSO/GSO packet
149  * - Possible context descriptor
150  * - Possible TSO header descriptor
151  */
152 #define XGBE_TX_MAX_DESCS	(MAX_SKB_FRAGS + XGBE_TX_MAX_SPLIT + 2)
153 
154 #define XGBE_RX_MIN_BUF_SIZE	(ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
155 #define XGBE_RX_BUF_ALIGN	64
156 #define XGBE_SKB_ALLOC_SIZE	256
157 #define XGBE_SPH_HDSMS_SIZE	2	/* Keep in sync with SKB_ALLOC_SIZE */
158 
159 #define XGBE_MAX_DMA_CHANNELS	16
160 #define XGBE_MAX_QUEUES		16
161 #define XGBE_DMA_STOP_TIMEOUT	5
162 
163 /* DMA cache settings - Outer sharable, write-back, write-allocate */
164 #define XGBE_DMA_OS_AXDOMAIN	0x2
165 #define XGBE_DMA_OS_ARCACHE	0xb
166 #define XGBE_DMA_OS_AWCACHE	0xf
167 
168 /* DMA cache settings - System, no caches used */
169 #define XGBE_DMA_SYS_AXDOMAIN	0x3
170 #define XGBE_DMA_SYS_ARCACHE	0x0
171 #define XGBE_DMA_SYS_AWCACHE	0x0
172 
173 #define XGBE_DMA_INTERRUPT_MASK	0x31c7
174 
175 #define XGMAC_MIN_PACKET	60
176 #define XGMAC_STD_PACKET_MTU	1500
177 #define XGMAC_MAX_STD_PACKET	1518
178 #define XGMAC_JUMBO_PACKET_MTU	9000
179 #define XGMAC_MAX_JUMBO_PACKET	9018
180 
181 /* MDIO bus phy name */
182 #define XGBE_PHY_NAME		"amd_xgbe_phy"
183 #define XGBE_PRTAD		0
184 
185 /* Device-tree clock names */
186 #define XGBE_DMA_CLOCK		"dma_clk"
187 #define XGBE_PTP_CLOCK		"ptp_clk"
188 #define XGBE_DMA_IRQS		"amd,per-channel-interrupt"
189 
190 /* Timestamp support - values based on 50MHz PTP clock
191  *   50MHz => 20 nsec
192  */
193 #define XGBE_TSTAMP_SSINC	20
194 #define XGBE_TSTAMP_SNSINC	0
195 
196 /* Driver PMT macros */
197 #define XGMAC_DRIVER_CONTEXT	1
198 #define XGMAC_IOCTL_CONTEXT	2
199 
200 #define XGBE_FIFO_MAX		81920
201 #define XGBE_FIFO_SIZE_B(x)	(x)
202 #define XGBE_FIFO_SIZE_KB(x)	(x * 1024)
203 
204 #define XGBE_TC_MIN_QUANTUM	10
205 
206 /* Helper macro for descriptor handling
207  *  Always use XGBE_GET_DESC_DATA to access the descriptor data
208  *  since the index is free-running and needs to be and-ed
209  *  with the descriptor count value of the ring to index to
210  *  the proper descriptor data.
211  */
212 #define XGBE_GET_DESC_DATA(_ring, _idx)				\
213 	((_ring)->rdata +					\
214 	 ((_idx) & ((_ring)->rdesc_count - 1)))
215 
216 /* Default coalescing parameters */
217 #define XGMAC_INIT_DMA_TX_USECS		50
218 #define XGMAC_INIT_DMA_TX_FRAMES	25
219 
220 #define XGMAC_MAX_DMA_RIWT		0xff
221 #define XGMAC_INIT_DMA_RX_USECS		30
222 #define XGMAC_INIT_DMA_RX_FRAMES	25
223 
224 /* Flow control queue count */
225 #define XGMAC_MAX_FLOW_CONTROL_QUEUES	8
226 
227 /* Maximum MAC address hash table size (256 bits = 8 bytes) */
228 #define XGBE_MAC_HASH_TABLE_SIZE	8
229 
230 /* Receive Side Scaling */
231 #define XGBE_RSS_HASH_KEY_SIZE		40
232 #define XGBE_RSS_MAX_TABLE_SIZE		256
233 #define XGBE_RSS_LOOKUP_TABLE_TYPE	0
234 #define XGBE_RSS_HASH_KEY_TYPE		1
235 
236 struct xgbe_prv_data;
237 
238 struct xgbe_packet_data {
239 	struct sk_buff *skb;
240 
241 	unsigned int attributes;
242 
243 	unsigned int errors;
244 
245 	unsigned int rdesc_count;
246 	unsigned int length;
247 
248 	unsigned int header_len;
249 	unsigned int tcp_header_len;
250 	unsigned int tcp_payload_len;
251 	unsigned short mss;
252 
253 	unsigned short vlan_ctag;
254 
255 	u64 rx_tstamp;
256 
257 	u32 rss_hash;
258 	enum pkt_hash_types rss_hash_type;
259 
260 	unsigned int tx_packets;
261 	unsigned int tx_bytes;
262 };
263 
264 /* Common Rx and Tx descriptor mapping */
265 struct xgbe_ring_desc {
266 	__le32 desc0;
267 	__le32 desc1;
268 	__le32 desc2;
269 	__le32 desc3;
270 };
271 
272 /* Page allocation related values */
273 struct xgbe_page_alloc {
274 	struct page *pages;
275 	unsigned int pages_len;
276 	unsigned int pages_offset;
277 
278 	dma_addr_t pages_dma;
279 };
280 
281 /* Ring entry buffer data */
282 struct xgbe_buffer_data {
283 	struct xgbe_page_alloc pa;
284 	struct xgbe_page_alloc pa_unmap;
285 
286 	dma_addr_t dma;
287 	unsigned int dma_len;
288 };
289 
290 /* Tx-related ring data */
291 struct xgbe_tx_ring_data {
292 	unsigned int packets;		/* BQL packet count */
293 	unsigned int bytes;		/* BQL byte count */
294 };
295 
296 /* Rx-related ring data */
297 struct xgbe_rx_ring_data {
298 	struct xgbe_buffer_data hdr;	/* Header locations */
299 	struct xgbe_buffer_data buf;	/* Payload locations */
300 
301 	unsigned short hdr_len;		/* Length of received header */
302 	unsigned short len;		/* Length of received packet */
303 };
304 
305 /* Structure used to hold information related to the descriptor
306  * and the packet associated with the descriptor (always use
307  * use the XGBE_GET_DESC_DATA macro to access this data from the ring)
308  */
309 struct xgbe_ring_data {
310 	struct xgbe_ring_desc *rdesc;	/* Virtual address of descriptor */
311 	dma_addr_t rdesc_dma;		/* DMA address of descriptor */
312 
313 	struct sk_buff *skb;		/* Virtual address of SKB */
314 	dma_addr_t skb_dma;		/* DMA address of SKB data */
315 	unsigned int skb_dma_len;	/* Length of SKB DMA area */
316 
317 	struct xgbe_tx_ring_data tx;	/* Tx-related data */
318 	struct xgbe_rx_ring_data rx;	/* Rx-related data */
319 
320 	unsigned int interrupt;		/* Interrupt indicator */
321 
322 	unsigned int mapped_as_page;
323 
324 	/* Incomplete receive save location.  If the budget is exhausted
325 	 * or the last descriptor (last normal descriptor or a following
326 	 * context descriptor) has not been DMA'd yet the current state
327 	 * of the receive processing needs to be saved.
328 	 */
329 	unsigned int state_saved;
330 	struct {
331 		unsigned int incomplete;
332 		unsigned int context_next;
333 		struct sk_buff *skb;
334 		unsigned int len;
335 		unsigned int error;
336 	} state;
337 };
338 
339 struct xgbe_ring {
340 	/* Ring lock - used just for TX rings at the moment */
341 	spinlock_t lock;
342 
343 	/* Per packet related information */
344 	struct xgbe_packet_data packet_data;
345 
346 	/* Virtual/DMA addresses and count of allocated descriptor memory */
347 	struct xgbe_ring_desc *rdesc;
348 	dma_addr_t rdesc_dma;
349 	unsigned int rdesc_count;
350 
351 	/* Array of descriptor data corresponding the descriptor memory
352 	 * (always use the XGBE_GET_DESC_DATA macro to access this data)
353 	 */
354 	struct xgbe_ring_data *rdata;
355 
356 	/* Page allocation for RX buffers */
357 	struct xgbe_page_alloc rx_hdr_pa;
358 	struct xgbe_page_alloc rx_buf_pa;
359 
360 	/* Ring index values
361 	 *  cur   - Tx: index of descriptor to be used for current transfer
362 	 *          Rx: index of descriptor to check for packet availability
363 	 *  dirty - Tx: index of descriptor to check for transfer complete
364 	 *          Rx: count of descriptors in which a packet has been received
365 	 *              (used with skb_realloc_index to refresh the ring)
366 	 */
367 	unsigned int cur;
368 	unsigned int dirty;
369 
370 	/* Coalesce frame count used for interrupt bit setting */
371 	unsigned int coalesce_count;
372 
373 	union {
374 		struct {
375 			unsigned int queue_stopped;
376 			unsigned int xmit_more;
377 			unsigned short cur_mss;
378 			unsigned short cur_vlan_ctag;
379 		} tx;
380 
381 		struct {
382 			unsigned int realloc_index;
383 			unsigned int realloc_threshold;
384 		} rx;
385 	};
386 } ____cacheline_aligned;
387 
388 /* Structure used to describe the descriptor rings associated with
389  * a DMA channel.
390  */
391 struct xgbe_channel {
392 	char name[16];
393 
394 	/* Address of private data area for device */
395 	struct xgbe_prv_data *pdata;
396 
397 	/* Queue index and base address of queue's DMA registers */
398 	unsigned int queue_index;
399 	void __iomem *dma_regs;
400 
401 	/* Per channel interrupt irq number */
402 	int dma_irq;
403 	char dma_irq_name[IFNAMSIZ + 32];
404 
405 	/* Netdev related settings */
406 	struct napi_struct napi;
407 
408 	unsigned int saved_ier;
409 
410 	unsigned int tx_timer_active;
411 	struct hrtimer tx_timer;
412 
413 	struct xgbe_ring *tx_ring;
414 	struct xgbe_ring *rx_ring;
415 } ____cacheline_aligned;
416 
417 enum xgbe_int {
418 	XGMAC_INT_DMA_CH_SR_TI,
419 	XGMAC_INT_DMA_CH_SR_TPS,
420 	XGMAC_INT_DMA_CH_SR_TBU,
421 	XGMAC_INT_DMA_CH_SR_RI,
422 	XGMAC_INT_DMA_CH_SR_RBU,
423 	XGMAC_INT_DMA_CH_SR_RPS,
424 	XGMAC_INT_DMA_CH_SR_TI_RI,
425 	XGMAC_INT_DMA_CH_SR_FBE,
426 	XGMAC_INT_DMA_ALL,
427 };
428 
429 enum xgbe_int_state {
430 	XGMAC_INT_STATE_SAVE,
431 	XGMAC_INT_STATE_RESTORE,
432 };
433 
434 enum xgbe_mtl_fifo_size {
435 	XGMAC_MTL_FIFO_SIZE_256  = 0x00,
436 	XGMAC_MTL_FIFO_SIZE_512  = 0x01,
437 	XGMAC_MTL_FIFO_SIZE_1K   = 0x03,
438 	XGMAC_MTL_FIFO_SIZE_2K   = 0x07,
439 	XGMAC_MTL_FIFO_SIZE_4K   = 0x0f,
440 	XGMAC_MTL_FIFO_SIZE_8K   = 0x1f,
441 	XGMAC_MTL_FIFO_SIZE_16K  = 0x3f,
442 	XGMAC_MTL_FIFO_SIZE_32K  = 0x7f,
443 	XGMAC_MTL_FIFO_SIZE_64K  = 0xff,
444 	XGMAC_MTL_FIFO_SIZE_128K = 0x1ff,
445 	XGMAC_MTL_FIFO_SIZE_256K = 0x3ff,
446 };
447 
448 struct xgbe_mmc_stats {
449 	/* Tx Stats */
450 	u64 txoctetcount_gb;
451 	u64 txframecount_gb;
452 	u64 txbroadcastframes_g;
453 	u64 txmulticastframes_g;
454 	u64 tx64octets_gb;
455 	u64 tx65to127octets_gb;
456 	u64 tx128to255octets_gb;
457 	u64 tx256to511octets_gb;
458 	u64 tx512to1023octets_gb;
459 	u64 tx1024tomaxoctets_gb;
460 	u64 txunicastframes_gb;
461 	u64 txmulticastframes_gb;
462 	u64 txbroadcastframes_gb;
463 	u64 txunderflowerror;
464 	u64 txoctetcount_g;
465 	u64 txframecount_g;
466 	u64 txpauseframes;
467 	u64 txvlanframes_g;
468 
469 	/* Rx Stats */
470 	u64 rxframecount_gb;
471 	u64 rxoctetcount_gb;
472 	u64 rxoctetcount_g;
473 	u64 rxbroadcastframes_g;
474 	u64 rxmulticastframes_g;
475 	u64 rxcrcerror;
476 	u64 rxrunterror;
477 	u64 rxjabbererror;
478 	u64 rxundersize_g;
479 	u64 rxoversize_g;
480 	u64 rx64octets_gb;
481 	u64 rx65to127octets_gb;
482 	u64 rx128to255octets_gb;
483 	u64 rx256to511octets_gb;
484 	u64 rx512to1023octets_gb;
485 	u64 rx1024tomaxoctets_gb;
486 	u64 rxunicastframes_g;
487 	u64 rxlengtherror;
488 	u64 rxoutofrangetype;
489 	u64 rxpauseframes;
490 	u64 rxfifooverflow;
491 	u64 rxvlanframes_gb;
492 	u64 rxwatchdogerror;
493 };
494 
495 struct xgbe_hw_if {
496 	int (*tx_complete)(struct xgbe_ring_desc *);
497 
498 	int (*set_promiscuous_mode)(struct xgbe_prv_data *, unsigned int);
499 	int (*set_all_multicast_mode)(struct xgbe_prv_data *, unsigned int);
500 	int (*add_mac_addresses)(struct xgbe_prv_data *);
501 	int (*set_mac_address)(struct xgbe_prv_data *, u8 *addr);
502 
503 	int (*enable_rx_csum)(struct xgbe_prv_data *);
504 	int (*disable_rx_csum)(struct xgbe_prv_data *);
505 
506 	int (*enable_rx_vlan_stripping)(struct xgbe_prv_data *);
507 	int (*disable_rx_vlan_stripping)(struct xgbe_prv_data *);
508 	int (*enable_rx_vlan_filtering)(struct xgbe_prv_data *);
509 	int (*disable_rx_vlan_filtering)(struct xgbe_prv_data *);
510 	int (*update_vlan_hash_table)(struct xgbe_prv_data *);
511 
512 	int (*read_mmd_regs)(struct xgbe_prv_data *, int, int);
513 	void (*write_mmd_regs)(struct xgbe_prv_data *, int, int, int);
514 	int (*set_gmii_speed)(struct xgbe_prv_data *);
515 	int (*set_gmii_2500_speed)(struct xgbe_prv_data *);
516 	int (*set_xgmii_speed)(struct xgbe_prv_data *);
517 
518 	void (*enable_tx)(struct xgbe_prv_data *);
519 	void (*disable_tx)(struct xgbe_prv_data *);
520 	void (*enable_rx)(struct xgbe_prv_data *);
521 	void (*disable_rx)(struct xgbe_prv_data *);
522 
523 	void (*powerup_tx)(struct xgbe_prv_data *);
524 	void (*powerdown_tx)(struct xgbe_prv_data *);
525 	void (*powerup_rx)(struct xgbe_prv_data *);
526 	void (*powerdown_rx)(struct xgbe_prv_data *);
527 
528 	int (*init)(struct xgbe_prv_data *);
529 	int (*exit)(struct xgbe_prv_data *);
530 
531 	int (*enable_int)(struct xgbe_channel *, enum xgbe_int);
532 	int (*disable_int)(struct xgbe_channel *, enum xgbe_int);
533 	void (*dev_xmit)(struct xgbe_channel *);
534 	int (*dev_read)(struct xgbe_channel *);
535 	void (*tx_desc_init)(struct xgbe_channel *);
536 	void (*rx_desc_init)(struct xgbe_channel *);
537 	void (*rx_desc_reset)(struct xgbe_ring_data *);
538 	void (*tx_desc_reset)(struct xgbe_ring_data *);
539 	int (*is_last_desc)(struct xgbe_ring_desc *);
540 	int (*is_context_desc)(struct xgbe_ring_desc *);
541 	void (*tx_start_xmit)(struct xgbe_channel *, struct xgbe_ring *);
542 
543 	/* For FLOW ctrl */
544 	int (*config_tx_flow_control)(struct xgbe_prv_data *);
545 	int (*config_rx_flow_control)(struct xgbe_prv_data *);
546 
547 	/* For RX coalescing */
548 	int (*config_rx_coalesce)(struct xgbe_prv_data *);
549 	int (*config_tx_coalesce)(struct xgbe_prv_data *);
550 	unsigned int (*usec_to_riwt)(struct xgbe_prv_data *, unsigned int);
551 	unsigned int (*riwt_to_usec)(struct xgbe_prv_data *, unsigned int);
552 
553 	/* For RX and TX threshold config */
554 	int (*config_rx_threshold)(struct xgbe_prv_data *, unsigned int);
555 	int (*config_tx_threshold)(struct xgbe_prv_data *, unsigned int);
556 
557 	/* For RX and TX Store and Forward Mode config */
558 	int (*config_rsf_mode)(struct xgbe_prv_data *, unsigned int);
559 	int (*config_tsf_mode)(struct xgbe_prv_data *, unsigned int);
560 
561 	/* For TX DMA Operate on Second Frame config */
562 	int (*config_osp_mode)(struct xgbe_prv_data *);
563 
564 	/* For RX and TX PBL config */
565 	int (*config_rx_pbl_val)(struct xgbe_prv_data *);
566 	int (*get_rx_pbl_val)(struct xgbe_prv_data *);
567 	int (*config_tx_pbl_val)(struct xgbe_prv_data *);
568 	int (*get_tx_pbl_val)(struct xgbe_prv_data *);
569 	int (*config_pblx8)(struct xgbe_prv_data *);
570 
571 	/* For MMC statistics */
572 	void (*rx_mmc_int)(struct xgbe_prv_data *);
573 	void (*tx_mmc_int)(struct xgbe_prv_data *);
574 	void (*read_mmc_stats)(struct xgbe_prv_data *);
575 
576 	/* For Timestamp config */
577 	int (*config_tstamp)(struct xgbe_prv_data *, unsigned int);
578 	void (*update_tstamp_addend)(struct xgbe_prv_data *, unsigned int);
579 	void (*set_tstamp_time)(struct xgbe_prv_data *, unsigned int sec,
580 				unsigned int nsec);
581 	u64 (*get_tstamp_time)(struct xgbe_prv_data *);
582 	u64 (*get_tx_tstamp)(struct xgbe_prv_data *);
583 
584 	/* For Data Center Bridging config */
585 	void (*config_dcb_tc)(struct xgbe_prv_data *);
586 	void (*config_dcb_pfc)(struct xgbe_prv_data *);
587 
588 	/* For Receive Side Scaling */
589 	int (*enable_rss)(struct xgbe_prv_data *);
590 	int (*disable_rss)(struct xgbe_prv_data *);
591 	int (*set_rss_hash_key)(struct xgbe_prv_data *, const u8 *);
592 	int (*set_rss_lookup_table)(struct xgbe_prv_data *, const u32 *);
593 };
594 
595 struct xgbe_desc_if {
596 	int (*alloc_ring_resources)(struct xgbe_prv_data *);
597 	void (*free_ring_resources)(struct xgbe_prv_data *);
598 	int (*map_tx_skb)(struct xgbe_channel *, struct sk_buff *);
599 	void (*realloc_rx_buffer)(struct xgbe_channel *);
600 	void (*unmap_rdata)(struct xgbe_prv_data *, struct xgbe_ring_data *);
601 	void (*wrapper_tx_desc_init)(struct xgbe_prv_data *);
602 	void (*wrapper_rx_desc_init)(struct xgbe_prv_data *);
603 };
604 
605 /* This structure contains flags that indicate what hardware features
606  * or configurations are present in the device.
607  */
608 struct xgbe_hw_features {
609 	/* HW Version */
610 	unsigned int version;
611 
612 	/* HW Feature Register0 */
613 	unsigned int gmii;		/* 1000 Mbps support */
614 	unsigned int vlhash;		/* VLAN Hash Filter */
615 	unsigned int sma;		/* SMA(MDIO) Interface */
616 	unsigned int rwk;		/* PMT remote wake-up packet */
617 	unsigned int mgk;		/* PMT magic packet */
618 	unsigned int mmc;		/* RMON module */
619 	unsigned int aoe;		/* ARP Offload */
620 	unsigned int ts;		/* IEEE 1588-2008 Adavanced Timestamp */
621 	unsigned int eee;		/* Energy Efficient Ethernet */
622 	unsigned int tx_coe;		/* Tx Checksum Offload */
623 	unsigned int rx_coe;		/* Rx Checksum Offload */
624 	unsigned int addn_mac;		/* Additional MAC Addresses */
625 	unsigned int ts_src;		/* Timestamp Source */
626 	unsigned int sa_vlan_ins;	/* Source Address or VLAN Insertion */
627 
628 	/* HW Feature Register1 */
629 	unsigned int rx_fifo_size;	/* MTL Receive FIFO Size */
630 	unsigned int tx_fifo_size;	/* MTL Transmit FIFO Size */
631 	unsigned int adv_ts_hi;		/* Advance Timestamping High Word */
632 	unsigned int dcb;		/* DCB Feature */
633 	unsigned int sph;		/* Split Header Feature */
634 	unsigned int tso;		/* TCP Segmentation Offload */
635 	unsigned int dma_debug;		/* DMA Debug Registers */
636 	unsigned int rss;		/* Receive Side Scaling */
637 	unsigned int tc_cnt;		/* Number of Traffic Classes */
638 	unsigned int hash_table_size;	/* Hash Table Size */
639 	unsigned int l3l4_filter_num;	/* Number of L3-L4 Filters */
640 
641 	/* HW Feature Register2 */
642 	unsigned int rx_q_cnt;		/* Number of MTL Receive Queues */
643 	unsigned int tx_q_cnt;		/* Number of MTL Transmit Queues */
644 	unsigned int rx_ch_cnt;		/* Number of DMA Receive Channels */
645 	unsigned int tx_ch_cnt;		/* Number of DMA Transmit Channels */
646 	unsigned int pps_out_num;	/* Number of PPS outputs */
647 	unsigned int aux_snap_num;	/* Number of Aux snapshot inputs */
648 };
649 
650 struct xgbe_prv_data {
651 	struct net_device *netdev;
652 	struct platform_device *pdev;
653 	struct device *dev;
654 
655 	/* XGMAC/XPCS related mmio registers */
656 	void __iomem *xgmac_regs;	/* XGMAC CSRs */
657 	void __iomem *xpcs_regs;	/* XPCS MMD registers */
658 
659 	/* Overall device lock */
660 	spinlock_t lock;
661 
662 	/* XPCS indirect addressing mutex */
663 	struct mutex xpcs_mutex;
664 
665 	/* RSS addressing mutex */
666 	struct mutex rss_mutex;
667 
668 	int dev_irq;
669 	unsigned int per_channel_irq;
670 
671 	struct xgbe_hw_if hw_if;
672 	struct xgbe_desc_if desc_if;
673 
674 	/* AXI DMA settings */
675 	unsigned int axdomain;
676 	unsigned int arcache;
677 	unsigned int awcache;
678 
679 	/* Rings for Tx/Rx on a DMA channel */
680 	struct xgbe_channel *channel;
681 	unsigned int channel_count;
682 	unsigned int tx_ring_count;
683 	unsigned int tx_desc_count;
684 	unsigned int rx_ring_count;
685 	unsigned int rx_desc_count;
686 
687 	unsigned int tx_q_count;
688 	unsigned int rx_q_count;
689 
690 	/* Tx/Rx common settings */
691 	unsigned int pblx8;
692 
693 	/* Tx settings */
694 	unsigned int tx_sf_mode;
695 	unsigned int tx_threshold;
696 	unsigned int tx_pbl;
697 	unsigned int tx_osp_mode;
698 
699 	/* Rx settings */
700 	unsigned int rx_sf_mode;
701 	unsigned int rx_threshold;
702 	unsigned int rx_pbl;
703 
704 	/* Tx coalescing settings */
705 	unsigned int tx_usecs;
706 	unsigned int tx_frames;
707 
708 	/* Rx coalescing settings */
709 	unsigned int rx_riwt;
710 	unsigned int rx_frames;
711 
712 	/* Current Rx buffer size */
713 	unsigned int rx_buf_size;
714 
715 	/* Flow control settings */
716 	unsigned int pause_autoneg;
717 	unsigned int tx_pause;
718 	unsigned int rx_pause;
719 
720 	/* Receive Side Scaling settings */
721 	u8 rss_key[XGBE_RSS_HASH_KEY_SIZE];
722 	u32 rss_table[XGBE_RSS_MAX_TABLE_SIZE];
723 	u32 rss_options;
724 
725 	/* MDIO settings */
726 	struct module *phy_module;
727 	char *mii_bus_id;
728 	struct mii_bus *mii;
729 	int mdio_mmd;
730 	struct phy_device *phydev;
731 	int default_autoneg;
732 	int default_speed;
733 
734 	/* Current PHY settings */
735 	phy_interface_t phy_mode;
736 	int phy_link;
737 	int phy_speed;
738 	unsigned int phy_tx_pause;
739 	unsigned int phy_rx_pause;
740 
741 	/* Netdev related settings */
742 	netdev_features_t netdev_features;
743 	struct napi_struct napi;
744 	struct xgbe_mmc_stats mmc_stats;
745 
746 	/* Filtering support */
747 	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
748 
749 	/* Device clocks */
750 	struct clk *sysclk;
751 	struct clk *ptpclk;
752 
753 	/* Timestamp support */
754 	spinlock_t tstamp_lock;
755 	struct ptp_clock_info ptp_clock_info;
756 	struct ptp_clock *ptp_clock;
757 	struct hwtstamp_config tstamp_config;
758 	struct cyclecounter tstamp_cc;
759 	struct timecounter tstamp_tc;
760 	unsigned int tstamp_addend;
761 	struct work_struct tx_tstamp_work;
762 	struct sk_buff *tx_tstamp_skb;
763 	u64 tx_tstamp;
764 
765 	/* DCB support */
766 	struct ieee_ets *ets;
767 	struct ieee_pfc *pfc;
768 	unsigned int q2tc_map[XGBE_MAX_QUEUES];
769 	unsigned int prio2q_map[IEEE_8021QAZ_MAX_TCS];
770 
771 	/* Hardware features of the device */
772 	struct xgbe_hw_features hw_feat;
773 
774 	/* Device restart work structure */
775 	struct work_struct restart_work;
776 
777 	/* Keeps track of power mode */
778 	unsigned int power_down;
779 
780 #ifdef CONFIG_DEBUG_FS
781 	struct dentry *xgbe_debugfs;
782 
783 	unsigned int debugfs_xgmac_reg;
784 
785 	unsigned int debugfs_xpcs_mmd;
786 	unsigned int debugfs_xpcs_reg;
787 #endif
788 };
789 
790 /* Function prototypes*/
791 
792 void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *);
793 void xgbe_init_function_ptrs_desc(struct xgbe_desc_if *);
794 struct net_device_ops *xgbe_get_netdev_ops(void);
795 struct ethtool_ops *xgbe_get_ethtool_ops(void);
796 #ifdef CONFIG_AMD_XGBE_DCB
797 const struct dcbnl_rtnl_ops *xgbe_get_dcbnl_ops(void);
798 #endif
799 
800 int xgbe_mdio_register(struct xgbe_prv_data *);
801 void xgbe_mdio_unregister(struct xgbe_prv_data *);
802 void xgbe_dump_phy_registers(struct xgbe_prv_data *);
803 void xgbe_ptp_register(struct xgbe_prv_data *);
804 void xgbe_ptp_unregister(struct xgbe_prv_data *);
805 void xgbe_dump_tx_desc(struct xgbe_ring *, unsigned int, unsigned int,
806 		       unsigned int);
807 void xgbe_dump_rx_desc(struct xgbe_ring *, struct xgbe_ring_desc *,
808 		       unsigned int);
809 void xgbe_print_pkt(struct net_device *, struct sk_buff *, bool);
810 void xgbe_get_all_hw_features(struct xgbe_prv_data *);
811 int xgbe_powerup(struct net_device *, unsigned int);
812 int xgbe_powerdown(struct net_device *, unsigned int);
813 void xgbe_init_rx_coalesce(struct xgbe_prv_data *);
814 void xgbe_init_tx_coalesce(struct xgbe_prv_data *);
815 
816 #ifdef CONFIG_DEBUG_FS
817 void xgbe_debugfs_init(struct xgbe_prv_data *);
818 void xgbe_debugfs_exit(struct xgbe_prv_data *);
819 #else
820 static inline void xgbe_debugfs_init(struct xgbe_prv_data *pdata) {}
821 static inline void xgbe_debugfs_exit(struct xgbe_prv_data *pdata) {}
822 #endif /* CONFIG_DEBUG_FS */
823 
824 /* NOTE: Uncomment for TX and RX DESCRIPTOR DUMP in KERNEL LOG */
825 #if 0
826 #define XGMAC_ENABLE_TX_DESC_DUMP
827 #define XGMAC_ENABLE_RX_DESC_DUMP
828 #endif
829 
830 /* NOTE: Uncomment for TX and RX PACKET DUMP in KERNEL LOG */
831 #if 0
832 #define XGMAC_ENABLE_TX_PKT_DUMP
833 #define XGMAC_ENABLE_RX_PKT_DUMP
834 #endif
835 
836 /* NOTE: Uncomment for function trace log messages in KERNEL LOG */
837 #if 0
838 #define YDEBUG
839 #define YDEBUG_MDIO
840 #endif
841 
842 /* For debug prints */
843 #ifdef YDEBUG
844 #define DBGPR(x...) pr_alert(x)
845 #define DBGPHY_REGS(x...) xgbe_dump_phy_registers(x)
846 #else
847 #define DBGPR(x...) do { } while (0)
848 #define DBGPHY_REGS(x...) do { } while (0)
849 #endif
850 
851 #ifdef YDEBUG_MDIO
852 #define DBGPR_MDIO(x...) pr_alert(x)
853 #else
854 #define DBGPR_MDIO(x...) do { } while (0)
855 #endif
856 
857 #endif
858