1 /* 2 * AMD 10Gb Ethernet driver 3 * 4 * This file is available to you under your choice of the following two 5 * licenses: 6 * 7 * License 1: GPLv2 8 * 9 * Copyright (c) 2014 Advanced Micro Devices, Inc. 10 * 11 * This file is free software; you may copy, redistribute and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation, either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program. If not, see <http://www.gnu.org/licenses/>. 23 * 24 * This file incorporates work covered by the following copyright and 25 * permission notice: 26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 28 * Inc. unless otherwise expressly agreed to in writing between Synopsys 29 * and you. 30 * 31 * The Software IS NOT an item of Licensed Software or Licensed Product 32 * under any End User Software License Agreement or Agreement for Licensed 33 * Product with Synopsys or any supplement thereto. Permission is hereby 34 * granted, free of charge, to any person obtaining a copy of this software 35 * annotated with this license and the Software, to deal in the Software 36 * without restriction, including without limitation the rights to use, 37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 38 * of the Software, and to permit persons to whom the Software is furnished 39 * to do so, subject to the following conditions: 40 * 41 * The above copyright notice and this permission notice shall be included 42 * in all copies or substantial portions of the Software. 43 * 44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 54 * THE POSSIBILITY OF SUCH DAMAGE. 55 * 56 * 57 * License 2: Modified BSD 58 * 59 * Copyright (c) 2014 Advanced Micro Devices, Inc. 60 * All rights reserved. 61 * 62 * Redistribution and use in source and binary forms, with or without 63 * modification, are permitted provided that the following conditions are met: 64 * * Redistributions of source code must retain the above copyright 65 * notice, this list of conditions and the following disclaimer. 66 * * Redistributions in binary form must reproduce the above copyright 67 * notice, this list of conditions and the following disclaimer in the 68 * documentation and/or other materials provided with the distribution. 69 * * Neither the name of Advanced Micro Devices, Inc. nor the 70 * names of its contributors may be used to endorse or promote products 71 * derived from this software without specific prior written permission. 72 * 73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY 77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 83 * 84 * This file incorporates work covered by the following copyright and 85 * permission notice: 86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 88 * Inc. unless otherwise expressly agreed to in writing between Synopsys 89 * and you. 90 * 91 * The Software IS NOT an item of Licensed Software or Licensed Product 92 * under any End User Software License Agreement or Agreement for Licensed 93 * Product with Synopsys or any supplement thereto. Permission is hereby 94 * granted, free of charge, to any person obtaining a copy of this software 95 * annotated with this license and the Software, to deal in the Software 96 * without restriction, including without limitation the rights to use, 97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 98 * of the Software, and to permit persons to whom the Software is furnished 99 * to do so, subject to the following conditions: 100 * 101 * The above copyright notice and this permission notice shall be included 102 * in all copies or substantial portions of the Software. 103 * 104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 114 * THE POSSIBILITY OF SUCH DAMAGE. 115 */ 116 117 #ifndef __XGBE_H__ 118 #define __XGBE_H__ 119 120 #include <linux/dma-mapping.h> 121 #include <linux/netdevice.h> 122 #include <linux/workqueue.h> 123 #include <linux/phy.h> 124 #include <linux/if_vlan.h> 125 #include <linux/bitops.h> 126 #include <linux/ptp_clock_kernel.h> 127 #include <linux/clocksource.h> 128 #include <linux/net_tstamp.h> 129 #include <net/dcbnl.h> 130 131 132 #define XGBE_DRV_NAME "amd-xgbe" 133 #define XGBE_DRV_VERSION "1.0.0-a" 134 #define XGBE_DRV_DESC "AMD 10 Gigabit Ethernet Driver" 135 136 /* Descriptor related defines */ 137 #define XGBE_TX_DESC_CNT 512 138 #define XGBE_TX_DESC_MIN_FREE (XGBE_TX_DESC_CNT >> 3) 139 #define XGBE_TX_DESC_MAX_PROC (XGBE_TX_DESC_CNT >> 1) 140 #define XGBE_RX_DESC_CNT 512 141 142 #define XGBE_TX_MAX_BUF_SIZE (0x3fff & ~(64 - 1)) 143 144 #define XGBE_RX_MIN_BUF_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN) 145 #define XGBE_RX_BUF_ALIGN 64 146 147 #define XGBE_MAX_DMA_CHANNELS 16 148 #define XGBE_MAX_QUEUES 16 149 150 /* DMA cache settings - Outer sharable, write-back, write-allocate */ 151 #define XGBE_DMA_OS_AXDOMAIN 0x2 152 #define XGBE_DMA_OS_ARCACHE 0xb 153 #define XGBE_DMA_OS_AWCACHE 0xf 154 155 /* DMA cache settings - System, no caches used */ 156 #define XGBE_DMA_SYS_AXDOMAIN 0x3 157 #define XGBE_DMA_SYS_ARCACHE 0x0 158 #define XGBE_DMA_SYS_AWCACHE 0x0 159 160 #define XGBE_DMA_INTERRUPT_MASK 0x31c7 161 162 #define XGMAC_MIN_PACKET 60 163 #define XGMAC_STD_PACKET_MTU 1500 164 #define XGMAC_MAX_STD_PACKET 1518 165 #define XGMAC_JUMBO_PACKET_MTU 9000 166 #define XGMAC_MAX_JUMBO_PACKET 9018 167 168 /* MDIO bus phy name */ 169 #define XGBE_PHY_NAME "amd_xgbe_phy" 170 #define XGBE_PRTAD 0 171 172 /* Device-tree clock names */ 173 #define XGBE_DMA_CLOCK "dma_clk" 174 #define XGBE_PTP_CLOCK "ptp_clk" 175 176 /* Timestamp support - values based on 50MHz PTP clock 177 * 50MHz => 20 nsec 178 */ 179 #define XGBE_TSTAMP_SSINC 20 180 #define XGBE_TSTAMP_SNSINC 0 181 182 /* Driver PMT macros */ 183 #define XGMAC_DRIVER_CONTEXT 1 184 #define XGMAC_IOCTL_CONTEXT 2 185 186 #define XGBE_FIFO_SIZE_B(x) (x) 187 #define XGBE_FIFO_SIZE_KB(x) (x * 1024) 188 189 #define XGBE_TC_MIN_QUANTUM 10 190 191 /* Helper macro for descriptor handling 192 * Always use XGBE_GET_DESC_DATA to access the descriptor data 193 * since the index is free-running and needs to be and-ed 194 * with the descriptor count value of the ring to index to 195 * the proper descriptor data. 196 */ 197 #define XGBE_GET_DESC_DATA(_ring, _idx) \ 198 ((_ring)->rdata + \ 199 ((_idx) & ((_ring)->rdesc_count - 1))) 200 201 202 /* Default coalescing parameters */ 203 #define XGMAC_INIT_DMA_TX_USECS 50 204 #define XGMAC_INIT_DMA_TX_FRAMES 25 205 206 #define XGMAC_MAX_DMA_RIWT 0xff 207 #define XGMAC_INIT_DMA_RX_USECS 30 208 #define XGMAC_INIT_DMA_RX_FRAMES 25 209 210 /* Flow control queue count */ 211 #define XGMAC_MAX_FLOW_CONTROL_QUEUES 8 212 213 /* Maximum MAC address hash table size (256 bits = 8 bytes) */ 214 #define XGBE_MAC_HASH_TABLE_SIZE 8 215 216 struct xgbe_prv_data; 217 218 struct xgbe_packet_data { 219 unsigned int attributes; 220 221 unsigned int errors; 222 223 unsigned int rdesc_count; 224 unsigned int length; 225 226 unsigned int header_len; 227 unsigned int tcp_header_len; 228 unsigned int tcp_payload_len; 229 unsigned short mss; 230 231 unsigned short vlan_ctag; 232 233 u64 rx_tstamp; 234 }; 235 236 /* Common Rx and Tx descriptor mapping */ 237 struct xgbe_ring_desc { 238 unsigned int desc0; 239 unsigned int desc1; 240 unsigned int desc2; 241 unsigned int desc3; 242 }; 243 244 /* Structure used to hold information related to the descriptor 245 * and the packet associated with the descriptor (always use 246 * use the XGBE_GET_DESC_DATA macro to access this data from the ring) 247 */ 248 struct xgbe_ring_data { 249 struct xgbe_ring_desc *rdesc; /* Virtual address of descriptor */ 250 dma_addr_t rdesc_dma; /* DMA address of descriptor */ 251 252 struct sk_buff *skb; /* Virtual address of SKB */ 253 dma_addr_t skb_dma; /* DMA address of SKB data */ 254 unsigned int skb_dma_len; /* Length of SKB DMA area */ 255 unsigned int tso_header; /* TSO header indicator */ 256 257 unsigned short len; /* Length of received Rx packet */ 258 259 unsigned int interrupt; /* Interrupt indicator */ 260 261 unsigned int mapped_as_page; 262 263 /* Incomplete receive save location. If the budget is exhausted 264 * or the last descriptor (last normal descriptor or a following 265 * context descriptor) has not been DMA'd yet the current state 266 * of the receive processing needs to be saved. 267 */ 268 unsigned int state_saved; 269 struct { 270 unsigned int incomplete; 271 unsigned int context_next; 272 struct sk_buff *skb; 273 unsigned int len; 274 unsigned int error; 275 } state; 276 }; 277 278 struct xgbe_ring { 279 /* Ring lock - used just for TX rings at the moment */ 280 spinlock_t lock; 281 282 /* Per packet related information */ 283 struct xgbe_packet_data packet_data; 284 285 /* Virtual/DMA addresses and count of allocated descriptor memory */ 286 struct xgbe_ring_desc *rdesc; 287 dma_addr_t rdesc_dma; 288 unsigned int rdesc_count; 289 290 /* Array of descriptor data corresponding the descriptor memory 291 * (always use the XGBE_GET_DESC_DATA macro to access this data) 292 */ 293 struct xgbe_ring_data *rdata; 294 295 /* Ring index values 296 * cur - Tx: index of descriptor to be used for current transfer 297 * Rx: index of descriptor to check for packet availability 298 * dirty - Tx: index of descriptor to check for transfer complete 299 * Rx: count of descriptors in which a packet has been received 300 * (used with skb_realloc_index to refresh the ring) 301 */ 302 unsigned int cur; 303 unsigned int dirty; 304 305 /* Coalesce frame count used for interrupt bit setting */ 306 unsigned int coalesce_count; 307 308 union { 309 struct { 310 unsigned int queue_stopped; 311 unsigned short cur_mss; 312 unsigned short cur_vlan_ctag; 313 } tx; 314 315 struct { 316 unsigned int realloc_index; 317 unsigned int realloc_threshold; 318 } rx; 319 }; 320 } ____cacheline_aligned; 321 322 /* Structure used to describe the descriptor rings associated with 323 * a DMA channel. 324 */ 325 struct xgbe_channel { 326 char name[16]; 327 328 /* Address of private data area for device */ 329 struct xgbe_prv_data *pdata; 330 331 /* Queue index and base address of queue's DMA registers */ 332 unsigned int queue_index; 333 void __iomem *dma_regs; 334 335 unsigned int saved_ier; 336 337 unsigned int tx_timer_active; 338 struct hrtimer tx_timer; 339 340 struct xgbe_ring *tx_ring; 341 struct xgbe_ring *rx_ring; 342 } ____cacheline_aligned; 343 344 enum xgbe_int { 345 XGMAC_INT_DMA_CH_SR_TI, 346 XGMAC_INT_DMA_CH_SR_TPS, 347 XGMAC_INT_DMA_CH_SR_TBU, 348 XGMAC_INT_DMA_CH_SR_RI, 349 XGMAC_INT_DMA_CH_SR_RBU, 350 XGMAC_INT_DMA_CH_SR_RPS, 351 XGMAC_INT_DMA_CH_SR_TI_RI, 352 XGMAC_INT_DMA_CH_SR_FBE, 353 XGMAC_INT_DMA_ALL, 354 }; 355 356 enum xgbe_int_state { 357 XGMAC_INT_STATE_SAVE, 358 XGMAC_INT_STATE_RESTORE, 359 }; 360 361 enum xgbe_mtl_fifo_size { 362 XGMAC_MTL_FIFO_SIZE_256 = 0x00, 363 XGMAC_MTL_FIFO_SIZE_512 = 0x01, 364 XGMAC_MTL_FIFO_SIZE_1K = 0x03, 365 XGMAC_MTL_FIFO_SIZE_2K = 0x07, 366 XGMAC_MTL_FIFO_SIZE_4K = 0x0f, 367 XGMAC_MTL_FIFO_SIZE_8K = 0x1f, 368 XGMAC_MTL_FIFO_SIZE_16K = 0x3f, 369 XGMAC_MTL_FIFO_SIZE_32K = 0x7f, 370 XGMAC_MTL_FIFO_SIZE_64K = 0xff, 371 XGMAC_MTL_FIFO_SIZE_128K = 0x1ff, 372 XGMAC_MTL_FIFO_SIZE_256K = 0x3ff, 373 }; 374 375 struct xgbe_mmc_stats { 376 /* Tx Stats */ 377 u64 txoctetcount_gb; 378 u64 txframecount_gb; 379 u64 txbroadcastframes_g; 380 u64 txmulticastframes_g; 381 u64 tx64octets_gb; 382 u64 tx65to127octets_gb; 383 u64 tx128to255octets_gb; 384 u64 tx256to511octets_gb; 385 u64 tx512to1023octets_gb; 386 u64 tx1024tomaxoctets_gb; 387 u64 txunicastframes_gb; 388 u64 txmulticastframes_gb; 389 u64 txbroadcastframes_gb; 390 u64 txunderflowerror; 391 u64 txoctetcount_g; 392 u64 txframecount_g; 393 u64 txpauseframes; 394 u64 txvlanframes_g; 395 396 /* Rx Stats */ 397 u64 rxframecount_gb; 398 u64 rxoctetcount_gb; 399 u64 rxoctetcount_g; 400 u64 rxbroadcastframes_g; 401 u64 rxmulticastframes_g; 402 u64 rxcrcerror; 403 u64 rxrunterror; 404 u64 rxjabbererror; 405 u64 rxundersize_g; 406 u64 rxoversize_g; 407 u64 rx64octets_gb; 408 u64 rx65to127octets_gb; 409 u64 rx128to255octets_gb; 410 u64 rx256to511octets_gb; 411 u64 rx512to1023octets_gb; 412 u64 rx1024tomaxoctets_gb; 413 u64 rxunicastframes_g; 414 u64 rxlengtherror; 415 u64 rxoutofrangetype; 416 u64 rxpauseframes; 417 u64 rxfifooverflow; 418 u64 rxvlanframes_gb; 419 u64 rxwatchdogerror; 420 }; 421 422 struct xgbe_hw_if { 423 int (*tx_complete)(struct xgbe_ring_desc *); 424 425 int (*set_promiscuous_mode)(struct xgbe_prv_data *, unsigned int); 426 int (*set_all_multicast_mode)(struct xgbe_prv_data *, unsigned int); 427 int (*add_mac_addresses)(struct xgbe_prv_data *); 428 int (*set_mac_address)(struct xgbe_prv_data *, u8 *addr); 429 430 int (*enable_rx_csum)(struct xgbe_prv_data *); 431 int (*disable_rx_csum)(struct xgbe_prv_data *); 432 433 int (*enable_rx_vlan_stripping)(struct xgbe_prv_data *); 434 int (*disable_rx_vlan_stripping)(struct xgbe_prv_data *); 435 int (*enable_rx_vlan_filtering)(struct xgbe_prv_data *); 436 int (*disable_rx_vlan_filtering)(struct xgbe_prv_data *); 437 int (*update_vlan_hash_table)(struct xgbe_prv_data *); 438 439 int (*read_mmd_regs)(struct xgbe_prv_data *, int, int); 440 void (*write_mmd_regs)(struct xgbe_prv_data *, int, int, int); 441 int (*set_gmii_speed)(struct xgbe_prv_data *); 442 int (*set_gmii_2500_speed)(struct xgbe_prv_data *); 443 int (*set_xgmii_speed)(struct xgbe_prv_data *); 444 445 void (*enable_tx)(struct xgbe_prv_data *); 446 void (*disable_tx)(struct xgbe_prv_data *); 447 void (*enable_rx)(struct xgbe_prv_data *); 448 void (*disable_rx)(struct xgbe_prv_data *); 449 450 void (*powerup_tx)(struct xgbe_prv_data *); 451 void (*powerdown_tx)(struct xgbe_prv_data *); 452 void (*powerup_rx)(struct xgbe_prv_data *); 453 void (*powerdown_rx)(struct xgbe_prv_data *); 454 455 int (*init)(struct xgbe_prv_data *); 456 int (*exit)(struct xgbe_prv_data *); 457 458 int (*enable_int)(struct xgbe_channel *, enum xgbe_int); 459 int (*disable_int)(struct xgbe_channel *, enum xgbe_int); 460 void (*pre_xmit)(struct xgbe_channel *); 461 int (*dev_read)(struct xgbe_channel *); 462 void (*tx_desc_init)(struct xgbe_channel *); 463 void (*rx_desc_init)(struct xgbe_channel *); 464 void (*rx_desc_reset)(struct xgbe_ring_data *); 465 void (*tx_desc_reset)(struct xgbe_ring_data *); 466 int (*is_last_desc)(struct xgbe_ring_desc *); 467 int (*is_context_desc)(struct xgbe_ring_desc *); 468 469 /* For FLOW ctrl */ 470 int (*config_tx_flow_control)(struct xgbe_prv_data *); 471 int (*config_rx_flow_control)(struct xgbe_prv_data *); 472 473 /* For RX coalescing */ 474 int (*config_rx_coalesce)(struct xgbe_prv_data *); 475 int (*config_tx_coalesce)(struct xgbe_prv_data *); 476 unsigned int (*usec_to_riwt)(struct xgbe_prv_data *, unsigned int); 477 unsigned int (*riwt_to_usec)(struct xgbe_prv_data *, unsigned int); 478 479 /* For RX and TX threshold config */ 480 int (*config_rx_threshold)(struct xgbe_prv_data *, unsigned int); 481 int (*config_tx_threshold)(struct xgbe_prv_data *, unsigned int); 482 483 /* For RX and TX Store and Forward Mode config */ 484 int (*config_rsf_mode)(struct xgbe_prv_data *, unsigned int); 485 int (*config_tsf_mode)(struct xgbe_prv_data *, unsigned int); 486 487 /* For TX DMA Operate on Second Frame config */ 488 int (*config_osp_mode)(struct xgbe_prv_data *); 489 490 /* For RX and TX PBL config */ 491 int (*config_rx_pbl_val)(struct xgbe_prv_data *); 492 int (*get_rx_pbl_val)(struct xgbe_prv_data *); 493 int (*config_tx_pbl_val)(struct xgbe_prv_data *); 494 int (*get_tx_pbl_val)(struct xgbe_prv_data *); 495 int (*config_pblx8)(struct xgbe_prv_data *); 496 497 /* For MMC statistics */ 498 void (*rx_mmc_int)(struct xgbe_prv_data *); 499 void (*tx_mmc_int)(struct xgbe_prv_data *); 500 void (*read_mmc_stats)(struct xgbe_prv_data *); 501 502 /* For Timestamp config */ 503 int (*config_tstamp)(struct xgbe_prv_data *, unsigned int); 504 void (*update_tstamp_addend)(struct xgbe_prv_data *, unsigned int); 505 void (*set_tstamp_time)(struct xgbe_prv_data *, unsigned int sec, 506 unsigned int nsec); 507 u64 (*get_tstamp_time)(struct xgbe_prv_data *); 508 u64 (*get_tx_tstamp)(struct xgbe_prv_data *); 509 510 /* For Data Center Bridging config */ 511 void (*config_dcb_tc)(struct xgbe_prv_data *); 512 void (*config_dcb_pfc)(struct xgbe_prv_data *); 513 }; 514 515 struct xgbe_desc_if { 516 int (*alloc_ring_resources)(struct xgbe_prv_data *); 517 void (*free_ring_resources)(struct xgbe_prv_data *); 518 int (*map_tx_skb)(struct xgbe_channel *, struct sk_buff *); 519 void (*realloc_skb)(struct xgbe_channel *); 520 void (*unmap_skb)(struct xgbe_prv_data *, struct xgbe_ring_data *); 521 void (*wrapper_tx_desc_init)(struct xgbe_prv_data *); 522 void (*wrapper_rx_desc_init)(struct xgbe_prv_data *); 523 }; 524 525 /* This structure contains flags that indicate what hardware features 526 * or configurations are present in the device. 527 */ 528 struct xgbe_hw_features { 529 /* HW Feature Register0 */ 530 unsigned int gmii; /* 1000 Mbps support */ 531 unsigned int vlhash; /* VLAN Hash Filter */ 532 unsigned int sma; /* SMA(MDIO) Interface */ 533 unsigned int rwk; /* PMT remote wake-up packet */ 534 unsigned int mgk; /* PMT magic packet */ 535 unsigned int mmc; /* RMON module */ 536 unsigned int aoe; /* ARP Offload */ 537 unsigned int ts; /* IEEE 1588-2008 Adavanced Timestamp */ 538 unsigned int eee; /* Energy Efficient Ethernet */ 539 unsigned int tx_coe; /* Tx Checksum Offload */ 540 unsigned int rx_coe; /* Rx Checksum Offload */ 541 unsigned int addn_mac; /* Additional MAC Addresses */ 542 unsigned int ts_src; /* Timestamp Source */ 543 unsigned int sa_vlan_ins; /* Source Address or VLAN Insertion */ 544 545 /* HW Feature Register1 */ 546 unsigned int rx_fifo_size; /* MTL Receive FIFO Size */ 547 unsigned int tx_fifo_size; /* MTL Transmit FIFO Size */ 548 unsigned int adv_ts_hi; /* Advance Timestamping High Word */ 549 unsigned int dcb; /* DCB Feature */ 550 unsigned int sph; /* Split Header Feature */ 551 unsigned int tso; /* TCP Segmentation Offload */ 552 unsigned int dma_debug; /* DMA Debug Registers */ 553 unsigned int rss; /* Receive Side Scaling */ 554 unsigned int tc_cnt; /* Number of Traffic Classes */ 555 unsigned int hash_table_size; /* Hash Table Size */ 556 unsigned int l3l4_filter_num; /* Number of L3-L4 Filters */ 557 558 /* HW Feature Register2 */ 559 unsigned int rx_q_cnt; /* Number of MTL Receive Queues */ 560 unsigned int tx_q_cnt; /* Number of MTL Transmit Queues */ 561 unsigned int rx_ch_cnt; /* Number of DMA Receive Channels */ 562 unsigned int tx_ch_cnt; /* Number of DMA Transmit Channels */ 563 unsigned int pps_out_num; /* Number of PPS outputs */ 564 unsigned int aux_snap_num; /* Number of Aux snapshot inputs */ 565 }; 566 567 struct xgbe_prv_data { 568 struct net_device *netdev; 569 struct platform_device *pdev; 570 struct device *dev; 571 572 /* XGMAC/XPCS related mmio registers */ 573 void __iomem *xgmac_regs; /* XGMAC CSRs */ 574 void __iomem *xpcs_regs; /* XPCS MMD registers */ 575 576 /* Overall device lock */ 577 spinlock_t lock; 578 579 /* XPCS indirect addressing mutex */ 580 struct mutex xpcs_mutex; 581 582 int irq_number; 583 584 struct xgbe_hw_if hw_if; 585 struct xgbe_desc_if desc_if; 586 587 /* AXI DMA settings */ 588 unsigned int axdomain; 589 unsigned int arcache; 590 unsigned int awcache; 591 592 /* Rings for Tx/Rx on a DMA channel */ 593 struct xgbe_channel *channel; 594 unsigned int channel_count; 595 unsigned int tx_ring_count; 596 unsigned int tx_desc_count; 597 unsigned int rx_ring_count; 598 unsigned int rx_desc_count; 599 600 unsigned int tx_q_count; 601 unsigned int rx_q_count; 602 603 /* Tx/Rx common settings */ 604 unsigned int pblx8; 605 606 /* Tx settings */ 607 unsigned int tx_sf_mode; 608 unsigned int tx_threshold; 609 unsigned int tx_pbl; 610 unsigned int tx_osp_mode; 611 612 /* Rx settings */ 613 unsigned int rx_sf_mode; 614 unsigned int rx_threshold; 615 unsigned int rx_pbl; 616 617 /* Tx coalescing settings */ 618 unsigned int tx_usecs; 619 unsigned int tx_frames; 620 621 /* Rx coalescing settings */ 622 unsigned int rx_riwt; 623 unsigned int rx_frames; 624 625 /* Current MTU */ 626 unsigned int rx_buf_size; 627 628 /* Flow control settings */ 629 unsigned int pause_autoneg; 630 unsigned int tx_pause; 631 unsigned int rx_pause; 632 633 /* MDIO settings */ 634 struct module *phy_module; 635 char *mii_bus_id; 636 struct mii_bus *mii; 637 int mdio_mmd; 638 struct phy_device *phydev; 639 int default_autoneg; 640 int default_speed; 641 642 /* Current PHY settings */ 643 phy_interface_t phy_mode; 644 int phy_link; 645 int phy_speed; 646 unsigned int phy_tx_pause; 647 unsigned int phy_rx_pause; 648 649 /* Netdev related settings */ 650 netdev_features_t netdev_features; 651 struct napi_struct napi; 652 struct xgbe_mmc_stats mmc_stats; 653 654 /* Filtering support */ 655 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 656 657 /* Device clocks */ 658 struct clk *sysclk; 659 struct clk *ptpclk; 660 661 /* Timestamp support */ 662 spinlock_t tstamp_lock; 663 struct ptp_clock_info ptp_clock_info; 664 struct ptp_clock *ptp_clock; 665 struct hwtstamp_config tstamp_config; 666 struct cyclecounter tstamp_cc; 667 struct timecounter tstamp_tc; 668 unsigned int tstamp_addend; 669 struct work_struct tx_tstamp_work; 670 struct sk_buff *tx_tstamp_skb; 671 u64 tx_tstamp; 672 673 /* DCB support */ 674 struct ieee_ets *ets; 675 struct ieee_pfc *pfc; 676 unsigned int q2tc_map[XGBE_MAX_QUEUES]; 677 unsigned int prio2q_map[IEEE_8021QAZ_MAX_TCS]; 678 679 /* Hardware features of the device */ 680 struct xgbe_hw_features hw_feat; 681 682 /* Device restart work structure */ 683 struct work_struct restart_work; 684 685 /* Keeps track of power mode */ 686 unsigned int power_down; 687 688 #ifdef CONFIG_DEBUG_FS 689 struct dentry *xgbe_debugfs; 690 691 unsigned int debugfs_xgmac_reg; 692 693 unsigned int debugfs_xpcs_mmd; 694 unsigned int debugfs_xpcs_reg; 695 #endif 696 }; 697 698 /* Function prototypes*/ 699 700 void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *); 701 void xgbe_init_function_ptrs_desc(struct xgbe_desc_if *); 702 struct net_device_ops *xgbe_get_netdev_ops(void); 703 struct ethtool_ops *xgbe_get_ethtool_ops(void); 704 #ifdef CONFIG_AMD_XGBE_DCB 705 const struct dcbnl_rtnl_ops *xgbe_get_dcbnl_ops(void); 706 #endif 707 708 int xgbe_mdio_register(struct xgbe_prv_data *); 709 void xgbe_mdio_unregister(struct xgbe_prv_data *); 710 void xgbe_dump_phy_registers(struct xgbe_prv_data *); 711 void xgbe_ptp_register(struct xgbe_prv_data *); 712 void xgbe_ptp_unregister(struct xgbe_prv_data *); 713 void xgbe_dump_tx_desc(struct xgbe_ring *, unsigned int, unsigned int, 714 unsigned int); 715 void xgbe_dump_rx_desc(struct xgbe_ring *, struct xgbe_ring_desc *, 716 unsigned int); 717 void xgbe_print_pkt(struct net_device *, struct sk_buff *, bool); 718 void xgbe_get_all_hw_features(struct xgbe_prv_data *); 719 int xgbe_powerup(struct net_device *, unsigned int); 720 int xgbe_powerdown(struct net_device *, unsigned int); 721 void xgbe_init_rx_coalesce(struct xgbe_prv_data *); 722 void xgbe_init_tx_coalesce(struct xgbe_prv_data *); 723 724 #ifdef CONFIG_DEBUG_FS 725 void xgbe_debugfs_init(struct xgbe_prv_data *); 726 void xgbe_debugfs_exit(struct xgbe_prv_data *); 727 #else 728 static inline void xgbe_debugfs_init(struct xgbe_prv_data *pdata) {} 729 static inline void xgbe_debugfs_exit(struct xgbe_prv_data *pdata) {} 730 #endif /* CONFIG_DEBUG_FS */ 731 732 /* NOTE: Uncomment for TX and RX DESCRIPTOR DUMP in KERNEL LOG */ 733 #if 0 734 #define XGMAC_ENABLE_TX_DESC_DUMP 735 #define XGMAC_ENABLE_RX_DESC_DUMP 736 #endif 737 738 /* NOTE: Uncomment for TX and RX PACKET DUMP in KERNEL LOG */ 739 #if 0 740 #define XGMAC_ENABLE_TX_PKT_DUMP 741 #define XGMAC_ENABLE_RX_PKT_DUMP 742 #endif 743 744 /* NOTE: Uncomment for function trace log messages in KERNEL LOG */ 745 #if 0 746 #define YDEBUG 747 #define YDEBUG_MDIO 748 #endif 749 750 /* For debug prints */ 751 #ifdef YDEBUG 752 #define DBGPR(x...) pr_alert(x) 753 #define DBGPHY_REGS(x...) xgbe_dump_phy_registers(x) 754 #else 755 #define DBGPR(x...) do { } while (0) 756 #define DBGPHY_REGS(x...) do { } while (0) 757 #endif 758 759 #ifdef YDEBUG_MDIO 760 #define DBGPR_MDIO(x...) pr_alert(x) 761 #else 762 #define DBGPR_MDIO(x...) do { } while (0) 763 #endif 764 765 #endif 766