1 /* 2 * AMD 10Gb Ethernet driver 3 * 4 * This file is available to you under your choice of the following two 5 * licenses: 6 * 7 * License 1: GPLv2 8 * 9 * Copyright (c) 2016 Advanced Micro Devices, Inc. 10 * 11 * This file is free software; you may copy, redistribute and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation, either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program. If not, see <http://www.gnu.org/licenses/>. 23 * 24 * This file incorporates work covered by the following copyright and 25 * permission notice: 26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 28 * Inc. unless otherwise expressly agreed to in writing between Synopsys 29 * and you. 30 * 31 * The Software IS NOT an item of Licensed Software or Licensed Product 32 * under any End User Software License Agreement or Agreement for Licensed 33 * Product with Synopsys or any supplement thereto. Permission is hereby 34 * granted, free of charge, to any person obtaining a copy of this software 35 * annotated with this license and the Software, to deal in the Software 36 * without restriction, including without limitation the rights to use, 37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 38 * of the Software, and to permit persons to whom the Software is furnished 39 * to do so, subject to the following conditions: 40 * 41 * The above copyright notice and this permission notice shall be included 42 * in all copies or substantial portions of the Software. 43 * 44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 54 * THE POSSIBILITY OF SUCH DAMAGE. 55 * 56 * 57 * License 2: Modified BSD 58 * 59 * Copyright (c) 2016 Advanced Micro Devices, Inc. 60 * All rights reserved. 61 * 62 * Redistribution and use in source and binary forms, with or without 63 * modification, are permitted provided that the following conditions are met: 64 * * Redistributions of source code must retain the above copyright 65 * notice, this list of conditions and the following disclaimer. 66 * * Redistributions in binary form must reproduce the above copyright 67 * notice, this list of conditions and the following disclaimer in the 68 * documentation and/or other materials provided with the distribution. 69 * * Neither the name of Advanced Micro Devices, Inc. nor the 70 * names of its contributors may be used to endorse or promote products 71 * derived from this software without specific prior written permission. 72 * 73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY 77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 83 * 84 * This file incorporates work covered by the following copyright and 85 * permission notice: 86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 88 * Inc. unless otherwise expressly agreed to in writing between Synopsys 89 * and you. 90 * 91 * The Software IS NOT an item of Licensed Software or Licensed Product 92 * under any End User Software License Agreement or Agreement for Licensed 93 * Product with Synopsys or any supplement thereto. Permission is hereby 94 * granted, free of charge, to any person obtaining a copy of this software 95 * annotated with this license and the Software, to deal in the Software 96 * without restriction, including without limitation the rights to use, 97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 98 * of the Software, and to permit persons to whom the Software is furnished 99 * to do so, subject to the following conditions: 100 * 101 * The above copyright notice and this permission notice shall be included 102 * in all copies or substantial portions of the Software. 103 * 104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 114 * THE POSSIBILITY OF SUCH DAMAGE. 115 */ 116 117 #include <linux/module.h> 118 #include <linux/device.h> 119 #include <linux/kmod.h> 120 #include <linux/mdio.h> 121 #include <linux/phy.h> 122 123 #include "xgbe.h" 124 #include "xgbe-common.h" 125 126 #define XGBE_PHY_PORT_SPEED_100 BIT(0) 127 #define XGBE_PHY_PORT_SPEED_1000 BIT(1) 128 #define XGBE_PHY_PORT_SPEED_2500 BIT(2) 129 #define XGBE_PHY_PORT_SPEED_10000 BIT(3) 130 131 #define XGBE_MUTEX_RELEASE 0x80000000 132 133 #define XGBE_SFP_DIRECT 7 134 135 /* I2C target addresses */ 136 #define XGBE_SFP_SERIAL_ID_ADDRESS 0x50 137 #define XGBE_SFP_DIAG_INFO_ADDRESS 0x51 138 #define XGBE_SFP_PHY_ADDRESS 0x56 139 #define XGBE_GPIO_ADDRESS_PCA9555 0x20 140 141 /* SFP sideband signal indicators */ 142 #define XGBE_GPIO_NO_TX_FAULT BIT(0) 143 #define XGBE_GPIO_NO_RATE_SELECT BIT(1) 144 #define XGBE_GPIO_NO_MOD_ABSENT BIT(2) 145 #define XGBE_GPIO_NO_RX_LOS BIT(3) 146 147 /* Rate-change complete wait/retry count */ 148 #define XGBE_RATECHANGE_COUNT 500 149 150 enum xgbe_port_mode { 151 XGBE_PORT_MODE_RSVD = 0, 152 XGBE_PORT_MODE_BACKPLANE, 153 XGBE_PORT_MODE_BACKPLANE_2500, 154 XGBE_PORT_MODE_1000BASE_T, 155 XGBE_PORT_MODE_1000BASE_X, 156 XGBE_PORT_MODE_NBASE_T, 157 XGBE_PORT_MODE_10GBASE_T, 158 XGBE_PORT_MODE_10GBASE_R, 159 XGBE_PORT_MODE_SFP, 160 XGBE_PORT_MODE_MAX, 161 }; 162 163 enum xgbe_conn_type { 164 XGBE_CONN_TYPE_NONE = 0, 165 XGBE_CONN_TYPE_SFP, 166 XGBE_CONN_TYPE_MDIO, 167 XGBE_CONN_TYPE_RSVD1, 168 XGBE_CONN_TYPE_BACKPLANE, 169 XGBE_CONN_TYPE_MAX, 170 }; 171 172 /* SFP/SFP+ related definitions */ 173 enum xgbe_sfp_comm { 174 XGBE_SFP_COMM_DIRECT = 0, 175 XGBE_SFP_COMM_PCA9545, 176 }; 177 178 enum xgbe_sfp_cable { 179 XGBE_SFP_CABLE_UNKNOWN = 0, 180 XGBE_SFP_CABLE_ACTIVE, 181 XGBE_SFP_CABLE_PASSIVE, 182 }; 183 184 enum xgbe_sfp_base { 185 XGBE_SFP_BASE_UNKNOWN = 0, 186 XGBE_SFP_BASE_1000_T, 187 XGBE_SFP_BASE_1000_SX, 188 XGBE_SFP_BASE_1000_LX, 189 XGBE_SFP_BASE_1000_CX, 190 XGBE_SFP_BASE_10000_SR, 191 XGBE_SFP_BASE_10000_LR, 192 XGBE_SFP_BASE_10000_LRM, 193 XGBE_SFP_BASE_10000_ER, 194 XGBE_SFP_BASE_10000_CR, 195 }; 196 197 enum xgbe_sfp_speed { 198 XGBE_SFP_SPEED_UNKNOWN = 0, 199 XGBE_SFP_SPEED_100_1000, 200 XGBE_SFP_SPEED_1000, 201 XGBE_SFP_SPEED_10000, 202 }; 203 204 /* SFP Serial ID Base ID values relative to an offset of 0 */ 205 #define XGBE_SFP_BASE_ID 0 206 #define XGBE_SFP_ID_SFP 0x03 207 208 #define XGBE_SFP_BASE_EXT_ID 1 209 #define XGBE_SFP_EXT_ID_SFP 0x04 210 211 #define XGBE_SFP_BASE_10GBE_CC 3 212 #define XGBE_SFP_BASE_10GBE_CC_SR BIT(4) 213 #define XGBE_SFP_BASE_10GBE_CC_LR BIT(5) 214 #define XGBE_SFP_BASE_10GBE_CC_LRM BIT(6) 215 #define XGBE_SFP_BASE_10GBE_CC_ER BIT(7) 216 217 #define XGBE_SFP_BASE_1GBE_CC 6 218 #define XGBE_SFP_BASE_1GBE_CC_SX BIT(0) 219 #define XGBE_SFP_BASE_1GBE_CC_LX BIT(1) 220 #define XGBE_SFP_BASE_1GBE_CC_CX BIT(2) 221 #define XGBE_SFP_BASE_1GBE_CC_T BIT(3) 222 223 #define XGBE_SFP_BASE_CABLE 8 224 #define XGBE_SFP_BASE_CABLE_PASSIVE BIT(2) 225 #define XGBE_SFP_BASE_CABLE_ACTIVE BIT(3) 226 227 #define XGBE_SFP_BASE_BR 12 228 #define XGBE_SFP_BASE_BR_1GBE_MIN 0x0a 229 #define XGBE_SFP_BASE_BR_1GBE_MAX 0x0d 230 #define XGBE_SFP_BASE_BR_10GBE_MIN 0x64 231 #define XGBE_SFP_BASE_BR_10GBE_MAX 0x68 232 233 #define XGBE_SFP_BASE_CU_CABLE_LEN 18 234 235 #define XGBE_SFP_BASE_VENDOR_NAME 20 236 #define XGBE_SFP_BASE_VENDOR_NAME_LEN 16 237 #define XGBE_SFP_BASE_VENDOR_PN 40 238 #define XGBE_SFP_BASE_VENDOR_PN_LEN 16 239 #define XGBE_SFP_BASE_VENDOR_REV 56 240 #define XGBE_SFP_BASE_VENDOR_REV_LEN 4 241 242 #define XGBE_SFP_BASE_CC 63 243 244 /* SFP Serial ID Extended ID values relative to an offset of 64 */ 245 #define XGBE_SFP_BASE_VENDOR_SN 4 246 #define XGBE_SFP_BASE_VENDOR_SN_LEN 16 247 248 #define XGBE_SFP_EXTD_DIAG 28 249 #define XGBE_SFP_EXTD_DIAG_ADDR_CHANGE BIT(2) 250 251 #define XGBE_SFP_EXTD_SFF_8472 30 252 253 #define XGBE_SFP_EXTD_CC 31 254 255 struct xgbe_sfp_eeprom { 256 u8 base[64]; 257 u8 extd[32]; 258 u8 vendor[32]; 259 }; 260 261 #define XGBE_BEL_FUSE_VENDOR "BEL-FUSE " 262 #define XGBE_BEL_FUSE_PARTNO "1GBT-SFP06 " 263 264 struct xgbe_sfp_ascii { 265 union { 266 char vendor[XGBE_SFP_BASE_VENDOR_NAME_LEN + 1]; 267 char partno[XGBE_SFP_BASE_VENDOR_PN_LEN + 1]; 268 char rev[XGBE_SFP_BASE_VENDOR_REV_LEN + 1]; 269 char serno[XGBE_SFP_BASE_VENDOR_SN_LEN + 1]; 270 } u; 271 }; 272 273 /* MDIO PHY reset types */ 274 enum xgbe_mdio_reset { 275 XGBE_MDIO_RESET_NONE = 0, 276 XGBE_MDIO_RESET_I2C_GPIO, 277 XGBE_MDIO_RESET_INT_GPIO, 278 XGBE_MDIO_RESET_MAX, 279 }; 280 281 /* Re-driver related definitions */ 282 enum xgbe_phy_redrv_if { 283 XGBE_PHY_REDRV_IF_MDIO = 0, 284 XGBE_PHY_REDRV_IF_I2C, 285 XGBE_PHY_REDRV_IF_MAX, 286 }; 287 288 enum xgbe_phy_redrv_model { 289 XGBE_PHY_REDRV_MODEL_4223 = 0, 290 XGBE_PHY_REDRV_MODEL_4227, 291 XGBE_PHY_REDRV_MODEL_MAX, 292 }; 293 294 enum xgbe_phy_redrv_mode { 295 XGBE_PHY_REDRV_MODE_CX = 5, 296 XGBE_PHY_REDRV_MODE_SR = 9, 297 }; 298 299 #define XGBE_PHY_REDRV_MODE_REG 0x12b0 300 301 /* PHY related configuration information */ 302 struct xgbe_phy_data { 303 enum xgbe_port_mode port_mode; 304 305 unsigned int port_id; 306 307 unsigned int port_speeds; 308 309 enum xgbe_conn_type conn_type; 310 311 enum xgbe_mode cur_mode; 312 enum xgbe_mode start_mode; 313 314 unsigned int rrc_count; 315 316 unsigned int mdio_addr; 317 318 unsigned int comm_owned; 319 320 /* SFP Support */ 321 enum xgbe_sfp_comm sfp_comm; 322 unsigned int sfp_mux_address; 323 unsigned int sfp_mux_channel; 324 325 unsigned int sfp_gpio_address; 326 unsigned int sfp_gpio_mask; 327 unsigned int sfp_gpio_rx_los; 328 unsigned int sfp_gpio_tx_fault; 329 unsigned int sfp_gpio_mod_absent; 330 unsigned int sfp_gpio_rate_select; 331 332 unsigned int sfp_rx_los; 333 unsigned int sfp_tx_fault; 334 unsigned int sfp_mod_absent; 335 unsigned int sfp_diags; 336 unsigned int sfp_changed; 337 unsigned int sfp_phy_avail; 338 unsigned int sfp_cable_len; 339 enum xgbe_sfp_base sfp_base; 340 enum xgbe_sfp_cable sfp_cable; 341 enum xgbe_sfp_speed sfp_speed; 342 struct xgbe_sfp_eeprom sfp_eeprom; 343 344 /* External PHY support */ 345 enum xgbe_mdio_mode phydev_mode; 346 struct mii_bus *mii; 347 struct phy_device *phydev; 348 enum xgbe_mdio_reset mdio_reset; 349 unsigned int mdio_reset_addr; 350 unsigned int mdio_reset_gpio; 351 352 /* Re-driver support */ 353 unsigned int redrv; 354 unsigned int redrv_if; 355 unsigned int redrv_addr; 356 unsigned int redrv_lane; 357 unsigned int redrv_model; 358 }; 359 360 /* I2C, MDIO and GPIO lines are muxed, so only one device at a time */ 361 static DEFINE_MUTEX(xgbe_phy_comm_lock); 362 363 static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata); 364 365 static int xgbe_phy_i2c_xfer(struct xgbe_prv_data *pdata, 366 struct xgbe_i2c_op *i2c_op) 367 { 368 struct xgbe_phy_data *phy_data = pdata->phy_data; 369 370 /* Be sure we own the bus */ 371 if (WARN_ON(!phy_data->comm_owned)) 372 return -EIO; 373 374 return pdata->i2c_if.i2c_xfer(pdata, i2c_op); 375 } 376 377 static int xgbe_phy_redrv_write(struct xgbe_prv_data *pdata, unsigned int reg, 378 unsigned int val) 379 { 380 struct xgbe_phy_data *phy_data = pdata->phy_data; 381 struct xgbe_i2c_op i2c_op; 382 __be16 *redrv_val; 383 u8 redrv_data[5], csum; 384 unsigned int i, retry; 385 int ret; 386 387 /* High byte of register contains read/write indicator */ 388 redrv_data[0] = ((reg >> 8) & 0xff) << 1; 389 redrv_data[1] = reg & 0xff; 390 redrv_val = (__be16 *)&redrv_data[2]; 391 *redrv_val = cpu_to_be16(val); 392 393 /* Calculate 1 byte checksum */ 394 csum = 0; 395 for (i = 0; i < 4; i++) { 396 csum += redrv_data[i]; 397 if (redrv_data[i] > csum) 398 csum++; 399 } 400 redrv_data[4] = ~csum; 401 402 retry = 1; 403 again1: 404 i2c_op.cmd = XGBE_I2C_CMD_WRITE; 405 i2c_op.target = phy_data->redrv_addr; 406 i2c_op.len = sizeof(redrv_data); 407 i2c_op.buf = redrv_data; 408 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op); 409 if (ret) { 410 if ((ret == -EAGAIN) && retry--) 411 goto again1; 412 413 return ret; 414 } 415 416 retry = 1; 417 again2: 418 i2c_op.cmd = XGBE_I2C_CMD_READ; 419 i2c_op.target = phy_data->redrv_addr; 420 i2c_op.len = 1; 421 i2c_op.buf = redrv_data; 422 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op); 423 if (ret) { 424 if ((ret == -EAGAIN) && retry--) 425 goto again2; 426 427 return ret; 428 } 429 430 if (redrv_data[0] != 0xff) { 431 netif_dbg(pdata, drv, pdata->netdev, 432 "Redriver write checksum error\n"); 433 ret = -EIO; 434 } 435 436 return ret; 437 } 438 439 static int xgbe_phy_i2c_write(struct xgbe_prv_data *pdata, unsigned int target, 440 void *val, unsigned int val_len) 441 { 442 struct xgbe_i2c_op i2c_op; 443 int retry, ret; 444 445 retry = 1; 446 again: 447 /* Write the specfied register */ 448 i2c_op.cmd = XGBE_I2C_CMD_WRITE; 449 i2c_op.target = target; 450 i2c_op.len = val_len; 451 i2c_op.buf = val; 452 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op); 453 if ((ret == -EAGAIN) && retry--) 454 goto again; 455 456 return ret; 457 } 458 459 static int xgbe_phy_i2c_read(struct xgbe_prv_data *pdata, unsigned int target, 460 void *reg, unsigned int reg_len, 461 void *val, unsigned int val_len) 462 { 463 struct xgbe_i2c_op i2c_op; 464 int retry, ret; 465 466 retry = 1; 467 again1: 468 /* Set the specified register to read */ 469 i2c_op.cmd = XGBE_I2C_CMD_WRITE; 470 i2c_op.target = target; 471 i2c_op.len = reg_len; 472 i2c_op.buf = reg; 473 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op); 474 if (ret) { 475 if ((ret == -EAGAIN) && retry--) 476 goto again1; 477 478 return ret; 479 } 480 481 retry = 1; 482 again2: 483 /* Read the specfied register */ 484 i2c_op.cmd = XGBE_I2C_CMD_READ; 485 i2c_op.target = target; 486 i2c_op.len = val_len; 487 i2c_op.buf = val; 488 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op); 489 if ((ret == -EAGAIN) && retry--) 490 goto again2; 491 492 return ret; 493 } 494 495 static int xgbe_phy_sfp_put_mux(struct xgbe_prv_data *pdata) 496 { 497 struct xgbe_phy_data *phy_data = pdata->phy_data; 498 struct xgbe_i2c_op i2c_op; 499 u8 mux_channel; 500 501 if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT) 502 return 0; 503 504 /* Select no mux channels */ 505 mux_channel = 0; 506 i2c_op.cmd = XGBE_I2C_CMD_WRITE; 507 i2c_op.target = phy_data->sfp_mux_address; 508 i2c_op.len = sizeof(mux_channel); 509 i2c_op.buf = &mux_channel; 510 511 return xgbe_phy_i2c_xfer(pdata, &i2c_op); 512 } 513 514 static int xgbe_phy_sfp_get_mux(struct xgbe_prv_data *pdata) 515 { 516 struct xgbe_phy_data *phy_data = pdata->phy_data; 517 struct xgbe_i2c_op i2c_op; 518 u8 mux_channel; 519 520 if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT) 521 return 0; 522 523 /* Select desired mux channel */ 524 mux_channel = 1 << phy_data->sfp_mux_channel; 525 i2c_op.cmd = XGBE_I2C_CMD_WRITE; 526 i2c_op.target = phy_data->sfp_mux_address; 527 i2c_op.len = sizeof(mux_channel); 528 i2c_op.buf = &mux_channel; 529 530 return xgbe_phy_i2c_xfer(pdata, &i2c_op); 531 } 532 533 static void xgbe_phy_put_comm_ownership(struct xgbe_prv_data *pdata) 534 { 535 struct xgbe_phy_data *phy_data = pdata->phy_data; 536 537 phy_data->comm_owned = 0; 538 539 mutex_unlock(&xgbe_phy_comm_lock); 540 } 541 542 static int xgbe_phy_get_comm_ownership(struct xgbe_prv_data *pdata) 543 { 544 struct xgbe_phy_data *phy_data = pdata->phy_data; 545 unsigned long timeout; 546 unsigned int mutex_id; 547 548 if (phy_data->comm_owned) 549 return 0; 550 551 /* The I2C and MDIO/GPIO bus is multiplexed between multiple devices, 552 * the driver needs to take the software mutex and then the hardware 553 * mutexes before being able to use the busses. 554 */ 555 mutex_lock(&xgbe_phy_comm_lock); 556 557 /* Clear the mutexes */ 558 XP_IOWRITE(pdata, XP_I2C_MUTEX, XGBE_MUTEX_RELEASE); 559 XP_IOWRITE(pdata, XP_MDIO_MUTEX, XGBE_MUTEX_RELEASE); 560 561 /* Mutex formats are the same for I2C and MDIO/GPIO */ 562 mutex_id = 0; 563 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ID, phy_data->port_id); 564 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ACTIVE, 1); 565 566 timeout = jiffies + (5 * HZ); 567 while (time_before(jiffies, timeout)) { 568 /* Must be all zeroes in order to obtain the mutex */ 569 if (XP_IOREAD(pdata, XP_I2C_MUTEX) || 570 XP_IOREAD(pdata, XP_MDIO_MUTEX)) { 571 usleep_range(100, 200); 572 continue; 573 } 574 575 /* Obtain the mutex */ 576 XP_IOWRITE(pdata, XP_I2C_MUTEX, mutex_id); 577 XP_IOWRITE(pdata, XP_MDIO_MUTEX, mutex_id); 578 579 phy_data->comm_owned = 1; 580 return 0; 581 } 582 583 mutex_unlock(&xgbe_phy_comm_lock); 584 585 netdev_err(pdata->netdev, "unable to obtain hardware mutexes\n"); 586 587 return -ETIMEDOUT; 588 } 589 590 static int xgbe_phy_mdio_mii_write(struct xgbe_prv_data *pdata, int addr, 591 int reg, u16 val) 592 { 593 struct xgbe_phy_data *phy_data = pdata->phy_data; 594 595 if (reg & MII_ADDR_C45) { 596 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45) 597 return -ENOTSUPP; 598 } else { 599 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22) 600 return -ENOTSUPP; 601 } 602 603 return pdata->hw_if.write_ext_mii_regs(pdata, addr, reg, val); 604 } 605 606 static int xgbe_phy_i2c_mii_write(struct xgbe_prv_data *pdata, int reg, u16 val) 607 { 608 __be16 *mii_val; 609 u8 mii_data[3]; 610 int ret; 611 612 ret = xgbe_phy_sfp_get_mux(pdata); 613 if (ret) 614 return ret; 615 616 mii_data[0] = reg & 0xff; 617 mii_val = (__be16 *)&mii_data[1]; 618 *mii_val = cpu_to_be16(val); 619 620 ret = xgbe_phy_i2c_write(pdata, XGBE_SFP_PHY_ADDRESS, 621 mii_data, sizeof(mii_data)); 622 623 xgbe_phy_sfp_put_mux(pdata); 624 625 return ret; 626 } 627 628 static int xgbe_phy_mii_write(struct mii_bus *mii, int addr, int reg, u16 val) 629 { 630 struct xgbe_prv_data *pdata = mii->priv; 631 struct xgbe_phy_data *phy_data = pdata->phy_data; 632 int ret; 633 634 ret = xgbe_phy_get_comm_ownership(pdata); 635 if (ret) 636 return ret; 637 638 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP) 639 ret = xgbe_phy_i2c_mii_write(pdata, reg, val); 640 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO) 641 ret = xgbe_phy_mdio_mii_write(pdata, addr, reg, val); 642 else 643 ret = -ENOTSUPP; 644 645 xgbe_phy_put_comm_ownership(pdata); 646 647 return ret; 648 } 649 650 static int xgbe_phy_mdio_mii_read(struct xgbe_prv_data *pdata, int addr, 651 int reg) 652 { 653 struct xgbe_phy_data *phy_data = pdata->phy_data; 654 655 if (reg & MII_ADDR_C45) { 656 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45) 657 return -ENOTSUPP; 658 } else { 659 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22) 660 return -ENOTSUPP; 661 } 662 663 return pdata->hw_if.read_ext_mii_regs(pdata, addr, reg); 664 } 665 666 static int xgbe_phy_i2c_mii_read(struct xgbe_prv_data *pdata, int reg) 667 { 668 __be16 mii_val; 669 u8 mii_reg; 670 int ret; 671 672 ret = xgbe_phy_sfp_get_mux(pdata); 673 if (ret) 674 return ret; 675 676 mii_reg = reg; 677 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_PHY_ADDRESS, 678 &mii_reg, sizeof(mii_reg), 679 &mii_val, sizeof(mii_val)); 680 if (!ret) 681 ret = be16_to_cpu(mii_val); 682 683 xgbe_phy_sfp_put_mux(pdata); 684 685 return ret; 686 } 687 688 static int xgbe_phy_mii_read(struct mii_bus *mii, int addr, int reg) 689 { 690 struct xgbe_prv_data *pdata = mii->priv; 691 struct xgbe_phy_data *phy_data = pdata->phy_data; 692 int ret; 693 694 ret = xgbe_phy_get_comm_ownership(pdata); 695 if (ret) 696 return ret; 697 698 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP) 699 ret = xgbe_phy_i2c_mii_read(pdata, reg); 700 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO) 701 ret = xgbe_phy_mdio_mii_read(pdata, addr, reg); 702 else 703 ret = -ENOTSUPP; 704 705 xgbe_phy_put_comm_ownership(pdata); 706 707 return ret; 708 } 709 710 static void xgbe_phy_sfp_phy_settings(struct xgbe_prv_data *pdata) 711 { 712 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 713 struct xgbe_phy_data *phy_data = pdata->phy_data; 714 715 if (!phy_data->sfp_mod_absent && !phy_data->sfp_changed) 716 return; 717 718 XGBE_ZERO_SUP(lks); 719 720 if (phy_data->sfp_mod_absent) { 721 pdata->phy.speed = SPEED_UNKNOWN; 722 pdata->phy.duplex = DUPLEX_UNKNOWN; 723 pdata->phy.autoneg = AUTONEG_ENABLE; 724 pdata->phy.pause_autoneg = AUTONEG_ENABLE; 725 726 XGBE_SET_SUP(lks, Autoneg); 727 XGBE_SET_SUP(lks, Pause); 728 XGBE_SET_SUP(lks, Asym_Pause); 729 XGBE_SET_SUP(lks, TP); 730 XGBE_SET_SUP(lks, FIBRE); 731 732 XGBE_LM_COPY(lks, advertising, lks, supported); 733 734 return; 735 } 736 737 switch (phy_data->sfp_base) { 738 case XGBE_SFP_BASE_1000_T: 739 case XGBE_SFP_BASE_1000_SX: 740 case XGBE_SFP_BASE_1000_LX: 741 case XGBE_SFP_BASE_1000_CX: 742 pdata->phy.speed = SPEED_UNKNOWN; 743 pdata->phy.duplex = DUPLEX_UNKNOWN; 744 pdata->phy.autoneg = AUTONEG_ENABLE; 745 pdata->phy.pause_autoneg = AUTONEG_ENABLE; 746 XGBE_SET_SUP(lks, Autoneg); 747 XGBE_SET_SUP(lks, Pause); 748 XGBE_SET_SUP(lks, Asym_Pause); 749 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T) { 750 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) 751 XGBE_SET_SUP(lks, 100baseT_Full); 752 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) 753 XGBE_SET_SUP(lks, 1000baseT_Full); 754 } else { 755 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) 756 XGBE_SET_SUP(lks, 1000baseX_Full); 757 } 758 break; 759 case XGBE_SFP_BASE_10000_SR: 760 case XGBE_SFP_BASE_10000_LR: 761 case XGBE_SFP_BASE_10000_LRM: 762 case XGBE_SFP_BASE_10000_ER: 763 case XGBE_SFP_BASE_10000_CR: 764 pdata->phy.speed = SPEED_10000; 765 pdata->phy.duplex = DUPLEX_FULL; 766 pdata->phy.autoneg = AUTONEG_DISABLE; 767 pdata->phy.pause_autoneg = AUTONEG_DISABLE; 768 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) { 769 switch (phy_data->sfp_base) { 770 case XGBE_SFP_BASE_10000_SR: 771 XGBE_SET_SUP(lks, 10000baseSR_Full); 772 break; 773 case XGBE_SFP_BASE_10000_LR: 774 XGBE_SET_SUP(lks, 10000baseLR_Full); 775 break; 776 case XGBE_SFP_BASE_10000_LRM: 777 XGBE_SET_SUP(lks, 10000baseLRM_Full); 778 break; 779 case XGBE_SFP_BASE_10000_ER: 780 XGBE_SET_SUP(lks, 10000baseER_Full); 781 break; 782 case XGBE_SFP_BASE_10000_CR: 783 XGBE_SET_SUP(lks, 10000baseCR_Full); 784 break; 785 default: 786 break; 787 } 788 } 789 break; 790 default: 791 pdata->phy.speed = SPEED_UNKNOWN; 792 pdata->phy.duplex = DUPLEX_UNKNOWN; 793 pdata->phy.autoneg = AUTONEG_DISABLE; 794 pdata->phy.pause_autoneg = AUTONEG_DISABLE; 795 break; 796 } 797 798 switch (phy_data->sfp_base) { 799 case XGBE_SFP_BASE_1000_T: 800 case XGBE_SFP_BASE_1000_CX: 801 case XGBE_SFP_BASE_10000_CR: 802 XGBE_SET_SUP(lks, TP); 803 break; 804 default: 805 XGBE_SET_SUP(lks, FIBRE); 806 break; 807 } 808 809 XGBE_LM_COPY(lks, advertising, lks, supported); 810 } 811 812 static bool xgbe_phy_sfp_bit_rate(struct xgbe_sfp_eeprom *sfp_eeprom, 813 enum xgbe_sfp_speed sfp_speed) 814 { 815 u8 *sfp_base, min, max; 816 817 sfp_base = sfp_eeprom->base; 818 819 switch (sfp_speed) { 820 case XGBE_SFP_SPEED_1000: 821 min = XGBE_SFP_BASE_BR_1GBE_MIN; 822 max = XGBE_SFP_BASE_BR_1GBE_MAX; 823 break; 824 case XGBE_SFP_SPEED_10000: 825 min = XGBE_SFP_BASE_BR_10GBE_MIN; 826 max = XGBE_SFP_BASE_BR_10GBE_MAX; 827 break; 828 default: 829 return false; 830 } 831 832 return ((sfp_base[XGBE_SFP_BASE_BR] >= min) && 833 (sfp_base[XGBE_SFP_BASE_BR] <= max)); 834 } 835 836 static void xgbe_phy_free_phy_device(struct xgbe_prv_data *pdata) 837 { 838 struct xgbe_phy_data *phy_data = pdata->phy_data; 839 840 if (phy_data->phydev) { 841 phy_detach(phy_data->phydev); 842 phy_device_remove(phy_data->phydev); 843 phy_device_free(phy_data->phydev); 844 phy_data->phydev = NULL; 845 } 846 } 847 848 static bool xgbe_phy_finisar_phy_quirks(struct xgbe_prv_data *pdata) 849 { 850 struct xgbe_phy_data *phy_data = pdata->phy_data; 851 unsigned int phy_id = phy_data->phydev->phy_id; 852 853 if ((phy_id & 0xfffffff0) != 0x01ff0cc0) 854 return false; 855 856 /* Enable Base-T AN */ 857 phy_write(phy_data->phydev, 0x16, 0x0001); 858 phy_write(phy_data->phydev, 0x00, 0x9140); 859 phy_write(phy_data->phydev, 0x16, 0x0000); 860 861 /* Enable SGMII at 100Base-T/1000Base-T Full Duplex */ 862 phy_write(phy_data->phydev, 0x1b, 0x9084); 863 phy_write(phy_data->phydev, 0x09, 0x0e00); 864 phy_write(phy_data->phydev, 0x00, 0x8140); 865 phy_write(phy_data->phydev, 0x04, 0x0d01); 866 phy_write(phy_data->phydev, 0x00, 0x9140); 867 868 phy_data->phydev->supported = PHY_GBIT_FEATURES; 869 phy_data->phydev->supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 870 phy_data->phydev->advertising = phy_data->phydev->supported; 871 872 netif_dbg(pdata, drv, pdata->netdev, 873 "Finisar PHY quirk in place\n"); 874 875 return true; 876 } 877 878 static void xgbe_phy_external_phy_quirks(struct xgbe_prv_data *pdata) 879 { 880 if (xgbe_phy_finisar_phy_quirks(pdata)) 881 return; 882 } 883 884 static int xgbe_phy_find_phy_device(struct xgbe_prv_data *pdata) 885 { 886 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 887 struct xgbe_phy_data *phy_data = pdata->phy_data; 888 struct phy_device *phydev; 889 u32 advertising; 890 int ret; 891 892 /* If we already have a PHY, just return */ 893 if (phy_data->phydev) 894 return 0; 895 896 /* Check for the use of an external PHY */ 897 if (phy_data->phydev_mode == XGBE_MDIO_MODE_NONE) 898 return 0; 899 900 /* For SFP, only use an external PHY if available */ 901 if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) && 902 !phy_data->sfp_phy_avail) 903 return 0; 904 905 /* Set the proper MDIO mode for the PHY */ 906 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr, 907 phy_data->phydev_mode); 908 if (ret) { 909 netdev_err(pdata->netdev, 910 "mdio port/clause not compatible (%u/%u)\n", 911 phy_data->mdio_addr, phy_data->phydev_mode); 912 return ret; 913 } 914 915 /* Create and connect to the PHY device */ 916 phydev = get_phy_device(phy_data->mii, phy_data->mdio_addr, 917 (phy_data->phydev_mode == XGBE_MDIO_MODE_CL45)); 918 if (IS_ERR(phydev)) { 919 netdev_err(pdata->netdev, "get_phy_device failed\n"); 920 return -ENODEV; 921 } 922 netif_dbg(pdata, drv, pdata->netdev, "external PHY id is %#010x\n", 923 phydev->phy_id); 924 925 /*TODO: If c45, add request_module based on one of the MMD ids? */ 926 927 ret = phy_device_register(phydev); 928 if (ret) { 929 netdev_err(pdata->netdev, "phy_device_register failed\n"); 930 phy_device_free(phydev); 931 return ret; 932 } 933 934 ret = phy_attach_direct(pdata->netdev, phydev, phydev->dev_flags, 935 PHY_INTERFACE_MODE_SGMII); 936 if (ret) { 937 netdev_err(pdata->netdev, "phy_attach_direct failed\n"); 938 phy_device_remove(phydev); 939 phy_device_free(phydev); 940 return ret; 941 } 942 phy_data->phydev = phydev; 943 944 xgbe_phy_external_phy_quirks(pdata); 945 946 ethtool_convert_link_mode_to_legacy_u32(&advertising, 947 lks->link_modes.advertising); 948 phydev->advertising &= advertising; 949 950 phy_start_aneg(phy_data->phydev); 951 952 return 0; 953 } 954 955 static void xgbe_phy_sfp_external_phy(struct xgbe_prv_data *pdata) 956 { 957 struct xgbe_phy_data *phy_data = pdata->phy_data; 958 int ret; 959 960 if (!phy_data->sfp_changed) 961 return; 962 963 phy_data->sfp_phy_avail = 0; 964 965 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T) 966 return; 967 968 /* Check access to the PHY by reading CTRL1 */ 969 ret = xgbe_phy_i2c_mii_read(pdata, MII_BMCR); 970 if (ret < 0) 971 return; 972 973 /* Successfully accessed the PHY */ 974 phy_data->sfp_phy_avail = 1; 975 } 976 977 static bool xgbe_phy_belfuse_parse_quirks(struct xgbe_prv_data *pdata) 978 { 979 struct xgbe_phy_data *phy_data = pdata->phy_data; 980 struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom; 981 982 if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME], 983 XGBE_BEL_FUSE_VENDOR, XGBE_SFP_BASE_VENDOR_NAME_LEN)) 984 return false; 985 986 if (!memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN], 987 XGBE_BEL_FUSE_PARTNO, XGBE_SFP_BASE_VENDOR_PN_LEN)) { 988 phy_data->sfp_base = XGBE_SFP_BASE_1000_SX; 989 phy_data->sfp_cable = XGBE_SFP_CABLE_ACTIVE; 990 phy_data->sfp_speed = XGBE_SFP_SPEED_1000; 991 if (phy_data->sfp_changed) 992 netif_dbg(pdata, drv, pdata->netdev, 993 "Bel-Fuse SFP quirk in place\n"); 994 return true; 995 } 996 997 return false; 998 } 999 1000 static bool xgbe_phy_sfp_parse_quirks(struct xgbe_prv_data *pdata) 1001 { 1002 if (xgbe_phy_belfuse_parse_quirks(pdata)) 1003 return true; 1004 1005 return false; 1006 } 1007 1008 static void xgbe_phy_sfp_parse_eeprom(struct xgbe_prv_data *pdata) 1009 { 1010 struct xgbe_phy_data *phy_data = pdata->phy_data; 1011 struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom; 1012 u8 *sfp_base; 1013 1014 sfp_base = sfp_eeprom->base; 1015 1016 if (sfp_base[XGBE_SFP_BASE_ID] != XGBE_SFP_ID_SFP) 1017 return; 1018 1019 if (sfp_base[XGBE_SFP_BASE_EXT_ID] != XGBE_SFP_EXT_ID_SFP) 1020 return; 1021 1022 if (xgbe_phy_sfp_parse_quirks(pdata)) 1023 return; 1024 1025 /* Assume ACTIVE cable unless told it is PASSIVE */ 1026 if (sfp_base[XGBE_SFP_BASE_CABLE] & XGBE_SFP_BASE_CABLE_PASSIVE) { 1027 phy_data->sfp_cable = XGBE_SFP_CABLE_PASSIVE; 1028 phy_data->sfp_cable_len = sfp_base[XGBE_SFP_BASE_CU_CABLE_LEN]; 1029 } else { 1030 phy_data->sfp_cable = XGBE_SFP_CABLE_ACTIVE; 1031 } 1032 1033 /* Determine the type of SFP */ 1034 if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_SR) 1035 phy_data->sfp_base = XGBE_SFP_BASE_10000_SR; 1036 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LR) 1037 phy_data->sfp_base = XGBE_SFP_BASE_10000_LR; 1038 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LRM) 1039 phy_data->sfp_base = XGBE_SFP_BASE_10000_LRM; 1040 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_ER) 1041 phy_data->sfp_base = XGBE_SFP_BASE_10000_ER; 1042 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_SX) 1043 phy_data->sfp_base = XGBE_SFP_BASE_1000_SX; 1044 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_LX) 1045 phy_data->sfp_base = XGBE_SFP_BASE_1000_LX; 1046 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_CX) 1047 phy_data->sfp_base = XGBE_SFP_BASE_1000_CX; 1048 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_T) 1049 phy_data->sfp_base = XGBE_SFP_BASE_1000_T; 1050 else if ((phy_data->sfp_cable == XGBE_SFP_CABLE_PASSIVE) && 1051 xgbe_phy_sfp_bit_rate(sfp_eeprom, XGBE_SFP_SPEED_10000)) 1052 phy_data->sfp_base = XGBE_SFP_BASE_10000_CR; 1053 1054 switch (phy_data->sfp_base) { 1055 case XGBE_SFP_BASE_1000_T: 1056 phy_data->sfp_speed = XGBE_SFP_SPEED_100_1000; 1057 break; 1058 case XGBE_SFP_BASE_1000_SX: 1059 case XGBE_SFP_BASE_1000_LX: 1060 case XGBE_SFP_BASE_1000_CX: 1061 phy_data->sfp_speed = XGBE_SFP_SPEED_1000; 1062 break; 1063 case XGBE_SFP_BASE_10000_SR: 1064 case XGBE_SFP_BASE_10000_LR: 1065 case XGBE_SFP_BASE_10000_LRM: 1066 case XGBE_SFP_BASE_10000_ER: 1067 case XGBE_SFP_BASE_10000_CR: 1068 phy_data->sfp_speed = XGBE_SFP_SPEED_10000; 1069 break; 1070 default: 1071 break; 1072 } 1073 } 1074 1075 static void xgbe_phy_sfp_eeprom_info(struct xgbe_prv_data *pdata, 1076 struct xgbe_sfp_eeprom *sfp_eeprom) 1077 { 1078 struct xgbe_sfp_ascii sfp_ascii; 1079 char *sfp_data = (char *)&sfp_ascii; 1080 1081 netif_dbg(pdata, drv, pdata->netdev, "SFP detected:\n"); 1082 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME], 1083 XGBE_SFP_BASE_VENDOR_NAME_LEN); 1084 sfp_data[XGBE_SFP_BASE_VENDOR_NAME_LEN] = '\0'; 1085 netif_dbg(pdata, drv, pdata->netdev, " vendor: %s\n", 1086 sfp_data); 1087 1088 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN], 1089 XGBE_SFP_BASE_VENDOR_PN_LEN); 1090 sfp_data[XGBE_SFP_BASE_VENDOR_PN_LEN] = '\0'; 1091 netif_dbg(pdata, drv, pdata->netdev, " part number: %s\n", 1092 sfp_data); 1093 1094 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_REV], 1095 XGBE_SFP_BASE_VENDOR_REV_LEN); 1096 sfp_data[XGBE_SFP_BASE_VENDOR_REV_LEN] = '\0'; 1097 netif_dbg(pdata, drv, pdata->netdev, " revision level: %s\n", 1098 sfp_data); 1099 1100 memcpy(sfp_data, &sfp_eeprom->extd[XGBE_SFP_BASE_VENDOR_SN], 1101 XGBE_SFP_BASE_VENDOR_SN_LEN); 1102 sfp_data[XGBE_SFP_BASE_VENDOR_SN_LEN] = '\0'; 1103 netif_dbg(pdata, drv, pdata->netdev, " serial number: %s\n", 1104 sfp_data); 1105 } 1106 1107 static bool xgbe_phy_sfp_verify_eeprom(u8 cc_in, u8 *buf, unsigned int len) 1108 { 1109 u8 cc; 1110 1111 for (cc = 0; len; buf++, len--) 1112 cc += *buf; 1113 1114 return (cc == cc_in) ? true : false; 1115 } 1116 1117 static int xgbe_phy_sfp_read_eeprom(struct xgbe_prv_data *pdata) 1118 { 1119 struct xgbe_phy_data *phy_data = pdata->phy_data; 1120 struct xgbe_sfp_eeprom sfp_eeprom; 1121 u8 eeprom_addr; 1122 int ret; 1123 1124 ret = xgbe_phy_sfp_get_mux(pdata); 1125 if (ret) { 1126 dev_err_once(pdata->dev, "%s: I2C error setting SFP MUX\n", 1127 netdev_name(pdata->netdev)); 1128 return ret; 1129 } 1130 1131 /* Read the SFP serial ID eeprom */ 1132 eeprom_addr = 0; 1133 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_SERIAL_ID_ADDRESS, 1134 &eeprom_addr, sizeof(eeprom_addr), 1135 &sfp_eeprom, sizeof(sfp_eeprom)); 1136 if (ret) { 1137 dev_err_once(pdata->dev, "%s: I2C error reading SFP EEPROM\n", 1138 netdev_name(pdata->netdev)); 1139 goto put; 1140 } 1141 1142 /* Validate the contents read */ 1143 if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.base[XGBE_SFP_BASE_CC], 1144 sfp_eeprom.base, 1145 sizeof(sfp_eeprom.base) - 1)) { 1146 ret = -EINVAL; 1147 goto put; 1148 } 1149 1150 if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.extd[XGBE_SFP_EXTD_CC], 1151 sfp_eeprom.extd, 1152 sizeof(sfp_eeprom.extd) - 1)) { 1153 ret = -EINVAL; 1154 goto put; 1155 } 1156 1157 /* Check for an added or changed SFP */ 1158 if (memcmp(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom))) { 1159 phy_data->sfp_changed = 1; 1160 1161 if (netif_msg_drv(pdata)) 1162 xgbe_phy_sfp_eeprom_info(pdata, &sfp_eeprom); 1163 1164 memcpy(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom)); 1165 1166 if (sfp_eeprom.extd[XGBE_SFP_EXTD_SFF_8472]) { 1167 u8 diag_type = sfp_eeprom.extd[XGBE_SFP_EXTD_DIAG]; 1168 1169 if (!(diag_type & XGBE_SFP_EXTD_DIAG_ADDR_CHANGE)) 1170 phy_data->sfp_diags = 1; 1171 } 1172 1173 xgbe_phy_free_phy_device(pdata); 1174 } else { 1175 phy_data->sfp_changed = 0; 1176 } 1177 1178 put: 1179 xgbe_phy_sfp_put_mux(pdata); 1180 1181 return ret; 1182 } 1183 1184 static void xgbe_phy_sfp_signals(struct xgbe_prv_data *pdata) 1185 { 1186 struct xgbe_phy_data *phy_data = pdata->phy_data; 1187 unsigned int gpio_input; 1188 u8 gpio_reg, gpio_ports[2]; 1189 int ret; 1190 1191 /* Read the input port registers */ 1192 gpio_reg = 0; 1193 ret = xgbe_phy_i2c_read(pdata, phy_data->sfp_gpio_address, 1194 &gpio_reg, sizeof(gpio_reg), 1195 gpio_ports, sizeof(gpio_ports)); 1196 if (ret) { 1197 dev_err_once(pdata->dev, "%s: I2C error reading SFP GPIOs\n", 1198 netdev_name(pdata->netdev)); 1199 return; 1200 } 1201 1202 gpio_input = (gpio_ports[1] << 8) | gpio_ports[0]; 1203 1204 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_MOD_ABSENT) { 1205 /* No GPIO, just assume the module is present for now */ 1206 phy_data->sfp_mod_absent = 0; 1207 } else { 1208 if (!(gpio_input & (1 << phy_data->sfp_gpio_mod_absent))) 1209 phy_data->sfp_mod_absent = 0; 1210 } 1211 1212 if (!(phy_data->sfp_gpio_mask & XGBE_GPIO_NO_RX_LOS) && 1213 (gpio_input & (1 << phy_data->sfp_gpio_rx_los))) 1214 phy_data->sfp_rx_los = 1; 1215 1216 if (!(phy_data->sfp_gpio_mask & XGBE_GPIO_NO_TX_FAULT) && 1217 (gpio_input & (1 << phy_data->sfp_gpio_tx_fault))) 1218 phy_data->sfp_tx_fault = 1; 1219 } 1220 1221 static void xgbe_phy_sfp_mod_absent(struct xgbe_prv_data *pdata) 1222 { 1223 struct xgbe_phy_data *phy_data = pdata->phy_data; 1224 1225 xgbe_phy_free_phy_device(pdata); 1226 1227 phy_data->sfp_mod_absent = 1; 1228 phy_data->sfp_phy_avail = 0; 1229 memset(&phy_data->sfp_eeprom, 0, sizeof(phy_data->sfp_eeprom)); 1230 } 1231 1232 static void xgbe_phy_sfp_reset(struct xgbe_phy_data *phy_data) 1233 { 1234 phy_data->sfp_rx_los = 0; 1235 phy_data->sfp_tx_fault = 0; 1236 phy_data->sfp_mod_absent = 1; 1237 phy_data->sfp_diags = 0; 1238 phy_data->sfp_base = XGBE_SFP_BASE_UNKNOWN; 1239 phy_data->sfp_cable = XGBE_SFP_CABLE_UNKNOWN; 1240 phy_data->sfp_speed = XGBE_SFP_SPEED_UNKNOWN; 1241 } 1242 1243 static void xgbe_phy_sfp_detect(struct xgbe_prv_data *pdata) 1244 { 1245 struct xgbe_phy_data *phy_data = pdata->phy_data; 1246 int ret; 1247 1248 /* Reset the SFP signals and info */ 1249 xgbe_phy_sfp_reset(phy_data); 1250 1251 ret = xgbe_phy_get_comm_ownership(pdata); 1252 if (ret) 1253 return; 1254 1255 /* Read the SFP signals and check for module presence */ 1256 xgbe_phy_sfp_signals(pdata); 1257 if (phy_data->sfp_mod_absent) { 1258 xgbe_phy_sfp_mod_absent(pdata); 1259 goto put; 1260 } 1261 1262 ret = xgbe_phy_sfp_read_eeprom(pdata); 1263 if (ret) { 1264 /* Treat any error as if there isn't an SFP plugged in */ 1265 xgbe_phy_sfp_reset(phy_data); 1266 xgbe_phy_sfp_mod_absent(pdata); 1267 goto put; 1268 } 1269 1270 xgbe_phy_sfp_parse_eeprom(pdata); 1271 1272 xgbe_phy_sfp_external_phy(pdata); 1273 1274 put: 1275 xgbe_phy_sfp_phy_settings(pdata); 1276 1277 xgbe_phy_put_comm_ownership(pdata); 1278 } 1279 1280 static void xgbe_phy_phydev_flowctrl(struct xgbe_prv_data *pdata) 1281 { 1282 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 1283 struct xgbe_phy_data *phy_data = pdata->phy_data; 1284 u16 lcl_adv = 0, rmt_adv = 0; 1285 u8 fc; 1286 1287 pdata->phy.tx_pause = 0; 1288 pdata->phy.rx_pause = 0; 1289 1290 if (!phy_data->phydev) 1291 return; 1292 1293 if (phy_data->phydev->advertising & ADVERTISED_Pause) 1294 lcl_adv |= ADVERTISE_PAUSE_CAP; 1295 if (phy_data->phydev->advertising & ADVERTISED_Asym_Pause) 1296 lcl_adv |= ADVERTISE_PAUSE_ASYM; 1297 1298 if (phy_data->phydev->pause) { 1299 XGBE_SET_LP_ADV(lks, Pause); 1300 rmt_adv |= LPA_PAUSE_CAP; 1301 } 1302 if (phy_data->phydev->asym_pause) { 1303 XGBE_SET_LP_ADV(lks, Asym_Pause); 1304 rmt_adv |= LPA_PAUSE_ASYM; 1305 } 1306 1307 fc = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv); 1308 if (fc & FLOW_CTRL_TX) 1309 pdata->phy.tx_pause = 1; 1310 if (fc & FLOW_CTRL_RX) 1311 pdata->phy.rx_pause = 1; 1312 } 1313 1314 static enum xgbe_mode xgbe_phy_an37_sgmii_outcome(struct xgbe_prv_data *pdata) 1315 { 1316 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 1317 enum xgbe_mode mode; 1318 1319 XGBE_SET_LP_ADV(lks, Autoneg); 1320 XGBE_SET_LP_ADV(lks, TP); 1321 1322 /* Use external PHY to determine flow control */ 1323 if (pdata->phy.pause_autoneg) 1324 xgbe_phy_phydev_flowctrl(pdata); 1325 1326 switch (pdata->an_status & XGBE_SGMII_AN_LINK_SPEED) { 1327 case XGBE_SGMII_AN_LINK_SPEED_100: 1328 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) { 1329 XGBE_SET_LP_ADV(lks, 100baseT_Full); 1330 mode = XGBE_MODE_SGMII_100; 1331 } else { 1332 /* Half-duplex not supported */ 1333 XGBE_SET_LP_ADV(lks, 100baseT_Half); 1334 mode = XGBE_MODE_UNKNOWN; 1335 } 1336 break; 1337 case XGBE_SGMII_AN_LINK_SPEED_1000: 1338 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) { 1339 XGBE_SET_LP_ADV(lks, 1000baseT_Full); 1340 mode = XGBE_MODE_SGMII_1000; 1341 } else { 1342 /* Half-duplex not supported */ 1343 XGBE_SET_LP_ADV(lks, 1000baseT_Half); 1344 mode = XGBE_MODE_UNKNOWN; 1345 } 1346 break; 1347 default: 1348 mode = XGBE_MODE_UNKNOWN; 1349 } 1350 1351 return mode; 1352 } 1353 1354 static enum xgbe_mode xgbe_phy_an37_outcome(struct xgbe_prv_data *pdata) 1355 { 1356 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 1357 enum xgbe_mode mode; 1358 unsigned int ad_reg, lp_reg; 1359 1360 XGBE_SET_LP_ADV(lks, Autoneg); 1361 XGBE_SET_LP_ADV(lks, FIBRE); 1362 1363 /* Compare Advertisement and Link Partner register */ 1364 ad_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE); 1365 lp_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_LP_ABILITY); 1366 if (lp_reg & 0x100) 1367 XGBE_SET_LP_ADV(lks, Pause); 1368 if (lp_reg & 0x80) 1369 XGBE_SET_LP_ADV(lks, Asym_Pause); 1370 1371 if (pdata->phy.pause_autoneg) { 1372 /* Set flow control based on auto-negotiation result */ 1373 pdata->phy.tx_pause = 0; 1374 pdata->phy.rx_pause = 0; 1375 1376 if (ad_reg & lp_reg & 0x100) { 1377 pdata->phy.tx_pause = 1; 1378 pdata->phy.rx_pause = 1; 1379 } else if (ad_reg & lp_reg & 0x80) { 1380 if (ad_reg & 0x100) 1381 pdata->phy.rx_pause = 1; 1382 else if (lp_reg & 0x100) 1383 pdata->phy.tx_pause = 1; 1384 } 1385 } 1386 1387 if (lp_reg & 0x20) 1388 XGBE_SET_LP_ADV(lks, 1000baseX_Full); 1389 1390 /* Half duplex is not supported */ 1391 ad_reg &= lp_reg; 1392 mode = (ad_reg & 0x20) ? XGBE_MODE_X : XGBE_MODE_UNKNOWN; 1393 1394 return mode; 1395 } 1396 1397 static enum xgbe_mode xgbe_phy_an73_redrv_outcome(struct xgbe_prv_data *pdata) 1398 { 1399 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 1400 struct xgbe_phy_data *phy_data = pdata->phy_data; 1401 enum xgbe_mode mode; 1402 unsigned int ad_reg, lp_reg; 1403 1404 XGBE_SET_LP_ADV(lks, Autoneg); 1405 XGBE_SET_LP_ADV(lks, Backplane); 1406 1407 /* Use external PHY to determine flow control */ 1408 if (pdata->phy.pause_autoneg) 1409 xgbe_phy_phydev_flowctrl(pdata); 1410 1411 /* Compare Advertisement and Link Partner register 2 */ 1412 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); 1413 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); 1414 if (lp_reg & 0x80) 1415 XGBE_SET_LP_ADV(lks, 10000baseKR_Full); 1416 if (lp_reg & 0x20) 1417 XGBE_SET_LP_ADV(lks, 1000baseKX_Full); 1418 1419 ad_reg &= lp_reg; 1420 if (ad_reg & 0x80) { 1421 switch (phy_data->port_mode) { 1422 case XGBE_PORT_MODE_BACKPLANE: 1423 mode = XGBE_MODE_KR; 1424 break; 1425 default: 1426 mode = XGBE_MODE_SFI; 1427 break; 1428 } 1429 } else if (ad_reg & 0x20) { 1430 switch (phy_data->port_mode) { 1431 case XGBE_PORT_MODE_BACKPLANE: 1432 mode = XGBE_MODE_KX_1000; 1433 break; 1434 case XGBE_PORT_MODE_1000BASE_X: 1435 mode = XGBE_MODE_X; 1436 break; 1437 case XGBE_PORT_MODE_SFP: 1438 switch (phy_data->sfp_base) { 1439 case XGBE_SFP_BASE_1000_T: 1440 if (phy_data->phydev && 1441 (phy_data->phydev->speed == SPEED_100)) 1442 mode = XGBE_MODE_SGMII_100; 1443 else 1444 mode = XGBE_MODE_SGMII_1000; 1445 break; 1446 case XGBE_SFP_BASE_1000_SX: 1447 case XGBE_SFP_BASE_1000_LX: 1448 case XGBE_SFP_BASE_1000_CX: 1449 default: 1450 mode = XGBE_MODE_X; 1451 break; 1452 } 1453 break; 1454 default: 1455 if (phy_data->phydev && 1456 (phy_data->phydev->speed == SPEED_100)) 1457 mode = XGBE_MODE_SGMII_100; 1458 else 1459 mode = XGBE_MODE_SGMII_1000; 1460 break; 1461 } 1462 } else { 1463 mode = XGBE_MODE_UNKNOWN; 1464 } 1465 1466 /* Compare Advertisement and Link Partner register 3 */ 1467 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); 1468 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); 1469 if (lp_reg & 0xc000) 1470 XGBE_SET_LP_ADV(lks, 10000baseR_FEC); 1471 1472 return mode; 1473 } 1474 1475 static enum xgbe_mode xgbe_phy_an73_outcome(struct xgbe_prv_data *pdata) 1476 { 1477 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 1478 enum xgbe_mode mode; 1479 unsigned int ad_reg, lp_reg; 1480 1481 XGBE_SET_LP_ADV(lks, Autoneg); 1482 XGBE_SET_LP_ADV(lks, Backplane); 1483 1484 /* Compare Advertisement and Link Partner register 1 */ 1485 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE); 1486 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA); 1487 if (lp_reg & 0x400) 1488 XGBE_SET_LP_ADV(lks, Pause); 1489 if (lp_reg & 0x800) 1490 XGBE_SET_LP_ADV(lks, Asym_Pause); 1491 1492 if (pdata->phy.pause_autoneg) { 1493 /* Set flow control based on auto-negotiation result */ 1494 pdata->phy.tx_pause = 0; 1495 pdata->phy.rx_pause = 0; 1496 1497 if (ad_reg & lp_reg & 0x400) { 1498 pdata->phy.tx_pause = 1; 1499 pdata->phy.rx_pause = 1; 1500 } else if (ad_reg & lp_reg & 0x800) { 1501 if (ad_reg & 0x400) 1502 pdata->phy.rx_pause = 1; 1503 else if (lp_reg & 0x400) 1504 pdata->phy.tx_pause = 1; 1505 } 1506 } 1507 1508 /* Compare Advertisement and Link Partner register 2 */ 1509 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); 1510 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); 1511 if (lp_reg & 0x80) 1512 XGBE_SET_LP_ADV(lks, 10000baseKR_Full); 1513 if (lp_reg & 0x20) 1514 XGBE_SET_LP_ADV(lks, 1000baseKX_Full); 1515 1516 ad_reg &= lp_reg; 1517 if (ad_reg & 0x80) 1518 mode = XGBE_MODE_KR; 1519 else if (ad_reg & 0x20) 1520 mode = XGBE_MODE_KX_1000; 1521 else 1522 mode = XGBE_MODE_UNKNOWN; 1523 1524 /* Compare Advertisement and Link Partner register 3 */ 1525 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); 1526 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); 1527 if (lp_reg & 0xc000) 1528 XGBE_SET_LP_ADV(lks, 10000baseR_FEC); 1529 1530 return mode; 1531 } 1532 1533 static enum xgbe_mode xgbe_phy_an_outcome(struct xgbe_prv_data *pdata) 1534 { 1535 switch (pdata->an_mode) { 1536 case XGBE_AN_MODE_CL73: 1537 return xgbe_phy_an73_outcome(pdata); 1538 case XGBE_AN_MODE_CL73_REDRV: 1539 return xgbe_phy_an73_redrv_outcome(pdata); 1540 case XGBE_AN_MODE_CL37: 1541 return xgbe_phy_an37_outcome(pdata); 1542 case XGBE_AN_MODE_CL37_SGMII: 1543 return xgbe_phy_an37_sgmii_outcome(pdata); 1544 default: 1545 return XGBE_MODE_UNKNOWN; 1546 } 1547 } 1548 1549 static void xgbe_phy_an_advertising(struct xgbe_prv_data *pdata, 1550 struct ethtool_link_ksettings *dlks) 1551 { 1552 struct ethtool_link_ksettings *slks = &pdata->phy.lks; 1553 struct xgbe_phy_data *phy_data = pdata->phy_data; 1554 1555 XGBE_LM_COPY(dlks, advertising, slks, advertising); 1556 1557 /* Without a re-driver, just return current advertising */ 1558 if (!phy_data->redrv) 1559 return; 1560 1561 /* With the KR re-driver we need to advertise a single speed */ 1562 XGBE_CLR_ADV(dlks, 1000baseKX_Full); 1563 XGBE_CLR_ADV(dlks, 10000baseKR_Full); 1564 1565 switch (phy_data->port_mode) { 1566 case XGBE_PORT_MODE_BACKPLANE: 1567 XGBE_SET_ADV(dlks, 10000baseKR_Full); 1568 break; 1569 case XGBE_PORT_MODE_BACKPLANE_2500: 1570 XGBE_SET_ADV(dlks, 1000baseKX_Full); 1571 break; 1572 case XGBE_PORT_MODE_1000BASE_T: 1573 case XGBE_PORT_MODE_1000BASE_X: 1574 case XGBE_PORT_MODE_NBASE_T: 1575 XGBE_SET_ADV(dlks, 1000baseKX_Full); 1576 break; 1577 case XGBE_PORT_MODE_10GBASE_T: 1578 if (phy_data->phydev && 1579 (phy_data->phydev->speed == SPEED_10000)) 1580 XGBE_SET_ADV(dlks, 10000baseKR_Full); 1581 else 1582 XGBE_SET_ADV(dlks, 1000baseKX_Full); 1583 break; 1584 case XGBE_PORT_MODE_10GBASE_R: 1585 XGBE_SET_ADV(dlks, 10000baseKR_Full); 1586 break; 1587 case XGBE_PORT_MODE_SFP: 1588 switch (phy_data->sfp_base) { 1589 case XGBE_SFP_BASE_1000_T: 1590 case XGBE_SFP_BASE_1000_SX: 1591 case XGBE_SFP_BASE_1000_LX: 1592 case XGBE_SFP_BASE_1000_CX: 1593 XGBE_SET_ADV(dlks, 1000baseKX_Full); 1594 break; 1595 default: 1596 XGBE_SET_ADV(dlks, 10000baseKR_Full); 1597 break; 1598 } 1599 break; 1600 default: 1601 XGBE_SET_ADV(dlks, 10000baseKR_Full); 1602 break; 1603 } 1604 } 1605 1606 static int xgbe_phy_an_config(struct xgbe_prv_data *pdata) 1607 { 1608 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 1609 struct xgbe_phy_data *phy_data = pdata->phy_data; 1610 u32 advertising; 1611 int ret; 1612 1613 ret = xgbe_phy_find_phy_device(pdata); 1614 if (ret) 1615 return ret; 1616 1617 if (!phy_data->phydev) 1618 return 0; 1619 1620 ethtool_convert_link_mode_to_legacy_u32(&advertising, 1621 lks->link_modes.advertising); 1622 1623 phy_data->phydev->autoneg = pdata->phy.autoneg; 1624 phy_data->phydev->advertising = phy_data->phydev->supported & 1625 advertising; 1626 1627 if (pdata->phy.autoneg != AUTONEG_ENABLE) { 1628 phy_data->phydev->speed = pdata->phy.speed; 1629 phy_data->phydev->duplex = pdata->phy.duplex; 1630 } 1631 1632 ret = phy_start_aneg(phy_data->phydev); 1633 1634 return ret; 1635 } 1636 1637 static enum xgbe_an_mode xgbe_phy_an_sfp_mode(struct xgbe_phy_data *phy_data) 1638 { 1639 switch (phy_data->sfp_base) { 1640 case XGBE_SFP_BASE_1000_T: 1641 return XGBE_AN_MODE_CL37_SGMII; 1642 case XGBE_SFP_BASE_1000_SX: 1643 case XGBE_SFP_BASE_1000_LX: 1644 case XGBE_SFP_BASE_1000_CX: 1645 return XGBE_AN_MODE_CL37; 1646 default: 1647 return XGBE_AN_MODE_NONE; 1648 } 1649 } 1650 1651 static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata) 1652 { 1653 struct xgbe_phy_data *phy_data = pdata->phy_data; 1654 1655 /* A KR re-driver will always require CL73 AN */ 1656 if (phy_data->redrv) 1657 return XGBE_AN_MODE_CL73_REDRV; 1658 1659 switch (phy_data->port_mode) { 1660 case XGBE_PORT_MODE_BACKPLANE: 1661 return XGBE_AN_MODE_CL73; 1662 case XGBE_PORT_MODE_BACKPLANE_2500: 1663 return XGBE_AN_MODE_NONE; 1664 case XGBE_PORT_MODE_1000BASE_T: 1665 return XGBE_AN_MODE_CL37_SGMII; 1666 case XGBE_PORT_MODE_1000BASE_X: 1667 return XGBE_AN_MODE_CL37; 1668 case XGBE_PORT_MODE_NBASE_T: 1669 return XGBE_AN_MODE_CL37_SGMII; 1670 case XGBE_PORT_MODE_10GBASE_T: 1671 return XGBE_AN_MODE_CL73; 1672 case XGBE_PORT_MODE_10GBASE_R: 1673 return XGBE_AN_MODE_NONE; 1674 case XGBE_PORT_MODE_SFP: 1675 return xgbe_phy_an_sfp_mode(phy_data); 1676 default: 1677 return XGBE_AN_MODE_NONE; 1678 } 1679 } 1680 1681 static int xgbe_phy_set_redrv_mode_mdio(struct xgbe_prv_data *pdata, 1682 enum xgbe_phy_redrv_mode mode) 1683 { 1684 struct xgbe_phy_data *phy_data = pdata->phy_data; 1685 u16 redrv_reg, redrv_val; 1686 1687 redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000); 1688 redrv_val = (u16)mode; 1689 1690 return pdata->hw_if.write_ext_mii_regs(pdata, phy_data->redrv_addr, 1691 redrv_reg, redrv_val); 1692 } 1693 1694 static int xgbe_phy_set_redrv_mode_i2c(struct xgbe_prv_data *pdata, 1695 enum xgbe_phy_redrv_mode mode) 1696 { 1697 struct xgbe_phy_data *phy_data = pdata->phy_data; 1698 unsigned int redrv_reg; 1699 int ret; 1700 1701 /* Calculate the register to write */ 1702 redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000); 1703 1704 ret = xgbe_phy_redrv_write(pdata, redrv_reg, mode); 1705 1706 return ret; 1707 } 1708 1709 static void xgbe_phy_set_redrv_mode(struct xgbe_prv_data *pdata) 1710 { 1711 struct xgbe_phy_data *phy_data = pdata->phy_data; 1712 enum xgbe_phy_redrv_mode mode; 1713 int ret; 1714 1715 if (!phy_data->redrv) 1716 return; 1717 1718 mode = XGBE_PHY_REDRV_MODE_CX; 1719 if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) && 1720 (phy_data->sfp_base != XGBE_SFP_BASE_1000_CX) && 1721 (phy_data->sfp_base != XGBE_SFP_BASE_10000_CR)) 1722 mode = XGBE_PHY_REDRV_MODE_SR; 1723 1724 ret = xgbe_phy_get_comm_ownership(pdata); 1725 if (ret) 1726 return; 1727 1728 if (phy_data->redrv_if) 1729 xgbe_phy_set_redrv_mode_i2c(pdata, mode); 1730 else 1731 xgbe_phy_set_redrv_mode_mdio(pdata, mode); 1732 1733 xgbe_phy_put_comm_ownership(pdata); 1734 } 1735 1736 static void xgbe_phy_perform_ratechange(struct xgbe_prv_data *pdata, 1737 unsigned int cmd, unsigned int sub_cmd) 1738 { 1739 unsigned int s0 = 0; 1740 unsigned int wait; 1741 1742 /* Log if a previous command did not complete */ 1743 if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) 1744 netif_dbg(pdata, link, pdata->netdev, 1745 "firmware mailbox not ready for command\n"); 1746 1747 /* Construct the command */ 1748 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, cmd); 1749 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, sub_cmd); 1750 1751 /* Issue the command */ 1752 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0); 1753 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0); 1754 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1); 1755 1756 /* Wait for command to complete */ 1757 wait = XGBE_RATECHANGE_COUNT; 1758 while (wait--) { 1759 if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) 1760 return; 1761 1762 usleep_range(1000, 2000); 1763 } 1764 1765 netif_dbg(pdata, link, pdata->netdev, 1766 "firmware mailbox command did not complete\n"); 1767 } 1768 1769 static void xgbe_phy_rrc(struct xgbe_prv_data *pdata) 1770 { 1771 /* Receiver Reset Cycle */ 1772 xgbe_phy_perform_ratechange(pdata, 5, 0); 1773 1774 netif_dbg(pdata, link, pdata->netdev, "receiver reset complete\n"); 1775 } 1776 1777 static void xgbe_phy_power_off(struct xgbe_prv_data *pdata) 1778 { 1779 struct xgbe_phy_data *phy_data = pdata->phy_data; 1780 1781 /* Power off */ 1782 xgbe_phy_perform_ratechange(pdata, 0, 0); 1783 1784 phy_data->cur_mode = XGBE_MODE_UNKNOWN; 1785 1786 netif_dbg(pdata, link, pdata->netdev, "phy powered off\n"); 1787 } 1788 1789 static void xgbe_phy_sfi_mode(struct xgbe_prv_data *pdata) 1790 { 1791 struct xgbe_phy_data *phy_data = pdata->phy_data; 1792 1793 xgbe_phy_set_redrv_mode(pdata); 1794 1795 /* 10G/SFI */ 1796 if (phy_data->sfp_cable != XGBE_SFP_CABLE_PASSIVE) { 1797 xgbe_phy_perform_ratechange(pdata, 3, 0); 1798 } else { 1799 if (phy_data->sfp_cable_len <= 1) 1800 xgbe_phy_perform_ratechange(pdata, 3, 1); 1801 else if (phy_data->sfp_cable_len <= 3) 1802 xgbe_phy_perform_ratechange(pdata, 3, 2); 1803 else 1804 xgbe_phy_perform_ratechange(pdata, 3, 3); 1805 } 1806 1807 phy_data->cur_mode = XGBE_MODE_SFI; 1808 1809 netif_dbg(pdata, link, pdata->netdev, "10GbE SFI mode set\n"); 1810 } 1811 1812 static void xgbe_phy_x_mode(struct xgbe_prv_data *pdata) 1813 { 1814 struct xgbe_phy_data *phy_data = pdata->phy_data; 1815 1816 xgbe_phy_set_redrv_mode(pdata); 1817 1818 /* 1G/X */ 1819 xgbe_phy_perform_ratechange(pdata, 1, 3); 1820 1821 phy_data->cur_mode = XGBE_MODE_X; 1822 1823 netif_dbg(pdata, link, pdata->netdev, "1GbE X mode set\n"); 1824 } 1825 1826 static void xgbe_phy_sgmii_1000_mode(struct xgbe_prv_data *pdata) 1827 { 1828 struct xgbe_phy_data *phy_data = pdata->phy_data; 1829 1830 xgbe_phy_set_redrv_mode(pdata); 1831 1832 /* 1G/SGMII */ 1833 xgbe_phy_perform_ratechange(pdata, 1, 2); 1834 1835 phy_data->cur_mode = XGBE_MODE_SGMII_1000; 1836 1837 netif_dbg(pdata, link, pdata->netdev, "1GbE SGMII mode set\n"); 1838 } 1839 1840 static void xgbe_phy_sgmii_100_mode(struct xgbe_prv_data *pdata) 1841 { 1842 struct xgbe_phy_data *phy_data = pdata->phy_data; 1843 1844 xgbe_phy_set_redrv_mode(pdata); 1845 1846 /* 100M/SGMII */ 1847 xgbe_phy_perform_ratechange(pdata, 1, 1); 1848 1849 phy_data->cur_mode = XGBE_MODE_SGMII_100; 1850 1851 netif_dbg(pdata, link, pdata->netdev, "100MbE SGMII mode set\n"); 1852 } 1853 1854 static void xgbe_phy_kr_mode(struct xgbe_prv_data *pdata) 1855 { 1856 struct xgbe_phy_data *phy_data = pdata->phy_data; 1857 1858 xgbe_phy_set_redrv_mode(pdata); 1859 1860 /* 10G/KR */ 1861 xgbe_phy_perform_ratechange(pdata, 4, 0); 1862 1863 phy_data->cur_mode = XGBE_MODE_KR; 1864 1865 netif_dbg(pdata, link, pdata->netdev, "10GbE KR mode set\n"); 1866 } 1867 1868 static void xgbe_phy_kx_2500_mode(struct xgbe_prv_data *pdata) 1869 { 1870 struct xgbe_phy_data *phy_data = pdata->phy_data; 1871 1872 xgbe_phy_set_redrv_mode(pdata); 1873 1874 /* 2.5G/KX */ 1875 xgbe_phy_perform_ratechange(pdata, 2, 0); 1876 1877 phy_data->cur_mode = XGBE_MODE_KX_2500; 1878 1879 netif_dbg(pdata, link, pdata->netdev, "2.5GbE KX mode set\n"); 1880 } 1881 1882 static void xgbe_phy_kx_1000_mode(struct xgbe_prv_data *pdata) 1883 { 1884 struct xgbe_phy_data *phy_data = pdata->phy_data; 1885 1886 xgbe_phy_set_redrv_mode(pdata); 1887 1888 /* 1G/KX */ 1889 xgbe_phy_perform_ratechange(pdata, 1, 3); 1890 1891 phy_data->cur_mode = XGBE_MODE_KX_1000; 1892 1893 netif_dbg(pdata, link, pdata->netdev, "1GbE KX mode set\n"); 1894 } 1895 1896 static enum xgbe_mode xgbe_phy_cur_mode(struct xgbe_prv_data *pdata) 1897 { 1898 struct xgbe_phy_data *phy_data = pdata->phy_data; 1899 1900 return phy_data->cur_mode; 1901 } 1902 1903 static enum xgbe_mode xgbe_phy_switch_baset_mode(struct xgbe_prv_data *pdata) 1904 { 1905 struct xgbe_phy_data *phy_data = pdata->phy_data; 1906 1907 /* No switching if not 10GBase-T */ 1908 if (phy_data->port_mode != XGBE_PORT_MODE_10GBASE_T) 1909 return xgbe_phy_cur_mode(pdata); 1910 1911 switch (xgbe_phy_cur_mode(pdata)) { 1912 case XGBE_MODE_SGMII_100: 1913 case XGBE_MODE_SGMII_1000: 1914 return XGBE_MODE_KR; 1915 case XGBE_MODE_KR: 1916 default: 1917 return XGBE_MODE_SGMII_1000; 1918 } 1919 } 1920 1921 static enum xgbe_mode xgbe_phy_switch_bp_2500_mode(struct xgbe_prv_data *pdata) 1922 { 1923 return XGBE_MODE_KX_2500; 1924 } 1925 1926 static enum xgbe_mode xgbe_phy_switch_bp_mode(struct xgbe_prv_data *pdata) 1927 { 1928 /* If we are in KR switch to KX, and vice-versa */ 1929 switch (xgbe_phy_cur_mode(pdata)) { 1930 case XGBE_MODE_KX_1000: 1931 return XGBE_MODE_KR; 1932 case XGBE_MODE_KR: 1933 default: 1934 return XGBE_MODE_KX_1000; 1935 } 1936 } 1937 1938 static enum xgbe_mode xgbe_phy_switch_mode(struct xgbe_prv_data *pdata) 1939 { 1940 struct xgbe_phy_data *phy_data = pdata->phy_data; 1941 1942 switch (phy_data->port_mode) { 1943 case XGBE_PORT_MODE_BACKPLANE: 1944 return xgbe_phy_switch_bp_mode(pdata); 1945 case XGBE_PORT_MODE_BACKPLANE_2500: 1946 return xgbe_phy_switch_bp_2500_mode(pdata); 1947 case XGBE_PORT_MODE_1000BASE_T: 1948 case XGBE_PORT_MODE_NBASE_T: 1949 case XGBE_PORT_MODE_10GBASE_T: 1950 return xgbe_phy_switch_baset_mode(pdata); 1951 case XGBE_PORT_MODE_1000BASE_X: 1952 case XGBE_PORT_MODE_10GBASE_R: 1953 case XGBE_PORT_MODE_SFP: 1954 /* No switching, so just return current mode */ 1955 return xgbe_phy_cur_mode(pdata); 1956 default: 1957 return XGBE_MODE_UNKNOWN; 1958 } 1959 } 1960 1961 static enum xgbe_mode xgbe_phy_get_basex_mode(struct xgbe_phy_data *phy_data, 1962 int speed) 1963 { 1964 switch (speed) { 1965 case SPEED_1000: 1966 return XGBE_MODE_X; 1967 case SPEED_10000: 1968 return XGBE_MODE_KR; 1969 default: 1970 return XGBE_MODE_UNKNOWN; 1971 } 1972 } 1973 1974 static enum xgbe_mode xgbe_phy_get_baset_mode(struct xgbe_phy_data *phy_data, 1975 int speed) 1976 { 1977 switch (speed) { 1978 case SPEED_100: 1979 return XGBE_MODE_SGMII_100; 1980 case SPEED_1000: 1981 return XGBE_MODE_SGMII_1000; 1982 case SPEED_2500: 1983 return XGBE_MODE_KX_2500; 1984 case SPEED_10000: 1985 return XGBE_MODE_KR; 1986 default: 1987 return XGBE_MODE_UNKNOWN; 1988 } 1989 } 1990 1991 static enum xgbe_mode xgbe_phy_get_sfp_mode(struct xgbe_phy_data *phy_data, 1992 int speed) 1993 { 1994 switch (speed) { 1995 case SPEED_100: 1996 return XGBE_MODE_SGMII_100; 1997 case SPEED_1000: 1998 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T) 1999 return XGBE_MODE_SGMII_1000; 2000 else 2001 return XGBE_MODE_X; 2002 case SPEED_10000: 2003 case SPEED_UNKNOWN: 2004 return XGBE_MODE_SFI; 2005 default: 2006 return XGBE_MODE_UNKNOWN; 2007 } 2008 } 2009 2010 static enum xgbe_mode xgbe_phy_get_bp_2500_mode(int speed) 2011 { 2012 switch (speed) { 2013 case SPEED_2500: 2014 return XGBE_MODE_KX_2500; 2015 default: 2016 return XGBE_MODE_UNKNOWN; 2017 } 2018 } 2019 2020 static enum xgbe_mode xgbe_phy_get_bp_mode(int speed) 2021 { 2022 switch (speed) { 2023 case SPEED_1000: 2024 return XGBE_MODE_KX_1000; 2025 case SPEED_10000: 2026 return XGBE_MODE_KR; 2027 default: 2028 return XGBE_MODE_UNKNOWN; 2029 } 2030 } 2031 2032 static enum xgbe_mode xgbe_phy_get_mode(struct xgbe_prv_data *pdata, 2033 int speed) 2034 { 2035 struct xgbe_phy_data *phy_data = pdata->phy_data; 2036 2037 switch (phy_data->port_mode) { 2038 case XGBE_PORT_MODE_BACKPLANE: 2039 return xgbe_phy_get_bp_mode(speed); 2040 case XGBE_PORT_MODE_BACKPLANE_2500: 2041 return xgbe_phy_get_bp_2500_mode(speed); 2042 case XGBE_PORT_MODE_1000BASE_T: 2043 case XGBE_PORT_MODE_NBASE_T: 2044 case XGBE_PORT_MODE_10GBASE_T: 2045 return xgbe_phy_get_baset_mode(phy_data, speed); 2046 case XGBE_PORT_MODE_1000BASE_X: 2047 case XGBE_PORT_MODE_10GBASE_R: 2048 return xgbe_phy_get_basex_mode(phy_data, speed); 2049 case XGBE_PORT_MODE_SFP: 2050 return xgbe_phy_get_sfp_mode(phy_data, speed); 2051 default: 2052 return XGBE_MODE_UNKNOWN; 2053 } 2054 } 2055 2056 static void xgbe_phy_set_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode) 2057 { 2058 switch (mode) { 2059 case XGBE_MODE_KX_1000: 2060 xgbe_phy_kx_1000_mode(pdata); 2061 break; 2062 case XGBE_MODE_KX_2500: 2063 xgbe_phy_kx_2500_mode(pdata); 2064 break; 2065 case XGBE_MODE_KR: 2066 xgbe_phy_kr_mode(pdata); 2067 break; 2068 case XGBE_MODE_SGMII_100: 2069 xgbe_phy_sgmii_100_mode(pdata); 2070 break; 2071 case XGBE_MODE_SGMII_1000: 2072 xgbe_phy_sgmii_1000_mode(pdata); 2073 break; 2074 case XGBE_MODE_X: 2075 xgbe_phy_x_mode(pdata); 2076 break; 2077 case XGBE_MODE_SFI: 2078 xgbe_phy_sfi_mode(pdata); 2079 break; 2080 default: 2081 break; 2082 } 2083 } 2084 2085 static bool xgbe_phy_check_mode(struct xgbe_prv_data *pdata, 2086 enum xgbe_mode mode, bool advert) 2087 { 2088 if (pdata->phy.autoneg == AUTONEG_ENABLE) { 2089 return advert; 2090 } else { 2091 enum xgbe_mode cur_mode; 2092 2093 cur_mode = xgbe_phy_get_mode(pdata, pdata->phy.speed); 2094 if (cur_mode == mode) 2095 return true; 2096 } 2097 2098 return false; 2099 } 2100 2101 static bool xgbe_phy_use_basex_mode(struct xgbe_prv_data *pdata, 2102 enum xgbe_mode mode) 2103 { 2104 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 2105 2106 switch (mode) { 2107 case XGBE_MODE_X: 2108 return xgbe_phy_check_mode(pdata, mode, 2109 XGBE_ADV(lks, 1000baseX_Full)); 2110 case XGBE_MODE_KR: 2111 return xgbe_phy_check_mode(pdata, mode, 2112 XGBE_ADV(lks, 10000baseKR_Full)); 2113 default: 2114 return false; 2115 } 2116 } 2117 2118 static bool xgbe_phy_use_baset_mode(struct xgbe_prv_data *pdata, 2119 enum xgbe_mode mode) 2120 { 2121 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 2122 2123 switch (mode) { 2124 case XGBE_MODE_SGMII_100: 2125 return xgbe_phy_check_mode(pdata, mode, 2126 XGBE_ADV(lks, 100baseT_Full)); 2127 case XGBE_MODE_SGMII_1000: 2128 return xgbe_phy_check_mode(pdata, mode, 2129 XGBE_ADV(lks, 1000baseT_Full)); 2130 case XGBE_MODE_KX_2500: 2131 return xgbe_phy_check_mode(pdata, mode, 2132 XGBE_ADV(lks, 2500baseT_Full)); 2133 case XGBE_MODE_KR: 2134 return xgbe_phy_check_mode(pdata, mode, 2135 XGBE_ADV(lks, 10000baseT_Full)); 2136 default: 2137 return false; 2138 } 2139 } 2140 2141 static bool xgbe_phy_use_sfp_mode(struct xgbe_prv_data *pdata, 2142 enum xgbe_mode mode) 2143 { 2144 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 2145 struct xgbe_phy_data *phy_data = pdata->phy_data; 2146 2147 switch (mode) { 2148 case XGBE_MODE_X: 2149 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T) 2150 return false; 2151 return xgbe_phy_check_mode(pdata, mode, 2152 XGBE_ADV(lks, 1000baseX_Full)); 2153 case XGBE_MODE_SGMII_100: 2154 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T) 2155 return false; 2156 return xgbe_phy_check_mode(pdata, mode, 2157 XGBE_ADV(lks, 100baseT_Full)); 2158 case XGBE_MODE_SGMII_1000: 2159 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T) 2160 return false; 2161 return xgbe_phy_check_mode(pdata, mode, 2162 XGBE_ADV(lks, 1000baseT_Full)); 2163 case XGBE_MODE_SFI: 2164 if (phy_data->sfp_mod_absent) 2165 return true; 2166 return xgbe_phy_check_mode(pdata, mode, 2167 XGBE_ADV(lks, 10000baseSR_Full) || 2168 XGBE_ADV(lks, 10000baseLR_Full) || 2169 XGBE_ADV(lks, 10000baseLRM_Full) || 2170 XGBE_ADV(lks, 10000baseER_Full) || 2171 XGBE_ADV(lks, 10000baseCR_Full)); 2172 default: 2173 return false; 2174 } 2175 } 2176 2177 static bool xgbe_phy_use_bp_2500_mode(struct xgbe_prv_data *pdata, 2178 enum xgbe_mode mode) 2179 { 2180 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 2181 2182 switch (mode) { 2183 case XGBE_MODE_KX_2500: 2184 return xgbe_phy_check_mode(pdata, mode, 2185 XGBE_ADV(lks, 2500baseX_Full)); 2186 default: 2187 return false; 2188 } 2189 } 2190 2191 static bool xgbe_phy_use_bp_mode(struct xgbe_prv_data *pdata, 2192 enum xgbe_mode mode) 2193 { 2194 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 2195 2196 switch (mode) { 2197 case XGBE_MODE_KX_1000: 2198 return xgbe_phy_check_mode(pdata, mode, 2199 XGBE_ADV(lks, 1000baseKX_Full)); 2200 case XGBE_MODE_KR: 2201 return xgbe_phy_check_mode(pdata, mode, 2202 XGBE_ADV(lks, 10000baseKR_Full)); 2203 default: 2204 return false; 2205 } 2206 } 2207 2208 static bool xgbe_phy_use_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode) 2209 { 2210 struct xgbe_phy_data *phy_data = pdata->phy_data; 2211 2212 switch (phy_data->port_mode) { 2213 case XGBE_PORT_MODE_BACKPLANE: 2214 return xgbe_phy_use_bp_mode(pdata, mode); 2215 case XGBE_PORT_MODE_BACKPLANE_2500: 2216 return xgbe_phy_use_bp_2500_mode(pdata, mode); 2217 case XGBE_PORT_MODE_1000BASE_T: 2218 case XGBE_PORT_MODE_NBASE_T: 2219 case XGBE_PORT_MODE_10GBASE_T: 2220 return xgbe_phy_use_baset_mode(pdata, mode); 2221 case XGBE_PORT_MODE_1000BASE_X: 2222 case XGBE_PORT_MODE_10GBASE_R: 2223 return xgbe_phy_use_basex_mode(pdata, mode); 2224 case XGBE_PORT_MODE_SFP: 2225 return xgbe_phy_use_sfp_mode(pdata, mode); 2226 default: 2227 return false; 2228 } 2229 } 2230 2231 static bool xgbe_phy_valid_speed_basex_mode(struct xgbe_phy_data *phy_data, 2232 int speed) 2233 { 2234 switch (speed) { 2235 case SPEED_1000: 2236 return (phy_data->port_mode == XGBE_PORT_MODE_1000BASE_X); 2237 case SPEED_10000: 2238 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_R); 2239 default: 2240 return false; 2241 } 2242 } 2243 2244 static bool xgbe_phy_valid_speed_baset_mode(struct xgbe_phy_data *phy_data, 2245 int speed) 2246 { 2247 switch (speed) { 2248 case SPEED_100: 2249 case SPEED_1000: 2250 return true; 2251 case SPEED_2500: 2252 return (phy_data->port_mode == XGBE_PORT_MODE_NBASE_T); 2253 case SPEED_10000: 2254 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_T); 2255 default: 2256 return false; 2257 } 2258 } 2259 2260 static bool xgbe_phy_valid_speed_sfp_mode(struct xgbe_phy_data *phy_data, 2261 int speed) 2262 { 2263 switch (speed) { 2264 case SPEED_100: 2265 return (phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000); 2266 case SPEED_1000: 2267 return ((phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000) || 2268 (phy_data->sfp_speed == XGBE_SFP_SPEED_1000)); 2269 case SPEED_10000: 2270 return (phy_data->sfp_speed == XGBE_SFP_SPEED_10000); 2271 default: 2272 return false; 2273 } 2274 } 2275 2276 static bool xgbe_phy_valid_speed_bp_2500_mode(int speed) 2277 { 2278 switch (speed) { 2279 case SPEED_2500: 2280 return true; 2281 default: 2282 return false; 2283 } 2284 } 2285 2286 static bool xgbe_phy_valid_speed_bp_mode(int speed) 2287 { 2288 switch (speed) { 2289 case SPEED_1000: 2290 case SPEED_10000: 2291 return true; 2292 default: 2293 return false; 2294 } 2295 } 2296 2297 static bool xgbe_phy_valid_speed(struct xgbe_prv_data *pdata, int speed) 2298 { 2299 struct xgbe_phy_data *phy_data = pdata->phy_data; 2300 2301 switch (phy_data->port_mode) { 2302 case XGBE_PORT_MODE_BACKPLANE: 2303 return xgbe_phy_valid_speed_bp_mode(speed); 2304 case XGBE_PORT_MODE_BACKPLANE_2500: 2305 return xgbe_phy_valid_speed_bp_2500_mode(speed); 2306 case XGBE_PORT_MODE_1000BASE_T: 2307 case XGBE_PORT_MODE_NBASE_T: 2308 case XGBE_PORT_MODE_10GBASE_T: 2309 return xgbe_phy_valid_speed_baset_mode(phy_data, speed); 2310 case XGBE_PORT_MODE_1000BASE_X: 2311 case XGBE_PORT_MODE_10GBASE_R: 2312 return xgbe_phy_valid_speed_basex_mode(phy_data, speed); 2313 case XGBE_PORT_MODE_SFP: 2314 return xgbe_phy_valid_speed_sfp_mode(phy_data, speed); 2315 default: 2316 return false; 2317 } 2318 } 2319 2320 static int xgbe_phy_link_status(struct xgbe_prv_data *pdata, int *an_restart) 2321 { 2322 struct xgbe_phy_data *phy_data = pdata->phy_data; 2323 unsigned int reg; 2324 int ret; 2325 2326 *an_restart = 0; 2327 2328 if (phy_data->port_mode == XGBE_PORT_MODE_SFP) { 2329 /* Check SFP signals */ 2330 xgbe_phy_sfp_detect(pdata); 2331 2332 if (phy_data->sfp_changed) { 2333 *an_restart = 1; 2334 return 0; 2335 } 2336 2337 if (phy_data->sfp_mod_absent || phy_data->sfp_rx_los) 2338 return 0; 2339 } 2340 2341 if (phy_data->phydev) { 2342 /* Check external PHY */ 2343 ret = phy_read_status(phy_data->phydev); 2344 if (ret < 0) 2345 return 0; 2346 2347 if ((pdata->phy.autoneg == AUTONEG_ENABLE) && 2348 !phy_aneg_done(phy_data->phydev)) 2349 return 0; 2350 2351 if (!phy_data->phydev->link) 2352 return 0; 2353 } 2354 2355 /* Link status is latched low, so read once to clear 2356 * and then read again to get current state 2357 */ 2358 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); 2359 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); 2360 if (reg & MDIO_STAT1_LSTATUS) 2361 return 1; 2362 2363 /* No link, attempt a receiver reset cycle */ 2364 if (phy_data->rrc_count++) { 2365 phy_data->rrc_count = 0; 2366 xgbe_phy_rrc(pdata); 2367 } 2368 2369 return 0; 2370 } 2371 2372 static void xgbe_phy_sfp_gpio_setup(struct xgbe_prv_data *pdata) 2373 { 2374 struct xgbe_phy_data *phy_data = pdata->phy_data; 2375 unsigned int reg; 2376 2377 reg = XP_IOREAD(pdata, XP_PROP_3); 2378 2379 phy_data->sfp_gpio_address = XGBE_GPIO_ADDRESS_PCA9555 + 2380 XP_GET_BITS(reg, XP_PROP_3, GPIO_ADDR); 2381 2382 phy_data->sfp_gpio_mask = XP_GET_BITS(reg, XP_PROP_3, GPIO_MASK); 2383 2384 phy_data->sfp_gpio_rx_los = XP_GET_BITS(reg, XP_PROP_3, 2385 GPIO_RX_LOS); 2386 phy_data->sfp_gpio_tx_fault = XP_GET_BITS(reg, XP_PROP_3, 2387 GPIO_TX_FAULT); 2388 phy_data->sfp_gpio_mod_absent = XP_GET_BITS(reg, XP_PROP_3, 2389 GPIO_MOD_ABS); 2390 phy_data->sfp_gpio_rate_select = XP_GET_BITS(reg, XP_PROP_3, 2391 GPIO_RATE_SELECT); 2392 2393 if (netif_msg_probe(pdata)) { 2394 dev_dbg(pdata->dev, "SFP: gpio_address=%#x\n", 2395 phy_data->sfp_gpio_address); 2396 dev_dbg(pdata->dev, "SFP: gpio_mask=%#x\n", 2397 phy_data->sfp_gpio_mask); 2398 dev_dbg(pdata->dev, "SFP: gpio_rx_los=%u\n", 2399 phy_data->sfp_gpio_rx_los); 2400 dev_dbg(pdata->dev, "SFP: gpio_tx_fault=%u\n", 2401 phy_data->sfp_gpio_tx_fault); 2402 dev_dbg(pdata->dev, "SFP: gpio_mod_absent=%u\n", 2403 phy_data->sfp_gpio_mod_absent); 2404 dev_dbg(pdata->dev, "SFP: gpio_rate_select=%u\n", 2405 phy_data->sfp_gpio_rate_select); 2406 } 2407 } 2408 2409 static void xgbe_phy_sfp_comm_setup(struct xgbe_prv_data *pdata) 2410 { 2411 struct xgbe_phy_data *phy_data = pdata->phy_data; 2412 unsigned int reg, mux_addr_hi, mux_addr_lo; 2413 2414 reg = XP_IOREAD(pdata, XP_PROP_4); 2415 2416 mux_addr_hi = XP_GET_BITS(reg, XP_PROP_4, MUX_ADDR_HI); 2417 mux_addr_lo = XP_GET_BITS(reg, XP_PROP_4, MUX_ADDR_LO); 2418 if (mux_addr_lo == XGBE_SFP_DIRECT) 2419 return; 2420 2421 phy_data->sfp_comm = XGBE_SFP_COMM_PCA9545; 2422 phy_data->sfp_mux_address = (mux_addr_hi << 2) + mux_addr_lo; 2423 phy_data->sfp_mux_channel = XP_GET_BITS(reg, XP_PROP_4, MUX_CHAN); 2424 2425 if (netif_msg_probe(pdata)) { 2426 dev_dbg(pdata->dev, "SFP: mux_address=%#x\n", 2427 phy_data->sfp_mux_address); 2428 dev_dbg(pdata->dev, "SFP: mux_channel=%u\n", 2429 phy_data->sfp_mux_channel); 2430 } 2431 } 2432 2433 static void xgbe_phy_sfp_setup(struct xgbe_prv_data *pdata) 2434 { 2435 xgbe_phy_sfp_comm_setup(pdata); 2436 xgbe_phy_sfp_gpio_setup(pdata); 2437 } 2438 2439 static int xgbe_phy_int_mdio_reset(struct xgbe_prv_data *pdata) 2440 { 2441 struct xgbe_phy_data *phy_data = pdata->phy_data; 2442 unsigned int ret; 2443 2444 ret = pdata->hw_if.set_gpio(pdata, phy_data->mdio_reset_gpio); 2445 if (ret) 2446 return ret; 2447 2448 ret = pdata->hw_if.clr_gpio(pdata, phy_data->mdio_reset_gpio); 2449 2450 return ret; 2451 } 2452 2453 static int xgbe_phy_i2c_mdio_reset(struct xgbe_prv_data *pdata) 2454 { 2455 struct xgbe_phy_data *phy_data = pdata->phy_data; 2456 u8 gpio_reg, gpio_ports[2], gpio_data[3]; 2457 int ret; 2458 2459 /* Read the output port registers */ 2460 gpio_reg = 2; 2461 ret = xgbe_phy_i2c_read(pdata, phy_data->mdio_reset_addr, 2462 &gpio_reg, sizeof(gpio_reg), 2463 gpio_ports, sizeof(gpio_ports)); 2464 if (ret) 2465 return ret; 2466 2467 /* Prepare to write the GPIO data */ 2468 gpio_data[0] = 2; 2469 gpio_data[1] = gpio_ports[0]; 2470 gpio_data[2] = gpio_ports[1]; 2471 2472 /* Set the GPIO pin */ 2473 if (phy_data->mdio_reset_gpio < 8) 2474 gpio_data[1] |= (1 << (phy_data->mdio_reset_gpio % 8)); 2475 else 2476 gpio_data[2] |= (1 << (phy_data->mdio_reset_gpio % 8)); 2477 2478 /* Write the output port registers */ 2479 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr, 2480 gpio_data, sizeof(gpio_data)); 2481 if (ret) 2482 return ret; 2483 2484 /* Clear the GPIO pin */ 2485 if (phy_data->mdio_reset_gpio < 8) 2486 gpio_data[1] &= ~(1 << (phy_data->mdio_reset_gpio % 8)); 2487 else 2488 gpio_data[2] &= ~(1 << (phy_data->mdio_reset_gpio % 8)); 2489 2490 /* Write the output port registers */ 2491 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr, 2492 gpio_data, sizeof(gpio_data)); 2493 2494 return ret; 2495 } 2496 2497 static int xgbe_phy_mdio_reset(struct xgbe_prv_data *pdata) 2498 { 2499 struct xgbe_phy_data *phy_data = pdata->phy_data; 2500 int ret; 2501 2502 if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO) 2503 return 0; 2504 2505 ret = xgbe_phy_get_comm_ownership(pdata); 2506 if (ret) 2507 return ret; 2508 2509 if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO) 2510 ret = xgbe_phy_i2c_mdio_reset(pdata); 2511 else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO) 2512 ret = xgbe_phy_int_mdio_reset(pdata); 2513 2514 xgbe_phy_put_comm_ownership(pdata); 2515 2516 return ret; 2517 } 2518 2519 static bool xgbe_phy_redrv_error(struct xgbe_phy_data *phy_data) 2520 { 2521 if (!phy_data->redrv) 2522 return false; 2523 2524 if (phy_data->redrv_if >= XGBE_PHY_REDRV_IF_MAX) 2525 return true; 2526 2527 switch (phy_data->redrv_model) { 2528 case XGBE_PHY_REDRV_MODEL_4223: 2529 if (phy_data->redrv_lane > 3) 2530 return true; 2531 break; 2532 case XGBE_PHY_REDRV_MODEL_4227: 2533 if (phy_data->redrv_lane > 1) 2534 return true; 2535 break; 2536 default: 2537 return true; 2538 } 2539 2540 return false; 2541 } 2542 2543 static int xgbe_phy_mdio_reset_setup(struct xgbe_prv_data *pdata) 2544 { 2545 struct xgbe_phy_data *phy_data = pdata->phy_data; 2546 unsigned int reg; 2547 2548 if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO) 2549 return 0; 2550 2551 reg = XP_IOREAD(pdata, XP_PROP_3); 2552 phy_data->mdio_reset = XP_GET_BITS(reg, XP_PROP_3, MDIO_RESET); 2553 switch (phy_data->mdio_reset) { 2554 case XGBE_MDIO_RESET_NONE: 2555 case XGBE_MDIO_RESET_I2C_GPIO: 2556 case XGBE_MDIO_RESET_INT_GPIO: 2557 break; 2558 default: 2559 dev_err(pdata->dev, "unsupported MDIO reset (%#x)\n", 2560 phy_data->mdio_reset); 2561 return -EINVAL; 2562 } 2563 2564 if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO) { 2565 phy_data->mdio_reset_addr = XGBE_GPIO_ADDRESS_PCA9555 + 2566 XP_GET_BITS(reg, XP_PROP_3, 2567 MDIO_RESET_I2C_ADDR); 2568 phy_data->mdio_reset_gpio = XP_GET_BITS(reg, XP_PROP_3, 2569 MDIO_RESET_I2C_GPIO); 2570 } else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO) { 2571 phy_data->mdio_reset_gpio = XP_GET_BITS(reg, XP_PROP_3, 2572 MDIO_RESET_INT_GPIO); 2573 } 2574 2575 return 0; 2576 } 2577 2578 static bool xgbe_phy_port_mode_mismatch(struct xgbe_prv_data *pdata) 2579 { 2580 struct xgbe_phy_data *phy_data = pdata->phy_data; 2581 2582 switch (phy_data->port_mode) { 2583 case XGBE_PORT_MODE_BACKPLANE: 2584 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) || 2585 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)) 2586 return false; 2587 break; 2588 case XGBE_PORT_MODE_BACKPLANE_2500: 2589 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500) 2590 return false; 2591 break; 2592 case XGBE_PORT_MODE_1000BASE_T: 2593 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) || 2594 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)) 2595 return false; 2596 break; 2597 case XGBE_PORT_MODE_1000BASE_X: 2598 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) 2599 return false; 2600 break; 2601 case XGBE_PORT_MODE_NBASE_T: 2602 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) || 2603 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) || 2604 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500)) 2605 return false; 2606 break; 2607 case XGBE_PORT_MODE_10GBASE_T: 2608 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) || 2609 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) || 2610 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)) 2611 return false; 2612 break; 2613 case XGBE_PORT_MODE_10GBASE_R: 2614 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) 2615 return false; 2616 break; 2617 case XGBE_PORT_MODE_SFP: 2618 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) || 2619 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) || 2620 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)) 2621 return false; 2622 break; 2623 default: 2624 break; 2625 } 2626 2627 return true; 2628 } 2629 2630 static bool xgbe_phy_conn_type_mismatch(struct xgbe_prv_data *pdata) 2631 { 2632 struct xgbe_phy_data *phy_data = pdata->phy_data; 2633 2634 switch (phy_data->port_mode) { 2635 case XGBE_PORT_MODE_BACKPLANE: 2636 case XGBE_PORT_MODE_BACKPLANE_2500: 2637 if (phy_data->conn_type == XGBE_CONN_TYPE_BACKPLANE) 2638 return false; 2639 break; 2640 case XGBE_PORT_MODE_1000BASE_T: 2641 case XGBE_PORT_MODE_1000BASE_X: 2642 case XGBE_PORT_MODE_NBASE_T: 2643 case XGBE_PORT_MODE_10GBASE_T: 2644 case XGBE_PORT_MODE_10GBASE_R: 2645 if (phy_data->conn_type == XGBE_CONN_TYPE_MDIO) 2646 return false; 2647 break; 2648 case XGBE_PORT_MODE_SFP: 2649 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP) 2650 return false; 2651 break; 2652 default: 2653 break; 2654 } 2655 2656 return true; 2657 } 2658 2659 static bool xgbe_phy_port_enabled(struct xgbe_prv_data *pdata) 2660 { 2661 unsigned int reg; 2662 2663 reg = XP_IOREAD(pdata, XP_PROP_0); 2664 if (!XP_GET_BITS(reg, XP_PROP_0, PORT_SPEEDS)) 2665 return false; 2666 if (!XP_GET_BITS(reg, XP_PROP_0, CONN_TYPE)) 2667 return false; 2668 2669 return true; 2670 } 2671 2672 static void xgbe_phy_stop(struct xgbe_prv_data *pdata) 2673 { 2674 struct xgbe_phy_data *phy_data = pdata->phy_data; 2675 2676 /* If we have an external PHY, free it */ 2677 xgbe_phy_free_phy_device(pdata); 2678 2679 /* Reset SFP data */ 2680 xgbe_phy_sfp_reset(phy_data); 2681 xgbe_phy_sfp_mod_absent(pdata); 2682 2683 /* Power off the PHY */ 2684 xgbe_phy_power_off(pdata); 2685 2686 /* Stop the I2C controller */ 2687 pdata->i2c_if.i2c_stop(pdata); 2688 } 2689 2690 static int xgbe_phy_start(struct xgbe_prv_data *pdata) 2691 { 2692 struct xgbe_phy_data *phy_data = pdata->phy_data; 2693 int ret; 2694 2695 /* Start the I2C controller */ 2696 ret = pdata->i2c_if.i2c_start(pdata); 2697 if (ret) 2698 return ret; 2699 2700 /* Set the proper MDIO mode for the re-driver */ 2701 if (phy_data->redrv && !phy_data->redrv_if) { 2702 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr, 2703 XGBE_MDIO_MODE_CL22); 2704 if (ret) { 2705 netdev_err(pdata->netdev, 2706 "redriver mdio port not compatible (%u)\n", 2707 phy_data->redrv_addr); 2708 return ret; 2709 } 2710 } 2711 2712 /* Start in highest supported mode */ 2713 xgbe_phy_set_mode(pdata, phy_data->start_mode); 2714 2715 /* After starting the I2C controller, we can check for an SFP */ 2716 switch (phy_data->port_mode) { 2717 case XGBE_PORT_MODE_SFP: 2718 xgbe_phy_sfp_detect(pdata); 2719 break; 2720 default: 2721 break; 2722 } 2723 2724 /* If we have an external PHY, start it */ 2725 ret = xgbe_phy_find_phy_device(pdata); 2726 if (ret) 2727 goto err_i2c; 2728 2729 return 0; 2730 2731 err_i2c: 2732 pdata->i2c_if.i2c_stop(pdata); 2733 2734 return ret; 2735 } 2736 2737 static int xgbe_phy_reset(struct xgbe_prv_data *pdata) 2738 { 2739 struct xgbe_phy_data *phy_data = pdata->phy_data; 2740 enum xgbe_mode cur_mode; 2741 int ret; 2742 2743 /* Reset by power cycling the PHY */ 2744 cur_mode = phy_data->cur_mode; 2745 xgbe_phy_power_off(pdata); 2746 xgbe_phy_set_mode(pdata, cur_mode); 2747 2748 if (!phy_data->phydev) 2749 return 0; 2750 2751 /* Reset the external PHY */ 2752 ret = xgbe_phy_mdio_reset(pdata); 2753 if (ret) 2754 return ret; 2755 2756 return phy_init_hw(phy_data->phydev); 2757 } 2758 2759 static void xgbe_phy_exit(struct xgbe_prv_data *pdata) 2760 { 2761 struct xgbe_phy_data *phy_data = pdata->phy_data; 2762 2763 /* Unregister for driving external PHYs */ 2764 mdiobus_unregister(phy_data->mii); 2765 } 2766 2767 static int xgbe_phy_init(struct xgbe_prv_data *pdata) 2768 { 2769 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 2770 struct xgbe_phy_data *phy_data; 2771 struct mii_bus *mii; 2772 unsigned int reg; 2773 int ret; 2774 2775 /* Check if enabled */ 2776 if (!xgbe_phy_port_enabled(pdata)) { 2777 dev_info(pdata->dev, "device is not enabled\n"); 2778 return -ENODEV; 2779 } 2780 2781 /* Initialize the I2C controller */ 2782 ret = pdata->i2c_if.i2c_init(pdata); 2783 if (ret) 2784 return ret; 2785 2786 phy_data = devm_kzalloc(pdata->dev, sizeof(*phy_data), GFP_KERNEL); 2787 if (!phy_data) 2788 return -ENOMEM; 2789 pdata->phy_data = phy_data; 2790 2791 reg = XP_IOREAD(pdata, XP_PROP_0); 2792 phy_data->port_mode = XP_GET_BITS(reg, XP_PROP_0, PORT_MODE); 2793 phy_data->port_id = XP_GET_BITS(reg, XP_PROP_0, PORT_ID); 2794 phy_data->port_speeds = XP_GET_BITS(reg, XP_PROP_0, PORT_SPEEDS); 2795 phy_data->conn_type = XP_GET_BITS(reg, XP_PROP_0, CONN_TYPE); 2796 phy_data->mdio_addr = XP_GET_BITS(reg, XP_PROP_0, MDIO_ADDR); 2797 if (netif_msg_probe(pdata)) { 2798 dev_dbg(pdata->dev, "port mode=%u\n", phy_data->port_mode); 2799 dev_dbg(pdata->dev, "port id=%u\n", phy_data->port_id); 2800 dev_dbg(pdata->dev, "port speeds=%#x\n", phy_data->port_speeds); 2801 dev_dbg(pdata->dev, "conn type=%u\n", phy_data->conn_type); 2802 dev_dbg(pdata->dev, "mdio addr=%u\n", phy_data->mdio_addr); 2803 } 2804 2805 reg = XP_IOREAD(pdata, XP_PROP_4); 2806 phy_data->redrv = XP_GET_BITS(reg, XP_PROP_4, REDRV_PRESENT); 2807 phy_data->redrv_if = XP_GET_BITS(reg, XP_PROP_4, REDRV_IF); 2808 phy_data->redrv_addr = XP_GET_BITS(reg, XP_PROP_4, REDRV_ADDR); 2809 phy_data->redrv_lane = XP_GET_BITS(reg, XP_PROP_4, REDRV_LANE); 2810 phy_data->redrv_model = XP_GET_BITS(reg, XP_PROP_4, REDRV_MODEL); 2811 if (phy_data->redrv && netif_msg_probe(pdata)) { 2812 dev_dbg(pdata->dev, "redrv present\n"); 2813 dev_dbg(pdata->dev, "redrv i/f=%u\n", phy_data->redrv_if); 2814 dev_dbg(pdata->dev, "redrv addr=%#x\n", phy_data->redrv_addr); 2815 dev_dbg(pdata->dev, "redrv lane=%u\n", phy_data->redrv_lane); 2816 dev_dbg(pdata->dev, "redrv model=%u\n", phy_data->redrv_model); 2817 } 2818 2819 /* Validate the connection requested */ 2820 if (xgbe_phy_conn_type_mismatch(pdata)) { 2821 dev_err(pdata->dev, "phy mode/connection mismatch (%#x/%#x)\n", 2822 phy_data->port_mode, phy_data->conn_type); 2823 return -EINVAL; 2824 } 2825 2826 /* Validate the mode requested */ 2827 if (xgbe_phy_port_mode_mismatch(pdata)) { 2828 dev_err(pdata->dev, "phy mode/speed mismatch (%#x/%#x)\n", 2829 phy_data->port_mode, phy_data->port_speeds); 2830 return -EINVAL; 2831 } 2832 2833 /* Check for and validate MDIO reset support */ 2834 ret = xgbe_phy_mdio_reset_setup(pdata); 2835 if (ret) 2836 return ret; 2837 2838 /* Validate the re-driver information */ 2839 if (xgbe_phy_redrv_error(phy_data)) { 2840 dev_err(pdata->dev, "phy re-driver settings error\n"); 2841 return -EINVAL; 2842 } 2843 pdata->kr_redrv = phy_data->redrv; 2844 2845 /* Indicate current mode is unknown */ 2846 phy_data->cur_mode = XGBE_MODE_UNKNOWN; 2847 2848 /* Initialize supported features */ 2849 XGBE_ZERO_SUP(lks); 2850 2851 switch (phy_data->port_mode) { 2852 /* Backplane support */ 2853 case XGBE_PORT_MODE_BACKPLANE: 2854 XGBE_SET_SUP(lks, Autoneg); 2855 XGBE_SET_SUP(lks, Pause); 2856 XGBE_SET_SUP(lks, Asym_Pause); 2857 XGBE_SET_SUP(lks, Backplane); 2858 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) { 2859 XGBE_SET_SUP(lks, 1000baseKX_Full); 2860 phy_data->start_mode = XGBE_MODE_KX_1000; 2861 } 2862 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) { 2863 XGBE_SET_SUP(lks, 10000baseKR_Full); 2864 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 2865 XGBE_SET_SUP(lks, 10000baseR_FEC); 2866 phy_data->start_mode = XGBE_MODE_KR; 2867 } 2868 2869 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE; 2870 break; 2871 case XGBE_PORT_MODE_BACKPLANE_2500: 2872 XGBE_SET_SUP(lks, Pause); 2873 XGBE_SET_SUP(lks, Asym_Pause); 2874 XGBE_SET_SUP(lks, Backplane); 2875 XGBE_SET_SUP(lks, 2500baseX_Full); 2876 phy_data->start_mode = XGBE_MODE_KX_2500; 2877 2878 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE; 2879 break; 2880 2881 /* MDIO 1GBase-T support */ 2882 case XGBE_PORT_MODE_1000BASE_T: 2883 XGBE_SET_SUP(lks, Autoneg); 2884 XGBE_SET_SUP(lks, Pause); 2885 XGBE_SET_SUP(lks, Asym_Pause); 2886 XGBE_SET_SUP(lks, TP); 2887 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) { 2888 XGBE_SET_SUP(lks, 100baseT_Full); 2889 phy_data->start_mode = XGBE_MODE_SGMII_100; 2890 } 2891 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) { 2892 XGBE_SET_SUP(lks, 1000baseT_Full); 2893 phy_data->start_mode = XGBE_MODE_SGMII_1000; 2894 } 2895 2896 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22; 2897 break; 2898 2899 /* MDIO Base-X support */ 2900 case XGBE_PORT_MODE_1000BASE_X: 2901 XGBE_SET_SUP(lks, Autoneg); 2902 XGBE_SET_SUP(lks, Pause); 2903 XGBE_SET_SUP(lks, Asym_Pause); 2904 XGBE_SET_SUP(lks, FIBRE); 2905 XGBE_SET_SUP(lks, 1000baseX_Full); 2906 phy_data->start_mode = XGBE_MODE_X; 2907 2908 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22; 2909 break; 2910 2911 /* MDIO NBase-T support */ 2912 case XGBE_PORT_MODE_NBASE_T: 2913 XGBE_SET_SUP(lks, Autoneg); 2914 XGBE_SET_SUP(lks, Pause); 2915 XGBE_SET_SUP(lks, Asym_Pause); 2916 XGBE_SET_SUP(lks, TP); 2917 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) { 2918 XGBE_SET_SUP(lks, 100baseT_Full); 2919 phy_data->start_mode = XGBE_MODE_SGMII_100; 2920 } 2921 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) { 2922 XGBE_SET_SUP(lks, 1000baseT_Full); 2923 phy_data->start_mode = XGBE_MODE_SGMII_1000; 2924 } 2925 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500) { 2926 XGBE_SET_SUP(lks, 2500baseT_Full); 2927 phy_data->start_mode = XGBE_MODE_KX_2500; 2928 } 2929 2930 phy_data->phydev_mode = XGBE_MDIO_MODE_CL45; 2931 break; 2932 2933 /* 10GBase-T support */ 2934 case XGBE_PORT_MODE_10GBASE_T: 2935 XGBE_SET_SUP(lks, Autoneg); 2936 XGBE_SET_SUP(lks, Pause); 2937 XGBE_SET_SUP(lks, Asym_Pause); 2938 XGBE_SET_SUP(lks, TP); 2939 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) { 2940 XGBE_SET_SUP(lks, 100baseT_Full); 2941 phy_data->start_mode = XGBE_MODE_SGMII_100; 2942 } 2943 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) { 2944 XGBE_SET_SUP(lks, 1000baseT_Full); 2945 phy_data->start_mode = XGBE_MODE_SGMII_1000; 2946 } 2947 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) { 2948 XGBE_SET_SUP(lks, 10000baseT_Full); 2949 phy_data->start_mode = XGBE_MODE_KR; 2950 } 2951 2952 phy_data->phydev_mode = XGBE_MDIO_MODE_CL45; 2953 break; 2954 2955 /* 10GBase-R support */ 2956 case XGBE_PORT_MODE_10GBASE_R: 2957 XGBE_SET_SUP(lks, Autoneg); 2958 XGBE_SET_SUP(lks, Pause); 2959 XGBE_SET_SUP(lks, Asym_Pause); 2960 XGBE_SET_SUP(lks, FIBRE); 2961 XGBE_SET_SUP(lks, 10000baseSR_Full); 2962 XGBE_SET_SUP(lks, 10000baseLR_Full); 2963 XGBE_SET_SUP(lks, 10000baseLRM_Full); 2964 XGBE_SET_SUP(lks, 10000baseER_Full); 2965 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 2966 XGBE_SET_SUP(lks, 10000baseR_FEC); 2967 phy_data->start_mode = XGBE_MODE_SFI; 2968 2969 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE; 2970 break; 2971 2972 /* SFP support */ 2973 case XGBE_PORT_MODE_SFP: 2974 XGBE_SET_SUP(lks, Autoneg); 2975 XGBE_SET_SUP(lks, Pause); 2976 XGBE_SET_SUP(lks, Asym_Pause); 2977 XGBE_SET_SUP(lks, TP); 2978 XGBE_SET_SUP(lks, FIBRE); 2979 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) 2980 phy_data->start_mode = XGBE_MODE_SGMII_100; 2981 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) 2982 phy_data->start_mode = XGBE_MODE_SGMII_1000; 2983 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) 2984 phy_data->start_mode = XGBE_MODE_SFI; 2985 2986 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22; 2987 2988 xgbe_phy_sfp_setup(pdata); 2989 break; 2990 default: 2991 return -EINVAL; 2992 } 2993 2994 if (netif_msg_probe(pdata)) 2995 dev_dbg(pdata->dev, "phy supported=0x%*pb\n", 2996 __ETHTOOL_LINK_MODE_MASK_NBITS, 2997 lks->link_modes.supported); 2998 2999 if ((phy_data->conn_type & XGBE_CONN_TYPE_MDIO) && 3000 (phy_data->phydev_mode != XGBE_MDIO_MODE_NONE)) { 3001 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr, 3002 phy_data->phydev_mode); 3003 if (ret) { 3004 dev_err(pdata->dev, 3005 "mdio port/clause not compatible (%d/%u)\n", 3006 phy_data->mdio_addr, phy_data->phydev_mode); 3007 return -EINVAL; 3008 } 3009 } 3010 3011 if (phy_data->redrv && !phy_data->redrv_if) { 3012 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr, 3013 XGBE_MDIO_MODE_CL22); 3014 if (ret) { 3015 dev_err(pdata->dev, 3016 "redriver mdio port not compatible (%u)\n", 3017 phy_data->redrv_addr); 3018 return -EINVAL; 3019 } 3020 } 3021 3022 /* Register for driving external PHYs */ 3023 mii = devm_mdiobus_alloc(pdata->dev); 3024 if (!mii) { 3025 dev_err(pdata->dev, "mdiobus_alloc failed\n"); 3026 return -ENOMEM; 3027 } 3028 3029 mii->priv = pdata; 3030 mii->name = "amd-xgbe-mii"; 3031 mii->read = xgbe_phy_mii_read; 3032 mii->write = xgbe_phy_mii_write; 3033 mii->parent = pdata->dev; 3034 mii->phy_mask = ~0; 3035 snprintf(mii->id, sizeof(mii->id), "%s", dev_name(pdata->dev)); 3036 ret = mdiobus_register(mii); 3037 if (ret) { 3038 dev_err(pdata->dev, "mdiobus_register failed\n"); 3039 return ret; 3040 } 3041 phy_data->mii = mii; 3042 3043 return 0; 3044 } 3045 3046 void xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if *phy_if) 3047 { 3048 struct xgbe_phy_impl_if *phy_impl = &phy_if->phy_impl; 3049 3050 phy_impl->init = xgbe_phy_init; 3051 phy_impl->exit = xgbe_phy_exit; 3052 3053 phy_impl->reset = xgbe_phy_reset; 3054 phy_impl->start = xgbe_phy_start; 3055 phy_impl->stop = xgbe_phy_stop; 3056 3057 phy_impl->link_status = xgbe_phy_link_status; 3058 3059 phy_impl->valid_speed = xgbe_phy_valid_speed; 3060 3061 phy_impl->use_mode = xgbe_phy_use_mode; 3062 phy_impl->set_mode = xgbe_phy_set_mode; 3063 phy_impl->get_mode = xgbe_phy_get_mode; 3064 phy_impl->switch_mode = xgbe_phy_switch_mode; 3065 phy_impl->cur_mode = xgbe_phy_cur_mode; 3066 3067 phy_impl->an_mode = xgbe_phy_an_mode; 3068 3069 phy_impl->an_config = xgbe_phy_an_config; 3070 3071 phy_impl->an_advertising = xgbe_phy_an_advertising; 3072 3073 phy_impl->an_outcome = xgbe_phy_an_outcome; 3074 } 3075