1 /* 2 * AMD 10Gb Ethernet driver 3 * 4 * This file is available to you under your choice of the following two 5 * licenses: 6 * 7 * License 1: GPLv2 8 * 9 * Copyright (c) 2016 Advanced Micro Devices, Inc. 10 * 11 * This file is free software; you may copy, redistribute and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation, either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program. If not, see <http://www.gnu.org/licenses/>. 23 * 24 * This file incorporates work covered by the following copyright and 25 * permission notice: 26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 28 * Inc. unless otherwise expressly agreed to in writing between Synopsys 29 * and you. 30 * 31 * The Software IS NOT an item of Licensed Software or Licensed Product 32 * under any End User Software License Agreement or Agreement for Licensed 33 * Product with Synopsys or any supplement thereto. Permission is hereby 34 * granted, free of charge, to any person obtaining a copy of this software 35 * annotated with this license and the Software, to deal in the Software 36 * without restriction, including without limitation the rights to use, 37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 38 * of the Software, and to permit persons to whom the Software is furnished 39 * to do so, subject to the following conditions: 40 * 41 * The above copyright notice and this permission notice shall be included 42 * in all copies or substantial portions of the Software. 43 * 44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 54 * THE POSSIBILITY OF SUCH DAMAGE. 55 * 56 * 57 * License 2: Modified BSD 58 * 59 * Copyright (c) 2016 Advanced Micro Devices, Inc. 60 * All rights reserved. 61 * 62 * Redistribution and use in source and binary forms, with or without 63 * modification, are permitted provided that the following conditions are met: 64 * * Redistributions of source code must retain the above copyright 65 * notice, this list of conditions and the following disclaimer. 66 * * Redistributions in binary form must reproduce the above copyright 67 * notice, this list of conditions and the following disclaimer in the 68 * documentation and/or other materials provided with the distribution. 69 * * Neither the name of Advanced Micro Devices, Inc. nor the 70 * names of its contributors may be used to endorse or promote products 71 * derived from this software without specific prior written permission. 72 * 73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY 77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 83 * 84 * This file incorporates work covered by the following copyright and 85 * permission notice: 86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 88 * Inc. unless otherwise expressly agreed to in writing between Synopsys 89 * and you. 90 * 91 * The Software IS NOT an item of Licensed Software or Licensed Product 92 * under any End User Software License Agreement or Agreement for Licensed 93 * Product with Synopsys or any supplement thereto. Permission is hereby 94 * granted, free of charge, to any person obtaining a copy of this software 95 * annotated with this license and the Software, to deal in the Software 96 * without restriction, including without limitation the rights to use, 97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 98 * of the Software, and to permit persons to whom the Software is furnished 99 * to do so, subject to the following conditions: 100 * 101 * The above copyright notice and this permission notice shall be included 102 * in all copies or substantial portions of the Software. 103 * 104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 114 * THE POSSIBILITY OF SUCH DAMAGE. 115 */ 116 117 #include <linux/module.h> 118 #include <linux/device.h> 119 #include <linux/kmod.h> 120 #include <linux/mdio.h> 121 #include <linux/phy.h> 122 #include <linux/ethtool.h> 123 124 #include "xgbe.h" 125 #include "xgbe-common.h" 126 127 #define XGBE_PHY_PORT_SPEED_100 BIT(1) 128 #define XGBE_PHY_PORT_SPEED_1000 BIT(2) 129 #define XGBE_PHY_PORT_SPEED_2500 BIT(3) 130 #define XGBE_PHY_PORT_SPEED_10000 BIT(4) 131 132 #define XGBE_MUTEX_RELEASE 0x80000000 133 134 #define XGBE_SFP_DIRECT 7 135 136 /* I2C target addresses */ 137 #define XGBE_SFP_SERIAL_ID_ADDRESS 0x50 138 #define XGBE_SFP_DIAG_INFO_ADDRESS 0x51 139 #define XGBE_SFP_PHY_ADDRESS 0x56 140 #define XGBE_GPIO_ADDRESS_PCA9555 0x20 141 142 /* SFP sideband signal indicators */ 143 #define XGBE_GPIO_NO_TX_FAULT BIT(0) 144 #define XGBE_GPIO_NO_RATE_SELECT BIT(1) 145 #define XGBE_GPIO_NO_MOD_ABSENT BIT(2) 146 #define XGBE_GPIO_NO_RX_LOS BIT(3) 147 148 /* Rate-change complete wait/retry count */ 149 #define XGBE_RATECHANGE_COUNT 500 150 151 /* CDR delay values for KR support (in usec) */ 152 #define XGBE_CDR_DELAY_INIT 10000 153 #define XGBE_CDR_DELAY_INC 10000 154 #define XGBE_CDR_DELAY_MAX 100000 155 156 /* RRC frequency during link status check */ 157 #define XGBE_RRC_FREQUENCY 10 158 159 enum xgbe_port_mode { 160 XGBE_PORT_MODE_RSVD = 0, 161 XGBE_PORT_MODE_BACKPLANE, 162 XGBE_PORT_MODE_BACKPLANE_2500, 163 XGBE_PORT_MODE_1000BASE_T, 164 XGBE_PORT_MODE_1000BASE_X, 165 XGBE_PORT_MODE_NBASE_T, 166 XGBE_PORT_MODE_10GBASE_T, 167 XGBE_PORT_MODE_10GBASE_R, 168 XGBE_PORT_MODE_SFP, 169 XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG, 170 XGBE_PORT_MODE_MAX, 171 }; 172 173 enum xgbe_conn_type { 174 XGBE_CONN_TYPE_NONE = 0, 175 XGBE_CONN_TYPE_SFP, 176 XGBE_CONN_TYPE_MDIO, 177 XGBE_CONN_TYPE_RSVD1, 178 XGBE_CONN_TYPE_BACKPLANE, 179 XGBE_CONN_TYPE_MAX, 180 }; 181 182 /* SFP/SFP+ related definitions */ 183 enum xgbe_sfp_comm { 184 XGBE_SFP_COMM_DIRECT = 0, 185 XGBE_SFP_COMM_PCA9545, 186 }; 187 188 enum xgbe_sfp_cable { 189 XGBE_SFP_CABLE_UNKNOWN = 0, 190 XGBE_SFP_CABLE_ACTIVE, 191 XGBE_SFP_CABLE_PASSIVE, 192 XGBE_SFP_CABLE_FIBER, 193 }; 194 195 enum xgbe_sfp_base { 196 XGBE_SFP_BASE_UNKNOWN = 0, 197 XGBE_SFP_BASE_1000_T, 198 XGBE_SFP_BASE_1000_SX, 199 XGBE_SFP_BASE_1000_LX, 200 XGBE_SFP_BASE_1000_CX, 201 XGBE_SFP_BASE_10000_SR, 202 XGBE_SFP_BASE_10000_LR, 203 XGBE_SFP_BASE_10000_LRM, 204 XGBE_SFP_BASE_10000_ER, 205 XGBE_SFP_BASE_10000_CR, 206 }; 207 208 enum xgbe_sfp_speed { 209 XGBE_SFP_SPEED_UNKNOWN = 0, 210 XGBE_SFP_SPEED_100_1000, 211 XGBE_SFP_SPEED_1000, 212 XGBE_SFP_SPEED_10000, 213 }; 214 215 /* SFP Serial ID Base ID values relative to an offset of 0 */ 216 #define XGBE_SFP_BASE_ID 0 217 #define XGBE_SFP_ID_SFP 0x03 218 219 #define XGBE_SFP_BASE_EXT_ID 1 220 #define XGBE_SFP_EXT_ID_SFP 0x04 221 222 #define XGBE_SFP_BASE_10GBE_CC 3 223 #define XGBE_SFP_BASE_10GBE_CC_SR BIT(4) 224 #define XGBE_SFP_BASE_10GBE_CC_LR BIT(5) 225 #define XGBE_SFP_BASE_10GBE_CC_LRM BIT(6) 226 #define XGBE_SFP_BASE_10GBE_CC_ER BIT(7) 227 228 #define XGBE_SFP_BASE_1GBE_CC 6 229 #define XGBE_SFP_BASE_1GBE_CC_SX BIT(0) 230 #define XGBE_SFP_BASE_1GBE_CC_LX BIT(1) 231 #define XGBE_SFP_BASE_1GBE_CC_CX BIT(2) 232 #define XGBE_SFP_BASE_1GBE_CC_T BIT(3) 233 234 #define XGBE_SFP_BASE_CABLE 8 235 #define XGBE_SFP_BASE_CABLE_PASSIVE BIT(2) 236 #define XGBE_SFP_BASE_CABLE_ACTIVE BIT(3) 237 238 #define XGBE_SFP_BASE_BR 12 239 #define XGBE_SFP_BASE_BR_1GBE_MIN 0x0a 240 #define XGBE_SFP_BASE_BR_10GBE_MIN 0x64 241 242 #define XGBE_SFP_BASE_CU_CABLE_LEN 18 243 244 #define XGBE_SFP_BASE_VENDOR_NAME 20 245 #define XGBE_SFP_BASE_VENDOR_NAME_LEN 16 246 #define XGBE_SFP_BASE_VENDOR_PN 40 247 #define XGBE_SFP_BASE_VENDOR_PN_LEN 16 248 #define XGBE_SFP_BASE_VENDOR_REV 56 249 #define XGBE_SFP_BASE_VENDOR_REV_LEN 4 250 251 #define XGBE_SFP_BASE_CC 63 252 253 /* SFP Serial ID Extended ID values relative to an offset of 64 */ 254 #define XGBE_SFP_BASE_VENDOR_SN 4 255 #define XGBE_SFP_BASE_VENDOR_SN_LEN 16 256 257 #define XGBE_SFP_EXTD_OPT1 1 258 #define XGBE_SFP_EXTD_OPT1_RX_LOS BIT(1) 259 #define XGBE_SFP_EXTD_OPT1_TX_FAULT BIT(3) 260 261 #define XGBE_SFP_EXTD_DIAG 28 262 #define XGBE_SFP_EXTD_DIAG_ADDR_CHANGE BIT(2) 263 264 #define XGBE_SFP_EXTD_SFF_8472 30 265 266 #define XGBE_SFP_EXTD_CC 31 267 268 struct xgbe_sfp_eeprom { 269 u8 base[64]; 270 u8 extd[32]; 271 u8 vendor[32]; 272 }; 273 274 #define XGBE_SFP_DIAGS_SUPPORTED(_x) \ 275 ((_x)->extd[XGBE_SFP_EXTD_SFF_8472] && \ 276 !((_x)->extd[XGBE_SFP_EXTD_DIAG] & XGBE_SFP_EXTD_DIAG_ADDR_CHANGE)) 277 278 #define XGBE_SFP_EEPROM_BASE_LEN 256 279 #define XGBE_SFP_EEPROM_DIAG_LEN 256 280 #define XGBE_SFP_EEPROM_MAX (XGBE_SFP_EEPROM_BASE_LEN + \ 281 XGBE_SFP_EEPROM_DIAG_LEN) 282 283 #define XGBE_BEL_FUSE_VENDOR "BEL-FUSE " 284 #define XGBE_BEL_FUSE_PARTNO "1GBT-SFP06 " 285 286 #define XGBE_MOLEX_VENDOR "Molex Inc. " 287 288 struct xgbe_sfp_ascii { 289 union { 290 char vendor[XGBE_SFP_BASE_VENDOR_NAME_LEN + 1]; 291 char partno[XGBE_SFP_BASE_VENDOR_PN_LEN + 1]; 292 char rev[XGBE_SFP_BASE_VENDOR_REV_LEN + 1]; 293 char serno[XGBE_SFP_BASE_VENDOR_SN_LEN + 1]; 294 } u; 295 }; 296 297 /* MDIO PHY reset types */ 298 enum xgbe_mdio_reset { 299 XGBE_MDIO_RESET_NONE = 0, 300 XGBE_MDIO_RESET_I2C_GPIO, 301 XGBE_MDIO_RESET_INT_GPIO, 302 XGBE_MDIO_RESET_MAX, 303 }; 304 305 /* Re-driver related definitions */ 306 enum xgbe_phy_redrv_if { 307 XGBE_PHY_REDRV_IF_MDIO = 0, 308 XGBE_PHY_REDRV_IF_I2C, 309 XGBE_PHY_REDRV_IF_MAX, 310 }; 311 312 enum xgbe_phy_redrv_model { 313 XGBE_PHY_REDRV_MODEL_4223 = 0, 314 XGBE_PHY_REDRV_MODEL_4227, 315 XGBE_PHY_REDRV_MODEL_MAX, 316 }; 317 318 enum xgbe_phy_redrv_mode { 319 XGBE_PHY_REDRV_MODE_CX = 5, 320 XGBE_PHY_REDRV_MODE_SR = 9, 321 }; 322 323 #define XGBE_PHY_REDRV_MODE_REG 0x12b0 324 325 /* PHY related configuration information */ 326 struct xgbe_phy_data { 327 enum xgbe_port_mode port_mode; 328 329 unsigned int port_id; 330 331 unsigned int port_speeds; 332 333 enum xgbe_conn_type conn_type; 334 335 enum xgbe_mode cur_mode; 336 enum xgbe_mode start_mode; 337 338 unsigned int rrc_count; 339 340 unsigned int mdio_addr; 341 342 /* SFP Support */ 343 enum xgbe_sfp_comm sfp_comm; 344 unsigned int sfp_mux_address; 345 unsigned int sfp_mux_channel; 346 347 unsigned int sfp_gpio_address; 348 unsigned int sfp_gpio_mask; 349 unsigned int sfp_gpio_inputs; 350 unsigned int sfp_gpio_rx_los; 351 unsigned int sfp_gpio_tx_fault; 352 unsigned int sfp_gpio_mod_absent; 353 unsigned int sfp_gpio_rate_select; 354 355 unsigned int sfp_rx_los; 356 unsigned int sfp_tx_fault; 357 unsigned int sfp_mod_absent; 358 unsigned int sfp_changed; 359 unsigned int sfp_phy_avail; 360 unsigned int sfp_cable_len; 361 enum xgbe_sfp_base sfp_base; 362 enum xgbe_sfp_cable sfp_cable; 363 enum xgbe_sfp_speed sfp_speed; 364 struct xgbe_sfp_eeprom sfp_eeprom; 365 366 /* External PHY support */ 367 enum xgbe_mdio_mode phydev_mode; 368 struct mii_bus *mii; 369 struct phy_device *phydev; 370 enum xgbe_mdio_reset mdio_reset; 371 unsigned int mdio_reset_addr; 372 unsigned int mdio_reset_gpio; 373 374 /* Re-driver support */ 375 unsigned int redrv; 376 unsigned int redrv_if; 377 unsigned int redrv_addr; 378 unsigned int redrv_lane; 379 unsigned int redrv_model; 380 381 /* KR AN support */ 382 unsigned int phy_cdr_notrack; 383 unsigned int phy_cdr_delay; 384 }; 385 386 /* I2C, MDIO and GPIO lines are muxed, so only one device at a time */ 387 static DEFINE_MUTEX(xgbe_phy_comm_lock); 388 389 static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata); 390 391 static int xgbe_phy_i2c_xfer(struct xgbe_prv_data *pdata, 392 struct xgbe_i2c_op *i2c_op) 393 { 394 return pdata->i2c_if.i2c_xfer(pdata, i2c_op); 395 } 396 397 static int xgbe_phy_redrv_write(struct xgbe_prv_data *pdata, unsigned int reg, 398 unsigned int val) 399 { 400 struct xgbe_phy_data *phy_data = pdata->phy_data; 401 struct xgbe_i2c_op i2c_op; 402 __be16 *redrv_val; 403 u8 redrv_data[5], csum; 404 unsigned int i, retry; 405 int ret; 406 407 /* High byte of register contains read/write indicator */ 408 redrv_data[0] = ((reg >> 8) & 0xff) << 1; 409 redrv_data[1] = reg & 0xff; 410 redrv_val = (__be16 *)&redrv_data[2]; 411 *redrv_val = cpu_to_be16(val); 412 413 /* Calculate 1 byte checksum */ 414 csum = 0; 415 for (i = 0; i < 4; i++) { 416 csum += redrv_data[i]; 417 if (redrv_data[i] > csum) 418 csum++; 419 } 420 redrv_data[4] = ~csum; 421 422 retry = 1; 423 again1: 424 i2c_op.cmd = XGBE_I2C_CMD_WRITE; 425 i2c_op.target = phy_data->redrv_addr; 426 i2c_op.len = sizeof(redrv_data); 427 i2c_op.buf = redrv_data; 428 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op); 429 if (ret) { 430 if ((ret == -EAGAIN) && retry--) 431 goto again1; 432 433 return ret; 434 } 435 436 retry = 1; 437 again2: 438 i2c_op.cmd = XGBE_I2C_CMD_READ; 439 i2c_op.target = phy_data->redrv_addr; 440 i2c_op.len = 1; 441 i2c_op.buf = redrv_data; 442 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op); 443 if (ret) { 444 if ((ret == -EAGAIN) && retry--) 445 goto again2; 446 447 return ret; 448 } 449 450 if (redrv_data[0] != 0xff) { 451 netif_dbg(pdata, drv, pdata->netdev, 452 "Redriver write checksum error\n"); 453 ret = -EIO; 454 } 455 456 return ret; 457 } 458 459 static int xgbe_phy_i2c_write(struct xgbe_prv_data *pdata, unsigned int target, 460 void *val, unsigned int val_len) 461 { 462 struct xgbe_i2c_op i2c_op; 463 int retry, ret; 464 465 retry = 1; 466 again: 467 /* Write the specfied register */ 468 i2c_op.cmd = XGBE_I2C_CMD_WRITE; 469 i2c_op.target = target; 470 i2c_op.len = val_len; 471 i2c_op.buf = val; 472 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op); 473 if ((ret == -EAGAIN) && retry--) 474 goto again; 475 476 return ret; 477 } 478 479 static int xgbe_phy_i2c_read(struct xgbe_prv_data *pdata, unsigned int target, 480 void *reg, unsigned int reg_len, 481 void *val, unsigned int val_len) 482 { 483 struct xgbe_i2c_op i2c_op; 484 int retry, ret; 485 486 retry = 1; 487 again1: 488 /* Set the specified register to read */ 489 i2c_op.cmd = XGBE_I2C_CMD_WRITE; 490 i2c_op.target = target; 491 i2c_op.len = reg_len; 492 i2c_op.buf = reg; 493 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op); 494 if (ret) { 495 if ((ret == -EAGAIN) && retry--) 496 goto again1; 497 498 return ret; 499 } 500 501 retry = 1; 502 again2: 503 /* Read the specfied register */ 504 i2c_op.cmd = XGBE_I2C_CMD_READ; 505 i2c_op.target = target; 506 i2c_op.len = val_len; 507 i2c_op.buf = val; 508 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op); 509 if ((ret == -EAGAIN) && retry--) 510 goto again2; 511 512 return ret; 513 } 514 515 static int xgbe_phy_sfp_put_mux(struct xgbe_prv_data *pdata) 516 { 517 struct xgbe_phy_data *phy_data = pdata->phy_data; 518 struct xgbe_i2c_op i2c_op; 519 u8 mux_channel; 520 521 if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT) 522 return 0; 523 524 /* Select no mux channels */ 525 mux_channel = 0; 526 i2c_op.cmd = XGBE_I2C_CMD_WRITE; 527 i2c_op.target = phy_data->sfp_mux_address; 528 i2c_op.len = sizeof(mux_channel); 529 i2c_op.buf = &mux_channel; 530 531 return xgbe_phy_i2c_xfer(pdata, &i2c_op); 532 } 533 534 static int xgbe_phy_sfp_get_mux(struct xgbe_prv_data *pdata) 535 { 536 struct xgbe_phy_data *phy_data = pdata->phy_data; 537 struct xgbe_i2c_op i2c_op; 538 u8 mux_channel; 539 540 if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT) 541 return 0; 542 543 /* Select desired mux channel */ 544 mux_channel = 1 << phy_data->sfp_mux_channel; 545 i2c_op.cmd = XGBE_I2C_CMD_WRITE; 546 i2c_op.target = phy_data->sfp_mux_address; 547 i2c_op.len = sizeof(mux_channel); 548 i2c_op.buf = &mux_channel; 549 550 return xgbe_phy_i2c_xfer(pdata, &i2c_op); 551 } 552 553 static void xgbe_phy_put_comm_ownership(struct xgbe_prv_data *pdata) 554 { 555 mutex_unlock(&xgbe_phy_comm_lock); 556 } 557 558 static int xgbe_phy_get_comm_ownership(struct xgbe_prv_data *pdata) 559 { 560 struct xgbe_phy_data *phy_data = pdata->phy_data; 561 unsigned long timeout; 562 unsigned int mutex_id; 563 564 /* The I2C and MDIO/GPIO bus is multiplexed between multiple devices, 565 * the driver needs to take the software mutex and then the hardware 566 * mutexes before being able to use the busses. 567 */ 568 mutex_lock(&xgbe_phy_comm_lock); 569 570 /* Clear the mutexes */ 571 XP_IOWRITE(pdata, XP_I2C_MUTEX, XGBE_MUTEX_RELEASE); 572 XP_IOWRITE(pdata, XP_MDIO_MUTEX, XGBE_MUTEX_RELEASE); 573 574 /* Mutex formats are the same for I2C and MDIO/GPIO */ 575 mutex_id = 0; 576 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ID, phy_data->port_id); 577 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ACTIVE, 1); 578 579 timeout = jiffies + (5 * HZ); 580 while (time_before(jiffies, timeout)) { 581 /* Must be all zeroes in order to obtain the mutex */ 582 if (XP_IOREAD(pdata, XP_I2C_MUTEX) || 583 XP_IOREAD(pdata, XP_MDIO_MUTEX)) { 584 usleep_range(100, 200); 585 continue; 586 } 587 588 /* Obtain the mutex */ 589 XP_IOWRITE(pdata, XP_I2C_MUTEX, mutex_id); 590 XP_IOWRITE(pdata, XP_MDIO_MUTEX, mutex_id); 591 592 return 0; 593 } 594 595 mutex_unlock(&xgbe_phy_comm_lock); 596 597 netdev_err(pdata->netdev, "unable to obtain hardware mutexes\n"); 598 599 return -ETIMEDOUT; 600 } 601 602 static int xgbe_phy_mdio_mii_write(struct xgbe_prv_data *pdata, int addr, 603 int reg, u16 val) 604 { 605 struct xgbe_phy_data *phy_data = pdata->phy_data; 606 607 if (reg & MII_ADDR_C45) { 608 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45) 609 return -ENOTSUPP; 610 } else { 611 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22) 612 return -ENOTSUPP; 613 } 614 615 return pdata->hw_if.write_ext_mii_regs(pdata, addr, reg, val); 616 } 617 618 static int xgbe_phy_i2c_mii_write(struct xgbe_prv_data *pdata, int reg, u16 val) 619 { 620 __be16 *mii_val; 621 u8 mii_data[3]; 622 int ret; 623 624 ret = xgbe_phy_sfp_get_mux(pdata); 625 if (ret) 626 return ret; 627 628 mii_data[0] = reg & 0xff; 629 mii_val = (__be16 *)&mii_data[1]; 630 *mii_val = cpu_to_be16(val); 631 632 ret = xgbe_phy_i2c_write(pdata, XGBE_SFP_PHY_ADDRESS, 633 mii_data, sizeof(mii_data)); 634 635 xgbe_phy_sfp_put_mux(pdata); 636 637 return ret; 638 } 639 640 static int xgbe_phy_mii_write(struct mii_bus *mii, int addr, int reg, u16 val) 641 { 642 struct xgbe_prv_data *pdata = mii->priv; 643 struct xgbe_phy_data *phy_data = pdata->phy_data; 644 int ret; 645 646 ret = xgbe_phy_get_comm_ownership(pdata); 647 if (ret) 648 return ret; 649 650 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP) 651 ret = xgbe_phy_i2c_mii_write(pdata, reg, val); 652 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO) 653 ret = xgbe_phy_mdio_mii_write(pdata, addr, reg, val); 654 else 655 ret = -ENOTSUPP; 656 657 xgbe_phy_put_comm_ownership(pdata); 658 659 return ret; 660 } 661 662 static int xgbe_phy_mdio_mii_read(struct xgbe_prv_data *pdata, int addr, 663 int reg) 664 { 665 struct xgbe_phy_data *phy_data = pdata->phy_data; 666 667 if (reg & MII_ADDR_C45) { 668 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45) 669 return -ENOTSUPP; 670 } else { 671 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22) 672 return -ENOTSUPP; 673 } 674 675 return pdata->hw_if.read_ext_mii_regs(pdata, addr, reg); 676 } 677 678 static int xgbe_phy_i2c_mii_read(struct xgbe_prv_data *pdata, int reg) 679 { 680 __be16 mii_val; 681 u8 mii_reg; 682 int ret; 683 684 ret = xgbe_phy_sfp_get_mux(pdata); 685 if (ret) 686 return ret; 687 688 mii_reg = reg; 689 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_PHY_ADDRESS, 690 &mii_reg, sizeof(mii_reg), 691 &mii_val, sizeof(mii_val)); 692 if (!ret) 693 ret = be16_to_cpu(mii_val); 694 695 xgbe_phy_sfp_put_mux(pdata); 696 697 return ret; 698 } 699 700 static int xgbe_phy_mii_read(struct mii_bus *mii, int addr, int reg) 701 { 702 struct xgbe_prv_data *pdata = mii->priv; 703 struct xgbe_phy_data *phy_data = pdata->phy_data; 704 int ret; 705 706 ret = xgbe_phy_get_comm_ownership(pdata); 707 if (ret) 708 return ret; 709 710 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP) 711 ret = xgbe_phy_i2c_mii_read(pdata, reg); 712 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO) 713 ret = xgbe_phy_mdio_mii_read(pdata, addr, reg); 714 else 715 ret = -ENOTSUPP; 716 717 xgbe_phy_put_comm_ownership(pdata); 718 719 return ret; 720 } 721 722 static void xgbe_phy_sfp_phy_settings(struct xgbe_prv_data *pdata) 723 { 724 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 725 struct xgbe_phy_data *phy_data = pdata->phy_data; 726 727 if (!phy_data->sfp_mod_absent && !phy_data->sfp_changed) 728 return; 729 730 XGBE_ZERO_SUP(lks); 731 732 if (phy_data->sfp_mod_absent) { 733 pdata->phy.speed = SPEED_UNKNOWN; 734 pdata->phy.duplex = DUPLEX_UNKNOWN; 735 pdata->phy.autoneg = AUTONEG_ENABLE; 736 pdata->phy.pause_autoneg = AUTONEG_ENABLE; 737 738 XGBE_SET_SUP(lks, Autoneg); 739 XGBE_SET_SUP(lks, Pause); 740 XGBE_SET_SUP(lks, Asym_Pause); 741 XGBE_SET_SUP(lks, TP); 742 XGBE_SET_SUP(lks, FIBRE); 743 744 XGBE_LM_COPY(lks, advertising, lks, supported); 745 746 return; 747 } 748 749 switch (phy_data->sfp_base) { 750 case XGBE_SFP_BASE_1000_T: 751 case XGBE_SFP_BASE_1000_SX: 752 case XGBE_SFP_BASE_1000_LX: 753 case XGBE_SFP_BASE_1000_CX: 754 pdata->phy.speed = SPEED_UNKNOWN; 755 pdata->phy.duplex = DUPLEX_UNKNOWN; 756 pdata->phy.autoneg = AUTONEG_ENABLE; 757 pdata->phy.pause_autoneg = AUTONEG_ENABLE; 758 XGBE_SET_SUP(lks, Autoneg); 759 XGBE_SET_SUP(lks, Pause); 760 XGBE_SET_SUP(lks, Asym_Pause); 761 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T) { 762 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) 763 XGBE_SET_SUP(lks, 100baseT_Full); 764 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) 765 XGBE_SET_SUP(lks, 1000baseT_Full); 766 } else { 767 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) 768 XGBE_SET_SUP(lks, 1000baseX_Full); 769 } 770 break; 771 case XGBE_SFP_BASE_10000_SR: 772 case XGBE_SFP_BASE_10000_LR: 773 case XGBE_SFP_BASE_10000_LRM: 774 case XGBE_SFP_BASE_10000_ER: 775 case XGBE_SFP_BASE_10000_CR: 776 pdata->phy.speed = SPEED_10000; 777 pdata->phy.duplex = DUPLEX_FULL; 778 pdata->phy.autoneg = AUTONEG_DISABLE; 779 pdata->phy.pause_autoneg = AUTONEG_DISABLE; 780 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) { 781 switch (phy_data->sfp_base) { 782 case XGBE_SFP_BASE_10000_SR: 783 XGBE_SET_SUP(lks, 10000baseSR_Full); 784 break; 785 case XGBE_SFP_BASE_10000_LR: 786 XGBE_SET_SUP(lks, 10000baseLR_Full); 787 break; 788 case XGBE_SFP_BASE_10000_LRM: 789 XGBE_SET_SUP(lks, 10000baseLRM_Full); 790 break; 791 case XGBE_SFP_BASE_10000_ER: 792 XGBE_SET_SUP(lks, 10000baseER_Full); 793 break; 794 case XGBE_SFP_BASE_10000_CR: 795 XGBE_SET_SUP(lks, 10000baseCR_Full); 796 break; 797 default: 798 break; 799 } 800 } 801 break; 802 default: 803 pdata->phy.speed = SPEED_UNKNOWN; 804 pdata->phy.duplex = DUPLEX_UNKNOWN; 805 pdata->phy.autoneg = AUTONEG_DISABLE; 806 pdata->phy.pause_autoneg = AUTONEG_DISABLE; 807 break; 808 } 809 810 switch (phy_data->sfp_base) { 811 case XGBE_SFP_BASE_1000_T: 812 case XGBE_SFP_BASE_1000_CX: 813 case XGBE_SFP_BASE_10000_CR: 814 XGBE_SET_SUP(lks, TP); 815 break; 816 default: 817 XGBE_SET_SUP(lks, FIBRE); 818 break; 819 } 820 821 XGBE_LM_COPY(lks, advertising, lks, supported); 822 } 823 824 static bool xgbe_phy_sfp_bit_rate(struct xgbe_sfp_eeprom *sfp_eeprom, 825 enum xgbe_sfp_speed sfp_speed) 826 { 827 u8 *sfp_base, min; 828 829 sfp_base = sfp_eeprom->base; 830 831 switch (sfp_speed) { 832 case XGBE_SFP_SPEED_1000: 833 min = XGBE_SFP_BASE_BR_1GBE_MIN; 834 break; 835 case XGBE_SFP_SPEED_10000: 836 min = XGBE_SFP_BASE_BR_10GBE_MIN; 837 break; 838 default: 839 return false; 840 } 841 842 return sfp_base[XGBE_SFP_BASE_BR] >= min; 843 } 844 845 static void xgbe_phy_free_phy_device(struct xgbe_prv_data *pdata) 846 { 847 struct xgbe_phy_data *phy_data = pdata->phy_data; 848 849 if (phy_data->phydev) { 850 phy_detach(phy_data->phydev); 851 phy_device_remove(phy_data->phydev); 852 phy_device_free(phy_data->phydev); 853 phy_data->phydev = NULL; 854 } 855 } 856 857 static bool xgbe_phy_finisar_phy_quirks(struct xgbe_prv_data *pdata) 858 { 859 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported) = { 0, }; 860 struct xgbe_phy_data *phy_data = pdata->phy_data; 861 unsigned int phy_id = phy_data->phydev->phy_id; 862 863 if (phy_data->port_mode != XGBE_PORT_MODE_SFP) 864 return false; 865 866 if ((phy_id & 0xfffffff0) != 0x01ff0cc0) 867 return false; 868 869 /* Enable Base-T AN */ 870 phy_write(phy_data->phydev, 0x16, 0x0001); 871 phy_write(phy_data->phydev, 0x00, 0x9140); 872 phy_write(phy_data->phydev, 0x16, 0x0000); 873 874 /* Enable SGMII at 100Base-T/1000Base-T Full Duplex */ 875 phy_write(phy_data->phydev, 0x1b, 0x9084); 876 phy_write(phy_data->phydev, 0x09, 0x0e00); 877 phy_write(phy_data->phydev, 0x00, 0x8140); 878 phy_write(phy_data->phydev, 0x04, 0x0d01); 879 phy_write(phy_data->phydev, 0x00, 0x9140); 880 881 linkmode_set_bit_array(phy_10_100_features_array, 882 ARRAY_SIZE(phy_10_100_features_array), 883 supported); 884 linkmode_set_bit_array(phy_gbit_features_array, 885 ARRAY_SIZE(phy_gbit_features_array), 886 supported); 887 888 linkmode_copy(phy_data->phydev->supported, supported); 889 890 phy_support_asym_pause(phy_data->phydev); 891 892 netif_dbg(pdata, drv, pdata->netdev, 893 "Finisar PHY quirk in place\n"); 894 895 return true; 896 } 897 898 static bool xgbe_phy_belfuse_phy_quirks(struct xgbe_prv_data *pdata) 899 { 900 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported) = { 0, }; 901 struct xgbe_phy_data *phy_data = pdata->phy_data; 902 struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom; 903 unsigned int phy_id = phy_data->phydev->phy_id; 904 int reg; 905 906 if (phy_data->port_mode != XGBE_PORT_MODE_SFP) 907 return false; 908 909 if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME], 910 XGBE_BEL_FUSE_VENDOR, XGBE_SFP_BASE_VENDOR_NAME_LEN)) 911 return false; 912 913 /* For Bel-Fuse, use the extra AN flag */ 914 pdata->an_again = 1; 915 916 if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN], 917 XGBE_BEL_FUSE_PARTNO, XGBE_SFP_BASE_VENDOR_PN_LEN)) 918 return false; 919 920 if ((phy_id & 0xfffffff0) != 0x03625d10) 921 return false; 922 923 /* Reset PHY - wait for self-clearing reset bit to clear */ 924 genphy_soft_reset(phy_data->phydev); 925 926 /* Disable RGMII mode */ 927 phy_write(phy_data->phydev, 0x18, 0x7007); 928 reg = phy_read(phy_data->phydev, 0x18); 929 phy_write(phy_data->phydev, 0x18, reg & ~0x0080); 930 931 /* Enable fiber register bank */ 932 phy_write(phy_data->phydev, 0x1c, 0x7c00); 933 reg = phy_read(phy_data->phydev, 0x1c); 934 reg &= 0x03ff; 935 reg &= ~0x0001; 936 phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg | 0x0001); 937 938 /* Power down SerDes */ 939 reg = phy_read(phy_data->phydev, 0x00); 940 phy_write(phy_data->phydev, 0x00, reg | 0x00800); 941 942 /* Configure SGMII-to-Copper mode */ 943 phy_write(phy_data->phydev, 0x1c, 0x7c00); 944 reg = phy_read(phy_data->phydev, 0x1c); 945 reg &= 0x03ff; 946 reg &= ~0x0006; 947 phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg | 0x0004); 948 949 /* Power up SerDes */ 950 reg = phy_read(phy_data->phydev, 0x00); 951 phy_write(phy_data->phydev, 0x00, reg & ~0x00800); 952 953 /* Enable copper register bank */ 954 phy_write(phy_data->phydev, 0x1c, 0x7c00); 955 reg = phy_read(phy_data->phydev, 0x1c); 956 reg &= 0x03ff; 957 reg &= ~0x0001; 958 phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg); 959 960 /* Power up SerDes */ 961 reg = phy_read(phy_data->phydev, 0x00); 962 phy_write(phy_data->phydev, 0x00, reg & ~0x00800); 963 964 linkmode_set_bit_array(phy_10_100_features_array, 965 ARRAY_SIZE(phy_10_100_features_array), 966 supported); 967 linkmode_set_bit_array(phy_gbit_features_array, 968 ARRAY_SIZE(phy_gbit_features_array), 969 supported); 970 linkmode_copy(phy_data->phydev->supported, supported); 971 phy_support_asym_pause(phy_data->phydev); 972 973 netif_dbg(pdata, drv, pdata->netdev, 974 "BelFuse PHY quirk in place\n"); 975 976 return true; 977 } 978 979 static void xgbe_phy_external_phy_quirks(struct xgbe_prv_data *pdata) 980 { 981 if (xgbe_phy_belfuse_phy_quirks(pdata)) 982 return; 983 984 if (xgbe_phy_finisar_phy_quirks(pdata)) 985 return; 986 } 987 988 static int xgbe_phy_find_phy_device(struct xgbe_prv_data *pdata) 989 { 990 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 991 struct xgbe_phy_data *phy_data = pdata->phy_data; 992 struct phy_device *phydev; 993 int ret; 994 995 /* If we already have a PHY, just return */ 996 if (phy_data->phydev) 997 return 0; 998 999 /* Clear the extra AN flag */ 1000 pdata->an_again = 0; 1001 1002 /* Check for the use of an external PHY */ 1003 if (phy_data->phydev_mode == XGBE_MDIO_MODE_NONE) 1004 return 0; 1005 1006 /* For SFP, only use an external PHY if available */ 1007 if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) && 1008 !phy_data->sfp_phy_avail) 1009 return 0; 1010 1011 /* Set the proper MDIO mode for the PHY */ 1012 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr, 1013 phy_data->phydev_mode); 1014 if (ret) { 1015 netdev_err(pdata->netdev, 1016 "mdio port/clause not compatible (%u/%u)\n", 1017 phy_data->mdio_addr, phy_data->phydev_mode); 1018 return ret; 1019 } 1020 1021 /* Create and connect to the PHY device */ 1022 phydev = get_phy_device(phy_data->mii, phy_data->mdio_addr, 1023 (phy_data->phydev_mode == XGBE_MDIO_MODE_CL45)); 1024 if (IS_ERR(phydev)) { 1025 netdev_err(pdata->netdev, "get_phy_device failed\n"); 1026 return -ENODEV; 1027 } 1028 netif_dbg(pdata, drv, pdata->netdev, "external PHY id is %#010x\n", 1029 phydev->phy_id); 1030 1031 /*TODO: If c45, add request_module based on one of the MMD ids? */ 1032 1033 ret = phy_device_register(phydev); 1034 if (ret) { 1035 netdev_err(pdata->netdev, "phy_device_register failed\n"); 1036 phy_device_free(phydev); 1037 return ret; 1038 } 1039 1040 ret = phy_attach_direct(pdata->netdev, phydev, phydev->dev_flags, 1041 PHY_INTERFACE_MODE_SGMII); 1042 if (ret) { 1043 netdev_err(pdata->netdev, "phy_attach_direct failed\n"); 1044 phy_device_remove(phydev); 1045 phy_device_free(phydev); 1046 return ret; 1047 } 1048 phy_data->phydev = phydev; 1049 1050 xgbe_phy_external_phy_quirks(pdata); 1051 1052 linkmode_and(phydev->advertising, phydev->advertising, 1053 lks->link_modes.advertising); 1054 1055 phy_start_aneg(phy_data->phydev); 1056 1057 return 0; 1058 } 1059 1060 static void xgbe_phy_sfp_external_phy(struct xgbe_prv_data *pdata) 1061 { 1062 struct xgbe_phy_data *phy_data = pdata->phy_data; 1063 int ret; 1064 1065 if (!phy_data->sfp_changed) 1066 return; 1067 1068 phy_data->sfp_phy_avail = 0; 1069 1070 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T) 1071 return; 1072 1073 /* Check access to the PHY by reading CTRL1 */ 1074 ret = xgbe_phy_i2c_mii_read(pdata, MII_BMCR); 1075 if (ret < 0) 1076 return; 1077 1078 /* Successfully accessed the PHY */ 1079 phy_data->sfp_phy_avail = 1; 1080 } 1081 1082 static bool xgbe_phy_check_sfp_rx_los(struct xgbe_phy_data *phy_data) 1083 { 1084 u8 *sfp_extd = phy_data->sfp_eeprom.extd; 1085 1086 if (!(sfp_extd[XGBE_SFP_EXTD_OPT1] & XGBE_SFP_EXTD_OPT1_RX_LOS)) 1087 return false; 1088 1089 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_RX_LOS) 1090 return false; 1091 1092 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_rx_los)) 1093 return true; 1094 1095 return false; 1096 } 1097 1098 static bool xgbe_phy_check_sfp_tx_fault(struct xgbe_phy_data *phy_data) 1099 { 1100 u8 *sfp_extd = phy_data->sfp_eeprom.extd; 1101 1102 if (!(sfp_extd[XGBE_SFP_EXTD_OPT1] & XGBE_SFP_EXTD_OPT1_TX_FAULT)) 1103 return false; 1104 1105 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_TX_FAULT) 1106 return false; 1107 1108 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_tx_fault)) 1109 return true; 1110 1111 return false; 1112 } 1113 1114 static bool xgbe_phy_check_sfp_mod_absent(struct xgbe_phy_data *phy_data) 1115 { 1116 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_MOD_ABSENT) 1117 return false; 1118 1119 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_mod_absent)) 1120 return true; 1121 1122 return false; 1123 } 1124 1125 static void xgbe_phy_sfp_parse_eeprom(struct xgbe_prv_data *pdata) 1126 { 1127 struct xgbe_phy_data *phy_data = pdata->phy_data; 1128 struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom; 1129 u8 *sfp_base; 1130 1131 sfp_base = sfp_eeprom->base; 1132 1133 if (sfp_base[XGBE_SFP_BASE_ID] != XGBE_SFP_ID_SFP) 1134 return; 1135 1136 if (sfp_base[XGBE_SFP_BASE_EXT_ID] != XGBE_SFP_EXT_ID_SFP) 1137 return; 1138 1139 /* Update transceiver signals (eeprom extd/options) */ 1140 phy_data->sfp_tx_fault = xgbe_phy_check_sfp_tx_fault(phy_data); 1141 phy_data->sfp_rx_los = xgbe_phy_check_sfp_rx_los(phy_data); 1142 1143 /* Assume FIBER cable unless told otherwise */ 1144 if (sfp_base[XGBE_SFP_BASE_CABLE] & XGBE_SFP_BASE_CABLE_PASSIVE) { 1145 phy_data->sfp_cable = XGBE_SFP_CABLE_PASSIVE; 1146 phy_data->sfp_cable_len = sfp_base[XGBE_SFP_BASE_CU_CABLE_LEN]; 1147 } else if (sfp_base[XGBE_SFP_BASE_CABLE] & XGBE_SFP_BASE_CABLE_ACTIVE) { 1148 phy_data->sfp_cable = XGBE_SFP_CABLE_ACTIVE; 1149 } else { 1150 phy_data->sfp_cable = XGBE_SFP_CABLE_FIBER; 1151 } 1152 1153 /* Determine the type of SFP */ 1154 if (phy_data->sfp_cable != XGBE_SFP_CABLE_FIBER && 1155 xgbe_phy_sfp_bit_rate(sfp_eeprom, XGBE_SFP_SPEED_10000)) 1156 phy_data->sfp_base = XGBE_SFP_BASE_10000_CR; 1157 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_SR) 1158 phy_data->sfp_base = XGBE_SFP_BASE_10000_SR; 1159 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LR) 1160 phy_data->sfp_base = XGBE_SFP_BASE_10000_LR; 1161 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LRM) 1162 phy_data->sfp_base = XGBE_SFP_BASE_10000_LRM; 1163 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_ER) 1164 phy_data->sfp_base = XGBE_SFP_BASE_10000_ER; 1165 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_SX) 1166 phy_data->sfp_base = XGBE_SFP_BASE_1000_SX; 1167 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_LX) 1168 phy_data->sfp_base = XGBE_SFP_BASE_1000_LX; 1169 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_CX) 1170 phy_data->sfp_base = XGBE_SFP_BASE_1000_CX; 1171 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_T) 1172 phy_data->sfp_base = XGBE_SFP_BASE_1000_T; 1173 1174 switch (phy_data->sfp_base) { 1175 case XGBE_SFP_BASE_1000_T: 1176 phy_data->sfp_speed = XGBE_SFP_SPEED_100_1000; 1177 break; 1178 case XGBE_SFP_BASE_1000_SX: 1179 case XGBE_SFP_BASE_1000_LX: 1180 case XGBE_SFP_BASE_1000_CX: 1181 phy_data->sfp_speed = XGBE_SFP_SPEED_1000; 1182 break; 1183 case XGBE_SFP_BASE_10000_SR: 1184 case XGBE_SFP_BASE_10000_LR: 1185 case XGBE_SFP_BASE_10000_LRM: 1186 case XGBE_SFP_BASE_10000_ER: 1187 case XGBE_SFP_BASE_10000_CR: 1188 phy_data->sfp_speed = XGBE_SFP_SPEED_10000; 1189 break; 1190 default: 1191 break; 1192 } 1193 } 1194 1195 static void xgbe_phy_sfp_eeprom_info(struct xgbe_prv_data *pdata, 1196 struct xgbe_sfp_eeprom *sfp_eeprom) 1197 { 1198 struct xgbe_sfp_ascii sfp_ascii; 1199 char *sfp_data = (char *)&sfp_ascii; 1200 1201 netif_dbg(pdata, drv, pdata->netdev, "SFP detected:\n"); 1202 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME], 1203 XGBE_SFP_BASE_VENDOR_NAME_LEN); 1204 sfp_data[XGBE_SFP_BASE_VENDOR_NAME_LEN] = '\0'; 1205 netif_dbg(pdata, drv, pdata->netdev, " vendor: %s\n", 1206 sfp_data); 1207 1208 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN], 1209 XGBE_SFP_BASE_VENDOR_PN_LEN); 1210 sfp_data[XGBE_SFP_BASE_VENDOR_PN_LEN] = '\0'; 1211 netif_dbg(pdata, drv, pdata->netdev, " part number: %s\n", 1212 sfp_data); 1213 1214 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_REV], 1215 XGBE_SFP_BASE_VENDOR_REV_LEN); 1216 sfp_data[XGBE_SFP_BASE_VENDOR_REV_LEN] = '\0'; 1217 netif_dbg(pdata, drv, pdata->netdev, " revision level: %s\n", 1218 sfp_data); 1219 1220 memcpy(sfp_data, &sfp_eeprom->extd[XGBE_SFP_BASE_VENDOR_SN], 1221 XGBE_SFP_BASE_VENDOR_SN_LEN); 1222 sfp_data[XGBE_SFP_BASE_VENDOR_SN_LEN] = '\0'; 1223 netif_dbg(pdata, drv, pdata->netdev, " serial number: %s\n", 1224 sfp_data); 1225 } 1226 1227 static bool xgbe_phy_sfp_verify_eeprom(u8 cc_in, u8 *buf, unsigned int len) 1228 { 1229 u8 cc; 1230 1231 for (cc = 0; len; buf++, len--) 1232 cc += *buf; 1233 1234 return cc == cc_in; 1235 } 1236 1237 static int xgbe_phy_sfp_read_eeprom(struct xgbe_prv_data *pdata) 1238 { 1239 struct xgbe_phy_data *phy_data = pdata->phy_data; 1240 struct xgbe_sfp_eeprom sfp_eeprom; 1241 u8 eeprom_addr; 1242 int ret; 1243 1244 ret = xgbe_phy_sfp_get_mux(pdata); 1245 if (ret) { 1246 dev_err_once(pdata->dev, "%s: I2C error setting SFP MUX\n", 1247 netdev_name(pdata->netdev)); 1248 return ret; 1249 } 1250 1251 /* Read the SFP serial ID eeprom */ 1252 eeprom_addr = 0; 1253 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_SERIAL_ID_ADDRESS, 1254 &eeprom_addr, sizeof(eeprom_addr), 1255 &sfp_eeprom, sizeof(sfp_eeprom)); 1256 if (ret) { 1257 dev_err_once(pdata->dev, "%s: I2C error reading SFP EEPROM\n", 1258 netdev_name(pdata->netdev)); 1259 goto put; 1260 } 1261 1262 /* Validate the contents read */ 1263 if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.base[XGBE_SFP_BASE_CC], 1264 sfp_eeprom.base, 1265 sizeof(sfp_eeprom.base) - 1)) { 1266 ret = -EINVAL; 1267 goto put; 1268 } 1269 1270 if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.extd[XGBE_SFP_EXTD_CC], 1271 sfp_eeprom.extd, 1272 sizeof(sfp_eeprom.extd) - 1)) { 1273 ret = -EINVAL; 1274 goto put; 1275 } 1276 1277 /* Check for an added or changed SFP */ 1278 if (memcmp(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom))) { 1279 phy_data->sfp_changed = 1; 1280 1281 if (netif_msg_drv(pdata)) 1282 xgbe_phy_sfp_eeprom_info(pdata, &sfp_eeprom); 1283 1284 memcpy(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom)); 1285 1286 xgbe_phy_free_phy_device(pdata); 1287 } else { 1288 phy_data->sfp_changed = 0; 1289 } 1290 1291 put: 1292 xgbe_phy_sfp_put_mux(pdata); 1293 1294 return ret; 1295 } 1296 1297 static void xgbe_phy_sfp_signals(struct xgbe_prv_data *pdata) 1298 { 1299 struct xgbe_phy_data *phy_data = pdata->phy_data; 1300 u8 gpio_reg, gpio_ports[2]; 1301 int ret; 1302 1303 /* Read the input port registers */ 1304 gpio_reg = 0; 1305 ret = xgbe_phy_i2c_read(pdata, phy_data->sfp_gpio_address, 1306 &gpio_reg, sizeof(gpio_reg), 1307 gpio_ports, sizeof(gpio_ports)); 1308 if (ret) { 1309 dev_err_once(pdata->dev, "%s: I2C error reading SFP GPIOs\n", 1310 netdev_name(pdata->netdev)); 1311 return; 1312 } 1313 1314 phy_data->sfp_gpio_inputs = (gpio_ports[1] << 8) | gpio_ports[0]; 1315 1316 phy_data->sfp_mod_absent = xgbe_phy_check_sfp_mod_absent(phy_data); 1317 } 1318 1319 static void xgbe_phy_sfp_mod_absent(struct xgbe_prv_data *pdata) 1320 { 1321 struct xgbe_phy_data *phy_data = pdata->phy_data; 1322 1323 xgbe_phy_free_phy_device(pdata); 1324 1325 phy_data->sfp_mod_absent = 1; 1326 phy_data->sfp_phy_avail = 0; 1327 memset(&phy_data->sfp_eeprom, 0, sizeof(phy_data->sfp_eeprom)); 1328 } 1329 1330 static void xgbe_phy_sfp_reset(struct xgbe_phy_data *phy_data) 1331 { 1332 phy_data->sfp_rx_los = 0; 1333 phy_data->sfp_tx_fault = 0; 1334 phy_data->sfp_mod_absent = 1; 1335 phy_data->sfp_base = XGBE_SFP_BASE_UNKNOWN; 1336 phy_data->sfp_cable = XGBE_SFP_CABLE_UNKNOWN; 1337 phy_data->sfp_speed = XGBE_SFP_SPEED_UNKNOWN; 1338 } 1339 1340 static void xgbe_phy_sfp_detect(struct xgbe_prv_data *pdata) 1341 { 1342 struct xgbe_phy_data *phy_data = pdata->phy_data; 1343 int ret; 1344 1345 /* Reset the SFP signals and info */ 1346 xgbe_phy_sfp_reset(phy_data); 1347 1348 ret = xgbe_phy_get_comm_ownership(pdata); 1349 if (ret) 1350 return; 1351 1352 /* Read the SFP signals and check for module presence */ 1353 xgbe_phy_sfp_signals(pdata); 1354 if (phy_data->sfp_mod_absent) { 1355 xgbe_phy_sfp_mod_absent(pdata); 1356 goto put; 1357 } 1358 1359 ret = xgbe_phy_sfp_read_eeprom(pdata); 1360 if (ret) { 1361 /* Treat any error as if there isn't an SFP plugged in */ 1362 xgbe_phy_sfp_reset(phy_data); 1363 xgbe_phy_sfp_mod_absent(pdata); 1364 goto put; 1365 } 1366 1367 xgbe_phy_sfp_parse_eeprom(pdata); 1368 1369 xgbe_phy_sfp_external_phy(pdata); 1370 1371 put: 1372 xgbe_phy_sfp_phy_settings(pdata); 1373 1374 xgbe_phy_put_comm_ownership(pdata); 1375 } 1376 1377 static int xgbe_phy_module_eeprom(struct xgbe_prv_data *pdata, 1378 struct ethtool_eeprom *eeprom, u8 *data) 1379 { 1380 struct xgbe_phy_data *phy_data = pdata->phy_data; 1381 u8 eeprom_addr, eeprom_data[XGBE_SFP_EEPROM_MAX]; 1382 struct xgbe_sfp_eeprom *sfp_eeprom; 1383 unsigned int i, j, rem; 1384 int ret; 1385 1386 rem = eeprom->len; 1387 1388 if (!eeprom->len) { 1389 ret = -EINVAL; 1390 goto done; 1391 } 1392 1393 if ((eeprom->offset + eeprom->len) > XGBE_SFP_EEPROM_MAX) { 1394 ret = -EINVAL; 1395 goto done; 1396 } 1397 1398 if (phy_data->port_mode != XGBE_PORT_MODE_SFP) { 1399 ret = -ENXIO; 1400 goto done; 1401 } 1402 1403 if (!netif_running(pdata->netdev)) { 1404 ret = -EIO; 1405 goto done; 1406 } 1407 1408 if (phy_data->sfp_mod_absent) { 1409 ret = -EIO; 1410 goto done; 1411 } 1412 1413 ret = xgbe_phy_get_comm_ownership(pdata); 1414 if (ret) { 1415 ret = -EIO; 1416 goto done; 1417 } 1418 1419 ret = xgbe_phy_sfp_get_mux(pdata); 1420 if (ret) { 1421 netdev_err(pdata->netdev, "I2C error setting SFP MUX\n"); 1422 ret = -EIO; 1423 goto put_own; 1424 } 1425 1426 /* Read the SFP serial ID eeprom */ 1427 eeprom_addr = 0; 1428 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_SERIAL_ID_ADDRESS, 1429 &eeprom_addr, sizeof(eeprom_addr), 1430 eeprom_data, XGBE_SFP_EEPROM_BASE_LEN); 1431 if (ret) { 1432 netdev_err(pdata->netdev, 1433 "I2C error reading SFP EEPROM\n"); 1434 ret = -EIO; 1435 goto put_mux; 1436 } 1437 1438 sfp_eeprom = (struct xgbe_sfp_eeprom *)eeprom_data; 1439 1440 if (XGBE_SFP_DIAGS_SUPPORTED(sfp_eeprom)) { 1441 /* Read the SFP diagnostic eeprom */ 1442 eeprom_addr = 0; 1443 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_DIAG_INFO_ADDRESS, 1444 &eeprom_addr, sizeof(eeprom_addr), 1445 eeprom_data + XGBE_SFP_EEPROM_BASE_LEN, 1446 XGBE_SFP_EEPROM_DIAG_LEN); 1447 if (ret) { 1448 netdev_err(pdata->netdev, 1449 "I2C error reading SFP DIAGS\n"); 1450 ret = -EIO; 1451 goto put_mux; 1452 } 1453 } 1454 1455 for (i = 0, j = eeprom->offset; i < eeprom->len; i++, j++) { 1456 if ((j >= XGBE_SFP_EEPROM_BASE_LEN) && 1457 !XGBE_SFP_DIAGS_SUPPORTED(sfp_eeprom)) 1458 break; 1459 1460 data[i] = eeprom_data[j]; 1461 rem--; 1462 } 1463 1464 put_mux: 1465 xgbe_phy_sfp_put_mux(pdata); 1466 1467 put_own: 1468 xgbe_phy_put_comm_ownership(pdata); 1469 1470 done: 1471 eeprom->len -= rem; 1472 1473 return ret; 1474 } 1475 1476 static int xgbe_phy_module_info(struct xgbe_prv_data *pdata, 1477 struct ethtool_modinfo *modinfo) 1478 { 1479 struct xgbe_phy_data *phy_data = pdata->phy_data; 1480 1481 if (phy_data->port_mode != XGBE_PORT_MODE_SFP) 1482 return -ENXIO; 1483 1484 if (!netif_running(pdata->netdev)) 1485 return -EIO; 1486 1487 if (phy_data->sfp_mod_absent) 1488 return -EIO; 1489 1490 if (XGBE_SFP_DIAGS_SUPPORTED(&phy_data->sfp_eeprom)) { 1491 modinfo->type = ETH_MODULE_SFF_8472; 1492 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 1493 } else { 1494 modinfo->type = ETH_MODULE_SFF_8079; 1495 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN; 1496 } 1497 1498 return 0; 1499 } 1500 1501 static void xgbe_phy_phydev_flowctrl(struct xgbe_prv_data *pdata) 1502 { 1503 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 1504 struct xgbe_phy_data *phy_data = pdata->phy_data; 1505 u16 lcl_adv = 0, rmt_adv = 0; 1506 u8 fc; 1507 1508 pdata->phy.tx_pause = 0; 1509 pdata->phy.rx_pause = 0; 1510 1511 if (!phy_data->phydev) 1512 return; 1513 1514 lcl_adv = linkmode_adv_to_lcl_adv_t(phy_data->phydev->advertising); 1515 1516 if (phy_data->phydev->pause) { 1517 XGBE_SET_LP_ADV(lks, Pause); 1518 rmt_adv |= LPA_PAUSE_CAP; 1519 } 1520 if (phy_data->phydev->asym_pause) { 1521 XGBE_SET_LP_ADV(lks, Asym_Pause); 1522 rmt_adv |= LPA_PAUSE_ASYM; 1523 } 1524 1525 fc = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv); 1526 if (fc & FLOW_CTRL_TX) 1527 pdata->phy.tx_pause = 1; 1528 if (fc & FLOW_CTRL_RX) 1529 pdata->phy.rx_pause = 1; 1530 } 1531 1532 static enum xgbe_mode xgbe_phy_an37_sgmii_outcome(struct xgbe_prv_data *pdata) 1533 { 1534 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 1535 enum xgbe_mode mode; 1536 1537 XGBE_SET_LP_ADV(lks, Autoneg); 1538 XGBE_SET_LP_ADV(lks, TP); 1539 1540 /* Use external PHY to determine flow control */ 1541 if (pdata->phy.pause_autoneg) 1542 xgbe_phy_phydev_flowctrl(pdata); 1543 1544 switch (pdata->an_status & XGBE_SGMII_AN_LINK_SPEED) { 1545 case XGBE_SGMII_AN_LINK_SPEED_100: 1546 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) { 1547 XGBE_SET_LP_ADV(lks, 100baseT_Full); 1548 mode = XGBE_MODE_SGMII_100; 1549 } else { 1550 /* Half-duplex not supported */ 1551 XGBE_SET_LP_ADV(lks, 100baseT_Half); 1552 mode = XGBE_MODE_UNKNOWN; 1553 } 1554 break; 1555 case XGBE_SGMII_AN_LINK_SPEED_1000: 1556 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) { 1557 XGBE_SET_LP_ADV(lks, 1000baseT_Full); 1558 mode = XGBE_MODE_SGMII_1000; 1559 } else { 1560 /* Half-duplex not supported */ 1561 XGBE_SET_LP_ADV(lks, 1000baseT_Half); 1562 mode = XGBE_MODE_UNKNOWN; 1563 } 1564 break; 1565 default: 1566 mode = XGBE_MODE_UNKNOWN; 1567 } 1568 1569 return mode; 1570 } 1571 1572 static enum xgbe_mode xgbe_phy_an37_outcome(struct xgbe_prv_data *pdata) 1573 { 1574 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 1575 enum xgbe_mode mode; 1576 unsigned int ad_reg, lp_reg; 1577 1578 XGBE_SET_LP_ADV(lks, Autoneg); 1579 XGBE_SET_LP_ADV(lks, FIBRE); 1580 1581 /* Compare Advertisement and Link Partner register */ 1582 ad_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE); 1583 lp_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_LP_ABILITY); 1584 if (lp_reg & 0x100) 1585 XGBE_SET_LP_ADV(lks, Pause); 1586 if (lp_reg & 0x80) 1587 XGBE_SET_LP_ADV(lks, Asym_Pause); 1588 1589 if (pdata->phy.pause_autoneg) { 1590 /* Set flow control based on auto-negotiation result */ 1591 pdata->phy.tx_pause = 0; 1592 pdata->phy.rx_pause = 0; 1593 1594 if (ad_reg & lp_reg & 0x100) { 1595 pdata->phy.tx_pause = 1; 1596 pdata->phy.rx_pause = 1; 1597 } else if (ad_reg & lp_reg & 0x80) { 1598 if (ad_reg & 0x100) 1599 pdata->phy.rx_pause = 1; 1600 else if (lp_reg & 0x100) 1601 pdata->phy.tx_pause = 1; 1602 } 1603 } 1604 1605 if (lp_reg & 0x20) 1606 XGBE_SET_LP_ADV(lks, 1000baseX_Full); 1607 1608 /* Half duplex is not supported */ 1609 ad_reg &= lp_reg; 1610 mode = (ad_reg & 0x20) ? XGBE_MODE_X : XGBE_MODE_UNKNOWN; 1611 1612 return mode; 1613 } 1614 1615 static enum xgbe_mode xgbe_phy_an73_redrv_outcome(struct xgbe_prv_data *pdata) 1616 { 1617 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 1618 struct xgbe_phy_data *phy_data = pdata->phy_data; 1619 enum xgbe_mode mode; 1620 unsigned int ad_reg, lp_reg; 1621 1622 XGBE_SET_LP_ADV(lks, Autoneg); 1623 XGBE_SET_LP_ADV(lks, Backplane); 1624 1625 /* Use external PHY to determine flow control */ 1626 if (pdata->phy.pause_autoneg) 1627 xgbe_phy_phydev_flowctrl(pdata); 1628 1629 /* Compare Advertisement and Link Partner register 2 */ 1630 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); 1631 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); 1632 if (lp_reg & 0x80) 1633 XGBE_SET_LP_ADV(lks, 10000baseKR_Full); 1634 if (lp_reg & 0x20) 1635 XGBE_SET_LP_ADV(lks, 1000baseKX_Full); 1636 1637 ad_reg &= lp_reg; 1638 if (ad_reg & 0x80) { 1639 switch (phy_data->port_mode) { 1640 case XGBE_PORT_MODE_BACKPLANE: 1641 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 1642 mode = XGBE_MODE_KR; 1643 break; 1644 default: 1645 mode = XGBE_MODE_SFI; 1646 break; 1647 } 1648 } else if (ad_reg & 0x20) { 1649 switch (phy_data->port_mode) { 1650 case XGBE_PORT_MODE_BACKPLANE: 1651 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 1652 mode = XGBE_MODE_KX_1000; 1653 break; 1654 case XGBE_PORT_MODE_1000BASE_X: 1655 mode = XGBE_MODE_X; 1656 break; 1657 case XGBE_PORT_MODE_SFP: 1658 switch (phy_data->sfp_base) { 1659 case XGBE_SFP_BASE_1000_T: 1660 if (phy_data->phydev && 1661 (phy_data->phydev->speed == SPEED_100)) 1662 mode = XGBE_MODE_SGMII_100; 1663 else 1664 mode = XGBE_MODE_SGMII_1000; 1665 break; 1666 case XGBE_SFP_BASE_1000_SX: 1667 case XGBE_SFP_BASE_1000_LX: 1668 case XGBE_SFP_BASE_1000_CX: 1669 default: 1670 mode = XGBE_MODE_X; 1671 break; 1672 } 1673 break; 1674 default: 1675 if (phy_data->phydev && 1676 (phy_data->phydev->speed == SPEED_100)) 1677 mode = XGBE_MODE_SGMII_100; 1678 else 1679 mode = XGBE_MODE_SGMII_1000; 1680 break; 1681 } 1682 } else { 1683 mode = XGBE_MODE_UNKNOWN; 1684 } 1685 1686 /* Compare Advertisement and Link Partner register 3 */ 1687 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); 1688 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); 1689 if (lp_reg & 0xc000) 1690 XGBE_SET_LP_ADV(lks, 10000baseR_FEC); 1691 1692 return mode; 1693 } 1694 1695 static enum xgbe_mode xgbe_phy_an73_outcome(struct xgbe_prv_data *pdata) 1696 { 1697 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 1698 enum xgbe_mode mode; 1699 unsigned int ad_reg, lp_reg; 1700 1701 XGBE_SET_LP_ADV(lks, Autoneg); 1702 XGBE_SET_LP_ADV(lks, Backplane); 1703 1704 /* Compare Advertisement and Link Partner register 1 */ 1705 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE); 1706 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA); 1707 if (lp_reg & 0x400) 1708 XGBE_SET_LP_ADV(lks, Pause); 1709 if (lp_reg & 0x800) 1710 XGBE_SET_LP_ADV(lks, Asym_Pause); 1711 1712 if (pdata->phy.pause_autoneg) { 1713 /* Set flow control based on auto-negotiation result */ 1714 pdata->phy.tx_pause = 0; 1715 pdata->phy.rx_pause = 0; 1716 1717 if (ad_reg & lp_reg & 0x400) { 1718 pdata->phy.tx_pause = 1; 1719 pdata->phy.rx_pause = 1; 1720 } else if (ad_reg & lp_reg & 0x800) { 1721 if (ad_reg & 0x400) 1722 pdata->phy.rx_pause = 1; 1723 else if (lp_reg & 0x400) 1724 pdata->phy.tx_pause = 1; 1725 } 1726 } 1727 1728 /* Compare Advertisement and Link Partner register 2 */ 1729 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); 1730 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); 1731 if (lp_reg & 0x80) 1732 XGBE_SET_LP_ADV(lks, 10000baseKR_Full); 1733 if (lp_reg & 0x20) 1734 XGBE_SET_LP_ADV(lks, 1000baseKX_Full); 1735 1736 ad_reg &= lp_reg; 1737 if (ad_reg & 0x80) 1738 mode = XGBE_MODE_KR; 1739 else if (ad_reg & 0x20) 1740 mode = XGBE_MODE_KX_1000; 1741 else 1742 mode = XGBE_MODE_UNKNOWN; 1743 1744 /* Compare Advertisement and Link Partner register 3 */ 1745 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); 1746 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); 1747 if (lp_reg & 0xc000) 1748 XGBE_SET_LP_ADV(lks, 10000baseR_FEC); 1749 1750 return mode; 1751 } 1752 1753 static enum xgbe_mode xgbe_phy_an_outcome(struct xgbe_prv_data *pdata) 1754 { 1755 switch (pdata->an_mode) { 1756 case XGBE_AN_MODE_CL73: 1757 return xgbe_phy_an73_outcome(pdata); 1758 case XGBE_AN_MODE_CL73_REDRV: 1759 return xgbe_phy_an73_redrv_outcome(pdata); 1760 case XGBE_AN_MODE_CL37: 1761 return xgbe_phy_an37_outcome(pdata); 1762 case XGBE_AN_MODE_CL37_SGMII: 1763 return xgbe_phy_an37_sgmii_outcome(pdata); 1764 default: 1765 return XGBE_MODE_UNKNOWN; 1766 } 1767 } 1768 1769 static void xgbe_phy_an_advertising(struct xgbe_prv_data *pdata, 1770 struct ethtool_link_ksettings *dlks) 1771 { 1772 struct ethtool_link_ksettings *slks = &pdata->phy.lks; 1773 struct xgbe_phy_data *phy_data = pdata->phy_data; 1774 1775 XGBE_LM_COPY(dlks, advertising, slks, advertising); 1776 1777 /* Without a re-driver, just return current advertising */ 1778 if (!phy_data->redrv) 1779 return; 1780 1781 /* With the KR re-driver we need to advertise a single speed */ 1782 XGBE_CLR_ADV(dlks, 1000baseKX_Full); 1783 XGBE_CLR_ADV(dlks, 10000baseKR_Full); 1784 1785 /* Advertise FEC support is present */ 1786 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 1787 XGBE_SET_ADV(dlks, 10000baseR_FEC); 1788 1789 switch (phy_data->port_mode) { 1790 case XGBE_PORT_MODE_BACKPLANE: 1791 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 1792 XGBE_SET_ADV(dlks, 10000baseKR_Full); 1793 break; 1794 case XGBE_PORT_MODE_BACKPLANE_2500: 1795 XGBE_SET_ADV(dlks, 1000baseKX_Full); 1796 break; 1797 case XGBE_PORT_MODE_1000BASE_T: 1798 case XGBE_PORT_MODE_1000BASE_X: 1799 case XGBE_PORT_MODE_NBASE_T: 1800 XGBE_SET_ADV(dlks, 1000baseKX_Full); 1801 break; 1802 case XGBE_PORT_MODE_10GBASE_T: 1803 if (phy_data->phydev && 1804 (phy_data->phydev->speed == SPEED_10000)) 1805 XGBE_SET_ADV(dlks, 10000baseKR_Full); 1806 else 1807 XGBE_SET_ADV(dlks, 1000baseKX_Full); 1808 break; 1809 case XGBE_PORT_MODE_10GBASE_R: 1810 XGBE_SET_ADV(dlks, 10000baseKR_Full); 1811 break; 1812 case XGBE_PORT_MODE_SFP: 1813 switch (phy_data->sfp_base) { 1814 case XGBE_SFP_BASE_1000_T: 1815 case XGBE_SFP_BASE_1000_SX: 1816 case XGBE_SFP_BASE_1000_LX: 1817 case XGBE_SFP_BASE_1000_CX: 1818 XGBE_SET_ADV(dlks, 1000baseKX_Full); 1819 break; 1820 default: 1821 XGBE_SET_ADV(dlks, 10000baseKR_Full); 1822 break; 1823 } 1824 break; 1825 default: 1826 XGBE_SET_ADV(dlks, 10000baseKR_Full); 1827 break; 1828 } 1829 } 1830 1831 static int xgbe_phy_an_config(struct xgbe_prv_data *pdata) 1832 { 1833 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 1834 struct xgbe_phy_data *phy_data = pdata->phy_data; 1835 int ret; 1836 1837 ret = xgbe_phy_find_phy_device(pdata); 1838 if (ret) 1839 return ret; 1840 1841 if (!phy_data->phydev) 1842 return 0; 1843 1844 phy_data->phydev->autoneg = pdata->phy.autoneg; 1845 linkmode_and(phy_data->phydev->advertising, 1846 phy_data->phydev->supported, 1847 lks->link_modes.advertising); 1848 1849 if (pdata->phy.autoneg != AUTONEG_ENABLE) { 1850 phy_data->phydev->speed = pdata->phy.speed; 1851 phy_data->phydev->duplex = pdata->phy.duplex; 1852 } 1853 1854 ret = phy_start_aneg(phy_data->phydev); 1855 1856 return ret; 1857 } 1858 1859 static enum xgbe_an_mode xgbe_phy_an_sfp_mode(struct xgbe_phy_data *phy_data) 1860 { 1861 switch (phy_data->sfp_base) { 1862 case XGBE_SFP_BASE_1000_T: 1863 return XGBE_AN_MODE_CL37_SGMII; 1864 case XGBE_SFP_BASE_1000_SX: 1865 case XGBE_SFP_BASE_1000_LX: 1866 case XGBE_SFP_BASE_1000_CX: 1867 return XGBE_AN_MODE_CL37; 1868 default: 1869 return XGBE_AN_MODE_NONE; 1870 } 1871 } 1872 1873 static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata) 1874 { 1875 struct xgbe_phy_data *phy_data = pdata->phy_data; 1876 1877 /* A KR re-driver will always require CL73 AN */ 1878 if (phy_data->redrv) 1879 return XGBE_AN_MODE_CL73_REDRV; 1880 1881 switch (phy_data->port_mode) { 1882 case XGBE_PORT_MODE_BACKPLANE: 1883 return XGBE_AN_MODE_CL73; 1884 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 1885 case XGBE_PORT_MODE_BACKPLANE_2500: 1886 return XGBE_AN_MODE_NONE; 1887 case XGBE_PORT_MODE_1000BASE_T: 1888 return XGBE_AN_MODE_CL37_SGMII; 1889 case XGBE_PORT_MODE_1000BASE_X: 1890 return XGBE_AN_MODE_CL37; 1891 case XGBE_PORT_MODE_NBASE_T: 1892 return XGBE_AN_MODE_CL37_SGMII; 1893 case XGBE_PORT_MODE_10GBASE_T: 1894 return XGBE_AN_MODE_CL73; 1895 case XGBE_PORT_MODE_10GBASE_R: 1896 return XGBE_AN_MODE_NONE; 1897 case XGBE_PORT_MODE_SFP: 1898 return xgbe_phy_an_sfp_mode(phy_data); 1899 default: 1900 return XGBE_AN_MODE_NONE; 1901 } 1902 } 1903 1904 static int xgbe_phy_set_redrv_mode_mdio(struct xgbe_prv_data *pdata, 1905 enum xgbe_phy_redrv_mode mode) 1906 { 1907 struct xgbe_phy_data *phy_data = pdata->phy_data; 1908 u16 redrv_reg, redrv_val; 1909 1910 redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000); 1911 redrv_val = (u16)mode; 1912 1913 return pdata->hw_if.write_ext_mii_regs(pdata, phy_data->redrv_addr, 1914 redrv_reg, redrv_val); 1915 } 1916 1917 static int xgbe_phy_set_redrv_mode_i2c(struct xgbe_prv_data *pdata, 1918 enum xgbe_phy_redrv_mode mode) 1919 { 1920 struct xgbe_phy_data *phy_data = pdata->phy_data; 1921 unsigned int redrv_reg; 1922 int ret; 1923 1924 /* Calculate the register to write */ 1925 redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000); 1926 1927 ret = xgbe_phy_redrv_write(pdata, redrv_reg, mode); 1928 1929 return ret; 1930 } 1931 1932 static void xgbe_phy_set_redrv_mode(struct xgbe_prv_data *pdata) 1933 { 1934 struct xgbe_phy_data *phy_data = pdata->phy_data; 1935 enum xgbe_phy_redrv_mode mode; 1936 int ret; 1937 1938 if (!phy_data->redrv) 1939 return; 1940 1941 mode = XGBE_PHY_REDRV_MODE_CX; 1942 if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) && 1943 (phy_data->sfp_base != XGBE_SFP_BASE_1000_CX) && 1944 (phy_data->sfp_base != XGBE_SFP_BASE_10000_CR)) 1945 mode = XGBE_PHY_REDRV_MODE_SR; 1946 1947 ret = xgbe_phy_get_comm_ownership(pdata); 1948 if (ret) 1949 return; 1950 1951 if (phy_data->redrv_if) 1952 xgbe_phy_set_redrv_mode_i2c(pdata, mode); 1953 else 1954 xgbe_phy_set_redrv_mode_mdio(pdata, mode); 1955 1956 xgbe_phy_put_comm_ownership(pdata); 1957 } 1958 1959 static void xgbe_phy_rx_reset(struct xgbe_prv_data *pdata) 1960 { 1961 int reg; 1962 1963 reg = XMDIO_READ_BITS(pdata, MDIO_MMD_PCS, MDIO_PCS_DIGITAL_STAT, 1964 XGBE_PCS_PSEQ_STATE_MASK); 1965 if (reg == XGBE_PCS_PSEQ_STATE_POWER_GOOD) { 1966 /* Mailbox command timed out, reset of RX block is required. 1967 * This can be done by asseting the reset bit and wait for 1968 * its compeletion. 1969 */ 1970 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_CTRL1, 1971 XGBE_PMA_RX_RST_0_MASK, XGBE_PMA_RX_RST_0_RESET_ON); 1972 ndelay(20); 1973 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_CTRL1, 1974 XGBE_PMA_RX_RST_0_MASK, XGBE_PMA_RX_RST_0_RESET_OFF); 1975 usleep_range(40, 50); 1976 netif_err(pdata, link, pdata->netdev, "firmware mailbox reset performed\n"); 1977 } 1978 } 1979 1980 static void xgbe_phy_pll_ctrl(struct xgbe_prv_data *pdata, bool enable) 1981 { 1982 /* PLL_CTRL feature needs to be enabled for fixed PHY modes (Non-Autoneg) only */ 1983 if (pdata->phy.autoneg != AUTONEG_DISABLE) 1984 return; 1985 1986 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_MISC_CTRL0, 1987 XGBE_PMA_PLL_CTRL_MASK, 1988 enable ? XGBE_PMA_PLL_CTRL_ENABLE 1989 : XGBE_PMA_PLL_CTRL_DISABLE); 1990 1991 /* Wait for command to complete */ 1992 usleep_range(100, 200); 1993 } 1994 1995 static void xgbe_phy_perform_ratechange(struct xgbe_prv_data *pdata, 1996 enum xgbe_mb_cmd cmd, enum xgbe_mb_subcmd sub_cmd) 1997 { 1998 unsigned int s0 = 0; 1999 unsigned int wait; 2000 2001 /* Disable PLL re-initialization during FW command processing */ 2002 xgbe_phy_pll_ctrl(pdata, false); 2003 2004 /* Log if a previous command did not complete */ 2005 if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) { 2006 netif_dbg(pdata, link, pdata->netdev, 2007 "firmware mailbox not ready for command\n"); 2008 xgbe_phy_rx_reset(pdata); 2009 } 2010 2011 /* Construct the command */ 2012 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, cmd); 2013 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, sub_cmd); 2014 2015 /* Issue the command */ 2016 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0); 2017 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0); 2018 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1); 2019 2020 /* Wait for command to complete */ 2021 wait = XGBE_RATECHANGE_COUNT; 2022 while (wait--) { 2023 if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) 2024 goto reenable_pll; 2025 2026 usleep_range(1000, 2000); 2027 } 2028 2029 netif_dbg(pdata, link, pdata->netdev, 2030 "firmware mailbox command did not complete\n"); 2031 2032 /* Reset on error */ 2033 xgbe_phy_rx_reset(pdata); 2034 2035 reenable_pll: 2036 /* Enable PLL re-initialization, not needed for PHY Power Off and RRC cmds */ 2037 if (cmd != XGBE_MB_CMD_POWER_OFF && 2038 cmd != XGBE_MB_CMD_RRC) 2039 xgbe_phy_pll_ctrl(pdata, true); 2040 } 2041 2042 static void xgbe_phy_rrc(struct xgbe_prv_data *pdata) 2043 { 2044 /* Receiver Reset Cycle */ 2045 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_RRC, XGBE_MB_SUBCMD_NONE); 2046 2047 netif_dbg(pdata, link, pdata->netdev, "receiver reset complete\n"); 2048 } 2049 2050 static void xgbe_phy_power_off(struct xgbe_prv_data *pdata) 2051 { 2052 struct xgbe_phy_data *phy_data = pdata->phy_data; 2053 2054 /* Power off */ 2055 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_POWER_OFF, XGBE_MB_SUBCMD_NONE); 2056 2057 phy_data->cur_mode = XGBE_MODE_UNKNOWN; 2058 2059 netif_dbg(pdata, link, pdata->netdev, "phy powered off\n"); 2060 } 2061 2062 static void xgbe_phy_sfi_mode(struct xgbe_prv_data *pdata) 2063 { 2064 struct xgbe_phy_data *phy_data = pdata->phy_data; 2065 2066 xgbe_phy_set_redrv_mode(pdata); 2067 2068 /* 10G/SFI */ 2069 if (phy_data->sfp_cable != XGBE_SFP_CABLE_PASSIVE) { 2070 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_10G_SFI, XGBE_MB_SUBCMD_ACTIVE); 2071 } else { 2072 if (phy_data->sfp_cable_len <= 1) 2073 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_10G_SFI, 2074 XGBE_MB_SUBCMD_PASSIVE_1M); 2075 else if (phy_data->sfp_cable_len <= 3) 2076 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_10G_SFI, 2077 XGBE_MB_SUBCMD_PASSIVE_3M); 2078 else 2079 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_10G_SFI, 2080 XGBE_MB_SUBCMD_PASSIVE_OTHER); 2081 } 2082 2083 phy_data->cur_mode = XGBE_MODE_SFI; 2084 2085 netif_dbg(pdata, link, pdata->netdev, "10GbE SFI mode set\n"); 2086 } 2087 2088 static void xgbe_phy_x_mode(struct xgbe_prv_data *pdata) 2089 { 2090 struct xgbe_phy_data *phy_data = pdata->phy_data; 2091 2092 xgbe_phy_set_redrv_mode(pdata); 2093 2094 /* 1G/X */ 2095 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_1G, XGBE_MB_SUBCMD_1G_KX); 2096 2097 phy_data->cur_mode = XGBE_MODE_X; 2098 2099 netif_dbg(pdata, link, pdata->netdev, "1GbE X mode set\n"); 2100 } 2101 2102 static void xgbe_phy_sgmii_1000_mode(struct xgbe_prv_data *pdata) 2103 { 2104 struct xgbe_phy_data *phy_data = pdata->phy_data; 2105 2106 xgbe_phy_set_redrv_mode(pdata); 2107 2108 /* 1G/SGMII */ 2109 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_1G, XGBE_MB_SUBCMD_1G_SGMII); 2110 2111 phy_data->cur_mode = XGBE_MODE_SGMII_1000; 2112 2113 netif_dbg(pdata, link, pdata->netdev, "1GbE SGMII mode set\n"); 2114 } 2115 2116 static void xgbe_phy_sgmii_100_mode(struct xgbe_prv_data *pdata) 2117 { 2118 struct xgbe_phy_data *phy_data = pdata->phy_data; 2119 2120 xgbe_phy_set_redrv_mode(pdata); 2121 2122 /* 100M/SGMII */ 2123 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_1G, XGBE_MB_SUBCMD_100MBITS); 2124 2125 phy_data->cur_mode = XGBE_MODE_SGMII_100; 2126 2127 netif_dbg(pdata, link, pdata->netdev, "100MbE SGMII mode set\n"); 2128 } 2129 2130 static void xgbe_phy_kr_mode(struct xgbe_prv_data *pdata) 2131 { 2132 struct xgbe_phy_data *phy_data = pdata->phy_data; 2133 2134 xgbe_phy_set_redrv_mode(pdata); 2135 2136 /* 10G/KR */ 2137 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_10G_KR, XGBE_MB_SUBCMD_NONE); 2138 2139 phy_data->cur_mode = XGBE_MODE_KR; 2140 2141 netif_dbg(pdata, link, pdata->netdev, "10GbE KR mode set\n"); 2142 } 2143 2144 static void xgbe_phy_kx_2500_mode(struct xgbe_prv_data *pdata) 2145 { 2146 struct xgbe_phy_data *phy_data = pdata->phy_data; 2147 2148 xgbe_phy_set_redrv_mode(pdata); 2149 2150 /* 2.5G/KX */ 2151 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_2_5G, XGBE_MB_SUBCMD_NONE); 2152 2153 phy_data->cur_mode = XGBE_MODE_KX_2500; 2154 2155 netif_dbg(pdata, link, pdata->netdev, "2.5GbE KX mode set\n"); 2156 } 2157 2158 static void xgbe_phy_kx_1000_mode(struct xgbe_prv_data *pdata) 2159 { 2160 struct xgbe_phy_data *phy_data = pdata->phy_data; 2161 2162 xgbe_phy_set_redrv_mode(pdata); 2163 2164 /* 1G/KX */ 2165 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_1G, XGBE_MB_SUBCMD_1G_KX); 2166 2167 phy_data->cur_mode = XGBE_MODE_KX_1000; 2168 2169 netif_dbg(pdata, link, pdata->netdev, "1GbE KX mode set\n"); 2170 } 2171 2172 static enum xgbe_mode xgbe_phy_cur_mode(struct xgbe_prv_data *pdata) 2173 { 2174 struct xgbe_phy_data *phy_data = pdata->phy_data; 2175 2176 return phy_data->cur_mode; 2177 } 2178 2179 static enum xgbe_mode xgbe_phy_switch_baset_mode(struct xgbe_prv_data *pdata) 2180 { 2181 struct xgbe_phy_data *phy_data = pdata->phy_data; 2182 2183 /* No switching if not 10GBase-T */ 2184 if (phy_data->port_mode != XGBE_PORT_MODE_10GBASE_T) 2185 return xgbe_phy_cur_mode(pdata); 2186 2187 switch (xgbe_phy_cur_mode(pdata)) { 2188 case XGBE_MODE_SGMII_100: 2189 case XGBE_MODE_SGMII_1000: 2190 return XGBE_MODE_KR; 2191 case XGBE_MODE_KR: 2192 default: 2193 return XGBE_MODE_SGMII_1000; 2194 } 2195 } 2196 2197 static enum xgbe_mode xgbe_phy_switch_bp_2500_mode(struct xgbe_prv_data *pdata) 2198 { 2199 return XGBE_MODE_KX_2500; 2200 } 2201 2202 static enum xgbe_mode xgbe_phy_switch_bp_mode(struct xgbe_prv_data *pdata) 2203 { 2204 /* If we are in KR switch to KX, and vice-versa */ 2205 switch (xgbe_phy_cur_mode(pdata)) { 2206 case XGBE_MODE_KX_1000: 2207 return XGBE_MODE_KR; 2208 case XGBE_MODE_KR: 2209 default: 2210 return XGBE_MODE_KX_1000; 2211 } 2212 } 2213 2214 static enum xgbe_mode xgbe_phy_switch_mode(struct xgbe_prv_data *pdata) 2215 { 2216 struct xgbe_phy_data *phy_data = pdata->phy_data; 2217 2218 switch (phy_data->port_mode) { 2219 case XGBE_PORT_MODE_BACKPLANE: 2220 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 2221 return xgbe_phy_switch_bp_mode(pdata); 2222 case XGBE_PORT_MODE_BACKPLANE_2500: 2223 return xgbe_phy_switch_bp_2500_mode(pdata); 2224 case XGBE_PORT_MODE_1000BASE_T: 2225 case XGBE_PORT_MODE_NBASE_T: 2226 case XGBE_PORT_MODE_10GBASE_T: 2227 return xgbe_phy_switch_baset_mode(pdata); 2228 case XGBE_PORT_MODE_1000BASE_X: 2229 case XGBE_PORT_MODE_10GBASE_R: 2230 case XGBE_PORT_MODE_SFP: 2231 /* No switching, so just return current mode */ 2232 return xgbe_phy_cur_mode(pdata); 2233 default: 2234 return XGBE_MODE_UNKNOWN; 2235 } 2236 } 2237 2238 static enum xgbe_mode xgbe_phy_get_basex_mode(struct xgbe_phy_data *phy_data, 2239 int speed) 2240 { 2241 switch (speed) { 2242 case SPEED_1000: 2243 return XGBE_MODE_X; 2244 case SPEED_10000: 2245 return XGBE_MODE_KR; 2246 default: 2247 return XGBE_MODE_UNKNOWN; 2248 } 2249 } 2250 2251 static enum xgbe_mode xgbe_phy_get_baset_mode(struct xgbe_phy_data *phy_data, 2252 int speed) 2253 { 2254 switch (speed) { 2255 case SPEED_100: 2256 return XGBE_MODE_SGMII_100; 2257 case SPEED_1000: 2258 return XGBE_MODE_SGMII_1000; 2259 case SPEED_2500: 2260 return XGBE_MODE_KX_2500; 2261 case SPEED_10000: 2262 return XGBE_MODE_KR; 2263 default: 2264 return XGBE_MODE_UNKNOWN; 2265 } 2266 } 2267 2268 static enum xgbe_mode xgbe_phy_get_sfp_mode(struct xgbe_phy_data *phy_data, 2269 int speed) 2270 { 2271 switch (speed) { 2272 case SPEED_100: 2273 return XGBE_MODE_SGMII_100; 2274 case SPEED_1000: 2275 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T) 2276 return XGBE_MODE_SGMII_1000; 2277 else 2278 return XGBE_MODE_X; 2279 case SPEED_10000: 2280 case SPEED_UNKNOWN: 2281 return XGBE_MODE_SFI; 2282 default: 2283 return XGBE_MODE_UNKNOWN; 2284 } 2285 } 2286 2287 static enum xgbe_mode xgbe_phy_get_bp_2500_mode(int speed) 2288 { 2289 switch (speed) { 2290 case SPEED_2500: 2291 return XGBE_MODE_KX_2500; 2292 default: 2293 return XGBE_MODE_UNKNOWN; 2294 } 2295 } 2296 2297 static enum xgbe_mode xgbe_phy_get_bp_mode(int speed) 2298 { 2299 switch (speed) { 2300 case SPEED_1000: 2301 return XGBE_MODE_KX_1000; 2302 case SPEED_10000: 2303 return XGBE_MODE_KR; 2304 default: 2305 return XGBE_MODE_UNKNOWN; 2306 } 2307 } 2308 2309 static enum xgbe_mode xgbe_phy_get_mode(struct xgbe_prv_data *pdata, 2310 int speed) 2311 { 2312 struct xgbe_phy_data *phy_data = pdata->phy_data; 2313 2314 switch (phy_data->port_mode) { 2315 case XGBE_PORT_MODE_BACKPLANE: 2316 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 2317 return xgbe_phy_get_bp_mode(speed); 2318 case XGBE_PORT_MODE_BACKPLANE_2500: 2319 return xgbe_phy_get_bp_2500_mode(speed); 2320 case XGBE_PORT_MODE_1000BASE_T: 2321 case XGBE_PORT_MODE_NBASE_T: 2322 case XGBE_PORT_MODE_10GBASE_T: 2323 return xgbe_phy_get_baset_mode(phy_data, speed); 2324 case XGBE_PORT_MODE_1000BASE_X: 2325 case XGBE_PORT_MODE_10GBASE_R: 2326 return xgbe_phy_get_basex_mode(phy_data, speed); 2327 case XGBE_PORT_MODE_SFP: 2328 return xgbe_phy_get_sfp_mode(phy_data, speed); 2329 default: 2330 return XGBE_MODE_UNKNOWN; 2331 } 2332 } 2333 2334 static void xgbe_phy_set_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode) 2335 { 2336 switch (mode) { 2337 case XGBE_MODE_KX_1000: 2338 xgbe_phy_kx_1000_mode(pdata); 2339 break; 2340 case XGBE_MODE_KX_2500: 2341 xgbe_phy_kx_2500_mode(pdata); 2342 break; 2343 case XGBE_MODE_KR: 2344 xgbe_phy_kr_mode(pdata); 2345 break; 2346 case XGBE_MODE_SGMII_100: 2347 xgbe_phy_sgmii_100_mode(pdata); 2348 break; 2349 case XGBE_MODE_SGMII_1000: 2350 xgbe_phy_sgmii_1000_mode(pdata); 2351 break; 2352 case XGBE_MODE_X: 2353 xgbe_phy_x_mode(pdata); 2354 break; 2355 case XGBE_MODE_SFI: 2356 xgbe_phy_sfi_mode(pdata); 2357 break; 2358 default: 2359 break; 2360 } 2361 } 2362 2363 static bool xgbe_phy_check_mode(struct xgbe_prv_data *pdata, 2364 enum xgbe_mode mode, bool advert) 2365 { 2366 if (pdata->phy.autoneg == AUTONEG_ENABLE) { 2367 return advert; 2368 } else { 2369 enum xgbe_mode cur_mode; 2370 2371 cur_mode = xgbe_phy_get_mode(pdata, pdata->phy.speed); 2372 if (cur_mode == mode) 2373 return true; 2374 } 2375 2376 return false; 2377 } 2378 2379 static bool xgbe_phy_use_basex_mode(struct xgbe_prv_data *pdata, 2380 enum xgbe_mode mode) 2381 { 2382 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 2383 2384 switch (mode) { 2385 case XGBE_MODE_X: 2386 return xgbe_phy_check_mode(pdata, mode, 2387 XGBE_ADV(lks, 1000baseX_Full)); 2388 case XGBE_MODE_KR: 2389 return xgbe_phy_check_mode(pdata, mode, 2390 XGBE_ADV(lks, 10000baseKR_Full)); 2391 default: 2392 return false; 2393 } 2394 } 2395 2396 static bool xgbe_phy_use_baset_mode(struct xgbe_prv_data *pdata, 2397 enum xgbe_mode mode) 2398 { 2399 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 2400 2401 switch (mode) { 2402 case XGBE_MODE_SGMII_100: 2403 return xgbe_phy_check_mode(pdata, mode, 2404 XGBE_ADV(lks, 100baseT_Full)); 2405 case XGBE_MODE_SGMII_1000: 2406 return xgbe_phy_check_mode(pdata, mode, 2407 XGBE_ADV(lks, 1000baseT_Full)); 2408 case XGBE_MODE_KX_2500: 2409 return xgbe_phy_check_mode(pdata, mode, 2410 XGBE_ADV(lks, 2500baseT_Full)); 2411 case XGBE_MODE_KR: 2412 return xgbe_phy_check_mode(pdata, mode, 2413 XGBE_ADV(lks, 10000baseT_Full)); 2414 default: 2415 return false; 2416 } 2417 } 2418 2419 static bool xgbe_phy_use_sfp_mode(struct xgbe_prv_data *pdata, 2420 enum xgbe_mode mode) 2421 { 2422 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 2423 struct xgbe_phy_data *phy_data = pdata->phy_data; 2424 2425 switch (mode) { 2426 case XGBE_MODE_X: 2427 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T) 2428 return false; 2429 return xgbe_phy_check_mode(pdata, mode, 2430 XGBE_ADV(lks, 1000baseX_Full)); 2431 case XGBE_MODE_SGMII_100: 2432 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T) 2433 return false; 2434 return xgbe_phy_check_mode(pdata, mode, 2435 XGBE_ADV(lks, 100baseT_Full)); 2436 case XGBE_MODE_SGMII_1000: 2437 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T) 2438 return false; 2439 return xgbe_phy_check_mode(pdata, mode, 2440 XGBE_ADV(lks, 1000baseT_Full)); 2441 case XGBE_MODE_SFI: 2442 if (phy_data->sfp_mod_absent) 2443 return true; 2444 return xgbe_phy_check_mode(pdata, mode, 2445 XGBE_ADV(lks, 10000baseSR_Full) || 2446 XGBE_ADV(lks, 10000baseLR_Full) || 2447 XGBE_ADV(lks, 10000baseLRM_Full) || 2448 XGBE_ADV(lks, 10000baseER_Full) || 2449 XGBE_ADV(lks, 10000baseCR_Full)); 2450 default: 2451 return false; 2452 } 2453 } 2454 2455 static bool xgbe_phy_use_bp_2500_mode(struct xgbe_prv_data *pdata, 2456 enum xgbe_mode mode) 2457 { 2458 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 2459 2460 switch (mode) { 2461 case XGBE_MODE_KX_2500: 2462 return xgbe_phy_check_mode(pdata, mode, 2463 XGBE_ADV(lks, 2500baseX_Full)); 2464 default: 2465 return false; 2466 } 2467 } 2468 2469 static bool xgbe_phy_use_bp_mode(struct xgbe_prv_data *pdata, 2470 enum xgbe_mode mode) 2471 { 2472 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 2473 2474 switch (mode) { 2475 case XGBE_MODE_KX_1000: 2476 return xgbe_phy_check_mode(pdata, mode, 2477 XGBE_ADV(lks, 1000baseKX_Full)); 2478 case XGBE_MODE_KR: 2479 return xgbe_phy_check_mode(pdata, mode, 2480 XGBE_ADV(lks, 10000baseKR_Full)); 2481 default: 2482 return false; 2483 } 2484 } 2485 2486 static bool xgbe_phy_use_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode) 2487 { 2488 struct xgbe_phy_data *phy_data = pdata->phy_data; 2489 2490 switch (phy_data->port_mode) { 2491 case XGBE_PORT_MODE_BACKPLANE: 2492 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 2493 return xgbe_phy_use_bp_mode(pdata, mode); 2494 case XGBE_PORT_MODE_BACKPLANE_2500: 2495 return xgbe_phy_use_bp_2500_mode(pdata, mode); 2496 case XGBE_PORT_MODE_1000BASE_T: 2497 case XGBE_PORT_MODE_NBASE_T: 2498 case XGBE_PORT_MODE_10GBASE_T: 2499 return xgbe_phy_use_baset_mode(pdata, mode); 2500 case XGBE_PORT_MODE_1000BASE_X: 2501 case XGBE_PORT_MODE_10GBASE_R: 2502 return xgbe_phy_use_basex_mode(pdata, mode); 2503 case XGBE_PORT_MODE_SFP: 2504 return xgbe_phy_use_sfp_mode(pdata, mode); 2505 default: 2506 return false; 2507 } 2508 } 2509 2510 static bool xgbe_phy_valid_speed_basex_mode(struct xgbe_phy_data *phy_data, 2511 int speed) 2512 { 2513 switch (speed) { 2514 case SPEED_1000: 2515 return (phy_data->port_mode == XGBE_PORT_MODE_1000BASE_X); 2516 case SPEED_10000: 2517 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_R); 2518 default: 2519 return false; 2520 } 2521 } 2522 2523 static bool xgbe_phy_valid_speed_baset_mode(struct xgbe_phy_data *phy_data, 2524 int speed) 2525 { 2526 switch (speed) { 2527 case SPEED_100: 2528 case SPEED_1000: 2529 return true; 2530 case SPEED_2500: 2531 return (phy_data->port_mode == XGBE_PORT_MODE_NBASE_T); 2532 case SPEED_10000: 2533 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_T); 2534 default: 2535 return false; 2536 } 2537 } 2538 2539 static bool xgbe_phy_valid_speed_sfp_mode(struct xgbe_phy_data *phy_data, 2540 int speed) 2541 { 2542 switch (speed) { 2543 case SPEED_100: 2544 return (phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000); 2545 case SPEED_1000: 2546 return ((phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000) || 2547 (phy_data->sfp_speed == XGBE_SFP_SPEED_1000)); 2548 case SPEED_10000: 2549 return (phy_data->sfp_speed == XGBE_SFP_SPEED_10000); 2550 default: 2551 return false; 2552 } 2553 } 2554 2555 static bool xgbe_phy_valid_speed_bp_2500_mode(int speed) 2556 { 2557 switch (speed) { 2558 case SPEED_2500: 2559 return true; 2560 default: 2561 return false; 2562 } 2563 } 2564 2565 static bool xgbe_phy_valid_speed_bp_mode(int speed) 2566 { 2567 switch (speed) { 2568 case SPEED_1000: 2569 case SPEED_10000: 2570 return true; 2571 default: 2572 return false; 2573 } 2574 } 2575 2576 static bool xgbe_phy_valid_speed(struct xgbe_prv_data *pdata, int speed) 2577 { 2578 struct xgbe_phy_data *phy_data = pdata->phy_data; 2579 2580 switch (phy_data->port_mode) { 2581 case XGBE_PORT_MODE_BACKPLANE: 2582 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 2583 return xgbe_phy_valid_speed_bp_mode(speed); 2584 case XGBE_PORT_MODE_BACKPLANE_2500: 2585 return xgbe_phy_valid_speed_bp_2500_mode(speed); 2586 case XGBE_PORT_MODE_1000BASE_T: 2587 case XGBE_PORT_MODE_NBASE_T: 2588 case XGBE_PORT_MODE_10GBASE_T: 2589 return xgbe_phy_valid_speed_baset_mode(phy_data, speed); 2590 case XGBE_PORT_MODE_1000BASE_X: 2591 case XGBE_PORT_MODE_10GBASE_R: 2592 return xgbe_phy_valid_speed_basex_mode(phy_data, speed); 2593 case XGBE_PORT_MODE_SFP: 2594 return xgbe_phy_valid_speed_sfp_mode(phy_data, speed); 2595 default: 2596 return false; 2597 } 2598 } 2599 2600 static int xgbe_phy_link_status(struct xgbe_prv_data *pdata, int *an_restart) 2601 { 2602 struct xgbe_phy_data *phy_data = pdata->phy_data; 2603 unsigned int reg; 2604 int ret; 2605 2606 *an_restart = 0; 2607 2608 if (phy_data->port_mode == XGBE_PORT_MODE_SFP) { 2609 /* Check SFP signals */ 2610 xgbe_phy_sfp_detect(pdata); 2611 2612 if (phy_data->sfp_changed) { 2613 *an_restart = 1; 2614 return 0; 2615 } 2616 2617 if (phy_data->sfp_mod_absent || phy_data->sfp_rx_los) 2618 return 0; 2619 } 2620 2621 if (phy_data->phydev) { 2622 /* Check external PHY */ 2623 ret = phy_read_status(phy_data->phydev); 2624 if (ret < 0) 2625 return 0; 2626 2627 if ((pdata->phy.autoneg == AUTONEG_ENABLE) && 2628 !phy_aneg_done(phy_data->phydev)) 2629 return 0; 2630 2631 if (!phy_data->phydev->link) 2632 return 0; 2633 } 2634 2635 /* Link status is latched low, so read once to clear 2636 * and then read again to get current state 2637 */ 2638 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); 2639 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); 2640 if (reg & MDIO_STAT1_LSTATUS) 2641 return 1; 2642 2643 if (pdata->phy.autoneg == AUTONEG_ENABLE && 2644 phy_data->port_mode == XGBE_PORT_MODE_BACKPLANE) { 2645 if (!test_bit(XGBE_LINK_INIT, &pdata->dev_state)) { 2646 netif_carrier_off(pdata->netdev); 2647 *an_restart = 1; 2648 } 2649 } 2650 2651 /* No link, attempt a receiver reset cycle */ 2652 if (pdata->vdata->enable_rrc && phy_data->rrc_count++ > XGBE_RRC_FREQUENCY) { 2653 phy_data->rrc_count = 0; 2654 xgbe_phy_rrc(pdata); 2655 } 2656 2657 return 0; 2658 } 2659 2660 static void xgbe_phy_sfp_gpio_setup(struct xgbe_prv_data *pdata) 2661 { 2662 struct xgbe_phy_data *phy_data = pdata->phy_data; 2663 2664 phy_data->sfp_gpio_address = XGBE_GPIO_ADDRESS_PCA9555 + 2665 XP_GET_BITS(pdata->pp3, XP_PROP_3, 2666 GPIO_ADDR); 2667 2668 phy_data->sfp_gpio_mask = XP_GET_BITS(pdata->pp3, XP_PROP_3, 2669 GPIO_MASK); 2670 2671 phy_data->sfp_gpio_rx_los = XP_GET_BITS(pdata->pp3, XP_PROP_3, 2672 GPIO_RX_LOS); 2673 phy_data->sfp_gpio_tx_fault = XP_GET_BITS(pdata->pp3, XP_PROP_3, 2674 GPIO_TX_FAULT); 2675 phy_data->sfp_gpio_mod_absent = XP_GET_BITS(pdata->pp3, XP_PROP_3, 2676 GPIO_MOD_ABS); 2677 phy_data->sfp_gpio_rate_select = XP_GET_BITS(pdata->pp3, XP_PROP_3, 2678 GPIO_RATE_SELECT); 2679 2680 if (netif_msg_probe(pdata)) { 2681 dev_dbg(pdata->dev, "SFP: gpio_address=%#x\n", 2682 phy_data->sfp_gpio_address); 2683 dev_dbg(pdata->dev, "SFP: gpio_mask=%#x\n", 2684 phy_data->sfp_gpio_mask); 2685 dev_dbg(pdata->dev, "SFP: gpio_rx_los=%u\n", 2686 phy_data->sfp_gpio_rx_los); 2687 dev_dbg(pdata->dev, "SFP: gpio_tx_fault=%u\n", 2688 phy_data->sfp_gpio_tx_fault); 2689 dev_dbg(pdata->dev, "SFP: gpio_mod_absent=%u\n", 2690 phy_data->sfp_gpio_mod_absent); 2691 dev_dbg(pdata->dev, "SFP: gpio_rate_select=%u\n", 2692 phy_data->sfp_gpio_rate_select); 2693 } 2694 } 2695 2696 static void xgbe_phy_sfp_comm_setup(struct xgbe_prv_data *pdata) 2697 { 2698 struct xgbe_phy_data *phy_data = pdata->phy_data; 2699 unsigned int mux_addr_hi, mux_addr_lo; 2700 2701 mux_addr_hi = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_HI); 2702 mux_addr_lo = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_LO); 2703 if (mux_addr_lo == XGBE_SFP_DIRECT) 2704 return; 2705 2706 phy_data->sfp_comm = XGBE_SFP_COMM_PCA9545; 2707 phy_data->sfp_mux_address = (mux_addr_hi << 2) + mux_addr_lo; 2708 phy_data->sfp_mux_channel = XP_GET_BITS(pdata->pp4, XP_PROP_4, 2709 MUX_CHAN); 2710 2711 if (netif_msg_probe(pdata)) { 2712 dev_dbg(pdata->dev, "SFP: mux_address=%#x\n", 2713 phy_data->sfp_mux_address); 2714 dev_dbg(pdata->dev, "SFP: mux_channel=%u\n", 2715 phy_data->sfp_mux_channel); 2716 } 2717 } 2718 2719 static void xgbe_phy_sfp_setup(struct xgbe_prv_data *pdata) 2720 { 2721 xgbe_phy_sfp_comm_setup(pdata); 2722 xgbe_phy_sfp_gpio_setup(pdata); 2723 } 2724 2725 static int xgbe_phy_int_mdio_reset(struct xgbe_prv_data *pdata) 2726 { 2727 struct xgbe_phy_data *phy_data = pdata->phy_data; 2728 unsigned int ret; 2729 2730 ret = pdata->hw_if.set_gpio(pdata, phy_data->mdio_reset_gpio); 2731 if (ret) 2732 return ret; 2733 2734 ret = pdata->hw_if.clr_gpio(pdata, phy_data->mdio_reset_gpio); 2735 2736 return ret; 2737 } 2738 2739 static int xgbe_phy_i2c_mdio_reset(struct xgbe_prv_data *pdata) 2740 { 2741 struct xgbe_phy_data *phy_data = pdata->phy_data; 2742 u8 gpio_reg, gpio_ports[2], gpio_data[3]; 2743 int ret; 2744 2745 /* Read the output port registers */ 2746 gpio_reg = 2; 2747 ret = xgbe_phy_i2c_read(pdata, phy_data->mdio_reset_addr, 2748 &gpio_reg, sizeof(gpio_reg), 2749 gpio_ports, sizeof(gpio_ports)); 2750 if (ret) 2751 return ret; 2752 2753 /* Prepare to write the GPIO data */ 2754 gpio_data[0] = 2; 2755 gpio_data[1] = gpio_ports[0]; 2756 gpio_data[2] = gpio_ports[1]; 2757 2758 /* Set the GPIO pin */ 2759 if (phy_data->mdio_reset_gpio < 8) 2760 gpio_data[1] |= (1 << (phy_data->mdio_reset_gpio % 8)); 2761 else 2762 gpio_data[2] |= (1 << (phy_data->mdio_reset_gpio % 8)); 2763 2764 /* Write the output port registers */ 2765 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr, 2766 gpio_data, sizeof(gpio_data)); 2767 if (ret) 2768 return ret; 2769 2770 /* Clear the GPIO pin */ 2771 if (phy_data->mdio_reset_gpio < 8) 2772 gpio_data[1] &= ~(1 << (phy_data->mdio_reset_gpio % 8)); 2773 else 2774 gpio_data[2] &= ~(1 << (phy_data->mdio_reset_gpio % 8)); 2775 2776 /* Write the output port registers */ 2777 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr, 2778 gpio_data, sizeof(gpio_data)); 2779 2780 return ret; 2781 } 2782 2783 static int xgbe_phy_mdio_reset(struct xgbe_prv_data *pdata) 2784 { 2785 struct xgbe_phy_data *phy_data = pdata->phy_data; 2786 int ret; 2787 2788 if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO) 2789 return 0; 2790 2791 ret = xgbe_phy_get_comm_ownership(pdata); 2792 if (ret) 2793 return ret; 2794 2795 if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO) 2796 ret = xgbe_phy_i2c_mdio_reset(pdata); 2797 else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO) 2798 ret = xgbe_phy_int_mdio_reset(pdata); 2799 2800 xgbe_phy_put_comm_ownership(pdata); 2801 2802 return ret; 2803 } 2804 2805 static bool xgbe_phy_redrv_error(struct xgbe_phy_data *phy_data) 2806 { 2807 if (!phy_data->redrv) 2808 return false; 2809 2810 if (phy_data->redrv_if >= XGBE_PHY_REDRV_IF_MAX) 2811 return true; 2812 2813 switch (phy_data->redrv_model) { 2814 case XGBE_PHY_REDRV_MODEL_4223: 2815 if (phy_data->redrv_lane > 3) 2816 return true; 2817 break; 2818 case XGBE_PHY_REDRV_MODEL_4227: 2819 if (phy_data->redrv_lane > 1) 2820 return true; 2821 break; 2822 default: 2823 return true; 2824 } 2825 2826 return false; 2827 } 2828 2829 static int xgbe_phy_mdio_reset_setup(struct xgbe_prv_data *pdata) 2830 { 2831 struct xgbe_phy_data *phy_data = pdata->phy_data; 2832 2833 if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO) 2834 return 0; 2835 2836 phy_data->mdio_reset = XP_GET_BITS(pdata->pp3, XP_PROP_3, MDIO_RESET); 2837 switch (phy_data->mdio_reset) { 2838 case XGBE_MDIO_RESET_NONE: 2839 case XGBE_MDIO_RESET_I2C_GPIO: 2840 case XGBE_MDIO_RESET_INT_GPIO: 2841 break; 2842 default: 2843 dev_err(pdata->dev, "unsupported MDIO reset (%#x)\n", 2844 phy_data->mdio_reset); 2845 return -EINVAL; 2846 } 2847 2848 if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO) { 2849 phy_data->mdio_reset_addr = XGBE_GPIO_ADDRESS_PCA9555 + 2850 XP_GET_BITS(pdata->pp3, XP_PROP_3, 2851 MDIO_RESET_I2C_ADDR); 2852 phy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3, 2853 MDIO_RESET_I2C_GPIO); 2854 } else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO) { 2855 phy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3, 2856 MDIO_RESET_INT_GPIO); 2857 } 2858 2859 return 0; 2860 } 2861 2862 static bool xgbe_phy_port_mode_mismatch(struct xgbe_prv_data *pdata) 2863 { 2864 struct xgbe_phy_data *phy_data = pdata->phy_data; 2865 2866 switch (phy_data->port_mode) { 2867 case XGBE_PORT_MODE_BACKPLANE: 2868 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 2869 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) || 2870 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)) 2871 return false; 2872 break; 2873 case XGBE_PORT_MODE_BACKPLANE_2500: 2874 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500) 2875 return false; 2876 break; 2877 case XGBE_PORT_MODE_1000BASE_T: 2878 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) || 2879 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)) 2880 return false; 2881 break; 2882 case XGBE_PORT_MODE_1000BASE_X: 2883 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) 2884 return false; 2885 break; 2886 case XGBE_PORT_MODE_NBASE_T: 2887 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) || 2888 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) || 2889 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500)) 2890 return false; 2891 break; 2892 case XGBE_PORT_MODE_10GBASE_T: 2893 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) || 2894 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) || 2895 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)) 2896 return false; 2897 break; 2898 case XGBE_PORT_MODE_10GBASE_R: 2899 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) 2900 return false; 2901 break; 2902 case XGBE_PORT_MODE_SFP: 2903 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) || 2904 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) || 2905 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)) 2906 return false; 2907 break; 2908 default: 2909 break; 2910 } 2911 2912 return true; 2913 } 2914 2915 static bool xgbe_phy_conn_type_mismatch(struct xgbe_prv_data *pdata) 2916 { 2917 struct xgbe_phy_data *phy_data = pdata->phy_data; 2918 2919 switch (phy_data->port_mode) { 2920 case XGBE_PORT_MODE_BACKPLANE: 2921 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 2922 case XGBE_PORT_MODE_BACKPLANE_2500: 2923 if (phy_data->conn_type == XGBE_CONN_TYPE_BACKPLANE) 2924 return false; 2925 break; 2926 case XGBE_PORT_MODE_1000BASE_T: 2927 case XGBE_PORT_MODE_1000BASE_X: 2928 case XGBE_PORT_MODE_NBASE_T: 2929 case XGBE_PORT_MODE_10GBASE_T: 2930 case XGBE_PORT_MODE_10GBASE_R: 2931 if (phy_data->conn_type == XGBE_CONN_TYPE_MDIO) 2932 return false; 2933 break; 2934 case XGBE_PORT_MODE_SFP: 2935 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP) 2936 return false; 2937 break; 2938 default: 2939 break; 2940 } 2941 2942 return true; 2943 } 2944 2945 static bool xgbe_phy_port_enabled(struct xgbe_prv_data *pdata) 2946 { 2947 if (!XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS)) 2948 return false; 2949 if (!XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE)) 2950 return false; 2951 2952 return true; 2953 } 2954 2955 static void xgbe_phy_cdr_track(struct xgbe_prv_data *pdata) 2956 { 2957 struct xgbe_phy_data *phy_data = pdata->phy_data; 2958 2959 if (!pdata->debugfs_an_cdr_workaround) 2960 return; 2961 2962 if (!phy_data->phy_cdr_notrack) 2963 return; 2964 2965 usleep_range(phy_data->phy_cdr_delay, 2966 phy_data->phy_cdr_delay + 500); 2967 2968 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL, 2969 XGBE_PMA_CDR_TRACK_EN_MASK, 2970 XGBE_PMA_CDR_TRACK_EN_ON); 2971 2972 phy_data->phy_cdr_notrack = 0; 2973 } 2974 2975 static void xgbe_phy_cdr_notrack(struct xgbe_prv_data *pdata) 2976 { 2977 struct xgbe_phy_data *phy_data = pdata->phy_data; 2978 2979 if (!pdata->debugfs_an_cdr_workaround) 2980 return; 2981 2982 if (phy_data->phy_cdr_notrack) 2983 return; 2984 2985 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL, 2986 XGBE_PMA_CDR_TRACK_EN_MASK, 2987 XGBE_PMA_CDR_TRACK_EN_OFF); 2988 2989 xgbe_phy_rrc(pdata); 2990 2991 phy_data->phy_cdr_notrack = 1; 2992 } 2993 2994 static void xgbe_phy_kr_training_post(struct xgbe_prv_data *pdata) 2995 { 2996 if (!pdata->debugfs_an_cdr_track_early) 2997 xgbe_phy_cdr_track(pdata); 2998 } 2999 3000 static void xgbe_phy_kr_training_pre(struct xgbe_prv_data *pdata) 3001 { 3002 if (pdata->debugfs_an_cdr_track_early) 3003 xgbe_phy_cdr_track(pdata); 3004 } 3005 3006 static void xgbe_phy_an_post(struct xgbe_prv_data *pdata) 3007 { 3008 struct xgbe_phy_data *phy_data = pdata->phy_data; 3009 3010 switch (pdata->an_mode) { 3011 case XGBE_AN_MODE_CL73: 3012 case XGBE_AN_MODE_CL73_REDRV: 3013 if (phy_data->cur_mode != XGBE_MODE_KR) 3014 break; 3015 3016 xgbe_phy_cdr_track(pdata); 3017 3018 switch (pdata->an_result) { 3019 case XGBE_AN_READY: 3020 case XGBE_AN_COMPLETE: 3021 break; 3022 default: 3023 if (phy_data->phy_cdr_delay < XGBE_CDR_DELAY_MAX) 3024 phy_data->phy_cdr_delay += XGBE_CDR_DELAY_INC; 3025 else 3026 phy_data->phy_cdr_delay = XGBE_CDR_DELAY_INIT; 3027 break; 3028 } 3029 break; 3030 default: 3031 break; 3032 } 3033 } 3034 3035 static void xgbe_phy_an_pre(struct xgbe_prv_data *pdata) 3036 { 3037 struct xgbe_phy_data *phy_data = pdata->phy_data; 3038 3039 switch (pdata->an_mode) { 3040 case XGBE_AN_MODE_CL73: 3041 case XGBE_AN_MODE_CL73_REDRV: 3042 if (phy_data->cur_mode != XGBE_MODE_KR) 3043 break; 3044 3045 xgbe_phy_cdr_notrack(pdata); 3046 break; 3047 default: 3048 break; 3049 } 3050 } 3051 3052 static void xgbe_phy_stop(struct xgbe_prv_data *pdata) 3053 { 3054 struct xgbe_phy_data *phy_data = pdata->phy_data; 3055 3056 /* If we have an external PHY, free it */ 3057 xgbe_phy_free_phy_device(pdata); 3058 3059 /* Reset SFP data */ 3060 xgbe_phy_sfp_reset(phy_data); 3061 xgbe_phy_sfp_mod_absent(pdata); 3062 3063 /* Reset CDR support */ 3064 xgbe_phy_cdr_track(pdata); 3065 3066 /* Power off the PHY */ 3067 xgbe_phy_power_off(pdata); 3068 3069 /* Stop the I2C controller */ 3070 pdata->i2c_if.i2c_stop(pdata); 3071 } 3072 3073 static int xgbe_phy_start(struct xgbe_prv_data *pdata) 3074 { 3075 struct xgbe_phy_data *phy_data = pdata->phy_data; 3076 int ret; 3077 3078 /* Start the I2C controller */ 3079 ret = pdata->i2c_if.i2c_start(pdata); 3080 if (ret) 3081 return ret; 3082 3083 /* Set the proper MDIO mode for the re-driver */ 3084 if (phy_data->redrv && !phy_data->redrv_if) { 3085 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr, 3086 XGBE_MDIO_MODE_CL22); 3087 if (ret) { 3088 netdev_err(pdata->netdev, 3089 "redriver mdio port not compatible (%u)\n", 3090 phy_data->redrv_addr); 3091 return ret; 3092 } 3093 } 3094 3095 /* Start in highest supported mode */ 3096 xgbe_phy_set_mode(pdata, phy_data->start_mode); 3097 3098 /* Reset CDR support */ 3099 xgbe_phy_cdr_track(pdata); 3100 3101 /* After starting the I2C controller, we can check for an SFP */ 3102 switch (phy_data->port_mode) { 3103 case XGBE_PORT_MODE_SFP: 3104 xgbe_phy_sfp_detect(pdata); 3105 break; 3106 default: 3107 break; 3108 } 3109 3110 /* If we have an external PHY, start it */ 3111 ret = xgbe_phy_find_phy_device(pdata); 3112 if (ret) 3113 goto err_i2c; 3114 3115 return 0; 3116 3117 err_i2c: 3118 pdata->i2c_if.i2c_stop(pdata); 3119 3120 return ret; 3121 } 3122 3123 static int xgbe_phy_reset(struct xgbe_prv_data *pdata) 3124 { 3125 struct xgbe_phy_data *phy_data = pdata->phy_data; 3126 enum xgbe_mode cur_mode; 3127 int ret; 3128 3129 /* Reset by power cycling the PHY */ 3130 cur_mode = phy_data->cur_mode; 3131 xgbe_phy_power_off(pdata); 3132 xgbe_phy_set_mode(pdata, cur_mode); 3133 3134 if (!phy_data->phydev) 3135 return 0; 3136 3137 /* Reset the external PHY */ 3138 ret = xgbe_phy_mdio_reset(pdata); 3139 if (ret) 3140 return ret; 3141 3142 return phy_init_hw(phy_data->phydev); 3143 } 3144 3145 static void xgbe_phy_exit(struct xgbe_prv_data *pdata) 3146 { 3147 struct xgbe_phy_data *phy_data = pdata->phy_data; 3148 3149 /* Unregister for driving external PHYs */ 3150 mdiobus_unregister(phy_data->mii); 3151 } 3152 3153 static int xgbe_phy_init(struct xgbe_prv_data *pdata) 3154 { 3155 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 3156 struct xgbe_phy_data *phy_data; 3157 struct mii_bus *mii; 3158 int ret; 3159 3160 /* Check if enabled */ 3161 if (!xgbe_phy_port_enabled(pdata)) { 3162 dev_info(pdata->dev, "device is not enabled\n"); 3163 return -ENODEV; 3164 } 3165 3166 /* Initialize the I2C controller */ 3167 ret = pdata->i2c_if.i2c_init(pdata); 3168 if (ret) 3169 return ret; 3170 3171 phy_data = devm_kzalloc(pdata->dev, sizeof(*phy_data), GFP_KERNEL); 3172 if (!phy_data) 3173 return -ENOMEM; 3174 pdata->phy_data = phy_data; 3175 3176 phy_data->port_mode = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_MODE); 3177 phy_data->port_id = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_ID); 3178 phy_data->port_speeds = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS); 3179 phy_data->conn_type = XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE); 3180 phy_data->mdio_addr = XP_GET_BITS(pdata->pp0, XP_PROP_0, MDIO_ADDR); 3181 if (netif_msg_probe(pdata)) { 3182 dev_dbg(pdata->dev, "port mode=%u\n", phy_data->port_mode); 3183 dev_dbg(pdata->dev, "port id=%u\n", phy_data->port_id); 3184 dev_dbg(pdata->dev, "port speeds=%#x\n", phy_data->port_speeds); 3185 dev_dbg(pdata->dev, "conn type=%u\n", phy_data->conn_type); 3186 dev_dbg(pdata->dev, "mdio addr=%u\n", phy_data->mdio_addr); 3187 } 3188 3189 phy_data->redrv = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_PRESENT); 3190 phy_data->redrv_if = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_IF); 3191 phy_data->redrv_addr = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_ADDR); 3192 phy_data->redrv_lane = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_LANE); 3193 phy_data->redrv_model = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_MODEL); 3194 if (phy_data->redrv && netif_msg_probe(pdata)) { 3195 dev_dbg(pdata->dev, "redrv present\n"); 3196 dev_dbg(pdata->dev, "redrv i/f=%u\n", phy_data->redrv_if); 3197 dev_dbg(pdata->dev, "redrv addr=%#x\n", phy_data->redrv_addr); 3198 dev_dbg(pdata->dev, "redrv lane=%u\n", phy_data->redrv_lane); 3199 dev_dbg(pdata->dev, "redrv model=%u\n", phy_data->redrv_model); 3200 } 3201 3202 /* Validate the connection requested */ 3203 if (xgbe_phy_conn_type_mismatch(pdata)) { 3204 dev_err(pdata->dev, "phy mode/connection mismatch (%#x/%#x)\n", 3205 phy_data->port_mode, phy_data->conn_type); 3206 return -EINVAL; 3207 } 3208 3209 /* Validate the mode requested */ 3210 if (xgbe_phy_port_mode_mismatch(pdata)) { 3211 dev_err(pdata->dev, "phy mode/speed mismatch (%#x/%#x)\n", 3212 phy_data->port_mode, phy_data->port_speeds); 3213 return -EINVAL; 3214 } 3215 3216 /* Check for and validate MDIO reset support */ 3217 ret = xgbe_phy_mdio_reset_setup(pdata); 3218 if (ret) 3219 return ret; 3220 3221 /* Validate the re-driver information */ 3222 if (xgbe_phy_redrv_error(phy_data)) { 3223 dev_err(pdata->dev, "phy re-driver settings error\n"); 3224 return -EINVAL; 3225 } 3226 pdata->kr_redrv = phy_data->redrv; 3227 3228 /* Indicate current mode is unknown */ 3229 phy_data->cur_mode = XGBE_MODE_UNKNOWN; 3230 3231 /* Initialize supported features */ 3232 XGBE_ZERO_SUP(lks); 3233 3234 switch (phy_data->port_mode) { 3235 /* Backplane support */ 3236 case XGBE_PORT_MODE_BACKPLANE: 3237 XGBE_SET_SUP(lks, Autoneg); 3238 fallthrough; 3239 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 3240 XGBE_SET_SUP(lks, Pause); 3241 XGBE_SET_SUP(lks, Asym_Pause); 3242 XGBE_SET_SUP(lks, Backplane); 3243 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) { 3244 XGBE_SET_SUP(lks, 1000baseKX_Full); 3245 phy_data->start_mode = XGBE_MODE_KX_1000; 3246 } 3247 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) { 3248 XGBE_SET_SUP(lks, 10000baseKR_Full); 3249 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 3250 XGBE_SET_SUP(lks, 10000baseR_FEC); 3251 phy_data->start_mode = XGBE_MODE_KR; 3252 } 3253 3254 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE; 3255 break; 3256 case XGBE_PORT_MODE_BACKPLANE_2500: 3257 XGBE_SET_SUP(lks, Pause); 3258 XGBE_SET_SUP(lks, Asym_Pause); 3259 XGBE_SET_SUP(lks, Backplane); 3260 XGBE_SET_SUP(lks, 2500baseX_Full); 3261 phy_data->start_mode = XGBE_MODE_KX_2500; 3262 3263 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE; 3264 break; 3265 3266 /* MDIO 1GBase-T support */ 3267 case XGBE_PORT_MODE_1000BASE_T: 3268 XGBE_SET_SUP(lks, Autoneg); 3269 XGBE_SET_SUP(lks, Pause); 3270 XGBE_SET_SUP(lks, Asym_Pause); 3271 XGBE_SET_SUP(lks, TP); 3272 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) { 3273 XGBE_SET_SUP(lks, 100baseT_Full); 3274 phy_data->start_mode = XGBE_MODE_SGMII_100; 3275 } 3276 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) { 3277 XGBE_SET_SUP(lks, 1000baseT_Full); 3278 phy_data->start_mode = XGBE_MODE_SGMII_1000; 3279 } 3280 3281 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22; 3282 break; 3283 3284 /* MDIO Base-X support */ 3285 case XGBE_PORT_MODE_1000BASE_X: 3286 XGBE_SET_SUP(lks, Autoneg); 3287 XGBE_SET_SUP(lks, Pause); 3288 XGBE_SET_SUP(lks, Asym_Pause); 3289 XGBE_SET_SUP(lks, FIBRE); 3290 XGBE_SET_SUP(lks, 1000baseX_Full); 3291 phy_data->start_mode = XGBE_MODE_X; 3292 3293 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22; 3294 break; 3295 3296 /* MDIO NBase-T support */ 3297 case XGBE_PORT_MODE_NBASE_T: 3298 XGBE_SET_SUP(lks, Autoneg); 3299 XGBE_SET_SUP(lks, Pause); 3300 XGBE_SET_SUP(lks, Asym_Pause); 3301 XGBE_SET_SUP(lks, TP); 3302 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) { 3303 XGBE_SET_SUP(lks, 100baseT_Full); 3304 phy_data->start_mode = XGBE_MODE_SGMII_100; 3305 } 3306 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) { 3307 XGBE_SET_SUP(lks, 1000baseT_Full); 3308 phy_data->start_mode = XGBE_MODE_SGMII_1000; 3309 } 3310 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500) { 3311 XGBE_SET_SUP(lks, 2500baseT_Full); 3312 phy_data->start_mode = XGBE_MODE_KX_2500; 3313 } 3314 3315 phy_data->phydev_mode = XGBE_MDIO_MODE_CL45; 3316 break; 3317 3318 /* 10GBase-T support */ 3319 case XGBE_PORT_MODE_10GBASE_T: 3320 XGBE_SET_SUP(lks, Autoneg); 3321 XGBE_SET_SUP(lks, Pause); 3322 XGBE_SET_SUP(lks, Asym_Pause); 3323 XGBE_SET_SUP(lks, TP); 3324 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) { 3325 XGBE_SET_SUP(lks, 100baseT_Full); 3326 phy_data->start_mode = XGBE_MODE_SGMII_100; 3327 } 3328 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) { 3329 XGBE_SET_SUP(lks, 1000baseT_Full); 3330 phy_data->start_mode = XGBE_MODE_SGMII_1000; 3331 } 3332 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) { 3333 XGBE_SET_SUP(lks, 10000baseT_Full); 3334 phy_data->start_mode = XGBE_MODE_KR; 3335 } 3336 3337 phy_data->phydev_mode = XGBE_MDIO_MODE_CL45; 3338 break; 3339 3340 /* 10GBase-R support */ 3341 case XGBE_PORT_MODE_10GBASE_R: 3342 XGBE_SET_SUP(lks, Autoneg); 3343 XGBE_SET_SUP(lks, Pause); 3344 XGBE_SET_SUP(lks, Asym_Pause); 3345 XGBE_SET_SUP(lks, FIBRE); 3346 XGBE_SET_SUP(lks, 10000baseSR_Full); 3347 XGBE_SET_SUP(lks, 10000baseLR_Full); 3348 XGBE_SET_SUP(lks, 10000baseLRM_Full); 3349 XGBE_SET_SUP(lks, 10000baseER_Full); 3350 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 3351 XGBE_SET_SUP(lks, 10000baseR_FEC); 3352 phy_data->start_mode = XGBE_MODE_SFI; 3353 3354 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE; 3355 break; 3356 3357 /* SFP support */ 3358 case XGBE_PORT_MODE_SFP: 3359 XGBE_SET_SUP(lks, Autoneg); 3360 XGBE_SET_SUP(lks, Pause); 3361 XGBE_SET_SUP(lks, Asym_Pause); 3362 XGBE_SET_SUP(lks, TP); 3363 XGBE_SET_SUP(lks, FIBRE); 3364 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) 3365 phy_data->start_mode = XGBE_MODE_SGMII_100; 3366 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) 3367 phy_data->start_mode = XGBE_MODE_SGMII_1000; 3368 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) 3369 phy_data->start_mode = XGBE_MODE_SFI; 3370 3371 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22; 3372 3373 xgbe_phy_sfp_setup(pdata); 3374 break; 3375 default: 3376 return -EINVAL; 3377 } 3378 3379 if (netif_msg_probe(pdata)) 3380 dev_dbg(pdata->dev, "phy supported=0x%*pb\n", 3381 __ETHTOOL_LINK_MODE_MASK_NBITS, 3382 lks->link_modes.supported); 3383 3384 if ((phy_data->conn_type & XGBE_CONN_TYPE_MDIO) && 3385 (phy_data->phydev_mode != XGBE_MDIO_MODE_NONE)) { 3386 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr, 3387 phy_data->phydev_mode); 3388 if (ret) { 3389 dev_err(pdata->dev, 3390 "mdio port/clause not compatible (%d/%u)\n", 3391 phy_data->mdio_addr, phy_data->phydev_mode); 3392 return -EINVAL; 3393 } 3394 } 3395 3396 if (phy_data->redrv && !phy_data->redrv_if) { 3397 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr, 3398 XGBE_MDIO_MODE_CL22); 3399 if (ret) { 3400 dev_err(pdata->dev, 3401 "redriver mdio port not compatible (%u)\n", 3402 phy_data->redrv_addr); 3403 return -EINVAL; 3404 } 3405 } 3406 3407 phy_data->phy_cdr_delay = XGBE_CDR_DELAY_INIT; 3408 3409 /* Register for driving external PHYs */ 3410 mii = devm_mdiobus_alloc(pdata->dev); 3411 if (!mii) { 3412 dev_err(pdata->dev, "mdiobus_alloc failed\n"); 3413 return -ENOMEM; 3414 } 3415 3416 mii->priv = pdata; 3417 mii->name = "amd-xgbe-mii"; 3418 mii->read = xgbe_phy_mii_read; 3419 mii->write = xgbe_phy_mii_write; 3420 mii->parent = pdata->dev; 3421 mii->phy_mask = ~0; 3422 snprintf(mii->id, sizeof(mii->id), "%s", dev_name(pdata->dev)); 3423 ret = mdiobus_register(mii); 3424 if (ret) { 3425 dev_err(pdata->dev, "mdiobus_register failed\n"); 3426 return ret; 3427 } 3428 phy_data->mii = mii; 3429 3430 return 0; 3431 } 3432 3433 void xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if *phy_if) 3434 { 3435 struct xgbe_phy_impl_if *phy_impl = &phy_if->phy_impl; 3436 3437 phy_impl->init = xgbe_phy_init; 3438 phy_impl->exit = xgbe_phy_exit; 3439 3440 phy_impl->reset = xgbe_phy_reset; 3441 phy_impl->start = xgbe_phy_start; 3442 phy_impl->stop = xgbe_phy_stop; 3443 3444 phy_impl->link_status = xgbe_phy_link_status; 3445 3446 phy_impl->valid_speed = xgbe_phy_valid_speed; 3447 3448 phy_impl->use_mode = xgbe_phy_use_mode; 3449 phy_impl->set_mode = xgbe_phy_set_mode; 3450 phy_impl->get_mode = xgbe_phy_get_mode; 3451 phy_impl->switch_mode = xgbe_phy_switch_mode; 3452 phy_impl->cur_mode = xgbe_phy_cur_mode; 3453 3454 phy_impl->an_mode = xgbe_phy_an_mode; 3455 3456 phy_impl->an_config = xgbe_phy_an_config; 3457 3458 phy_impl->an_advertising = xgbe_phy_an_advertising; 3459 3460 phy_impl->an_outcome = xgbe_phy_an_outcome; 3461 3462 phy_impl->an_pre = xgbe_phy_an_pre; 3463 phy_impl->an_post = xgbe_phy_an_post; 3464 3465 phy_impl->kr_training_pre = xgbe_phy_kr_training_pre; 3466 phy_impl->kr_training_post = xgbe_phy_kr_training_post; 3467 3468 phy_impl->module_info = xgbe_phy_module_info; 3469 phy_impl->module_eeprom = xgbe_phy_module_eeprom; 3470 } 3471