1 /* 2 * AMD 10Gb Ethernet driver 3 * 4 * This file is available to you under your choice of the following two 5 * licenses: 6 * 7 * License 1: GPLv2 8 * 9 * Copyright (c) 2016 Advanced Micro Devices, Inc. 10 * 11 * This file is free software; you may copy, redistribute and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation, either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program. If not, see <http://www.gnu.org/licenses/>. 23 * 24 * This file incorporates work covered by the following copyright and 25 * permission notice: 26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 28 * Inc. unless otherwise expressly agreed to in writing between Synopsys 29 * and you. 30 * 31 * The Software IS NOT an item of Licensed Software or Licensed Product 32 * under any End User Software License Agreement or Agreement for Licensed 33 * Product with Synopsys or any supplement thereto. Permission is hereby 34 * granted, free of charge, to any person obtaining a copy of this software 35 * annotated with this license and the Software, to deal in the Software 36 * without restriction, including without limitation the rights to use, 37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 38 * of the Software, and to permit persons to whom the Software is furnished 39 * to do so, subject to the following conditions: 40 * 41 * The above copyright notice and this permission notice shall be included 42 * in all copies or substantial portions of the Software. 43 * 44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 54 * THE POSSIBILITY OF SUCH DAMAGE. 55 * 56 * 57 * License 2: Modified BSD 58 * 59 * Copyright (c) 2016 Advanced Micro Devices, Inc. 60 * All rights reserved. 61 * 62 * Redistribution and use in source and binary forms, with or without 63 * modification, are permitted provided that the following conditions are met: 64 * * Redistributions of source code must retain the above copyright 65 * notice, this list of conditions and the following disclaimer. 66 * * Redistributions in binary form must reproduce the above copyright 67 * notice, this list of conditions and the following disclaimer in the 68 * documentation and/or other materials provided with the distribution. 69 * * Neither the name of Advanced Micro Devices, Inc. nor the 70 * names of its contributors may be used to endorse or promote products 71 * derived from this software without specific prior written permission. 72 * 73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY 77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 83 * 84 * This file incorporates work covered by the following copyright and 85 * permission notice: 86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 88 * Inc. unless otherwise expressly agreed to in writing between Synopsys 89 * and you. 90 * 91 * The Software IS NOT an item of Licensed Software or Licensed Product 92 * under any End User Software License Agreement or Agreement for Licensed 93 * Product with Synopsys or any supplement thereto. Permission is hereby 94 * granted, free of charge, to any person obtaining a copy of this software 95 * annotated with this license and the Software, to deal in the Software 96 * without restriction, including without limitation the rights to use, 97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 98 * of the Software, and to permit persons to whom the Software is furnished 99 * to do so, subject to the following conditions: 100 * 101 * The above copyright notice and this permission notice shall be included 102 * in all copies or substantial portions of the Software. 103 * 104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 114 * THE POSSIBILITY OF SUCH DAMAGE. 115 */ 116 117 #include <linux/module.h> 118 #include <linux/device.h> 119 #include <linux/kmod.h> 120 #include <linux/mdio.h> 121 #include <linux/phy.h> 122 123 #include "xgbe.h" 124 #include "xgbe-common.h" 125 126 #define XGBE_PHY_PORT_SPEED_100 BIT(0) 127 #define XGBE_PHY_PORT_SPEED_1000 BIT(1) 128 #define XGBE_PHY_PORT_SPEED_2500 BIT(2) 129 #define XGBE_PHY_PORT_SPEED_10000 BIT(3) 130 131 #define XGBE_MUTEX_RELEASE 0x80000000 132 133 #define XGBE_SFP_DIRECT 7 134 135 /* I2C target addresses */ 136 #define XGBE_SFP_SERIAL_ID_ADDRESS 0x50 137 #define XGBE_SFP_DIAG_INFO_ADDRESS 0x51 138 #define XGBE_SFP_PHY_ADDRESS 0x56 139 #define XGBE_GPIO_ADDRESS_PCA9555 0x20 140 141 /* SFP sideband signal indicators */ 142 #define XGBE_GPIO_NO_TX_FAULT BIT(0) 143 #define XGBE_GPIO_NO_RATE_SELECT BIT(1) 144 #define XGBE_GPIO_NO_MOD_ABSENT BIT(2) 145 #define XGBE_GPIO_NO_RX_LOS BIT(3) 146 147 /* Rate-change complete wait/retry count */ 148 #define XGBE_RATECHANGE_COUNT 500 149 150 enum xgbe_port_mode { 151 XGBE_PORT_MODE_RSVD = 0, 152 XGBE_PORT_MODE_BACKPLANE, 153 XGBE_PORT_MODE_BACKPLANE_2500, 154 XGBE_PORT_MODE_1000BASE_T, 155 XGBE_PORT_MODE_1000BASE_X, 156 XGBE_PORT_MODE_NBASE_T, 157 XGBE_PORT_MODE_10GBASE_T, 158 XGBE_PORT_MODE_10GBASE_R, 159 XGBE_PORT_MODE_SFP, 160 XGBE_PORT_MODE_MAX, 161 }; 162 163 enum xgbe_conn_type { 164 XGBE_CONN_TYPE_NONE = 0, 165 XGBE_CONN_TYPE_SFP, 166 XGBE_CONN_TYPE_MDIO, 167 XGBE_CONN_TYPE_RSVD1, 168 XGBE_CONN_TYPE_BACKPLANE, 169 XGBE_CONN_TYPE_MAX, 170 }; 171 172 /* SFP/SFP+ related definitions */ 173 enum xgbe_sfp_comm { 174 XGBE_SFP_COMM_DIRECT = 0, 175 XGBE_SFP_COMM_PCA9545, 176 }; 177 178 enum xgbe_sfp_cable { 179 XGBE_SFP_CABLE_UNKNOWN = 0, 180 XGBE_SFP_CABLE_ACTIVE, 181 XGBE_SFP_CABLE_PASSIVE, 182 }; 183 184 enum xgbe_sfp_base { 185 XGBE_SFP_BASE_UNKNOWN = 0, 186 XGBE_SFP_BASE_1000_T, 187 XGBE_SFP_BASE_1000_SX, 188 XGBE_SFP_BASE_1000_LX, 189 XGBE_SFP_BASE_1000_CX, 190 XGBE_SFP_BASE_10000_SR, 191 XGBE_SFP_BASE_10000_LR, 192 XGBE_SFP_BASE_10000_LRM, 193 XGBE_SFP_BASE_10000_ER, 194 XGBE_SFP_BASE_10000_CR, 195 }; 196 197 enum xgbe_sfp_speed { 198 XGBE_SFP_SPEED_UNKNOWN = 0, 199 XGBE_SFP_SPEED_100_1000, 200 XGBE_SFP_SPEED_1000, 201 XGBE_SFP_SPEED_10000, 202 }; 203 204 /* SFP Serial ID Base ID values relative to an offset of 0 */ 205 #define XGBE_SFP_BASE_ID 0 206 #define XGBE_SFP_ID_SFP 0x03 207 208 #define XGBE_SFP_BASE_EXT_ID 1 209 #define XGBE_SFP_EXT_ID_SFP 0x04 210 211 #define XGBE_SFP_BASE_10GBE_CC 3 212 #define XGBE_SFP_BASE_10GBE_CC_SR BIT(4) 213 #define XGBE_SFP_BASE_10GBE_CC_LR BIT(5) 214 #define XGBE_SFP_BASE_10GBE_CC_LRM BIT(6) 215 #define XGBE_SFP_BASE_10GBE_CC_ER BIT(7) 216 217 #define XGBE_SFP_BASE_1GBE_CC 6 218 #define XGBE_SFP_BASE_1GBE_CC_SX BIT(0) 219 #define XGBE_SFP_BASE_1GBE_CC_LX BIT(1) 220 #define XGBE_SFP_BASE_1GBE_CC_CX BIT(2) 221 #define XGBE_SFP_BASE_1GBE_CC_T BIT(3) 222 223 #define XGBE_SFP_BASE_CABLE 8 224 #define XGBE_SFP_BASE_CABLE_PASSIVE BIT(2) 225 #define XGBE_SFP_BASE_CABLE_ACTIVE BIT(3) 226 227 #define XGBE_SFP_BASE_BR 12 228 #define XGBE_SFP_BASE_BR_1GBE_MIN 0x0a 229 #define XGBE_SFP_BASE_BR_1GBE_MAX 0x0d 230 #define XGBE_SFP_BASE_BR_10GBE_MIN 0x64 231 #define XGBE_SFP_BASE_BR_10GBE_MAX 0x68 232 233 #define XGBE_SFP_BASE_CU_CABLE_LEN 18 234 235 #define XGBE_SFP_BASE_VENDOR_NAME 20 236 #define XGBE_SFP_BASE_VENDOR_NAME_LEN 16 237 #define XGBE_SFP_BASE_VENDOR_PN 40 238 #define XGBE_SFP_BASE_VENDOR_PN_LEN 16 239 #define XGBE_SFP_BASE_VENDOR_REV 56 240 #define XGBE_SFP_BASE_VENDOR_REV_LEN 4 241 242 #define XGBE_SFP_BASE_CC 63 243 244 /* SFP Serial ID Extended ID values relative to an offset of 64 */ 245 #define XGBE_SFP_BASE_VENDOR_SN 4 246 #define XGBE_SFP_BASE_VENDOR_SN_LEN 16 247 248 #define XGBE_SFP_EXTD_DIAG 28 249 #define XGBE_SFP_EXTD_DIAG_ADDR_CHANGE BIT(2) 250 251 #define XGBE_SFP_EXTD_SFF_8472 30 252 253 #define XGBE_SFP_EXTD_CC 31 254 255 struct xgbe_sfp_eeprom { 256 u8 base[64]; 257 u8 extd[32]; 258 u8 vendor[32]; 259 }; 260 261 #define XGBE_BEL_FUSE_VENDOR "BEL-FUSE " 262 #define XGBE_BEL_FUSE_PARTNO "1GBT-SFP06 " 263 264 struct xgbe_sfp_ascii { 265 union { 266 char vendor[XGBE_SFP_BASE_VENDOR_NAME_LEN + 1]; 267 char partno[XGBE_SFP_BASE_VENDOR_PN_LEN + 1]; 268 char rev[XGBE_SFP_BASE_VENDOR_REV_LEN + 1]; 269 char serno[XGBE_SFP_BASE_VENDOR_SN_LEN + 1]; 270 } u; 271 }; 272 273 /* MDIO PHY reset types */ 274 enum xgbe_mdio_reset { 275 XGBE_MDIO_RESET_NONE = 0, 276 XGBE_MDIO_RESET_I2C_GPIO, 277 XGBE_MDIO_RESET_INT_GPIO, 278 XGBE_MDIO_RESET_MAX, 279 }; 280 281 /* Re-driver related definitions */ 282 enum xgbe_phy_redrv_if { 283 XGBE_PHY_REDRV_IF_MDIO = 0, 284 XGBE_PHY_REDRV_IF_I2C, 285 XGBE_PHY_REDRV_IF_MAX, 286 }; 287 288 enum xgbe_phy_redrv_model { 289 XGBE_PHY_REDRV_MODEL_4223 = 0, 290 XGBE_PHY_REDRV_MODEL_4227, 291 XGBE_PHY_REDRV_MODEL_MAX, 292 }; 293 294 enum xgbe_phy_redrv_mode { 295 XGBE_PHY_REDRV_MODE_CX = 5, 296 XGBE_PHY_REDRV_MODE_SR = 9, 297 }; 298 299 #define XGBE_PHY_REDRV_MODE_REG 0x12b0 300 301 /* PHY related configuration information */ 302 struct xgbe_phy_data { 303 enum xgbe_port_mode port_mode; 304 305 unsigned int port_id; 306 307 unsigned int port_speeds; 308 309 enum xgbe_conn_type conn_type; 310 311 enum xgbe_mode cur_mode; 312 enum xgbe_mode start_mode; 313 314 unsigned int rrc_count; 315 316 unsigned int mdio_addr; 317 318 unsigned int comm_owned; 319 320 /* SFP Support */ 321 enum xgbe_sfp_comm sfp_comm; 322 unsigned int sfp_mux_address; 323 unsigned int sfp_mux_channel; 324 325 unsigned int sfp_gpio_address; 326 unsigned int sfp_gpio_mask; 327 unsigned int sfp_gpio_rx_los; 328 unsigned int sfp_gpio_tx_fault; 329 unsigned int sfp_gpio_mod_absent; 330 unsigned int sfp_gpio_rate_select; 331 332 unsigned int sfp_rx_los; 333 unsigned int sfp_tx_fault; 334 unsigned int sfp_mod_absent; 335 unsigned int sfp_diags; 336 unsigned int sfp_changed; 337 unsigned int sfp_phy_avail; 338 unsigned int sfp_cable_len; 339 enum xgbe_sfp_base sfp_base; 340 enum xgbe_sfp_cable sfp_cable; 341 enum xgbe_sfp_speed sfp_speed; 342 struct xgbe_sfp_eeprom sfp_eeprom; 343 344 /* External PHY support */ 345 enum xgbe_mdio_mode phydev_mode; 346 struct mii_bus *mii; 347 struct phy_device *phydev; 348 enum xgbe_mdio_reset mdio_reset; 349 unsigned int mdio_reset_addr; 350 unsigned int mdio_reset_gpio; 351 352 /* Re-driver support */ 353 unsigned int redrv; 354 unsigned int redrv_if; 355 unsigned int redrv_addr; 356 unsigned int redrv_lane; 357 unsigned int redrv_model; 358 }; 359 360 /* I2C, MDIO and GPIO lines are muxed, so only one device at a time */ 361 static DEFINE_MUTEX(xgbe_phy_comm_lock); 362 363 static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata); 364 365 static int xgbe_phy_i2c_xfer(struct xgbe_prv_data *pdata, 366 struct xgbe_i2c_op *i2c_op) 367 { 368 struct xgbe_phy_data *phy_data = pdata->phy_data; 369 370 /* Be sure we own the bus */ 371 if (WARN_ON(!phy_data->comm_owned)) 372 return -EIO; 373 374 return pdata->i2c_if.i2c_xfer(pdata, i2c_op); 375 } 376 377 static int xgbe_phy_redrv_write(struct xgbe_prv_data *pdata, unsigned int reg, 378 unsigned int val) 379 { 380 struct xgbe_phy_data *phy_data = pdata->phy_data; 381 struct xgbe_i2c_op i2c_op; 382 __be16 *redrv_val; 383 u8 redrv_data[5], csum; 384 unsigned int i, retry; 385 int ret; 386 387 /* High byte of register contains read/write indicator */ 388 redrv_data[0] = ((reg >> 8) & 0xff) << 1; 389 redrv_data[1] = reg & 0xff; 390 redrv_val = (__be16 *)&redrv_data[2]; 391 *redrv_val = cpu_to_be16(val); 392 393 /* Calculate 1 byte checksum */ 394 csum = 0; 395 for (i = 0; i < 4; i++) { 396 csum += redrv_data[i]; 397 if (redrv_data[i] > csum) 398 csum++; 399 } 400 redrv_data[4] = ~csum; 401 402 retry = 1; 403 again1: 404 i2c_op.cmd = XGBE_I2C_CMD_WRITE; 405 i2c_op.target = phy_data->redrv_addr; 406 i2c_op.len = sizeof(redrv_data); 407 i2c_op.buf = redrv_data; 408 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op); 409 if (ret) { 410 if ((ret == -EAGAIN) && retry--) 411 goto again1; 412 413 return ret; 414 } 415 416 retry = 1; 417 again2: 418 i2c_op.cmd = XGBE_I2C_CMD_READ; 419 i2c_op.target = phy_data->redrv_addr; 420 i2c_op.len = 1; 421 i2c_op.buf = redrv_data; 422 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op); 423 if (ret) { 424 if ((ret == -EAGAIN) && retry--) 425 goto again2; 426 427 return ret; 428 } 429 430 if (redrv_data[0] != 0xff) { 431 netif_dbg(pdata, drv, pdata->netdev, 432 "Redriver write checksum error\n"); 433 ret = -EIO; 434 } 435 436 return ret; 437 } 438 439 static int xgbe_phy_i2c_write(struct xgbe_prv_data *pdata, unsigned int target, 440 void *val, unsigned int val_len) 441 { 442 struct xgbe_i2c_op i2c_op; 443 int retry, ret; 444 445 retry = 1; 446 again: 447 /* Write the specfied register */ 448 i2c_op.cmd = XGBE_I2C_CMD_WRITE; 449 i2c_op.target = target; 450 i2c_op.len = val_len; 451 i2c_op.buf = val; 452 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op); 453 if ((ret == -EAGAIN) && retry--) 454 goto again; 455 456 return ret; 457 } 458 459 static int xgbe_phy_i2c_read(struct xgbe_prv_data *pdata, unsigned int target, 460 void *reg, unsigned int reg_len, 461 void *val, unsigned int val_len) 462 { 463 struct xgbe_i2c_op i2c_op; 464 int retry, ret; 465 466 retry = 1; 467 again1: 468 /* Set the specified register to read */ 469 i2c_op.cmd = XGBE_I2C_CMD_WRITE; 470 i2c_op.target = target; 471 i2c_op.len = reg_len; 472 i2c_op.buf = reg; 473 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op); 474 if (ret) { 475 if ((ret == -EAGAIN) && retry--) 476 goto again1; 477 478 return ret; 479 } 480 481 retry = 1; 482 again2: 483 /* Read the specfied register */ 484 i2c_op.cmd = XGBE_I2C_CMD_READ; 485 i2c_op.target = target; 486 i2c_op.len = val_len; 487 i2c_op.buf = val; 488 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op); 489 if ((ret == -EAGAIN) && retry--) 490 goto again2; 491 492 return ret; 493 } 494 495 static int xgbe_phy_sfp_put_mux(struct xgbe_prv_data *pdata) 496 { 497 struct xgbe_phy_data *phy_data = pdata->phy_data; 498 struct xgbe_i2c_op i2c_op; 499 u8 mux_channel; 500 501 if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT) 502 return 0; 503 504 /* Select no mux channels */ 505 mux_channel = 0; 506 i2c_op.cmd = XGBE_I2C_CMD_WRITE; 507 i2c_op.target = phy_data->sfp_mux_address; 508 i2c_op.len = sizeof(mux_channel); 509 i2c_op.buf = &mux_channel; 510 511 return xgbe_phy_i2c_xfer(pdata, &i2c_op); 512 } 513 514 static int xgbe_phy_sfp_get_mux(struct xgbe_prv_data *pdata) 515 { 516 struct xgbe_phy_data *phy_data = pdata->phy_data; 517 struct xgbe_i2c_op i2c_op; 518 u8 mux_channel; 519 520 if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT) 521 return 0; 522 523 /* Select desired mux channel */ 524 mux_channel = 1 << phy_data->sfp_mux_channel; 525 i2c_op.cmd = XGBE_I2C_CMD_WRITE; 526 i2c_op.target = phy_data->sfp_mux_address; 527 i2c_op.len = sizeof(mux_channel); 528 i2c_op.buf = &mux_channel; 529 530 return xgbe_phy_i2c_xfer(pdata, &i2c_op); 531 } 532 533 static void xgbe_phy_put_comm_ownership(struct xgbe_prv_data *pdata) 534 { 535 struct xgbe_phy_data *phy_data = pdata->phy_data; 536 537 phy_data->comm_owned = 0; 538 539 mutex_unlock(&xgbe_phy_comm_lock); 540 } 541 542 static int xgbe_phy_get_comm_ownership(struct xgbe_prv_data *pdata) 543 { 544 struct xgbe_phy_data *phy_data = pdata->phy_data; 545 unsigned long timeout; 546 unsigned int mutex_id; 547 548 if (phy_data->comm_owned) 549 return 0; 550 551 /* The I2C and MDIO/GPIO bus is multiplexed between multiple devices, 552 * the driver needs to take the software mutex and then the hardware 553 * mutexes before being able to use the busses. 554 */ 555 mutex_lock(&xgbe_phy_comm_lock); 556 557 /* Clear the mutexes */ 558 XP_IOWRITE(pdata, XP_I2C_MUTEX, XGBE_MUTEX_RELEASE); 559 XP_IOWRITE(pdata, XP_MDIO_MUTEX, XGBE_MUTEX_RELEASE); 560 561 /* Mutex formats are the same for I2C and MDIO/GPIO */ 562 mutex_id = 0; 563 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ID, phy_data->port_id); 564 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ACTIVE, 1); 565 566 timeout = jiffies + (5 * HZ); 567 while (time_before(jiffies, timeout)) { 568 /* Must be all zeroes in order to obtain the mutex */ 569 if (XP_IOREAD(pdata, XP_I2C_MUTEX) || 570 XP_IOREAD(pdata, XP_MDIO_MUTEX)) { 571 usleep_range(100, 200); 572 continue; 573 } 574 575 /* Obtain the mutex */ 576 XP_IOWRITE(pdata, XP_I2C_MUTEX, mutex_id); 577 XP_IOWRITE(pdata, XP_MDIO_MUTEX, mutex_id); 578 579 phy_data->comm_owned = 1; 580 return 0; 581 } 582 583 mutex_unlock(&xgbe_phy_comm_lock); 584 585 netdev_err(pdata->netdev, "unable to obtain hardware mutexes\n"); 586 587 return -ETIMEDOUT; 588 } 589 590 static int xgbe_phy_mdio_mii_write(struct xgbe_prv_data *pdata, int addr, 591 int reg, u16 val) 592 { 593 struct xgbe_phy_data *phy_data = pdata->phy_data; 594 595 if (reg & MII_ADDR_C45) { 596 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45) 597 return -ENOTSUPP; 598 } else { 599 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22) 600 return -ENOTSUPP; 601 } 602 603 return pdata->hw_if.write_ext_mii_regs(pdata, addr, reg, val); 604 } 605 606 static int xgbe_phy_i2c_mii_write(struct xgbe_prv_data *pdata, int reg, u16 val) 607 { 608 __be16 *mii_val; 609 u8 mii_data[3]; 610 int ret; 611 612 ret = xgbe_phy_sfp_get_mux(pdata); 613 if (ret) 614 return ret; 615 616 mii_data[0] = reg & 0xff; 617 mii_val = (__be16 *)&mii_data[1]; 618 *mii_val = cpu_to_be16(val); 619 620 ret = xgbe_phy_i2c_write(pdata, XGBE_SFP_PHY_ADDRESS, 621 mii_data, sizeof(mii_data)); 622 623 xgbe_phy_sfp_put_mux(pdata); 624 625 return ret; 626 } 627 628 static int xgbe_phy_mii_write(struct mii_bus *mii, int addr, int reg, u16 val) 629 { 630 struct xgbe_prv_data *pdata = mii->priv; 631 struct xgbe_phy_data *phy_data = pdata->phy_data; 632 int ret; 633 634 ret = xgbe_phy_get_comm_ownership(pdata); 635 if (ret) 636 return ret; 637 638 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP) 639 ret = xgbe_phy_i2c_mii_write(pdata, reg, val); 640 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO) 641 ret = xgbe_phy_mdio_mii_write(pdata, addr, reg, val); 642 else 643 ret = -ENOTSUPP; 644 645 xgbe_phy_put_comm_ownership(pdata); 646 647 return ret; 648 } 649 650 static int xgbe_phy_mdio_mii_read(struct xgbe_prv_data *pdata, int addr, 651 int reg) 652 { 653 struct xgbe_phy_data *phy_data = pdata->phy_data; 654 655 if (reg & MII_ADDR_C45) { 656 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45) 657 return -ENOTSUPP; 658 } else { 659 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22) 660 return -ENOTSUPP; 661 } 662 663 return pdata->hw_if.read_ext_mii_regs(pdata, addr, reg); 664 } 665 666 static int xgbe_phy_i2c_mii_read(struct xgbe_prv_data *pdata, int reg) 667 { 668 __be16 mii_val; 669 u8 mii_reg; 670 int ret; 671 672 ret = xgbe_phy_sfp_get_mux(pdata); 673 if (ret) 674 return ret; 675 676 mii_reg = reg; 677 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_PHY_ADDRESS, 678 &mii_reg, sizeof(mii_reg), 679 &mii_val, sizeof(mii_val)); 680 if (!ret) 681 ret = be16_to_cpu(mii_val); 682 683 xgbe_phy_sfp_put_mux(pdata); 684 685 return ret; 686 } 687 688 static int xgbe_phy_mii_read(struct mii_bus *mii, int addr, int reg) 689 { 690 struct xgbe_prv_data *pdata = mii->priv; 691 struct xgbe_phy_data *phy_data = pdata->phy_data; 692 int ret; 693 694 ret = xgbe_phy_get_comm_ownership(pdata); 695 if (ret) 696 return ret; 697 698 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP) 699 ret = xgbe_phy_i2c_mii_read(pdata, reg); 700 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO) 701 ret = xgbe_phy_mdio_mii_read(pdata, addr, reg); 702 else 703 ret = -ENOTSUPP; 704 705 xgbe_phy_put_comm_ownership(pdata); 706 707 return ret; 708 } 709 710 static void xgbe_phy_sfp_phy_settings(struct xgbe_prv_data *pdata) 711 { 712 struct xgbe_phy_data *phy_data = pdata->phy_data; 713 714 if (phy_data->sfp_mod_absent) { 715 pdata->phy.speed = SPEED_UNKNOWN; 716 pdata->phy.duplex = DUPLEX_UNKNOWN; 717 pdata->phy.autoneg = AUTONEG_ENABLE; 718 pdata->phy.advertising = pdata->phy.supported; 719 720 return; 721 } 722 723 pdata->phy.advertising &= ~ADVERTISED_Autoneg; 724 pdata->phy.advertising &= ~ADVERTISED_TP; 725 pdata->phy.advertising &= ~ADVERTISED_FIBRE; 726 pdata->phy.advertising &= ~ADVERTISED_100baseT_Full; 727 pdata->phy.advertising &= ~ADVERTISED_1000baseT_Full; 728 pdata->phy.advertising &= ~ADVERTISED_10000baseT_Full; 729 pdata->phy.advertising &= ~ADVERTISED_10000baseR_FEC; 730 731 switch (phy_data->sfp_base) { 732 case XGBE_SFP_BASE_1000_T: 733 case XGBE_SFP_BASE_1000_SX: 734 case XGBE_SFP_BASE_1000_LX: 735 case XGBE_SFP_BASE_1000_CX: 736 pdata->phy.speed = SPEED_UNKNOWN; 737 pdata->phy.duplex = DUPLEX_UNKNOWN; 738 pdata->phy.autoneg = AUTONEG_ENABLE; 739 pdata->phy.advertising |= ADVERTISED_Autoneg; 740 break; 741 case XGBE_SFP_BASE_10000_SR: 742 case XGBE_SFP_BASE_10000_LR: 743 case XGBE_SFP_BASE_10000_LRM: 744 case XGBE_SFP_BASE_10000_ER: 745 case XGBE_SFP_BASE_10000_CR: 746 default: 747 pdata->phy.speed = SPEED_10000; 748 pdata->phy.duplex = DUPLEX_FULL; 749 pdata->phy.autoneg = AUTONEG_DISABLE; 750 break; 751 } 752 753 switch (phy_data->sfp_base) { 754 case XGBE_SFP_BASE_1000_T: 755 case XGBE_SFP_BASE_1000_CX: 756 case XGBE_SFP_BASE_10000_CR: 757 pdata->phy.advertising |= ADVERTISED_TP; 758 break; 759 default: 760 pdata->phy.advertising |= ADVERTISED_FIBRE; 761 } 762 763 switch (phy_data->sfp_speed) { 764 case XGBE_SFP_SPEED_100_1000: 765 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) 766 pdata->phy.advertising |= ADVERTISED_100baseT_Full; 767 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) 768 pdata->phy.advertising |= ADVERTISED_1000baseT_Full; 769 break; 770 case XGBE_SFP_SPEED_1000: 771 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) 772 pdata->phy.advertising |= ADVERTISED_1000baseT_Full; 773 break; 774 case XGBE_SFP_SPEED_10000: 775 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) 776 pdata->phy.advertising |= ADVERTISED_10000baseT_Full; 777 break; 778 default: 779 /* Choose the fastest supported speed */ 780 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) 781 pdata->phy.advertising |= ADVERTISED_10000baseT_Full; 782 else if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) 783 pdata->phy.advertising |= ADVERTISED_1000baseT_Full; 784 else if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) 785 pdata->phy.advertising |= ADVERTISED_100baseT_Full; 786 } 787 } 788 789 static bool xgbe_phy_sfp_bit_rate(struct xgbe_sfp_eeprom *sfp_eeprom, 790 enum xgbe_sfp_speed sfp_speed) 791 { 792 u8 *sfp_base, min, max; 793 794 sfp_base = sfp_eeprom->base; 795 796 switch (sfp_speed) { 797 case XGBE_SFP_SPEED_1000: 798 min = XGBE_SFP_BASE_BR_1GBE_MIN; 799 max = XGBE_SFP_BASE_BR_1GBE_MAX; 800 break; 801 case XGBE_SFP_SPEED_10000: 802 min = XGBE_SFP_BASE_BR_10GBE_MIN; 803 max = XGBE_SFP_BASE_BR_10GBE_MAX; 804 break; 805 default: 806 return false; 807 } 808 809 return ((sfp_base[XGBE_SFP_BASE_BR] >= min) && 810 (sfp_base[XGBE_SFP_BASE_BR] <= max)); 811 } 812 813 static void xgbe_phy_free_phy_device(struct xgbe_prv_data *pdata) 814 { 815 struct xgbe_phy_data *phy_data = pdata->phy_data; 816 817 if (phy_data->phydev) { 818 phy_detach(phy_data->phydev); 819 phy_device_remove(phy_data->phydev); 820 phy_device_free(phy_data->phydev); 821 phy_data->phydev = NULL; 822 } 823 } 824 825 static bool xgbe_phy_finisar_phy_quirks(struct xgbe_prv_data *pdata) 826 { 827 struct xgbe_phy_data *phy_data = pdata->phy_data; 828 unsigned int phy_id = phy_data->phydev->phy_id; 829 830 if ((phy_id & 0xfffffff0) != 0x01ff0cc0) 831 return false; 832 833 /* Enable Base-T AN */ 834 phy_write(phy_data->phydev, 0x16, 0x0001); 835 phy_write(phy_data->phydev, 0x00, 0x9140); 836 phy_write(phy_data->phydev, 0x16, 0x0000); 837 838 /* Enable SGMII at 100Base-T/1000Base-T Full Duplex */ 839 phy_write(phy_data->phydev, 0x1b, 0x9084); 840 phy_write(phy_data->phydev, 0x09, 0x0e00); 841 phy_write(phy_data->phydev, 0x00, 0x8140); 842 phy_write(phy_data->phydev, 0x04, 0x0d01); 843 phy_write(phy_data->phydev, 0x00, 0x9140); 844 845 phy_data->phydev->supported = PHY_GBIT_FEATURES; 846 phy_data->phydev->supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 847 phy_data->phydev->advertising = phy_data->phydev->supported; 848 849 netif_dbg(pdata, drv, pdata->netdev, 850 "Finisar PHY quirk in place\n"); 851 852 return true; 853 } 854 855 static void xgbe_phy_external_phy_quirks(struct xgbe_prv_data *pdata) 856 { 857 if (xgbe_phy_finisar_phy_quirks(pdata)) 858 return; 859 } 860 861 static int xgbe_phy_find_phy_device(struct xgbe_prv_data *pdata) 862 { 863 struct xgbe_phy_data *phy_data = pdata->phy_data; 864 struct phy_device *phydev; 865 int ret; 866 867 /* If we already have a PHY, just return */ 868 if (phy_data->phydev) 869 return 0; 870 871 /* Check for the use of an external PHY */ 872 if (phy_data->phydev_mode == XGBE_MDIO_MODE_NONE) 873 return 0; 874 875 /* For SFP, only use an external PHY if available */ 876 if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) && 877 !phy_data->sfp_phy_avail) 878 return 0; 879 880 /* Set the proper MDIO mode for the PHY */ 881 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr, 882 phy_data->phydev_mode); 883 if (ret) { 884 netdev_err(pdata->netdev, 885 "mdio port/clause not compatible (%u/%u)\n", 886 phy_data->mdio_addr, phy_data->phydev_mode); 887 return ret; 888 } 889 890 /* Create and connect to the PHY device */ 891 phydev = get_phy_device(phy_data->mii, phy_data->mdio_addr, 892 (phy_data->phydev_mode == XGBE_MDIO_MODE_CL45)); 893 if (IS_ERR(phydev)) { 894 netdev_err(pdata->netdev, "get_phy_device failed\n"); 895 return -ENODEV; 896 } 897 netif_dbg(pdata, drv, pdata->netdev, "external PHY id is %#010x\n", 898 phydev->phy_id); 899 900 /*TODO: If c45, add request_module based on one of the MMD ids? */ 901 902 ret = phy_device_register(phydev); 903 if (ret) { 904 netdev_err(pdata->netdev, "phy_device_register failed\n"); 905 phy_device_free(phydev); 906 return ret; 907 } 908 909 ret = phy_attach_direct(pdata->netdev, phydev, phydev->dev_flags, 910 PHY_INTERFACE_MODE_SGMII); 911 if (ret) { 912 netdev_err(pdata->netdev, "phy_attach_direct failed\n"); 913 phy_device_remove(phydev); 914 phy_device_free(phydev); 915 return ret; 916 } 917 phy_data->phydev = phydev; 918 919 xgbe_phy_external_phy_quirks(pdata); 920 phydev->advertising &= pdata->phy.advertising; 921 922 phy_start_aneg(phy_data->phydev); 923 924 return 0; 925 } 926 927 static void xgbe_phy_sfp_external_phy(struct xgbe_prv_data *pdata) 928 { 929 struct xgbe_phy_data *phy_data = pdata->phy_data; 930 int ret; 931 932 if (!phy_data->sfp_changed) 933 return; 934 935 phy_data->sfp_phy_avail = 0; 936 937 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T) 938 return; 939 940 /* Check access to the PHY by reading CTRL1 */ 941 ret = xgbe_phy_i2c_mii_read(pdata, MII_BMCR); 942 if (ret < 0) 943 return; 944 945 /* Successfully accessed the PHY */ 946 phy_data->sfp_phy_avail = 1; 947 } 948 949 static bool xgbe_phy_belfuse_parse_quirks(struct xgbe_prv_data *pdata) 950 { 951 struct xgbe_phy_data *phy_data = pdata->phy_data; 952 struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom; 953 954 if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME], 955 XGBE_BEL_FUSE_VENDOR, XGBE_SFP_BASE_VENDOR_NAME_LEN)) 956 return false; 957 958 if (!memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN], 959 XGBE_BEL_FUSE_PARTNO, XGBE_SFP_BASE_VENDOR_PN_LEN)) { 960 phy_data->sfp_base = XGBE_SFP_BASE_1000_SX; 961 phy_data->sfp_cable = XGBE_SFP_CABLE_ACTIVE; 962 phy_data->sfp_speed = XGBE_SFP_SPEED_1000; 963 if (phy_data->sfp_changed) 964 netif_dbg(pdata, drv, pdata->netdev, 965 "Bel-Fuse SFP quirk in place\n"); 966 return true; 967 } 968 969 return false; 970 } 971 972 static bool xgbe_phy_sfp_parse_quirks(struct xgbe_prv_data *pdata) 973 { 974 if (xgbe_phy_belfuse_parse_quirks(pdata)) 975 return true; 976 977 return false; 978 } 979 980 static void xgbe_phy_sfp_parse_eeprom(struct xgbe_prv_data *pdata) 981 { 982 struct xgbe_phy_data *phy_data = pdata->phy_data; 983 struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom; 984 u8 *sfp_base; 985 986 sfp_base = sfp_eeprom->base; 987 988 if (sfp_base[XGBE_SFP_BASE_ID] != XGBE_SFP_ID_SFP) 989 return; 990 991 if (sfp_base[XGBE_SFP_BASE_EXT_ID] != XGBE_SFP_EXT_ID_SFP) 992 return; 993 994 if (xgbe_phy_sfp_parse_quirks(pdata)) 995 return; 996 997 /* Assume ACTIVE cable unless told it is PASSIVE */ 998 if (sfp_base[XGBE_SFP_BASE_CABLE] & XGBE_SFP_BASE_CABLE_PASSIVE) { 999 phy_data->sfp_cable = XGBE_SFP_CABLE_PASSIVE; 1000 phy_data->sfp_cable_len = sfp_base[XGBE_SFP_BASE_CU_CABLE_LEN]; 1001 } else { 1002 phy_data->sfp_cable = XGBE_SFP_CABLE_ACTIVE; 1003 } 1004 1005 /* Determine the type of SFP */ 1006 if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_SR) 1007 phy_data->sfp_base = XGBE_SFP_BASE_10000_SR; 1008 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LR) 1009 phy_data->sfp_base = XGBE_SFP_BASE_10000_LR; 1010 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LRM) 1011 phy_data->sfp_base = XGBE_SFP_BASE_10000_LRM; 1012 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_ER) 1013 phy_data->sfp_base = XGBE_SFP_BASE_10000_ER; 1014 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_SX) 1015 phy_data->sfp_base = XGBE_SFP_BASE_1000_SX; 1016 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_LX) 1017 phy_data->sfp_base = XGBE_SFP_BASE_1000_LX; 1018 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_CX) 1019 phy_data->sfp_base = XGBE_SFP_BASE_1000_CX; 1020 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_T) 1021 phy_data->sfp_base = XGBE_SFP_BASE_1000_T; 1022 else if ((phy_data->sfp_cable == XGBE_SFP_CABLE_PASSIVE) && 1023 xgbe_phy_sfp_bit_rate(sfp_eeprom, XGBE_SFP_SPEED_10000)) 1024 phy_data->sfp_base = XGBE_SFP_BASE_10000_CR; 1025 1026 switch (phy_data->sfp_base) { 1027 case XGBE_SFP_BASE_1000_T: 1028 phy_data->sfp_speed = XGBE_SFP_SPEED_100_1000; 1029 break; 1030 case XGBE_SFP_BASE_1000_SX: 1031 case XGBE_SFP_BASE_1000_LX: 1032 case XGBE_SFP_BASE_1000_CX: 1033 phy_data->sfp_speed = XGBE_SFP_SPEED_1000; 1034 break; 1035 case XGBE_SFP_BASE_10000_SR: 1036 case XGBE_SFP_BASE_10000_LR: 1037 case XGBE_SFP_BASE_10000_LRM: 1038 case XGBE_SFP_BASE_10000_ER: 1039 case XGBE_SFP_BASE_10000_CR: 1040 phy_data->sfp_speed = XGBE_SFP_SPEED_10000; 1041 break; 1042 default: 1043 break; 1044 } 1045 } 1046 1047 static void xgbe_phy_sfp_eeprom_info(struct xgbe_prv_data *pdata, 1048 struct xgbe_sfp_eeprom *sfp_eeprom) 1049 { 1050 struct xgbe_sfp_ascii sfp_ascii; 1051 char *sfp_data = (char *)&sfp_ascii; 1052 1053 netif_dbg(pdata, drv, pdata->netdev, "SFP detected:\n"); 1054 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME], 1055 XGBE_SFP_BASE_VENDOR_NAME_LEN); 1056 sfp_data[XGBE_SFP_BASE_VENDOR_NAME_LEN] = '\0'; 1057 netif_dbg(pdata, drv, pdata->netdev, " vendor: %s\n", 1058 sfp_data); 1059 1060 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN], 1061 XGBE_SFP_BASE_VENDOR_PN_LEN); 1062 sfp_data[XGBE_SFP_BASE_VENDOR_PN_LEN] = '\0'; 1063 netif_dbg(pdata, drv, pdata->netdev, " part number: %s\n", 1064 sfp_data); 1065 1066 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_REV], 1067 XGBE_SFP_BASE_VENDOR_REV_LEN); 1068 sfp_data[XGBE_SFP_BASE_VENDOR_REV_LEN] = '\0'; 1069 netif_dbg(pdata, drv, pdata->netdev, " revision level: %s\n", 1070 sfp_data); 1071 1072 memcpy(sfp_data, &sfp_eeprom->extd[XGBE_SFP_BASE_VENDOR_SN], 1073 XGBE_SFP_BASE_VENDOR_SN_LEN); 1074 sfp_data[XGBE_SFP_BASE_VENDOR_SN_LEN] = '\0'; 1075 netif_dbg(pdata, drv, pdata->netdev, " serial number: %s\n", 1076 sfp_data); 1077 } 1078 1079 static bool xgbe_phy_sfp_verify_eeprom(u8 cc_in, u8 *buf, unsigned int len) 1080 { 1081 u8 cc; 1082 1083 for (cc = 0; len; buf++, len--) 1084 cc += *buf; 1085 1086 return (cc == cc_in) ? true : false; 1087 } 1088 1089 static int xgbe_phy_sfp_read_eeprom(struct xgbe_prv_data *pdata) 1090 { 1091 struct xgbe_phy_data *phy_data = pdata->phy_data; 1092 struct xgbe_sfp_eeprom sfp_eeprom; 1093 u8 eeprom_addr; 1094 int ret; 1095 1096 ret = xgbe_phy_sfp_get_mux(pdata); 1097 if (ret) { 1098 netdev_err(pdata->netdev, "I2C error setting SFP MUX\n"); 1099 return ret; 1100 } 1101 1102 /* Read the SFP serial ID eeprom */ 1103 eeprom_addr = 0; 1104 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_SERIAL_ID_ADDRESS, 1105 &eeprom_addr, sizeof(eeprom_addr), 1106 &sfp_eeprom, sizeof(sfp_eeprom)); 1107 if (ret) { 1108 netdev_err(pdata->netdev, "I2C error reading SFP EEPROM\n"); 1109 goto put; 1110 } 1111 1112 /* Validate the contents read */ 1113 if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.base[XGBE_SFP_BASE_CC], 1114 sfp_eeprom.base, 1115 sizeof(sfp_eeprom.base) - 1)) { 1116 ret = -EINVAL; 1117 goto put; 1118 } 1119 1120 if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.extd[XGBE_SFP_EXTD_CC], 1121 sfp_eeprom.extd, 1122 sizeof(sfp_eeprom.extd) - 1)) { 1123 ret = -EINVAL; 1124 goto put; 1125 } 1126 1127 /* Check for an added or changed SFP */ 1128 if (memcmp(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom))) { 1129 phy_data->sfp_changed = 1; 1130 1131 if (netif_msg_drv(pdata)) 1132 xgbe_phy_sfp_eeprom_info(pdata, &sfp_eeprom); 1133 1134 memcpy(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom)); 1135 1136 if (sfp_eeprom.extd[XGBE_SFP_EXTD_SFF_8472]) { 1137 u8 diag_type = sfp_eeprom.extd[XGBE_SFP_EXTD_DIAG]; 1138 1139 if (!(diag_type & XGBE_SFP_EXTD_DIAG_ADDR_CHANGE)) 1140 phy_data->sfp_diags = 1; 1141 } 1142 1143 xgbe_phy_free_phy_device(pdata); 1144 } else { 1145 phy_data->sfp_changed = 0; 1146 } 1147 1148 put: 1149 xgbe_phy_sfp_put_mux(pdata); 1150 1151 return ret; 1152 } 1153 1154 static void xgbe_phy_sfp_signals(struct xgbe_prv_data *pdata) 1155 { 1156 struct xgbe_phy_data *phy_data = pdata->phy_data; 1157 unsigned int gpio_input; 1158 u8 gpio_reg, gpio_ports[2]; 1159 int ret; 1160 1161 /* Read the input port registers */ 1162 gpio_reg = 0; 1163 ret = xgbe_phy_i2c_read(pdata, phy_data->sfp_gpio_address, 1164 &gpio_reg, sizeof(gpio_reg), 1165 gpio_ports, sizeof(gpio_ports)); 1166 if (ret) { 1167 netdev_err(pdata->netdev, "I2C error reading SFP GPIOs\n"); 1168 return; 1169 } 1170 1171 gpio_input = (gpio_ports[1] << 8) | gpio_ports[0]; 1172 1173 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_MOD_ABSENT) { 1174 /* No GPIO, just assume the module is present for now */ 1175 phy_data->sfp_mod_absent = 0; 1176 } else { 1177 if (!(gpio_input & (1 << phy_data->sfp_gpio_mod_absent))) 1178 phy_data->sfp_mod_absent = 0; 1179 } 1180 1181 if (!(phy_data->sfp_gpio_mask & XGBE_GPIO_NO_RX_LOS) && 1182 (gpio_input & (1 << phy_data->sfp_gpio_rx_los))) 1183 phy_data->sfp_rx_los = 1; 1184 1185 if (!(phy_data->sfp_gpio_mask & XGBE_GPIO_NO_TX_FAULT) && 1186 (gpio_input & (1 << phy_data->sfp_gpio_tx_fault))) 1187 phy_data->sfp_tx_fault = 1; 1188 } 1189 1190 static void xgbe_phy_sfp_mod_absent(struct xgbe_prv_data *pdata) 1191 { 1192 struct xgbe_phy_data *phy_data = pdata->phy_data; 1193 1194 xgbe_phy_free_phy_device(pdata); 1195 1196 phy_data->sfp_mod_absent = 1; 1197 phy_data->sfp_phy_avail = 0; 1198 memset(&phy_data->sfp_eeprom, 0, sizeof(phy_data->sfp_eeprom)); 1199 } 1200 1201 static void xgbe_phy_sfp_reset(struct xgbe_phy_data *phy_data) 1202 { 1203 phy_data->sfp_rx_los = 0; 1204 phy_data->sfp_tx_fault = 0; 1205 phy_data->sfp_mod_absent = 1; 1206 phy_data->sfp_diags = 0; 1207 phy_data->sfp_base = XGBE_SFP_BASE_UNKNOWN; 1208 phy_data->sfp_cable = XGBE_SFP_CABLE_UNKNOWN; 1209 phy_data->sfp_speed = XGBE_SFP_SPEED_UNKNOWN; 1210 } 1211 1212 static void xgbe_phy_sfp_detect(struct xgbe_prv_data *pdata) 1213 { 1214 struct xgbe_phy_data *phy_data = pdata->phy_data; 1215 int ret; 1216 1217 /* Reset the SFP signals and info */ 1218 xgbe_phy_sfp_reset(phy_data); 1219 1220 ret = xgbe_phy_get_comm_ownership(pdata); 1221 if (ret) 1222 return; 1223 1224 /* Read the SFP signals and check for module presence */ 1225 xgbe_phy_sfp_signals(pdata); 1226 if (phy_data->sfp_mod_absent) { 1227 xgbe_phy_sfp_mod_absent(pdata); 1228 goto put; 1229 } 1230 1231 ret = xgbe_phy_sfp_read_eeprom(pdata); 1232 if (ret) { 1233 /* Treat any error as if there isn't an SFP plugged in */ 1234 xgbe_phy_sfp_reset(phy_data); 1235 xgbe_phy_sfp_mod_absent(pdata); 1236 goto put; 1237 } 1238 1239 xgbe_phy_sfp_parse_eeprom(pdata); 1240 1241 xgbe_phy_sfp_external_phy(pdata); 1242 1243 put: 1244 xgbe_phy_sfp_phy_settings(pdata); 1245 1246 xgbe_phy_put_comm_ownership(pdata); 1247 } 1248 1249 static void xgbe_phy_phydev_flowctrl(struct xgbe_prv_data *pdata) 1250 { 1251 struct xgbe_phy_data *phy_data = pdata->phy_data; 1252 u16 lcl_adv = 0, rmt_adv = 0; 1253 u8 fc; 1254 1255 pdata->phy.tx_pause = 0; 1256 pdata->phy.rx_pause = 0; 1257 1258 if (!phy_data->phydev) 1259 return; 1260 1261 if (phy_data->phydev->advertising & ADVERTISED_Pause) 1262 lcl_adv |= ADVERTISE_PAUSE_CAP; 1263 if (phy_data->phydev->advertising & ADVERTISED_Asym_Pause) 1264 lcl_adv |= ADVERTISE_PAUSE_ASYM; 1265 1266 if (phy_data->phydev->pause) { 1267 pdata->phy.lp_advertising |= ADVERTISED_Pause; 1268 rmt_adv |= LPA_PAUSE_CAP; 1269 } 1270 if (phy_data->phydev->asym_pause) { 1271 pdata->phy.lp_advertising |= ADVERTISED_Asym_Pause; 1272 rmt_adv |= LPA_PAUSE_ASYM; 1273 } 1274 1275 fc = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv); 1276 if (fc & FLOW_CTRL_TX) 1277 pdata->phy.tx_pause = 1; 1278 if (fc & FLOW_CTRL_RX) 1279 pdata->phy.rx_pause = 1; 1280 } 1281 1282 static enum xgbe_mode xgbe_phy_an37_sgmii_outcome(struct xgbe_prv_data *pdata) 1283 { 1284 enum xgbe_mode mode; 1285 1286 pdata->phy.lp_advertising |= ADVERTISED_Autoneg; 1287 pdata->phy.lp_advertising |= ADVERTISED_TP; 1288 1289 /* Use external PHY to determine flow control */ 1290 if (pdata->phy.pause_autoneg) 1291 xgbe_phy_phydev_flowctrl(pdata); 1292 1293 switch (pdata->an_status & XGBE_SGMII_AN_LINK_SPEED) { 1294 case XGBE_SGMII_AN_LINK_SPEED_100: 1295 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) { 1296 pdata->phy.lp_advertising |= ADVERTISED_100baseT_Full; 1297 mode = XGBE_MODE_SGMII_100; 1298 } else { 1299 /* Half-duplex not supported */ 1300 pdata->phy.lp_advertising |= ADVERTISED_100baseT_Half; 1301 mode = XGBE_MODE_UNKNOWN; 1302 } 1303 break; 1304 case XGBE_SGMII_AN_LINK_SPEED_1000: 1305 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) { 1306 pdata->phy.lp_advertising |= ADVERTISED_1000baseT_Full; 1307 mode = XGBE_MODE_SGMII_1000; 1308 } else { 1309 /* Half-duplex not supported */ 1310 pdata->phy.lp_advertising |= ADVERTISED_1000baseT_Half; 1311 mode = XGBE_MODE_UNKNOWN; 1312 } 1313 break; 1314 default: 1315 mode = XGBE_MODE_UNKNOWN; 1316 } 1317 1318 return mode; 1319 } 1320 1321 static enum xgbe_mode xgbe_phy_an37_outcome(struct xgbe_prv_data *pdata) 1322 { 1323 enum xgbe_mode mode; 1324 unsigned int ad_reg, lp_reg; 1325 1326 pdata->phy.lp_advertising |= ADVERTISED_Autoneg; 1327 pdata->phy.lp_advertising |= ADVERTISED_FIBRE; 1328 1329 /* Compare Advertisement and Link Partner register */ 1330 ad_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE); 1331 lp_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_LP_ABILITY); 1332 if (lp_reg & 0x100) 1333 pdata->phy.lp_advertising |= ADVERTISED_Pause; 1334 if (lp_reg & 0x80) 1335 pdata->phy.lp_advertising |= ADVERTISED_Asym_Pause; 1336 1337 if (pdata->phy.pause_autoneg) { 1338 /* Set flow control based on auto-negotiation result */ 1339 pdata->phy.tx_pause = 0; 1340 pdata->phy.rx_pause = 0; 1341 1342 if (ad_reg & lp_reg & 0x100) { 1343 pdata->phy.tx_pause = 1; 1344 pdata->phy.rx_pause = 1; 1345 } else if (ad_reg & lp_reg & 0x80) { 1346 if (ad_reg & 0x100) 1347 pdata->phy.rx_pause = 1; 1348 else if (lp_reg & 0x100) 1349 pdata->phy.tx_pause = 1; 1350 } 1351 } 1352 1353 if (lp_reg & 0x40) 1354 pdata->phy.lp_advertising |= ADVERTISED_1000baseT_Half; 1355 if (lp_reg & 0x20) 1356 pdata->phy.lp_advertising |= ADVERTISED_1000baseT_Full; 1357 1358 /* Half duplex is not supported */ 1359 ad_reg &= lp_reg; 1360 mode = (ad_reg & 0x20) ? XGBE_MODE_X : XGBE_MODE_UNKNOWN; 1361 1362 return mode; 1363 } 1364 1365 static enum xgbe_mode xgbe_phy_an73_redrv_outcome(struct xgbe_prv_data *pdata) 1366 { 1367 struct xgbe_phy_data *phy_data = pdata->phy_data; 1368 enum xgbe_mode mode; 1369 unsigned int ad_reg, lp_reg; 1370 1371 pdata->phy.lp_advertising |= ADVERTISED_Autoneg; 1372 pdata->phy.lp_advertising |= ADVERTISED_Backplane; 1373 1374 /* Use external PHY to determine flow control */ 1375 if (pdata->phy.pause_autoneg) 1376 xgbe_phy_phydev_flowctrl(pdata); 1377 1378 /* Compare Advertisement and Link Partner register 2 */ 1379 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); 1380 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); 1381 if (lp_reg & 0x80) 1382 pdata->phy.lp_advertising |= ADVERTISED_10000baseKR_Full; 1383 if (lp_reg & 0x20) 1384 pdata->phy.lp_advertising |= ADVERTISED_1000baseKX_Full; 1385 1386 ad_reg &= lp_reg; 1387 if (ad_reg & 0x80) { 1388 switch (phy_data->port_mode) { 1389 case XGBE_PORT_MODE_BACKPLANE: 1390 mode = XGBE_MODE_KR; 1391 break; 1392 default: 1393 mode = XGBE_MODE_SFI; 1394 break; 1395 } 1396 } else if (ad_reg & 0x20) { 1397 switch (phy_data->port_mode) { 1398 case XGBE_PORT_MODE_BACKPLANE: 1399 mode = XGBE_MODE_KX_1000; 1400 break; 1401 case XGBE_PORT_MODE_1000BASE_X: 1402 mode = XGBE_MODE_X; 1403 break; 1404 case XGBE_PORT_MODE_SFP: 1405 switch (phy_data->sfp_base) { 1406 case XGBE_SFP_BASE_1000_T: 1407 if (phy_data->phydev && 1408 (phy_data->phydev->speed == SPEED_100)) 1409 mode = XGBE_MODE_SGMII_100; 1410 else 1411 mode = XGBE_MODE_SGMII_1000; 1412 break; 1413 case XGBE_SFP_BASE_1000_SX: 1414 case XGBE_SFP_BASE_1000_LX: 1415 case XGBE_SFP_BASE_1000_CX: 1416 default: 1417 mode = XGBE_MODE_X; 1418 break; 1419 } 1420 break; 1421 default: 1422 if (phy_data->phydev && 1423 (phy_data->phydev->speed == SPEED_100)) 1424 mode = XGBE_MODE_SGMII_100; 1425 else 1426 mode = XGBE_MODE_SGMII_1000; 1427 break; 1428 } 1429 } else { 1430 mode = XGBE_MODE_UNKNOWN; 1431 } 1432 1433 /* Compare Advertisement and Link Partner register 3 */ 1434 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); 1435 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); 1436 if (lp_reg & 0xc000) 1437 pdata->phy.lp_advertising |= ADVERTISED_10000baseR_FEC; 1438 1439 return mode; 1440 } 1441 1442 static enum xgbe_mode xgbe_phy_an73_outcome(struct xgbe_prv_data *pdata) 1443 { 1444 enum xgbe_mode mode; 1445 unsigned int ad_reg, lp_reg; 1446 1447 pdata->phy.lp_advertising |= ADVERTISED_Autoneg; 1448 pdata->phy.lp_advertising |= ADVERTISED_Backplane; 1449 1450 /* Compare Advertisement and Link Partner register 1 */ 1451 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE); 1452 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA); 1453 if (lp_reg & 0x400) 1454 pdata->phy.lp_advertising |= ADVERTISED_Pause; 1455 if (lp_reg & 0x800) 1456 pdata->phy.lp_advertising |= ADVERTISED_Asym_Pause; 1457 1458 if (pdata->phy.pause_autoneg) { 1459 /* Set flow control based on auto-negotiation result */ 1460 pdata->phy.tx_pause = 0; 1461 pdata->phy.rx_pause = 0; 1462 1463 if (ad_reg & lp_reg & 0x400) { 1464 pdata->phy.tx_pause = 1; 1465 pdata->phy.rx_pause = 1; 1466 } else if (ad_reg & lp_reg & 0x800) { 1467 if (ad_reg & 0x400) 1468 pdata->phy.rx_pause = 1; 1469 else if (lp_reg & 0x400) 1470 pdata->phy.tx_pause = 1; 1471 } 1472 } 1473 1474 /* Compare Advertisement and Link Partner register 2 */ 1475 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); 1476 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); 1477 if (lp_reg & 0x80) 1478 pdata->phy.lp_advertising |= ADVERTISED_10000baseKR_Full; 1479 if (lp_reg & 0x20) 1480 pdata->phy.lp_advertising |= ADVERTISED_1000baseKX_Full; 1481 1482 ad_reg &= lp_reg; 1483 if (ad_reg & 0x80) 1484 mode = XGBE_MODE_KR; 1485 else if (ad_reg & 0x20) 1486 mode = XGBE_MODE_KX_1000; 1487 else 1488 mode = XGBE_MODE_UNKNOWN; 1489 1490 /* Compare Advertisement and Link Partner register 3 */ 1491 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); 1492 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); 1493 if (lp_reg & 0xc000) 1494 pdata->phy.lp_advertising |= ADVERTISED_10000baseR_FEC; 1495 1496 return mode; 1497 } 1498 1499 static enum xgbe_mode xgbe_phy_an_outcome(struct xgbe_prv_data *pdata) 1500 { 1501 switch (pdata->an_mode) { 1502 case XGBE_AN_MODE_CL73: 1503 return xgbe_phy_an73_outcome(pdata); 1504 case XGBE_AN_MODE_CL73_REDRV: 1505 return xgbe_phy_an73_redrv_outcome(pdata); 1506 case XGBE_AN_MODE_CL37: 1507 return xgbe_phy_an37_outcome(pdata); 1508 case XGBE_AN_MODE_CL37_SGMII: 1509 return xgbe_phy_an37_sgmii_outcome(pdata); 1510 default: 1511 return XGBE_MODE_UNKNOWN; 1512 } 1513 } 1514 1515 static unsigned int xgbe_phy_an_advertising(struct xgbe_prv_data *pdata) 1516 { 1517 struct xgbe_phy_data *phy_data = pdata->phy_data; 1518 unsigned int advertising; 1519 1520 /* Without a re-driver, just return current advertising */ 1521 if (!phy_data->redrv) 1522 return pdata->phy.advertising; 1523 1524 /* With the KR re-driver we need to advertise a single speed */ 1525 advertising = pdata->phy.advertising; 1526 advertising &= ~ADVERTISED_1000baseKX_Full; 1527 advertising &= ~ADVERTISED_10000baseKR_Full; 1528 1529 switch (phy_data->port_mode) { 1530 case XGBE_PORT_MODE_BACKPLANE: 1531 advertising |= ADVERTISED_10000baseKR_Full; 1532 break; 1533 case XGBE_PORT_MODE_BACKPLANE_2500: 1534 advertising |= ADVERTISED_1000baseKX_Full; 1535 break; 1536 case XGBE_PORT_MODE_1000BASE_T: 1537 case XGBE_PORT_MODE_1000BASE_X: 1538 case XGBE_PORT_MODE_NBASE_T: 1539 advertising |= ADVERTISED_1000baseKX_Full; 1540 break; 1541 case XGBE_PORT_MODE_10GBASE_T: 1542 if (phy_data->phydev && 1543 (phy_data->phydev->speed == SPEED_10000)) 1544 advertising |= ADVERTISED_10000baseKR_Full; 1545 else 1546 advertising |= ADVERTISED_1000baseKX_Full; 1547 break; 1548 case XGBE_PORT_MODE_10GBASE_R: 1549 advertising |= ADVERTISED_10000baseKR_Full; 1550 break; 1551 case XGBE_PORT_MODE_SFP: 1552 switch (phy_data->sfp_base) { 1553 case XGBE_SFP_BASE_1000_T: 1554 case XGBE_SFP_BASE_1000_SX: 1555 case XGBE_SFP_BASE_1000_LX: 1556 case XGBE_SFP_BASE_1000_CX: 1557 advertising |= ADVERTISED_1000baseKX_Full; 1558 break; 1559 default: 1560 advertising |= ADVERTISED_10000baseKR_Full; 1561 break; 1562 } 1563 break; 1564 default: 1565 advertising |= ADVERTISED_10000baseKR_Full; 1566 break; 1567 } 1568 1569 return advertising; 1570 } 1571 1572 static int xgbe_phy_an_config(struct xgbe_prv_data *pdata) 1573 { 1574 struct xgbe_phy_data *phy_data = pdata->phy_data; 1575 int ret; 1576 1577 ret = xgbe_phy_find_phy_device(pdata); 1578 if (ret) 1579 return ret; 1580 1581 if (!phy_data->phydev) 1582 return 0; 1583 1584 phy_data->phydev->autoneg = pdata->phy.autoneg; 1585 phy_data->phydev->advertising = phy_data->phydev->supported & 1586 pdata->phy.advertising; 1587 1588 if (pdata->phy.autoneg != AUTONEG_ENABLE) { 1589 phy_data->phydev->speed = pdata->phy.speed; 1590 phy_data->phydev->duplex = pdata->phy.duplex; 1591 } 1592 1593 ret = phy_start_aneg(phy_data->phydev); 1594 1595 return ret; 1596 } 1597 1598 static enum xgbe_an_mode xgbe_phy_an_sfp_mode(struct xgbe_phy_data *phy_data) 1599 { 1600 switch (phy_data->sfp_base) { 1601 case XGBE_SFP_BASE_1000_T: 1602 return XGBE_AN_MODE_CL37_SGMII; 1603 case XGBE_SFP_BASE_1000_SX: 1604 case XGBE_SFP_BASE_1000_LX: 1605 case XGBE_SFP_BASE_1000_CX: 1606 return XGBE_AN_MODE_CL37; 1607 default: 1608 return XGBE_AN_MODE_NONE; 1609 } 1610 } 1611 1612 static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata) 1613 { 1614 struct xgbe_phy_data *phy_data = pdata->phy_data; 1615 1616 /* A KR re-driver will always require CL73 AN */ 1617 if (phy_data->redrv) 1618 return XGBE_AN_MODE_CL73_REDRV; 1619 1620 switch (phy_data->port_mode) { 1621 case XGBE_PORT_MODE_BACKPLANE: 1622 return XGBE_AN_MODE_CL73; 1623 case XGBE_PORT_MODE_BACKPLANE_2500: 1624 return XGBE_AN_MODE_NONE; 1625 case XGBE_PORT_MODE_1000BASE_T: 1626 return XGBE_AN_MODE_CL37_SGMII; 1627 case XGBE_PORT_MODE_1000BASE_X: 1628 return XGBE_AN_MODE_CL37; 1629 case XGBE_PORT_MODE_NBASE_T: 1630 return XGBE_AN_MODE_CL37_SGMII; 1631 case XGBE_PORT_MODE_10GBASE_T: 1632 return XGBE_AN_MODE_CL73; 1633 case XGBE_PORT_MODE_10GBASE_R: 1634 return XGBE_AN_MODE_NONE; 1635 case XGBE_PORT_MODE_SFP: 1636 return xgbe_phy_an_sfp_mode(phy_data); 1637 default: 1638 return XGBE_AN_MODE_NONE; 1639 } 1640 } 1641 1642 static int xgbe_phy_set_redrv_mode_mdio(struct xgbe_prv_data *pdata, 1643 enum xgbe_phy_redrv_mode mode) 1644 { 1645 struct xgbe_phy_data *phy_data = pdata->phy_data; 1646 u16 redrv_reg, redrv_val; 1647 1648 redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000); 1649 redrv_val = (u16)mode; 1650 1651 return pdata->hw_if.write_ext_mii_regs(pdata, phy_data->redrv_addr, 1652 redrv_reg, redrv_val); 1653 } 1654 1655 static int xgbe_phy_set_redrv_mode_i2c(struct xgbe_prv_data *pdata, 1656 enum xgbe_phy_redrv_mode mode) 1657 { 1658 struct xgbe_phy_data *phy_data = pdata->phy_data; 1659 unsigned int redrv_reg; 1660 int ret; 1661 1662 /* Calculate the register to write */ 1663 redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000); 1664 1665 ret = xgbe_phy_redrv_write(pdata, redrv_reg, mode); 1666 1667 return ret; 1668 } 1669 1670 static void xgbe_phy_set_redrv_mode(struct xgbe_prv_data *pdata) 1671 { 1672 struct xgbe_phy_data *phy_data = pdata->phy_data; 1673 enum xgbe_phy_redrv_mode mode; 1674 int ret; 1675 1676 if (!phy_data->redrv) 1677 return; 1678 1679 mode = XGBE_PHY_REDRV_MODE_CX; 1680 if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) && 1681 (phy_data->sfp_base != XGBE_SFP_BASE_1000_CX) && 1682 (phy_data->sfp_base != XGBE_SFP_BASE_10000_CR)) 1683 mode = XGBE_PHY_REDRV_MODE_SR; 1684 1685 ret = xgbe_phy_get_comm_ownership(pdata); 1686 if (ret) 1687 return; 1688 1689 if (phy_data->redrv_if) 1690 xgbe_phy_set_redrv_mode_i2c(pdata, mode); 1691 else 1692 xgbe_phy_set_redrv_mode_mdio(pdata, mode); 1693 1694 xgbe_phy_put_comm_ownership(pdata); 1695 } 1696 1697 static void xgbe_phy_start_ratechange(struct xgbe_prv_data *pdata) 1698 { 1699 if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) 1700 return; 1701 1702 /* Log if a previous command did not complete */ 1703 netif_dbg(pdata, link, pdata->netdev, 1704 "firmware mailbox not ready for command\n"); 1705 } 1706 1707 static void xgbe_phy_complete_ratechange(struct xgbe_prv_data *pdata) 1708 { 1709 unsigned int wait; 1710 1711 /* Wait for command to complete */ 1712 wait = XGBE_RATECHANGE_COUNT; 1713 while (wait--) { 1714 if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) 1715 return; 1716 1717 usleep_range(1000, 2000); 1718 } 1719 1720 netif_dbg(pdata, link, pdata->netdev, 1721 "firmware mailbox command did not complete\n"); 1722 } 1723 1724 static void xgbe_phy_rrc(struct xgbe_prv_data *pdata) 1725 { 1726 unsigned int s0; 1727 1728 xgbe_phy_start_ratechange(pdata); 1729 1730 /* Receiver Reset Cycle */ 1731 s0 = 0; 1732 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 5); 1733 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 0); 1734 1735 /* Call FW to make the change */ 1736 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0); 1737 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0); 1738 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1); 1739 1740 xgbe_phy_complete_ratechange(pdata); 1741 1742 netif_dbg(pdata, link, pdata->netdev, "receiver reset complete\n"); 1743 } 1744 1745 static void xgbe_phy_power_off(struct xgbe_prv_data *pdata) 1746 { 1747 struct xgbe_phy_data *phy_data = pdata->phy_data; 1748 1749 xgbe_phy_start_ratechange(pdata); 1750 1751 /* Call FW to make the change */ 1752 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, 0); 1753 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0); 1754 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1); 1755 1756 xgbe_phy_complete_ratechange(pdata); 1757 1758 phy_data->cur_mode = XGBE_MODE_UNKNOWN; 1759 1760 netif_dbg(pdata, link, pdata->netdev, "phy powered off\n"); 1761 } 1762 1763 static void xgbe_phy_sfi_mode(struct xgbe_prv_data *pdata) 1764 { 1765 struct xgbe_phy_data *phy_data = pdata->phy_data; 1766 unsigned int s0; 1767 1768 xgbe_phy_set_redrv_mode(pdata); 1769 1770 xgbe_phy_start_ratechange(pdata); 1771 1772 /* 10G/SFI */ 1773 s0 = 0; 1774 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 3); 1775 if (phy_data->sfp_cable != XGBE_SFP_CABLE_PASSIVE) { 1776 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 0); 1777 } else { 1778 if (phy_data->sfp_cable_len <= 1) 1779 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 1); 1780 else if (phy_data->sfp_cable_len <= 3) 1781 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 2); 1782 else 1783 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 3); 1784 } 1785 1786 /* Call FW to make the change */ 1787 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0); 1788 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0); 1789 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1); 1790 1791 xgbe_phy_complete_ratechange(pdata); 1792 1793 phy_data->cur_mode = XGBE_MODE_SFI; 1794 1795 netif_dbg(pdata, link, pdata->netdev, "10GbE SFI mode set\n"); 1796 } 1797 1798 static void xgbe_phy_x_mode(struct xgbe_prv_data *pdata) 1799 { 1800 struct xgbe_phy_data *phy_data = pdata->phy_data; 1801 unsigned int s0; 1802 1803 xgbe_phy_set_redrv_mode(pdata); 1804 1805 xgbe_phy_start_ratechange(pdata); 1806 1807 /* 1G/X */ 1808 s0 = 0; 1809 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 1); 1810 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 3); 1811 1812 /* Call FW to make the change */ 1813 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0); 1814 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0); 1815 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1); 1816 1817 xgbe_phy_complete_ratechange(pdata); 1818 1819 phy_data->cur_mode = XGBE_MODE_X; 1820 1821 netif_dbg(pdata, link, pdata->netdev, "1GbE X mode set\n"); 1822 } 1823 1824 static void xgbe_phy_sgmii_1000_mode(struct xgbe_prv_data *pdata) 1825 { 1826 struct xgbe_phy_data *phy_data = pdata->phy_data; 1827 unsigned int s0; 1828 1829 xgbe_phy_set_redrv_mode(pdata); 1830 1831 xgbe_phy_start_ratechange(pdata); 1832 1833 /* 1G/SGMII */ 1834 s0 = 0; 1835 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 1); 1836 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 2); 1837 1838 /* Call FW to make the change */ 1839 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0); 1840 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0); 1841 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1); 1842 1843 xgbe_phy_complete_ratechange(pdata); 1844 1845 phy_data->cur_mode = XGBE_MODE_SGMII_1000; 1846 1847 netif_dbg(pdata, link, pdata->netdev, "1GbE SGMII mode set\n"); 1848 } 1849 1850 static void xgbe_phy_sgmii_100_mode(struct xgbe_prv_data *pdata) 1851 { 1852 struct xgbe_phy_data *phy_data = pdata->phy_data; 1853 unsigned int s0; 1854 1855 xgbe_phy_set_redrv_mode(pdata); 1856 1857 xgbe_phy_start_ratechange(pdata); 1858 1859 /* 1G/SGMII */ 1860 s0 = 0; 1861 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 1); 1862 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 1); 1863 1864 /* Call FW to make the change */ 1865 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0); 1866 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0); 1867 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1); 1868 1869 xgbe_phy_complete_ratechange(pdata); 1870 1871 phy_data->cur_mode = XGBE_MODE_SGMII_100; 1872 1873 netif_dbg(pdata, link, pdata->netdev, "100MbE SGMII mode set\n"); 1874 } 1875 1876 static void xgbe_phy_kr_mode(struct xgbe_prv_data *pdata) 1877 { 1878 struct xgbe_phy_data *phy_data = pdata->phy_data; 1879 unsigned int s0; 1880 1881 xgbe_phy_set_redrv_mode(pdata); 1882 1883 xgbe_phy_start_ratechange(pdata); 1884 1885 /* 10G/KR */ 1886 s0 = 0; 1887 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 4); 1888 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 0); 1889 1890 /* Call FW to make the change */ 1891 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0); 1892 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0); 1893 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1); 1894 1895 xgbe_phy_complete_ratechange(pdata); 1896 1897 phy_data->cur_mode = XGBE_MODE_KR; 1898 1899 netif_dbg(pdata, link, pdata->netdev, "10GbE KR mode set\n"); 1900 } 1901 1902 static void xgbe_phy_kx_2500_mode(struct xgbe_prv_data *pdata) 1903 { 1904 struct xgbe_phy_data *phy_data = pdata->phy_data; 1905 unsigned int s0; 1906 1907 xgbe_phy_set_redrv_mode(pdata); 1908 1909 xgbe_phy_start_ratechange(pdata); 1910 1911 /* 2.5G/KX */ 1912 s0 = 0; 1913 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 2); 1914 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 0); 1915 1916 /* Call FW to make the change */ 1917 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0); 1918 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0); 1919 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1); 1920 1921 xgbe_phy_complete_ratechange(pdata); 1922 1923 phy_data->cur_mode = XGBE_MODE_KX_2500; 1924 1925 netif_dbg(pdata, link, pdata->netdev, "2.5GbE KX mode set\n"); 1926 } 1927 1928 static void xgbe_phy_kx_1000_mode(struct xgbe_prv_data *pdata) 1929 { 1930 struct xgbe_phy_data *phy_data = pdata->phy_data; 1931 unsigned int s0; 1932 1933 xgbe_phy_set_redrv_mode(pdata); 1934 1935 xgbe_phy_start_ratechange(pdata); 1936 1937 /* 1G/KX */ 1938 s0 = 0; 1939 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 1); 1940 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 3); 1941 1942 /* Call FW to make the change */ 1943 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0); 1944 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0); 1945 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1); 1946 1947 xgbe_phy_complete_ratechange(pdata); 1948 1949 phy_data->cur_mode = XGBE_MODE_KX_1000; 1950 1951 netif_dbg(pdata, link, pdata->netdev, "1GbE KX mode set\n"); 1952 } 1953 1954 static enum xgbe_mode xgbe_phy_cur_mode(struct xgbe_prv_data *pdata) 1955 { 1956 struct xgbe_phy_data *phy_data = pdata->phy_data; 1957 1958 return phy_data->cur_mode; 1959 } 1960 1961 static enum xgbe_mode xgbe_phy_switch_baset_mode(struct xgbe_prv_data *pdata) 1962 { 1963 struct xgbe_phy_data *phy_data = pdata->phy_data; 1964 1965 /* No switching if not 10GBase-T */ 1966 if (phy_data->port_mode != XGBE_PORT_MODE_10GBASE_T) 1967 return xgbe_phy_cur_mode(pdata); 1968 1969 switch (xgbe_phy_cur_mode(pdata)) { 1970 case XGBE_MODE_SGMII_100: 1971 case XGBE_MODE_SGMII_1000: 1972 return XGBE_MODE_KR; 1973 case XGBE_MODE_KR: 1974 default: 1975 return XGBE_MODE_SGMII_1000; 1976 } 1977 } 1978 1979 static enum xgbe_mode xgbe_phy_switch_bp_2500_mode(struct xgbe_prv_data *pdata) 1980 { 1981 return XGBE_MODE_KX_2500; 1982 } 1983 1984 static enum xgbe_mode xgbe_phy_switch_bp_mode(struct xgbe_prv_data *pdata) 1985 { 1986 /* If we are in KR switch to KX, and vice-versa */ 1987 switch (xgbe_phy_cur_mode(pdata)) { 1988 case XGBE_MODE_KX_1000: 1989 return XGBE_MODE_KR; 1990 case XGBE_MODE_KR: 1991 default: 1992 return XGBE_MODE_KX_1000; 1993 } 1994 } 1995 1996 static enum xgbe_mode xgbe_phy_switch_mode(struct xgbe_prv_data *pdata) 1997 { 1998 struct xgbe_phy_data *phy_data = pdata->phy_data; 1999 2000 switch (phy_data->port_mode) { 2001 case XGBE_PORT_MODE_BACKPLANE: 2002 return xgbe_phy_switch_bp_mode(pdata); 2003 case XGBE_PORT_MODE_BACKPLANE_2500: 2004 return xgbe_phy_switch_bp_2500_mode(pdata); 2005 case XGBE_PORT_MODE_1000BASE_T: 2006 case XGBE_PORT_MODE_NBASE_T: 2007 case XGBE_PORT_MODE_10GBASE_T: 2008 return xgbe_phy_switch_baset_mode(pdata); 2009 case XGBE_PORT_MODE_1000BASE_X: 2010 case XGBE_PORT_MODE_10GBASE_R: 2011 case XGBE_PORT_MODE_SFP: 2012 /* No switching, so just return current mode */ 2013 return xgbe_phy_cur_mode(pdata); 2014 default: 2015 return XGBE_MODE_UNKNOWN; 2016 } 2017 } 2018 2019 static enum xgbe_mode xgbe_phy_get_basex_mode(struct xgbe_phy_data *phy_data, 2020 int speed) 2021 { 2022 switch (speed) { 2023 case SPEED_1000: 2024 return XGBE_MODE_X; 2025 case SPEED_10000: 2026 return XGBE_MODE_KR; 2027 default: 2028 return XGBE_MODE_UNKNOWN; 2029 } 2030 } 2031 2032 static enum xgbe_mode xgbe_phy_get_baset_mode(struct xgbe_phy_data *phy_data, 2033 int speed) 2034 { 2035 switch (speed) { 2036 case SPEED_100: 2037 return XGBE_MODE_SGMII_100; 2038 case SPEED_1000: 2039 return XGBE_MODE_SGMII_1000; 2040 case SPEED_10000: 2041 return XGBE_MODE_KR; 2042 default: 2043 return XGBE_MODE_UNKNOWN; 2044 } 2045 } 2046 2047 static enum xgbe_mode xgbe_phy_get_sfp_mode(struct xgbe_phy_data *phy_data, 2048 int speed) 2049 { 2050 switch (speed) { 2051 case SPEED_100: 2052 return XGBE_MODE_SGMII_100; 2053 case SPEED_1000: 2054 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T) 2055 return XGBE_MODE_SGMII_1000; 2056 else 2057 return XGBE_MODE_X; 2058 case SPEED_10000: 2059 case SPEED_UNKNOWN: 2060 return XGBE_MODE_SFI; 2061 default: 2062 return XGBE_MODE_UNKNOWN; 2063 } 2064 } 2065 2066 static enum xgbe_mode xgbe_phy_get_bp_2500_mode(int speed) 2067 { 2068 switch (speed) { 2069 case SPEED_2500: 2070 return XGBE_MODE_KX_2500; 2071 default: 2072 return XGBE_MODE_UNKNOWN; 2073 } 2074 } 2075 2076 static enum xgbe_mode xgbe_phy_get_bp_mode(int speed) 2077 { 2078 switch (speed) { 2079 case SPEED_1000: 2080 return XGBE_MODE_KX_1000; 2081 case SPEED_10000: 2082 return XGBE_MODE_KR; 2083 default: 2084 return XGBE_MODE_UNKNOWN; 2085 } 2086 } 2087 2088 static enum xgbe_mode xgbe_phy_get_mode(struct xgbe_prv_data *pdata, 2089 int speed) 2090 { 2091 struct xgbe_phy_data *phy_data = pdata->phy_data; 2092 2093 switch (phy_data->port_mode) { 2094 case XGBE_PORT_MODE_BACKPLANE: 2095 return xgbe_phy_get_bp_mode(speed); 2096 case XGBE_PORT_MODE_BACKPLANE_2500: 2097 return xgbe_phy_get_bp_2500_mode(speed); 2098 case XGBE_PORT_MODE_1000BASE_T: 2099 case XGBE_PORT_MODE_NBASE_T: 2100 case XGBE_PORT_MODE_10GBASE_T: 2101 return xgbe_phy_get_baset_mode(phy_data, speed); 2102 case XGBE_PORT_MODE_1000BASE_X: 2103 case XGBE_PORT_MODE_10GBASE_R: 2104 return xgbe_phy_get_basex_mode(phy_data, speed); 2105 case XGBE_PORT_MODE_SFP: 2106 return xgbe_phy_get_sfp_mode(phy_data, speed); 2107 default: 2108 return XGBE_MODE_UNKNOWN; 2109 } 2110 } 2111 2112 static void xgbe_phy_set_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode) 2113 { 2114 switch (mode) { 2115 case XGBE_MODE_KX_1000: 2116 xgbe_phy_kx_1000_mode(pdata); 2117 break; 2118 case XGBE_MODE_KX_2500: 2119 xgbe_phy_kx_2500_mode(pdata); 2120 break; 2121 case XGBE_MODE_KR: 2122 xgbe_phy_kr_mode(pdata); 2123 break; 2124 case XGBE_MODE_SGMII_100: 2125 xgbe_phy_sgmii_100_mode(pdata); 2126 break; 2127 case XGBE_MODE_SGMII_1000: 2128 xgbe_phy_sgmii_1000_mode(pdata); 2129 break; 2130 case XGBE_MODE_X: 2131 xgbe_phy_x_mode(pdata); 2132 break; 2133 case XGBE_MODE_SFI: 2134 xgbe_phy_sfi_mode(pdata); 2135 break; 2136 default: 2137 break; 2138 } 2139 } 2140 2141 static bool xgbe_phy_check_mode(struct xgbe_prv_data *pdata, 2142 enum xgbe_mode mode, u32 advert) 2143 { 2144 if (pdata->phy.autoneg == AUTONEG_ENABLE) { 2145 if (pdata->phy.advertising & advert) 2146 return true; 2147 } else { 2148 enum xgbe_mode cur_mode; 2149 2150 cur_mode = xgbe_phy_get_mode(pdata, pdata->phy.speed); 2151 if (cur_mode == mode) 2152 return true; 2153 } 2154 2155 return false; 2156 } 2157 2158 static bool xgbe_phy_use_basex_mode(struct xgbe_prv_data *pdata, 2159 enum xgbe_mode mode) 2160 { 2161 switch (mode) { 2162 case XGBE_MODE_X: 2163 return xgbe_phy_check_mode(pdata, mode, 2164 ADVERTISED_1000baseT_Full); 2165 case XGBE_MODE_KR: 2166 return xgbe_phy_check_mode(pdata, mode, 2167 ADVERTISED_10000baseT_Full); 2168 default: 2169 return false; 2170 } 2171 } 2172 2173 static bool xgbe_phy_use_baset_mode(struct xgbe_prv_data *pdata, 2174 enum xgbe_mode mode) 2175 { 2176 switch (mode) { 2177 case XGBE_MODE_SGMII_100: 2178 return xgbe_phy_check_mode(pdata, mode, 2179 ADVERTISED_100baseT_Full); 2180 case XGBE_MODE_SGMII_1000: 2181 return xgbe_phy_check_mode(pdata, mode, 2182 ADVERTISED_1000baseT_Full); 2183 case XGBE_MODE_KR: 2184 return xgbe_phy_check_mode(pdata, mode, 2185 ADVERTISED_10000baseT_Full); 2186 default: 2187 return false; 2188 } 2189 } 2190 2191 static bool xgbe_phy_use_sfp_mode(struct xgbe_prv_data *pdata, 2192 enum xgbe_mode mode) 2193 { 2194 struct xgbe_phy_data *phy_data = pdata->phy_data; 2195 2196 switch (mode) { 2197 case XGBE_MODE_X: 2198 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T) 2199 return false; 2200 return xgbe_phy_check_mode(pdata, mode, 2201 ADVERTISED_1000baseT_Full); 2202 case XGBE_MODE_SGMII_100: 2203 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T) 2204 return false; 2205 return xgbe_phy_check_mode(pdata, mode, 2206 ADVERTISED_100baseT_Full); 2207 case XGBE_MODE_SGMII_1000: 2208 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T) 2209 return false; 2210 return xgbe_phy_check_mode(pdata, mode, 2211 ADVERTISED_1000baseT_Full); 2212 case XGBE_MODE_SFI: 2213 return xgbe_phy_check_mode(pdata, mode, 2214 ADVERTISED_10000baseT_Full); 2215 default: 2216 return false; 2217 } 2218 } 2219 2220 static bool xgbe_phy_use_bp_2500_mode(struct xgbe_prv_data *pdata, 2221 enum xgbe_mode mode) 2222 { 2223 switch (mode) { 2224 case XGBE_MODE_KX_2500: 2225 return xgbe_phy_check_mode(pdata, mode, 2226 ADVERTISED_2500baseX_Full); 2227 default: 2228 return false; 2229 } 2230 } 2231 2232 static bool xgbe_phy_use_bp_mode(struct xgbe_prv_data *pdata, 2233 enum xgbe_mode mode) 2234 { 2235 switch (mode) { 2236 case XGBE_MODE_KX_1000: 2237 return xgbe_phy_check_mode(pdata, mode, 2238 ADVERTISED_1000baseKX_Full); 2239 case XGBE_MODE_KR: 2240 return xgbe_phy_check_mode(pdata, mode, 2241 ADVERTISED_10000baseKR_Full); 2242 default: 2243 return false; 2244 } 2245 } 2246 2247 static bool xgbe_phy_use_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode) 2248 { 2249 struct xgbe_phy_data *phy_data = pdata->phy_data; 2250 2251 switch (phy_data->port_mode) { 2252 case XGBE_PORT_MODE_BACKPLANE: 2253 return xgbe_phy_use_bp_mode(pdata, mode); 2254 case XGBE_PORT_MODE_BACKPLANE_2500: 2255 return xgbe_phy_use_bp_2500_mode(pdata, mode); 2256 case XGBE_PORT_MODE_1000BASE_T: 2257 case XGBE_PORT_MODE_NBASE_T: 2258 case XGBE_PORT_MODE_10GBASE_T: 2259 return xgbe_phy_use_baset_mode(pdata, mode); 2260 case XGBE_PORT_MODE_1000BASE_X: 2261 case XGBE_PORT_MODE_10GBASE_R: 2262 return xgbe_phy_use_basex_mode(pdata, mode); 2263 case XGBE_PORT_MODE_SFP: 2264 return xgbe_phy_use_sfp_mode(pdata, mode); 2265 default: 2266 return false; 2267 } 2268 } 2269 2270 static bool xgbe_phy_valid_speed_basex_mode(struct xgbe_phy_data *phy_data, 2271 int speed) 2272 { 2273 switch (speed) { 2274 case SPEED_1000: 2275 return (phy_data->port_mode == XGBE_PORT_MODE_1000BASE_X); 2276 case SPEED_10000: 2277 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_R); 2278 default: 2279 return false; 2280 } 2281 } 2282 2283 static bool xgbe_phy_valid_speed_baset_mode(struct xgbe_phy_data *phy_data, 2284 int speed) 2285 { 2286 switch (speed) { 2287 case SPEED_100: 2288 case SPEED_1000: 2289 return true; 2290 case SPEED_10000: 2291 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_T); 2292 default: 2293 return false; 2294 } 2295 } 2296 2297 static bool xgbe_phy_valid_speed_sfp_mode(struct xgbe_phy_data *phy_data, 2298 int speed) 2299 { 2300 switch (speed) { 2301 case SPEED_100: 2302 return (phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000); 2303 case SPEED_1000: 2304 return ((phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000) || 2305 (phy_data->sfp_speed == XGBE_SFP_SPEED_1000)); 2306 case SPEED_10000: 2307 return (phy_data->sfp_speed == XGBE_SFP_SPEED_10000); 2308 default: 2309 return false; 2310 } 2311 } 2312 2313 static bool xgbe_phy_valid_speed_bp_2500_mode(int speed) 2314 { 2315 switch (speed) { 2316 case SPEED_2500: 2317 return true; 2318 default: 2319 return false; 2320 } 2321 } 2322 2323 static bool xgbe_phy_valid_speed_bp_mode(int speed) 2324 { 2325 switch (speed) { 2326 case SPEED_1000: 2327 case SPEED_10000: 2328 return true; 2329 default: 2330 return false; 2331 } 2332 } 2333 2334 static bool xgbe_phy_valid_speed(struct xgbe_prv_data *pdata, int speed) 2335 { 2336 struct xgbe_phy_data *phy_data = pdata->phy_data; 2337 2338 switch (phy_data->port_mode) { 2339 case XGBE_PORT_MODE_BACKPLANE: 2340 return xgbe_phy_valid_speed_bp_mode(speed); 2341 case XGBE_PORT_MODE_BACKPLANE_2500: 2342 return xgbe_phy_valid_speed_bp_2500_mode(speed); 2343 case XGBE_PORT_MODE_1000BASE_T: 2344 case XGBE_PORT_MODE_NBASE_T: 2345 case XGBE_PORT_MODE_10GBASE_T: 2346 return xgbe_phy_valid_speed_baset_mode(phy_data, speed); 2347 case XGBE_PORT_MODE_1000BASE_X: 2348 case XGBE_PORT_MODE_10GBASE_R: 2349 return xgbe_phy_valid_speed_basex_mode(phy_data, speed); 2350 case XGBE_PORT_MODE_SFP: 2351 return xgbe_phy_valid_speed_sfp_mode(phy_data, speed); 2352 default: 2353 return false; 2354 } 2355 } 2356 2357 static int xgbe_phy_link_status(struct xgbe_prv_data *pdata, int *an_restart) 2358 { 2359 struct xgbe_phy_data *phy_data = pdata->phy_data; 2360 unsigned int reg; 2361 int ret; 2362 2363 *an_restart = 0; 2364 2365 if (phy_data->port_mode == XGBE_PORT_MODE_SFP) { 2366 /* Check SFP signals */ 2367 xgbe_phy_sfp_detect(pdata); 2368 2369 if (phy_data->sfp_changed) { 2370 *an_restart = 1; 2371 return 0; 2372 } 2373 2374 if (phy_data->sfp_mod_absent || phy_data->sfp_rx_los) 2375 return 0; 2376 } 2377 2378 if (phy_data->phydev) { 2379 /* Check external PHY */ 2380 ret = phy_read_status(phy_data->phydev); 2381 if (ret < 0) 2382 return 0; 2383 2384 if ((pdata->phy.autoneg == AUTONEG_ENABLE) && 2385 !phy_aneg_done(phy_data->phydev)) 2386 return 0; 2387 2388 if (!phy_data->phydev->link) 2389 return 0; 2390 } 2391 2392 /* Link status is latched low, so read once to clear 2393 * and then read again to get current state 2394 */ 2395 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); 2396 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); 2397 if (reg & MDIO_STAT1_LSTATUS) 2398 return 1; 2399 2400 /* No link, attempt a receiver reset cycle */ 2401 if (phy_data->rrc_count++) { 2402 phy_data->rrc_count = 0; 2403 xgbe_phy_rrc(pdata); 2404 } 2405 2406 return 0; 2407 } 2408 2409 static void xgbe_phy_sfp_gpio_setup(struct xgbe_prv_data *pdata) 2410 { 2411 struct xgbe_phy_data *phy_data = pdata->phy_data; 2412 unsigned int reg; 2413 2414 reg = XP_IOREAD(pdata, XP_PROP_3); 2415 2416 phy_data->sfp_gpio_address = XGBE_GPIO_ADDRESS_PCA9555 + 2417 XP_GET_BITS(reg, XP_PROP_3, GPIO_ADDR); 2418 2419 phy_data->sfp_gpio_mask = XP_GET_BITS(reg, XP_PROP_3, GPIO_MASK); 2420 2421 phy_data->sfp_gpio_rx_los = XP_GET_BITS(reg, XP_PROP_3, 2422 GPIO_RX_LOS); 2423 phy_data->sfp_gpio_tx_fault = XP_GET_BITS(reg, XP_PROP_3, 2424 GPIO_TX_FAULT); 2425 phy_data->sfp_gpio_mod_absent = XP_GET_BITS(reg, XP_PROP_3, 2426 GPIO_MOD_ABS); 2427 phy_data->sfp_gpio_rate_select = XP_GET_BITS(reg, XP_PROP_3, 2428 GPIO_RATE_SELECT); 2429 2430 if (netif_msg_probe(pdata)) { 2431 dev_dbg(pdata->dev, "SFP: gpio_address=%#x\n", 2432 phy_data->sfp_gpio_address); 2433 dev_dbg(pdata->dev, "SFP: gpio_mask=%#x\n", 2434 phy_data->sfp_gpio_mask); 2435 dev_dbg(pdata->dev, "SFP: gpio_rx_los=%u\n", 2436 phy_data->sfp_gpio_rx_los); 2437 dev_dbg(pdata->dev, "SFP: gpio_tx_fault=%u\n", 2438 phy_data->sfp_gpio_tx_fault); 2439 dev_dbg(pdata->dev, "SFP: gpio_mod_absent=%u\n", 2440 phy_data->sfp_gpio_mod_absent); 2441 dev_dbg(pdata->dev, "SFP: gpio_rate_select=%u\n", 2442 phy_data->sfp_gpio_rate_select); 2443 } 2444 } 2445 2446 static void xgbe_phy_sfp_comm_setup(struct xgbe_prv_data *pdata) 2447 { 2448 struct xgbe_phy_data *phy_data = pdata->phy_data; 2449 unsigned int reg, mux_addr_hi, mux_addr_lo; 2450 2451 reg = XP_IOREAD(pdata, XP_PROP_4); 2452 2453 mux_addr_hi = XP_GET_BITS(reg, XP_PROP_4, MUX_ADDR_HI); 2454 mux_addr_lo = XP_GET_BITS(reg, XP_PROP_4, MUX_ADDR_LO); 2455 if (mux_addr_lo == XGBE_SFP_DIRECT) 2456 return; 2457 2458 phy_data->sfp_comm = XGBE_SFP_COMM_PCA9545; 2459 phy_data->sfp_mux_address = (mux_addr_hi << 2) + mux_addr_lo; 2460 phy_data->sfp_mux_channel = XP_GET_BITS(reg, XP_PROP_4, MUX_CHAN); 2461 2462 if (netif_msg_probe(pdata)) { 2463 dev_dbg(pdata->dev, "SFP: mux_address=%#x\n", 2464 phy_data->sfp_mux_address); 2465 dev_dbg(pdata->dev, "SFP: mux_channel=%u\n", 2466 phy_data->sfp_mux_channel); 2467 } 2468 } 2469 2470 static void xgbe_phy_sfp_setup(struct xgbe_prv_data *pdata) 2471 { 2472 xgbe_phy_sfp_comm_setup(pdata); 2473 xgbe_phy_sfp_gpio_setup(pdata); 2474 } 2475 2476 static int xgbe_phy_int_mdio_reset(struct xgbe_prv_data *pdata) 2477 { 2478 struct xgbe_phy_data *phy_data = pdata->phy_data; 2479 unsigned int ret; 2480 2481 ret = pdata->hw_if.set_gpio(pdata, phy_data->mdio_reset_gpio); 2482 if (ret) 2483 return ret; 2484 2485 ret = pdata->hw_if.clr_gpio(pdata, phy_data->mdio_reset_gpio); 2486 2487 return ret; 2488 } 2489 2490 static int xgbe_phy_i2c_mdio_reset(struct xgbe_prv_data *pdata) 2491 { 2492 struct xgbe_phy_data *phy_data = pdata->phy_data; 2493 u8 gpio_reg, gpio_ports[2], gpio_data[3]; 2494 int ret; 2495 2496 /* Read the output port registers */ 2497 gpio_reg = 2; 2498 ret = xgbe_phy_i2c_read(pdata, phy_data->mdio_reset_addr, 2499 &gpio_reg, sizeof(gpio_reg), 2500 gpio_ports, sizeof(gpio_ports)); 2501 if (ret) 2502 return ret; 2503 2504 /* Prepare to write the GPIO data */ 2505 gpio_data[0] = 2; 2506 gpio_data[1] = gpio_ports[0]; 2507 gpio_data[2] = gpio_ports[1]; 2508 2509 /* Set the GPIO pin */ 2510 if (phy_data->mdio_reset_gpio < 8) 2511 gpio_data[1] |= (1 << (phy_data->mdio_reset_gpio % 8)); 2512 else 2513 gpio_data[2] |= (1 << (phy_data->mdio_reset_gpio % 8)); 2514 2515 /* Write the output port registers */ 2516 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr, 2517 gpio_data, sizeof(gpio_data)); 2518 if (ret) 2519 return ret; 2520 2521 /* Clear the GPIO pin */ 2522 if (phy_data->mdio_reset_gpio < 8) 2523 gpio_data[1] &= ~(1 << (phy_data->mdio_reset_gpio % 8)); 2524 else 2525 gpio_data[2] &= ~(1 << (phy_data->mdio_reset_gpio % 8)); 2526 2527 /* Write the output port registers */ 2528 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr, 2529 gpio_data, sizeof(gpio_data)); 2530 2531 return ret; 2532 } 2533 2534 static int xgbe_phy_mdio_reset(struct xgbe_prv_data *pdata) 2535 { 2536 struct xgbe_phy_data *phy_data = pdata->phy_data; 2537 int ret; 2538 2539 if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO) 2540 return 0; 2541 2542 ret = xgbe_phy_get_comm_ownership(pdata); 2543 if (ret) 2544 return ret; 2545 2546 if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO) 2547 ret = xgbe_phy_i2c_mdio_reset(pdata); 2548 else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO) 2549 ret = xgbe_phy_int_mdio_reset(pdata); 2550 2551 xgbe_phy_put_comm_ownership(pdata); 2552 2553 return ret; 2554 } 2555 2556 static bool xgbe_phy_redrv_error(struct xgbe_phy_data *phy_data) 2557 { 2558 if (!phy_data->redrv) 2559 return false; 2560 2561 if (phy_data->redrv_if >= XGBE_PHY_REDRV_IF_MAX) 2562 return true; 2563 2564 switch (phy_data->redrv_model) { 2565 case XGBE_PHY_REDRV_MODEL_4223: 2566 if (phy_data->redrv_lane > 3) 2567 return true; 2568 break; 2569 case XGBE_PHY_REDRV_MODEL_4227: 2570 if (phy_data->redrv_lane > 1) 2571 return true; 2572 break; 2573 default: 2574 return true; 2575 } 2576 2577 return false; 2578 } 2579 2580 static int xgbe_phy_mdio_reset_setup(struct xgbe_prv_data *pdata) 2581 { 2582 struct xgbe_phy_data *phy_data = pdata->phy_data; 2583 unsigned int reg; 2584 2585 if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO) 2586 return 0; 2587 2588 reg = XP_IOREAD(pdata, XP_PROP_3); 2589 phy_data->mdio_reset = XP_GET_BITS(reg, XP_PROP_3, MDIO_RESET); 2590 switch (phy_data->mdio_reset) { 2591 case XGBE_MDIO_RESET_NONE: 2592 case XGBE_MDIO_RESET_I2C_GPIO: 2593 case XGBE_MDIO_RESET_INT_GPIO: 2594 break; 2595 default: 2596 dev_err(pdata->dev, "unsupported MDIO reset (%#x)\n", 2597 phy_data->mdio_reset); 2598 return -EINVAL; 2599 } 2600 2601 if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO) { 2602 phy_data->mdio_reset_addr = XGBE_GPIO_ADDRESS_PCA9555 + 2603 XP_GET_BITS(reg, XP_PROP_3, 2604 MDIO_RESET_I2C_ADDR); 2605 phy_data->mdio_reset_gpio = XP_GET_BITS(reg, XP_PROP_3, 2606 MDIO_RESET_I2C_GPIO); 2607 } else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO) { 2608 phy_data->mdio_reset_gpio = XP_GET_BITS(reg, XP_PROP_3, 2609 MDIO_RESET_INT_GPIO); 2610 } 2611 2612 return 0; 2613 } 2614 2615 static bool xgbe_phy_port_mode_mismatch(struct xgbe_prv_data *pdata) 2616 { 2617 struct xgbe_phy_data *phy_data = pdata->phy_data; 2618 2619 switch (phy_data->port_mode) { 2620 case XGBE_PORT_MODE_BACKPLANE: 2621 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) || 2622 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)) 2623 return false; 2624 break; 2625 case XGBE_PORT_MODE_BACKPLANE_2500: 2626 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500) 2627 return false; 2628 break; 2629 case XGBE_PORT_MODE_1000BASE_T: 2630 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) || 2631 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)) 2632 return false; 2633 break; 2634 case XGBE_PORT_MODE_1000BASE_X: 2635 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) 2636 return false; 2637 break; 2638 case XGBE_PORT_MODE_NBASE_T: 2639 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) || 2640 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) || 2641 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500)) 2642 return false; 2643 break; 2644 case XGBE_PORT_MODE_10GBASE_T: 2645 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) || 2646 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) || 2647 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)) 2648 return false; 2649 break; 2650 case XGBE_PORT_MODE_10GBASE_R: 2651 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) 2652 return false; 2653 break; 2654 case XGBE_PORT_MODE_SFP: 2655 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) || 2656 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) || 2657 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)) 2658 return false; 2659 break; 2660 default: 2661 break; 2662 } 2663 2664 return true; 2665 } 2666 2667 static bool xgbe_phy_conn_type_mismatch(struct xgbe_prv_data *pdata) 2668 { 2669 struct xgbe_phy_data *phy_data = pdata->phy_data; 2670 2671 switch (phy_data->port_mode) { 2672 case XGBE_PORT_MODE_BACKPLANE: 2673 case XGBE_PORT_MODE_BACKPLANE_2500: 2674 if (phy_data->conn_type == XGBE_CONN_TYPE_BACKPLANE) 2675 return false; 2676 break; 2677 case XGBE_PORT_MODE_1000BASE_T: 2678 case XGBE_PORT_MODE_1000BASE_X: 2679 case XGBE_PORT_MODE_NBASE_T: 2680 case XGBE_PORT_MODE_10GBASE_T: 2681 case XGBE_PORT_MODE_10GBASE_R: 2682 if (phy_data->conn_type == XGBE_CONN_TYPE_MDIO) 2683 return false; 2684 break; 2685 case XGBE_PORT_MODE_SFP: 2686 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP) 2687 return false; 2688 break; 2689 default: 2690 break; 2691 } 2692 2693 return true; 2694 } 2695 2696 static bool xgbe_phy_port_enabled(struct xgbe_prv_data *pdata) 2697 { 2698 unsigned int reg; 2699 2700 reg = XP_IOREAD(pdata, XP_PROP_0); 2701 if (!XP_GET_BITS(reg, XP_PROP_0, PORT_SPEEDS)) 2702 return false; 2703 if (!XP_GET_BITS(reg, XP_PROP_0, CONN_TYPE)) 2704 return false; 2705 2706 return true; 2707 } 2708 2709 static void xgbe_phy_stop(struct xgbe_prv_data *pdata) 2710 { 2711 struct xgbe_phy_data *phy_data = pdata->phy_data; 2712 2713 /* If we have an external PHY, free it */ 2714 xgbe_phy_free_phy_device(pdata); 2715 2716 /* Reset SFP data */ 2717 xgbe_phy_sfp_reset(phy_data); 2718 xgbe_phy_sfp_mod_absent(pdata); 2719 2720 /* Power off the PHY */ 2721 xgbe_phy_power_off(pdata); 2722 2723 /* Stop the I2C controller */ 2724 pdata->i2c_if.i2c_stop(pdata); 2725 } 2726 2727 static int xgbe_phy_start(struct xgbe_prv_data *pdata) 2728 { 2729 struct xgbe_phy_data *phy_data = pdata->phy_data; 2730 int ret; 2731 2732 /* Start the I2C controller */ 2733 ret = pdata->i2c_if.i2c_start(pdata); 2734 if (ret) 2735 return ret; 2736 2737 /* Set the proper MDIO mode for the re-driver */ 2738 if (phy_data->redrv && !phy_data->redrv_if) { 2739 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr, 2740 XGBE_MDIO_MODE_CL22); 2741 if (ret) { 2742 netdev_err(pdata->netdev, 2743 "redriver mdio port not compatible (%u)\n", 2744 phy_data->redrv_addr); 2745 return ret; 2746 } 2747 } 2748 2749 /* Start in highest supported mode */ 2750 xgbe_phy_set_mode(pdata, phy_data->start_mode); 2751 2752 /* After starting the I2C controller, we can check for an SFP */ 2753 switch (phy_data->port_mode) { 2754 case XGBE_PORT_MODE_SFP: 2755 xgbe_phy_sfp_detect(pdata); 2756 break; 2757 default: 2758 break; 2759 } 2760 2761 /* If we have an external PHY, start it */ 2762 ret = xgbe_phy_find_phy_device(pdata); 2763 if (ret) 2764 goto err_i2c; 2765 2766 return 0; 2767 2768 err_i2c: 2769 pdata->i2c_if.i2c_stop(pdata); 2770 2771 return ret; 2772 } 2773 2774 static int xgbe_phy_reset(struct xgbe_prv_data *pdata) 2775 { 2776 struct xgbe_phy_data *phy_data = pdata->phy_data; 2777 enum xgbe_mode cur_mode; 2778 int ret; 2779 2780 /* Reset by power cycling the PHY */ 2781 cur_mode = phy_data->cur_mode; 2782 xgbe_phy_power_off(pdata); 2783 xgbe_phy_set_mode(pdata, cur_mode); 2784 2785 if (!phy_data->phydev) 2786 return 0; 2787 2788 /* Reset the external PHY */ 2789 ret = xgbe_phy_mdio_reset(pdata); 2790 if (ret) 2791 return ret; 2792 2793 return phy_init_hw(phy_data->phydev); 2794 } 2795 2796 static void xgbe_phy_exit(struct xgbe_prv_data *pdata) 2797 { 2798 struct xgbe_phy_data *phy_data = pdata->phy_data; 2799 2800 /* Unregister for driving external PHYs */ 2801 mdiobus_unregister(phy_data->mii); 2802 } 2803 2804 static int xgbe_phy_init(struct xgbe_prv_data *pdata) 2805 { 2806 struct xgbe_phy_data *phy_data; 2807 struct mii_bus *mii; 2808 unsigned int reg; 2809 int ret; 2810 2811 /* Check if enabled */ 2812 if (!xgbe_phy_port_enabled(pdata)) { 2813 dev_info(pdata->dev, "device is not enabled\n"); 2814 return -ENODEV; 2815 } 2816 2817 /* Initialize the I2C controller */ 2818 ret = pdata->i2c_if.i2c_init(pdata); 2819 if (ret) 2820 return ret; 2821 2822 phy_data = devm_kzalloc(pdata->dev, sizeof(*phy_data), GFP_KERNEL); 2823 if (!phy_data) 2824 return -ENOMEM; 2825 pdata->phy_data = phy_data; 2826 2827 reg = XP_IOREAD(pdata, XP_PROP_0); 2828 phy_data->port_mode = XP_GET_BITS(reg, XP_PROP_0, PORT_MODE); 2829 phy_data->port_id = XP_GET_BITS(reg, XP_PROP_0, PORT_ID); 2830 phy_data->port_speeds = XP_GET_BITS(reg, XP_PROP_0, PORT_SPEEDS); 2831 phy_data->conn_type = XP_GET_BITS(reg, XP_PROP_0, CONN_TYPE); 2832 phy_data->mdio_addr = XP_GET_BITS(reg, XP_PROP_0, MDIO_ADDR); 2833 if (netif_msg_probe(pdata)) { 2834 dev_dbg(pdata->dev, "port mode=%u\n", phy_data->port_mode); 2835 dev_dbg(pdata->dev, "port id=%u\n", phy_data->port_id); 2836 dev_dbg(pdata->dev, "port speeds=%#x\n", phy_data->port_speeds); 2837 dev_dbg(pdata->dev, "conn type=%u\n", phy_data->conn_type); 2838 dev_dbg(pdata->dev, "mdio addr=%u\n", phy_data->mdio_addr); 2839 } 2840 2841 reg = XP_IOREAD(pdata, XP_PROP_4); 2842 phy_data->redrv = XP_GET_BITS(reg, XP_PROP_4, REDRV_PRESENT); 2843 phy_data->redrv_if = XP_GET_BITS(reg, XP_PROP_4, REDRV_IF); 2844 phy_data->redrv_addr = XP_GET_BITS(reg, XP_PROP_4, REDRV_ADDR); 2845 phy_data->redrv_lane = XP_GET_BITS(reg, XP_PROP_4, REDRV_LANE); 2846 phy_data->redrv_model = XP_GET_BITS(reg, XP_PROP_4, REDRV_MODEL); 2847 if (phy_data->redrv && netif_msg_probe(pdata)) { 2848 dev_dbg(pdata->dev, "redrv present\n"); 2849 dev_dbg(pdata->dev, "redrv i/f=%u\n", phy_data->redrv_if); 2850 dev_dbg(pdata->dev, "redrv addr=%#x\n", phy_data->redrv_addr); 2851 dev_dbg(pdata->dev, "redrv lane=%u\n", phy_data->redrv_lane); 2852 dev_dbg(pdata->dev, "redrv model=%u\n", phy_data->redrv_model); 2853 } 2854 2855 /* Validate the connection requested */ 2856 if (xgbe_phy_conn_type_mismatch(pdata)) { 2857 dev_err(pdata->dev, "phy mode/connection mismatch (%#x/%#x)\n", 2858 phy_data->port_mode, phy_data->conn_type); 2859 return -EINVAL; 2860 } 2861 2862 /* Validate the mode requested */ 2863 if (xgbe_phy_port_mode_mismatch(pdata)) { 2864 dev_err(pdata->dev, "phy mode/speed mismatch (%#x/%#x)\n", 2865 phy_data->port_mode, phy_data->port_speeds); 2866 return -EINVAL; 2867 } 2868 2869 /* Check for and validate MDIO reset support */ 2870 ret = xgbe_phy_mdio_reset_setup(pdata); 2871 if (ret) 2872 return ret; 2873 2874 /* Validate the re-driver information */ 2875 if (xgbe_phy_redrv_error(phy_data)) { 2876 dev_err(pdata->dev, "phy re-driver settings error\n"); 2877 return -EINVAL; 2878 } 2879 pdata->kr_redrv = phy_data->redrv; 2880 2881 /* Indicate current mode is unknown */ 2882 phy_data->cur_mode = XGBE_MODE_UNKNOWN; 2883 2884 /* Initialize supported features */ 2885 pdata->phy.supported = 0; 2886 2887 switch (phy_data->port_mode) { 2888 /* Backplane support */ 2889 case XGBE_PORT_MODE_BACKPLANE: 2890 pdata->phy.supported |= SUPPORTED_Autoneg; 2891 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2892 pdata->phy.supported |= SUPPORTED_Backplane; 2893 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) { 2894 pdata->phy.supported |= SUPPORTED_1000baseKX_Full; 2895 phy_data->start_mode = XGBE_MODE_KX_1000; 2896 } 2897 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) { 2898 pdata->phy.supported |= SUPPORTED_10000baseKR_Full; 2899 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 2900 pdata->phy.supported |= 2901 SUPPORTED_10000baseR_FEC; 2902 phy_data->start_mode = XGBE_MODE_KR; 2903 } 2904 2905 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE; 2906 break; 2907 case XGBE_PORT_MODE_BACKPLANE_2500: 2908 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2909 pdata->phy.supported |= SUPPORTED_Backplane; 2910 pdata->phy.supported |= SUPPORTED_2500baseX_Full; 2911 phy_data->start_mode = XGBE_MODE_KX_2500; 2912 2913 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE; 2914 break; 2915 2916 /* MDIO 1GBase-T support */ 2917 case XGBE_PORT_MODE_1000BASE_T: 2918 pdata->phy.supported |= SUPPORTED_Autoneg; 2919 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2920 pdata->phy.supported |= SUPPORTED_TP; 2921 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) { 2922 pdata->phy.supported |= SUPPORTED_100baseT_Full; 2923 phy_data->start_mode = XGBE_MODE_SGMII_100; 2924 } 2925 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) { 2926 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 2927 phy_data->start_mode = XGBE_MODE_SGMII_1000; 2928 } 2929 2930 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22; 2931 break; 2932 2933 /* MDIO Base-X support */ 2934 case XGBE_PORT_MODE_1000BASE_X: 2935 pdata->phy.supported |= SUPPORTED_Autoneg; 2936 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2937 pdata->phy.supported |= SUPPORTED_FIBRE; 2938 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 2939 phy_data->start_mode = XGBE_MODE_X; 2940 2941 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22; 2942 break; 2943 2944 /* MDIO NBase-T support */ 2945 case XGBE_PORT_MODE_NBASE_T: 2946 pdata->phy.supported |= SUPPORTED_Autoneg; 2947 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2948 pdata->phy.supported |= SUPPORTED_TP; 2949 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) { 2950 pdata->phy.supported |= SUPPORTED_100baseT_Full; 2951 phy_data->start_mode = XGBE_MODE_SGMII_100; 2952 } 2953 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) { 2954 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 2955 phy_data->start_mode = XGBE_MODE_SGMII_1000; 2956 } 2957 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500) { 2958 pdata->phy.supported |= SUPPORTED_2500baseX_Full; 2959 phy_data->start_mode = XGBE_MODE_KX_2500; 2960 } 2961 2962 phy_data->phydev_mode = XGBE_MDIO_MODE_CL45; 2963 break; 2964 2965 /* 10GBase-T support */ 2966 case XGBE_PORT_MODE_10GBASE_T: 2967 pdata->phy.supported |= SUPPORTED_Autoneg; 2968 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2969 pdata->phy.supported |= SUPPORTED_TP; 2970 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) { 2971 pdata->phy.supported |= SUPPORTED_100baseT_Full; 2972 phy_data->start_mode = XGBE_MODE_SGMII_100; 2973 } 2974 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) { 2975 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 2976 phy_data->start_mode = XGBE_MODE_SGMII_1000; 2977 } 2978 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) { 2979 pdata->phy.supported |= SUPPORTED_10000baseT_Full; 2980 phy_data->start_mode = XGBE_MODE_KR; 2981 } 2982 2983 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE; 2984 break; 2985 2986 /* 10GBase-R support */ 2987 case XGBE_PORT_MODE_10GBASE_R: 2988 pdata->phy.supported |= SUPPORTED_Autoneg; 2989 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2990 pdata->phy.supported |= SUPPORTED_TP; 2991 pdata->phy.supported |= SUPPORTED_10000baseT_Full; 2992 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 2993 pdata->phy.supported |= SUPPORTED_10000baseR_FEC; 2994 phy_data->start_mode = XGBE_MODE_SFI; 2995 2996 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE; 2997 break; 2998 2999 /* SFP support */ 3000 case XGBE_PORT_MODE_SFP: 3001 pdata->phy.supported |= SUPPORTED_Autoneg; 3002 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 3003 pdata->phy.supported |= SUPPORTED_TP; 3004 pdata->phy.supported |= SUPPORTED_FIBRE; 3005 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) { 3006 pdata->phy.supported |= SUPPORTED_100baseT_Full; 3007 phy_data->start_mode = XGBE_MODE_SGMII_100; 3008 } 3009 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) { 3010 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 3011 phy_data->start_mode = XGBE_MODE_SGMII_1000; 3012 } 3013 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) { 3014 pdata->phy.supported |= SUPPORTED_10000baseT_Full; 3015 phy_data->start_mode = XGBE_MODE_SFI; 3016 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 3017 pdata->phy.supported |= 3018 SUPPORTED_10000baseR_FEC; 3019 } 3020 3021 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22; 3022 3023 xgbe_phy_sfp_setup(pdata); 3024 break; 3025 default: 3026 return -EINVAL; 3027 } 3028 3029 if (netif_msg_probe(pdata)) 3030 dev_dbg(pdata->dev, "phy supported=%#x\n", 3031 pdata->phy.supported); 3032 3033 if ((phy_data->conn_type & XGBE_CONN_TYPE_MDIO) && 3034 (phy_data->phydev_mode != XGBE_MDIO_MODE_NONE)) { 3035 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr, 3036 phy_data->phydev_mode); 3037 if (ret) { 3038 dev_err(pdata->dev, 3039 "mdio port/clause not compatible (%d/%u)\n", 3040 phy_data->mdio_addr, phy_data->phydev_mode); 3041 return -EINVAL; 3042 } 3043 } 3044 3045 if (phy_data->redrv && !phy_data->redrv_if) { 3046 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr, 3047 XGBE_MDIO_MODE_CL22); 3048 if (ret) { 3049 dev_err(pdata->dev, 3050 "redriver mdio port not compatible (%u)\n", 3051 phy_data->redrv_addr); 3052 return -EINVAL; 3053 } 3054 } 3055 3056 /* Register for driving external PHYs */ 3057 mii = devm_mdiobus_alloc(pdata->dev); 3058 if (!mii) { 3059 dev_err(pdata->dev, "mdiobus_alloc failed\n"); 3060 return -ENOMEM; 3061 } 3062 3063 mii->priv = pdata; 3064 mii->name = "amd-xgbe-mii"; 3065 mii->read = xgbe_phy_mii_read; 3066 mii->write = xgbe_phy_mii_write; 3067 mii->parent = pdata->dev; 3068 mii->phy_mask = ~0; 3069 snprintf(mii->id, sizeof(mii->id), "%s", dev_name(pdata->dev)); 3070 ret = mdiobus_register(mii); 3071 if (ret) { 3072 dev_err(pdata->dev, "mdiobus_register failed\n"); 3073 return ret; 3074 } 3075 phy_data->mii = mii; 3076 3077 return 0; 3078 } 3079 3080 void xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if *phy_if) 3081 { 3082 struct xgbe_phy_impl_if *phy_impl = &phy_if->phy_impl; 3083 3084 phy_impl->init = xgbe_phy_init; 3085 phy_impl->exit = xgbe_phy_exit; 3086 3087 phy_impl->reset = xgbe_phy_reset; 3088 phy_impl->start = xgbe_phy_start; 3089 phy_impl->stop = xgbe_phy_stop; 3090 3091 phy_impl->link_status = xgbe_phy_link_status; 3092 3093 phy_impl->valid_speed = xgbe_phy_valid_speed; 3094 3095 phy_impl->use_mode = xgbe_phy_use_mode; 3096 phy_impl->set_mode = xgbe_phy_set_mode; 3097 phy_impl->get_mode = xgbe_phy_get_mode; 3098 phy_impl->switch_mode = xgbe_phy_switch_mode; 3099 phy_impl->cur_mode = xgbe_phy_cur_mode; 3100 3101 phy_impl->an_mode = xgbe_phy_an_mode; 3102 3103 phy_impl->an_config = xgbe_phy_an_config; 3104 3105 phy_impl->an_advertising = xgbe_phy_an_advertising; 3106 3107 phy_impl->an_outcome = xgbe_phy_an_outcome; 3108 } 3109