1 /*
2  * AMD 10Gb Ethernet driver
3  *
4  * This file is available to you under your choice of the following two
5  * licenses:
6  *
7  * License 1: GPLv2
8  *
9  * Copyright (c) 2016 Advanced Micro Devices, Inc.
10  *
11  * This file is free software; you may copy, redistribute and/or modify
12  * it under the terms of the GNU General Public License as published by
13  * the Free Software Foundation, either version 2 of the License, or (at
14  * your option) any later version.
15  *
16  * This file is distributed in the hope that it will be useful, but
17  * WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19  * General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
23  *
24  * This file incorporates work covered by the following copyright and
25  * permission notice:
26  *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
27  *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28  *     Inc. unless otherwise expressly agreed to in writing between Synopsys
29  *     and you.
30  *
31  *     The Software IS NOT an item of Licensed Software or Licensed Product
32  *     under any End User Software License Agreement or Agreement for Licensed
33  *     Product with Synopsys or any supplement thereto.  Permission is hereby
34  *     granted, free of charge, to any person obtaining a copy of this software
35  *     annotated with this license and the Software, to deal in the Software
36  *     without restriction, including without limitation the rights to use,
37  *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38  *     of the Software, and to permit persons to whom the Software is furnished
39  *     to do so, subject to the following conditions:
40  *
41  *     The above copyright notice and this permission notice shall be included
42  *     in all copies or substantial portions of the Software.
43  *
44  *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45  *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46  *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47  *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48  *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49  *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50  *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51  *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52  *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53  *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54  *     THE POSSIBILITY OF SUCH DAMAGE.
55  *
56  *
57  * License 2: Modified BSD
58  *
59  * Copyright (c) 2016 Advanced Micro Devices, Inc.
60  * All rights reserved.
61  *
62  * Redistribution and use in source and binary forms, with or without
63  * modification, are permitted provided that the following conditions are met:
64  *     * Redistributions of source code must retain the above copyright
65  *       notice, this list of conditions and the following disclaimer.
66  *     * Redistributions in binary form must reproduce the above copyright
67  *       notice, this list of conditions and the following disclaimer in the
68  *       documentation and/or other materials provided with the distribution.
69  *     * Neither the name of Advanced Micro Devices, Inc. nor the
70  *       names of its contributors may be used to endorse or promote products
71  *       derived from this software without specific prior written permission.
72  *
73  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76  * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
83  *
84  * This file incorporates work covered by the following copyright and
85  * permission notice:
86  *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
87  *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88  *     Inc. unless otherwise expressly agreed to in writing between Synopsys
89  *     and you.
90  *
91  *     The Software IS NOT an item of Licensed Software or Licensed Product
92  *     under any End User Software License Agreement or Agreement for Licensed
93  *     Product with Synopsys or any supplement thereto.  Permission is hereby
94  *     granted, free of charge, to any person obtaining a copy of this software
95  *     annotated with this license and the Software, to deal in the Software
96  *     without restriction, including without limitation the rights to use,
97  *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98  *     of the Software, and to permit persons to whom the Software is furnished
99  *     to do so, subject to the following conditions:
100  *
101  *     The above copyright notice and this permission notice shall be included
102  *     in all copies or substantial portions of the Software.
103  *
104  *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105  *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106  *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107  *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108  *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109  *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110  *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111  *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112  *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113  *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114  *     THE POSSIBILITY OF SUCH DAMAGE.
115  */
116 
117 #include <linux/module.h>
118 #include <linux/device.h>
119 #include <linux/kmod.h>
120 #include <linux/mdio.h>
121 #include <linux/phy.h>
122 #include <linux/ethtool.h>
123 
124 #include "xgbe.h"
125 #include "xgbe-common.h"
126 
127 #define XGBE_PHY_PORT_SPEED_10		BIT(0)
128 #define XGBE_PHY_PORT_SPEED_100		BIT(1)
129 #define XGBE_PHY_PORT_SPEED_1000	BIT(2)
130 #define XGBE_PHY_PORT_SPEED_2500	BIT(3)
131 #define XGBE_PHY_PORT_SPEED_10000	BIT(4)
132 
133 #define XGBE_MUTEX_RELEASE		0x80000000
134 
135 #define XGBE_SFP_DIRECT			7
136 
137 /* I2C target addresses */
138 #define XGBE_SFP_SERIAL_ID_ADDRESS	0x50
139 #define XGBE_SFP_DIAG_INFO_ADDRESS	0x51
140 #define XGBE_SFP_PHY_ADDRESS		0x56
141 #define XGBE_GPIO_ADDRESS_PCA9555	0x20
142 
143 /* SFP sideband signal indicators */
144 #define XGBE_GPIO_NO_TX_FAULT		BIT(0)
145 #define XGBE_GPIO_NO_RATE_SELECT	BIT(1)
146 #define XGBE_GPIO_NO_MOD_ABSENT		BIT(2)
147 #define XGBE_GPIO_NO_RX_LOS		BIT(3)
148 
149 /* Rate-change complete wait/retry count */
150 #define XGBE_RATECHANGE_COUNT		500
151 
152 /* CDR delay values for KR support (in usec) */
153 #define XGBE_CDR_DELAY_INIT		10000
154 #define XGBE_CDR_DELAY_INC		10000
155 #define XGBE_CDR_DELAY_MAX		100000
156 
157 /* RRC frequency during link status check */
158 #define XGBE_RRC_FREQUENCY		10
159 
160 enum xgbe_port_mode {
161 	XGBE_PORT_MODE_RSVD = 0,
162 	XGBE_PORT_MODE_BACKPLANE,
163 	XGBE_PORT_MODE_BACKPLANE_2500,
164 	XGBE_PORT_MODE_1000BASE_T,
165 	XGBE_PORT_MODE_1000BASE_X,
166 	XGBE_PORT_MODE_NBASE_T,
167 	XGBE_PORT_MODE_10GBASE_T,
168 	XGBE_PORT_MODE_10GBASE_R,
169 	XGBE_PORT_MODE_SFP,
170 	XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG,
171 	XGBE_PORT_MODE_MAX,
172 };
173 
174 enum xgbe_conn_type {
175 	XGBE_CONN_TYPE_NONE = 0,
176 	XGBE_CONN_TYPE_SFP,
177 	XGBE_CONN_TYPE_MDIO,
178 	XGBE_CONN_TYPE_RSVD1,
179 	XGBE_CONN_TYPE_BACKPLANE,
180 	XGBE_CONN_TYPE_MAX,
181 };
182 
183 /* SFP/SFP+ related definitions */
184 enum xgbe_sfp_comm {
185 	XGBE_SFP_COMM_DIRECT = 0,
186 	XGBE_SFP_COMM_PCA9545,
187 };
188 
189 enum xgbe_sfp_cable {
190 	XGBE_SFP_CABLE_UNKNOWN = 0,
191 	XGBE_SFP_CABLE_ACTIVE,
192 	XGBE_SFP_CABLE_PASSIVE,
193 	XGBE_SFP_CABLE_FIBER,
194 };
195 
196 enum xgbe_sfp_base {
197 	XGBE_SFP_BASE_UNKNOWN = 0,
198 	XGBE_SFP_BASE_1000_T,
199 	XGBE_SFP_BASE_1000_SX,
200 	XGBE_SFP_BASE_1000_LX,
201 	XGBE_SFP_BASE_1000_CX,
202 	XGBE_SFP_BASE_10000_SR,
203 	XGBE_SFP_BASE_10000_LR,
204 	XGBE_SFP_BASE_10000_LRM,
205 	XGBE_SFP_BASE_10000_ER,
206 	XGBE_SFP_BASE_10000_CR,
207 };
208 
209 enum xgbe_sfp_speed {
210 	XGBE_SFP_SPEED_UNKNOWN = 0,
211 	XGBE_SFP_SPEED_100_1000,
212 	XGBE_SFP_SPEED_1000,
213 	XGBE_SFP_SPEED_10000,
214 };
215 
216 /* SFP Serial ID Base ID values relative to an offset of 0 */
217 #define XGBE_SFP_BASE_ID			0
218 #define XGBE_SFP_ID_SFP				0x03
219 
220 #define XGBE_SFP_BASE_EXT_ID			1
221 #define XGBE_SFP_EXT_ID_SFP			0x04
222 
223 #define XGBE_SFP_BASE_10GBE_CC			3
224 #define XGBE_SFP_BASE_10GBE_CC_SR		BIT(4)
225 #define XGBE_SFP_BASE_10GBE_CC_LR		BIT(5)
226 #define XGBE_SFP_BASE_10GBE_CC_LRM		BIT(6)
227 #define XGBE_SFP_BASE_10GBE_CC_ER		BIT(7)
228 
229 #define XGBE_SFP_BASE_1GBE_CC			6
230 #define XGBE_SFP_BASE_1GBE_CC_SX		BIT(0)
231 #define XGBE_SFP_BASE_1GBE_CC_LX		BIT(1)
232 #define XGBE_SFP_BASE_1GBE_CC_CX		BIT(2)
233 #define XGBE_SFP_BASE_1GBE_CC_T			BIT(3)
234 
235 #define XGBE_SFP_BASE_CABLE			8
236 #define XGBE_SFP_BASE_CABLE_PASSIVE		BIT(2)
237 #define XGBE_SFP_BASE_CABLE_ACTIVE		BIT(3)
238 
239 #define XGBE_SFP_BASE_BR			12
240 #define XGBE_SFP_BASE_BR_1GBE_MIN		0x0a
241 #define XGBE_SFP_BASE_BR_10GBE_MIN		0x64
242 
243 #define XGBE_SFP_BASE_CU_CABLE_LEN		18
244 
245 #define XGBE_SFP_BASE_VENDOR_NAME		20
246 #define XGBE_SFP_BASE_VENDOR_NAME_LEN		16
247 #define XGBE_SFP_BASE_VENDOR_PN			40
248 #define XGBE_SFP_BASE_VENDOR_PN_LEN		16
249 #define XGBE_SFP_BASE_VENDOR_REV		56
250 #define XGBE_SFP_BASE_VENDOR_REV_LEN		4
251 
252 #define XGBE_SFP_BASE_CC			63
253 
254 /* SFP Serial ID Extended ID values relative to an offset of 64 */
255 #define XGBE_SFP_BASE_VENDOR_SN			4
256 #define XGBE_SFP_BASE_VENDOR_SN_LEN		16
257 
258 #define XGBE_SFP_EXTD_OPT1			1
259 #define XGBE_SFP_EXTD_OPT1_RX_LOS		BIT(1)
260 #define XGBE_SFP_EXTD_OPT1_TX_FAULT		BIT(3)
261 
262 #define XGBE_SFP_EXTD_DIAG			28
263 #define XGBE_SFP_EXTD_DIAG_ADDR_CHANGE		BIT(2)
264 
265 #define XGBE_SFP_EXTD_SFF_8472			30
266 
267 #define XGBE_SFP_EXTD_CC			31
268 
269 struct xgbe_sfp_eeprom {
270 	u8 base[64];
271 	u8 extd[32];
272 	u8 vendor[32];
273 };
274 
275 #define XGBE_SFP_DIAGS_SUPPORTED(_x)			\
276 	((_x)->extd[XGBE_SFP_EXTD_SFF_8472] &&		\
277 	 !((_x)->extd[XGBE_SFP_EXTD_DIAG] & XGBE_SFP_EXTD_DIAG_ADDR_CHANGE))
278 
279 #define XGBE_SFP_EEPROM_BASE_LEN	256
280 #define XGBE_SFP_EEPROM_DIAG_LEN	256
281 #define XGBE_SFP_EEPROM_MAX		(XGBE_SFP_EEPROM_BASE_LEN +	\
282 					 XGBE_SFP_EEPROM_DIAG_LEN)
283 
284 #define XGBE_BEL_FUSE_VENDOR	"BEL-FUSE        "
285 #define XGBE_BEL_FUSE_PARTNO	"1GBT-SFP06      "
286 
287 #define XGBE_MOLEX_VENDOR	"Molex Inc.      "
288 
289 struct xgbe_sfp_ascii {
290 	union {
291 		char vendor[XGBE_SFP_BASE_VENDOR_NAME_LEN + 1];
292 		char partno[XGBE_SFP_BASE_VENDOR_PN_LEN + 1];
293 		char rev[XGBE_SFP_BASE_VENDOR_REV_LEN + 1];
294 		char serno[XGBE_SFP_BASE_VENDOR_SN_LEN + 1];
295 	} u;
296 };
297 
298 /* MDIO PHY reset types */
299 enum xgbe_mdio_reset {
300 	XGBE_MDIO_RESET_NONE = 0,
301 	XGBE_MDIO_RESET_I2C_GPIO,
302 	XGBE_MDIO_RESET_INT_GPIO,
303 	XGBE_MDIO_RESET_MAX,
304 };
305 
306 /* Re-driver related definitions */
307 enum xgbe_phy_redrv_if {
308 	XGBE_PHY_REDRV_IF_MDIO = 0,
309 	XGBE_PHY_REDRV_IF_I2C,
310 	XGBE_PHY_REDRV_IF_MAX,
311 };
312 
313 enum xgbe_phy_redrv_model {
314 	XGBE_PHY_REDRV_MODEL_4223 = 0,
315 	XGBE_PHY_REDRV_MODEL_4227,
316 	XGBE_PHY_REDRV_MODEL_MAX,
317 };
318 
319 enum xgbe_phy_redrv_mode {
320 	XGBE_PHY_REDRV_MODE_CX = 5,
321 	XGBE_PHY_REDRV_MODE_SR = 9,
322 };
323 
324 #define XGBE_PHY_REDRV_MODE_REG	0x12b0
325 
326 /* PHY related configuration information */
327 struct xgbe_phy_data {
328 	enum xgbe_port_mode port_mode;
329 
330 	unsigned int port_id;
331 
332 	unsigned int port_speeds;
333 
334 	enum xgbe_conn_type conn_type;
335 
336 	enum xgbe_mode cur_mode;
337 	enum xgbe_mode start_mode;
338 
339 	unsigned int rrc_count;
340 
341 	unsigned int mdio_addr;
342 
343 	/* SFP Support */
344 	enum xgbe_sfp_comm sfp_comm;
345 	unsigned int sfp_mux_address;
346 	unsigned int sfp_mux_channel;
347 
348 	unsigned int sfp_gpio_address;
349 	unsigned int sfp_gpio_mask;
350 	unsigned int sfp_gpio_inputs;
351 	unsigned int sfp_gpio_rx_los;
352 	unsigned int sfp_gpio_tx_fault;
353 	unsigned int sfp_gpio_mod_absent;
354 	unsigned int sfp_gpio_rate_select;
355 
356 	unsigned int sfp_rx_los;
357 	unsigned int sfp_tx_fault;
358 	unsigned int sfp_mod_absent;
359 	unsigned int sfp_changed;
360 	unsigned int sfp_phy_avail;
361 	unsigned int sfp_cable_len;
362 	enum xgbe_sfp_base sfp_base;
363 	enum xgbe_sfp_cable sfp_cable;
364 	enum xgbe_sfp_speed sfp_speed;
365 	struct xgbe_sfp_eeprom sfp_eeprom;
366 
367 	/* External PHY support */
368 	enum xgbe_mdio_mode phydev_mode;
369 	struct mii_bus *mii;
370 	struct phy_device *phydev;
371 	enum xgbe_mdio_reset mdio_reset;
372 	unsigned int mdio_reset_addr;
373 	unsigned int mdio_reset_gpio;
374 
375 	/* Re-driver support */
376 	unsigned int redrv;
377 	unsigned int redrv_if;
378 	unsigned int redrv_addr;
379 	unsigned int redrv_lane;
380 	unsigned int redrv_model;
381 
382 	/* KR AN support */
383 	unsigned int phy_cdr_notrack;
384 	unsigned int phy_cdr_delay;
385 };
386 
387 /* I2C, MDIO and GPIO lines are muxed, so only one device at a time */
388 static DEFINE_MUTEX(xgbe_phy_comm_lock);
389 
390 static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata);
391 static void xgbe_phy_rrc(struct xgbe_prv_data *pdata);
392 static void xgbe_phy_perform_ratechange(struct xgbe_prv_data *pdata,
393 					enum xgbe_mb_cmd cmd,
394 					enum xgbe_mb_subcmd sub_cmd);
395 
396 static int xgbe_phy_i2c_xfer(struct xgbe_prv_data *pdata,
397 			     struct xgbe_i2c_op *i2c_op)
398 {
399 	return pdata->i2c_if.i2c_xfer(pdata, i2c_op);
400 }
401 
402 static int xgbe_phy_redrv_write(struct xgbe_prv_data *pdata, unsigned int reg,
403 				unsigned int val)
404 {
405 	struct xgbe_phy_data *phy_data = pdata->phy_data;
406 	struct xgbe_i2c_op i2c_op;
407 	__be16 *redrv_val;
408 	u8 redrv_data[5], csum;
409 	unsigned int i, retry;
410 	int ret;
411 
412 	/* High byte of register contains read/write indicator */
413 	redrv_data[0] = ((reg >> 8) & 0xff) << 1;
414 	redrv_data[1] = reg & 0xff;
415 	redrv_val = (__be16 *)&redrv_data[2];
416 	*redrv_val = cpu_to_be16(val);
417 
418 	/* Calculate 1 byte checksum */
419 	csum = 0;
420 	for (i = 0; i < 4; i++) {
421 		csum += redrv_data[i];
422 		if (redrv_data[i] > csum)
423 			csum++;
424 	}
425 	redrv_data[4] = ~csum;
426 
427 	retry = 1;
428 again1:
429 	i2c_op.cmd = XGBE_I2C_CMD_WRITE;
430 	i2c_op.target = phy_data->redrv_addr;
431 	i2c_op.len = sizeof(redrv_data);
432 	i2c_op.buf = redrv_data;
433 	ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
434 	if (ret) {
435 		if ((ret == -EAGAIN) && retry--)
436 			goto again1;
437 
438 		return ret;
439 	}
440 
441 	retry = 1;
442 again2:
443 	i2c_op.cmd = XGBE_I2C_CMD_READ;
444 	i2c_op.target = phy_data->redrv_addr;
445 	i2c_op.len = 1;
446 	i2c_op.buf = redrv_data;
447 	ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
448 	if (ret) {
449 		if ((ret == -EAGAIN) && retry--)
450 			goto again2;
451 
452 		return ret;
453 	}
454 
455 	if (redrv_data[0] != 0xff) {
456 		netif_dbg(pdata, drv, pdata->netdev,
457 			  "Redriver write checksum error\n");
458 		ret = -EIO;
459 	}
460 
461 	return ret;
462 }
463 
464 static int xgbe_phy_i2c_write(struct xgbe_prv_data *pdata, unsigned int target,
465 			      void *val, unsigned int val_len)
466 {
467 	struct xgbe_i2c_op i2c_op;
468 	int retry, ret;
469 
470 	retry = 1;
471 again:
472 	/* Write the specfied register */
473 	i2c_op.cmd = XGBE_I2C_CMD_WRITE;
474 	i2c_op.target = target;
475 	i2c_op.len = val_len;
476 	i2c_op.buf = val;
477 	ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
478 	if ((ret == -EAGAIN) && retry--)
479 		goto again;
480 
481 	return ret;
482 }
483 
484 static int xgbe_phy_i2c_read(struct xgbe_prv_data *pdata, unsigned int target,
485 			     void *reg, unsigned int reg_len,
486 			     void *val, unsigned int val_len)
487 {
488 	struct xgbe_i2c_op i2c_op;
489 	int retry, ret;
490 
491 	retry = 1;
492 again1:
493 	/* Set the specified register to read */
494 	i2c_op.cmd = XGBE_I2C_CMD_WRITE;
495 	i2c_op.target = target;
496 	i2c_op.len = reg_len;
497 	i2c_op.buf = reg;
498 	ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
499 	if (ret) {
500 		if ((ret == -EAGAIN) && retry--)
501 			goto again1;
502 
503 		return ret;
504 	}
505 
506 	retry = 1;
507 again2:
508 	/* Read the specfied register */
509 	i2c_op.cmd = XGBE_I2C_CMD_READ;
510 	i2c_op.target = target;
511 	i2c_op.len = val_len;
512 	i2c_op.buf = val;
513 	ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
514 	if ((ret == -EAGAIN) && retry--)
515 		goto again2;
516 
517 	return ret;
518 }
519 
520 static int xgbe_phy_sfp_put_mux(struct xgbe_prv_data *pdata)
521 {
522 	struct xgbe_phy_data *phy_data = pdata->phy_data;
523 	struct xgbe_i2c_op i2c_op;
524 	u8 mux_channel;
525 
526 	if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT)
527 		return 0;
528 
529 	/* Select no mux channels */
530 	mux_channel = 0;
531 	i2c_op.cmd = XGBE_I2C_CMD_WRITE;
532 	i2c_op.target = phy_data->sfp_mux_address;
533 	i2c_op.len = sizeof(mux_channel);
534 	i2c_op.buf = &mux_channel;
535 
536 	return xgbe_phy_i2c_xfer(pdata, &i2c_op);
537 }
538 
539 static int xgbe_phy_sfp_get_mux(struct xgbe_prv_data *pdata)
540 {
541 	struct xgbe_phy_data *phy_data = pdata->phy_data;
542 	struct xgbe_i2c_op i2c_op;
543 	u8 mux_channel;
544 
545 	if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT)
546 		return 0;
547 
548 	/* Select desired mux channel */
549 	mux_channel = 1 << phy_data->sfp_mux_channel;
550 	i2c_op.cmd = XGBE_I2C_CMD_WRITE;
551 	i2c_op.target = phy_data->sfp_mux_address;
552 	i2c_op.len = sizeof(mux_channel);
553 	i2c_op.buf = &mux_channel;
554 
555 	return xgbe_phy_i2c_xfer(pdata, &i2c_op);
556 }
557 
558 static void xgbe_phy_put_comm_ownership(struct xgbe_prv_data *pdata)
559 {
560 	mutex_unlock(&xgbe_phy_comm_lock);
561 }
562 
563 static int xgbe_phy_get_comm_ownership(struct xgbe_prv_data *pdata)
564 {
565 	struct xgbe_phy_data *phy_data = pdata->phy_data;
566 	unsigned long timeout;
567 	unsigned int mutex_id;
568 
569 	/* The I2C and MDIO/GPIO bus is multiplexed between multiple devices,
570 	 * the driver needs to take the software mutex and then the hardware
571 	 * mutexes before being able to use the busses.
572 	 */
573 	mutex_lock(&xgbe_phy_comm_lock);
574 
575 	/* Clear the mutexes */
576 	XP_IOWRITE(pdata, XP_I2C_MUTEX, XGBE_MUTEX_RELEASE);
577 	XP_IOWRITE(pdata, XP_MDIO_MUTEX, XGBE_MUTEX_RELEASE);
578 
579 	/* Mutex formats are the same for I2C and MDIO/GPIO */
580 	mutex_id = 0;
581 	XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ID, phy_data->port_id);
582 	XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ACTIVE, 1);
583 
584 	timeout = jiffies + (5 * HZ);
585 	while (time_before(jiffies, timeout)) {
586 		/* Must be all zeroes in order to obtain the mutex */
587 		if (XP_IOREAD(pdata, XP_I2C_MUTEX) ||
588 		    XP_IOREAD(pdata, XP_MDIO_MUTEX)) {
589 			usleep_range(100, 200);
590 			continue;
591 		}
592 
593 		/* Obtain the mutex */
594 		XP_IOWRITE(pdata, XP_I2C_MUTEX, mutex_id);
595 		XP_IOWRITE(pdata, XP_MDIO_MUTEX, mutex_id);
596 
597 		return 0;
598 	}
599 
600 	mutex_unlock(&xgbe_phy_comm_lock);
601 
602 	netdev_err(pdata->netdev, "unable to obtain hardware mutexes\n");
603 
604 	return -ETIMEDOUT;
605 }
606 
607 static int xgbe_phy_mdio_mii_write_c22(struct xgbe_prv_data *pdata, int addr,
608 				       int reg, u16 val)
609 {
610 	struct xgbe_phy_data *phy_data = pdata->phy_data;
611 
612 	if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22)
613 		return -EOPNOTSUPP;
614 
615 	return pdata->hw_if.write_ext_mii_regs_c22(pdata, addr, reg, val);
616 }
617 
618 static int xgbe_phy_mdio_mii_write_c45(struct xgbe_prv_data *pdata, int addr,
619 				       int devad, int reg, u16 val)
620 {
621 	struct xgbe_phy_data *phy_data = pdata->phy_data;
622 
623 	if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45)
624 		return -EOPNOTSUPP;
625 
626 	return pdata->hw_if.write_ext_mii_regs_c45(pdata, addr, devad,
627 						   reg, val);
628 }
629 
630 static int xgbe_phy_i2c_mii_write(struct xgbe_prv_data *pdata, int reg, u16 val)
631 {
632 	__be16 *mii_val;
633 	u8 mii_data[3];
634 	int ret;
635 
636 	ret = xgbe_phy_sfp_get_mux(pdata);
637 	if (ret)
638 		return ret;
639 
640 	mii_data[0] = reg & 0xff;
641 	mii_val = (__be16 *)&mii_data[1];
642 	*mii_val = cpu_to_be16(val);
643 
644 	ret = xgbe_phy_i2c_write(pdata, XGBE_SFP_PHY_ADDRESS,
645 				 mii_data, sizeof(mii_data));
646 
647 	xgbe_phy_sfp_put_mux(pdata);
648 
649 	return ret;
650 }
651 
652 static int xgbe_phy_mii_write_c22(struct mii_bus *mii, int addr, int reg,
653 				  u16 val)
654 {
655 	struct xgbe_prv_data *pdata = mii->priv;
656 	struct xgbe_phy_data *phy_data = pdata->phy_data;
657 	int ret;
658 
659 	ret = xgbe_phy_get_comm_ownership(pdata);
660 	if (ret)
661 		return ret;
662 
663 	if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
664 		ret = xgbe_phy_i2c_mii_write(pdata, reg, val);
665 	else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO)
666 		ret = xgbe_phy_mdio_mii_write_c22(pdata, addr, reg, val);
667 	else
668 		ret = -EOPNOTSUPP;
669 
670 	xgbe_phy_put_comm_ownership(pdata);
671 
672 	return ret;
673 }
674 
675 static int xgbe_phy_mii_write_c45(struct mii_bus *mii, int addr, int devad,
676 				  int reg, u16 val)
677 {
678 	struct xgbe_prv_data *pdata = mii->priv;
679 	struct xgbe_phy_data *phy_data = pdata->phy_data;
680 	int ret;
681 
682 	ret = xgbe_phy_get_comm_ownership(pdata);
683 	if (ret)
684 		return ret;
685 
686 	if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
687 		ret = -EOPNOTSUPP;
688 	else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO)
689 		ret = xgbe_phy_mdio_mii_write_c45(pdata, addr, devad, reg, val);
690 	else
691 		ret = -EOPNOTSUPP;
692 
693 	xgbe_phy_put_comm_ownership(pdata);
694 
695 	return ret;
696 }
697 
698 static int xgbe_phy_mdio_mii_read_c22(struct xgbe_prv_data *pdata, int addr,
699 				      int reg)
700 {
701 	struct xgbe_phy_data *phy_data = pdata->phy_data;
702 
703 	if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22)
704 		return -EOPNOTSUPP;
705 
706 	return pdata->hw_if.read_ext_mii_regs_c22(pdata, addr, reg);
707 }
708 
709 static int xgbe_phy_mdio_mii_read_c45(struct xgbe_prv_data *pdata, int addr,
710 				      int devad, int reg)
711 {
712 	struct xgbe_phy_data *phy_data = pdata->phy_data;
713 
714 	if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45)
715 		return -EOPNOTSUPP;
716 
717 	return pdata->hw_if.read_ext_mii_regs_c45(pdata, addr, devad, reg);
718 }
719 
720 static int xgbe_phy_i2c_mii_read(struct xgbe_prv_data *pdata, int reg)
721 {
722 	__be16 mii_val;
723 	u8 mii_reg;
724 	int ret;
725 
726 	ret = xgbe_phy_sfp_get_mux(pdata);
727 	if (ret)
728 		return ret;
729 
730 	mii_reg = reg;
731 	ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_PHY_ADDRESS,
732 				&mii_reg, sizeof(mii_reg),
733 				&mii_val, sizeof(mii_val));
734 	if (!ret)
735 		ret = be16_to_cpu(mii_val);
736 
737 	xgbe_phy_sfp_put_mux(pdata);
738 
739 	return ret;
740 }
741 
742 static int xgbe_phy_mii_read_c22(struct mii_bus *mii, int addr, int reg)
743 {
744 	struct xgbe_prv_data *pdata = mii->priv;
745 	struct xgbe_phy_data *phy_data = pdata->phy_data;
746 	int ret;
747 
748 	ret = xgbe_phy_get_comm_ownership(pdata);
749 	if (ret)
750 		return ret;
751 
752 	if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
753 		ret = xgbe_phy_i2c_mii_read(pdata, reg);
754 	else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO)
755 		ret = xgbe_phy_mdio_mii_read_c22(pdata, addr, reg);
756 	else
757 		ret = -EOPNOTSUPP;
758 
759 	xgbe_phy_put_comm_ownership(pdata);
760 
761 	return ret;
762 }
763 
764 static int xgbe_phy_mii_read_c45(struct mii_bus *mii, int addr, int devad,
765 				 int reg)
766 {
767 	struct xgbe_prv_data *pdata = mii->priv;
768 	struct xgbe_phy_data *phy_data = pdata->phy_data;
769 	int ret;
770 
771 	ret = xgbe_phy_get_comm_ownership(pdata);
772 	if (ret)
773 		return ret;
774 
775 	if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
776 		ret = -EOPNOTSUPP;
777 	else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO)
778 		ret = xgbe_phy_mdio_mii_read_c45(pdata, addr, devad, reg);
779 	else
780 		ret = -ENOTSUPP;
781 
782 	xgbe_phy_put_comm_ownership(pdata);
783 
784 	return ret;
785 }
786 
787 static void xgbe_phy_sfp_phy_settings(struct xgbe_prv_data *pdata)
788 {
789 	struct ethtool_link_ksettings *lks = &pdata->phy.lks;
790 	struct xgbe_phy_data *phy_data = pdata->phy_data;
791 
792 	if (!phy_data->sfp_mod_absent && !phy_data->sfp_changed)
793 		return;
794 
795 	XGBE_ZERO_SUP(lks);
796 
797 	if (phy_data->sfp_mod_absent) {
798 		pdata->phy.speed = SPEED_UNKNOWN;
799 		pdata->phy.duplex = DUPLEX_UNKNOWN;
800 		pdata->phy.autoneg = AUTONEG_ENABLE;
801 		pdata->phy.pause_autoneg = AUTONEG_ENABLE;
802 
803 		XGBE_SET_SUP(lks, Autoneg);
804 		XGBE_SET_SUP(lks, Pause);
805 		XGBE_SET_SUP(lks, Asym_Pause);
806 		XGBE_SET_SUP(lks, TP);
807 		XGBE_SET_SUP(lks, FIBRE);
808 
809 		XGBE_LM_COPY(lks, advertising, lks, supported);
810 
811 		return;
812 	}
813 
814 	switch (phy_data->sfp_base) {
815 	case XGBE_SFP_BASE_1000_T:
816 	case XGBE_SFP_BASE_1000_SX:
817 	case XGBE_SFP_BASE_1000_LX:
818 	case XGBE_SFP_BASE_1000_CX:
819 		pdata->phy.speed = SPEED_UNKNOWN;
820 		pdata->phy.duplex = DUPLEX_UNKNOWN;
821 		pdata->phy.autoneg = AUTONEG_ENABLE;
822 		pdata->phy.pause_autoneg = AUTONEG_ENABLE;
823 		XGBE_SET_SUP(lks, Autoneg);
824 		XGBE_SET_SUP(lks, Pause);
825 		XGBE_SET_SUP(lks, Asym_Pause);
826 		if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T) {
827 			if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10)
828 				XGBE_SET_SUP(lks, 10baseT_Full);
829 			if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100)
830 				XGBE_SET_SUP(lks, 100baseT_Full);
831 			if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
832 				XGBE_SET_SUP(lks, 1000baseT_Full);
833 		} else {
834 			if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
835 				XGBE_SET_SUP(lks, 1000baseX_Full);
836 		}
837 		break;
838 	case XGBE_SFP_BASE_10000_SR:
839 	case XGBE_SFP_BASE_10000_LR:
840 	case XGBE_SFP_BASE_10000_LRM:
841 	case XGBE_SFP_BASE_10000_ER:
842 	case XGBE_SFP_BASE_10000_CR:
843 		pdata->phy.speed = SPEED_10000;
844 		pdata->phy.duplex = DUPLEX_FULL;
845 		pdata->phy.autoneg = AUTONEG_DISABLE;
846 		pdata->phy.pause_autoneg = AUTONEG_DISABLE;
847 		if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
848 			switch (phy_data->sfp_base) {
849 			case XGBE_SFP_BASE_10000_SR:
850 				XGBE_SET_SUP(lks, 10000baseSR_Full);
851 				break;
852 			case XGBE_SFP_BASE_10000_LR:
853 				XGBE_SET_SUP(lks, 10000baseLR_Full);
854 				break;
855 			case XGBE_SFP_BASE_10000_LRM:
856 				XGBE_SET_SUP(lks, 10000baseLRM_Full);
857 				break;
858 			case XGBE_SFP_BASE_10000_ER:
859 				XGBE_SET_SUP(lks, 10000baseER_Full);
860 				break;
861 			case XGBE_SFP_BASE_10000_CR:
862 				XGBE_SET_SUP(lks, 10000baseCR_Full);
863 				break;
864 			default:
865 				break;
866 			}
867 		}
868 		break;
869 	default:
870 		pdata->phy.speed = SPEED_UNKNOWN;
871 		pdata->phy.duplex = DUPLEX_UNKNOWN;
872 		pdata->phy.autoneg = AUTONEG_DISABLE;
873 		pdata->phy.pause_autoneg = AUTONEG_DISABLE;
874 		break;
875 	}
876 
877 	switch (phy_data->sfp_base) {
878 	case XGBE_SFP_BASE_1000_T:
879 	case XGBE_SFP_BASE_1000_CX:
880 	case XGBE_SFP_BASE_10000_CR:
881 		XGBE_SET_SUP(lks, TP);
882 		break;
883 	default:
884 		XGBE_SET_SUP(lks, FIBRE);
885 		break;
886 	}
887 
888 	XGBE_LM_COPY(lks, advertising, lks, supported);
889 }
890 
891 static bool xgbe_phy_sfp_bit_rate(struct xgbe_sfp_eeprom *sfp_eeprom,
892 				  enum xgbe_sfp_speed sfp_speed)
893 {
894 	u8 *sfp_base, min;
895 
896 	sfp_base = sfp_eeprom->base;
897 
898 	switch (sfp_speed) {
899 	case XGBE_SFP_SPEED_1000:
900 		min = XGBE_SFP_BASE_BR_1GBE_MIN;
901 		break;
902 	case XGBE_SFP_SPEED_10000:
903 		min = XGBE_SFP_BASE_BR_10GBE_MIN;
904 		break;
905 	default:
906 		return false;
907 	}
908 
909 	return sfp_base[XGBE_SFP_BASE_BR] >= min;
910 }
911 
912 static void xgbe_phy_free_phy_device(struct xgbe_prv_data *pdata)
913 {
914 	struct xgbe_phy_data *phy_data = pdata->phy_data;
915 
916 	if (phy_data->phydev) {
917 		phy_detach(phy_data->phydev);
918 		phy_device_remove(phy_data->phydev);
919 		phy_device_free(phy_data->phydev);
920 		phy_data->phydev = NULL;
921 	}
922 }
923 
924 static bool xgbe_phy_finisar_phy_quirks(struct xgbe_prv_data *pdata)
925 {
926 	__ETHTOOL_DECLARE_LINK_MODE_MASK(supported) = { 0, };
927 	struct xgbe_phy_data *phy_data = pdata->phy_data;
928 	unsigned int phy_id = phy_data->phydev->phy_id;
929 
930 	if (phy_data->port_mode != XGBE_PORT_MODE_SFP)
931 		return false;
932 
933 	if ((phy_id & 0xfffffff0) != 0x01ff0cc0)
934 		return false;
935 
936 	/* Enable Base-T AN */
937 	phy_write(phy_data->phydev, 0x16, 0x0001);
938 	phy_write(phy_data->phydev, 0x00, 0x9140);
939 	phy_write(phy_data->phydev, 0x16, 0x0000);
940 
941 	/* Enable SGMII at 100Base-T/1000Base-T Full Duplex */
942 	phy_write(phy_data->phydev, 0x1b, 0x9084);
943 	phy_write(phy_data->phydev, 0x09, 0x0e00);
944 	phy_write(phy_data->phydev, 0x00, 0x8140);
945 	phy_write(phy_data->phydev, 0x04, 0x0d01);
946 	phy_write(phy_data->phydev, 0x00, 0x9140);
947 
948 	linkmode_set_bit_array(phy_10_100_features_array,
949 			       ARRAY_SIZE(phy_10_100_features_array),
950 			       supported);
951 	linkmode_set_bit_array(phy_gbit_features_array,
952 			       ARRAY_SIZE(phy_gbit_features_array),
953 			       supported);
954 
955 	linkmode_copy(phy_data->phydev->supported, supported);
956 
957 	phy_support_asym_pause(phy_data->phydev);
958 
959 	netif_dbg(pdata, drv, pdata->netdev,
960 		  "Finisar PHY quirk in place\n");
961 
962 	return true;
963 }
964 
965 static bool xgbe_phy_belfuse_phy_quirks(struct xgbe_prv_data *pdata)
966 {
967 	__ETHTOOL_DECLARE_LINK_MODE_MASK(supported) = { 0, };
968 	struct xgbe_phy_data *phy_data = pdata->phy_data;
969 	struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom;
970 	unsigned int phy_id = phy_data->phydev->phy_id;
971 	int reg;
972 
973 	if (phy_data->port_mode != XGBE_PORT_MODE_SFP)
974 		return false;
975 
976 	if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME],
977 		   XGBE_BEL_FUSE_VENDOR, XGBE_SFP_BASE_VENDOR_NAME_LEN))
978 		return false;
979 
980 	/* For Bel-Fuse, use the extra AN flag */
981 	pdata->an_again = 1;
982 
983 	if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN],
984 		   XGBE_BEL_FUSE_PARTNO, XGBE_SFP_BASE_VENDOR_PN_LEN))
985 		return false;
986 
987 	if ((phy_id & 0xfffffff0) != 0x03625d10)
988 		return false;
989 
990 	/* Reset PHY - wait for self-clearing reset bit to clear */
991 	genphy_soft_reset(phy_data->phydev);
992 
993 	/* Disable RGMII mode */
994 	phy_write(phy_data->phydev, 0x18, 0x7007);
995 	reg = phy_read(phy_data->phydev, 0x18);
996 	phy_write(phy_data->phydev, 0x18, reg & ~0x0080);
997 
998 	/* Enable fiber register bank */
999 	phy_write(phy_data->phydev, 0x1c, 0x7c00);
1000 	reg = phy_read(phy_data->phydev, 0x1c);
1001 	reg &= 0x03ff;
1002 	reg &= ~0x0001;
1003 	phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg | 0x0001);
1004 
1005 	/* Power down SerDes */
1006 	reg = phy_read(phy_data->phydev, 0x00);
1007 	phy_write(phy_data->phydev, 0x00, reg | 0x00800);
1008 
1009 	/* Configure SGMII-to-Copper mode */
1010 	phy_write(phy_data->phydev, 0x1c, 0x7c00);
1011 	reg = phy_read(phy_data->phydev, 0x1c);
1012 	reg &= 0x03ff;
1013 	reg &= ~0x0006;
1014 	phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg | 0x0004);
1015 
1016 	/* Power up SerDes */
1017 	reg = phy_read(phy_data->phydev, 0x00);
1018 	phy_write(phy_data->phydev, 0x00, reg & ~0x00800);
1019 
1020 	/* Enable copper register bank */
1021 	phy_write(phy_data->phydev, 0x1c, 0x7c00);
1022 	reg = phy_read(phy_data->phydev, 0x1c);
1023 	reg &= 0x03ff;
1024 	reg &= ~0x0001;
1025 	phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg);
1026 
1027 	/* Power up SerDes */
1028 	reg = phy_read(phy_data->phydev, 0x00);
1029 	phy_write(phy_data->phydev, 0x00, reg & ~0x00800);
1030 
1031 	linkmode_set_bit_array(phy_10_100_features_array,
1032 			       ARRAY_SIZE(phy_10_100_features_array),
1033 			       supported);
1034 	linkmode_set_bit_array(phy_gbit_features_array,
1035 			       ARRAY_SIZE(phy_gbit_features_array),
1036 			       supported);
1037 	linkmode_copy(phy_data->phydev->supported, supported);
1038 	phy_support_asym_pause(phy_data->phydev);
1039 
1040 	netif_dbg(pdata, drv, pdata->netdev,
1041 		  "BelFuse PHY quirk in place\n");
1042 
1043 	return true;
1044 }
1045 
1046 static void xgbe_phy_external_phy_quirks(struct xgbe_prv_data *pdata)
1047 {
1048 	if (xgbe_phy_belfuse_phy_quirks(pdata))
1049 		return;
1050 
1051 	if (xgbe_phy_finisar_phy_quirks(pdata))
1052 		return;
1053 }
1054 
1055 static int xgbe_phy_find_phy_device(struct xgbe_prv_data *pdata)
1056 {
1057 	struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1058 	struct xgbe_phy_data *phy_data = pdata->phy_data;
1059 	struct phy_device *phydev;
1060 	int ret;
1061 
1062 	/* If we already have a PHY, just return */
1063 	if (phy_data->phydev)
1064 		return 0;
1065 
1066 	/* Clear the extra AN flag */
1067 	pdata->an_again = 0;
1068 
1069 	/* Check for the use of an external PHY */
1070 	if (phy_data->phydev_mode == XGBE_MDIO_MODE_NONE)
1071 		return 0;
1072 
1073 	/* For SFP, only use an external PHY if available */
1074 	if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) &&
1075 	    !phy_data->sfp_phy_avail)
1076 		return 0;
1077 
1078 	/* Set the proper MDIO mode for the PHY */
1079 	ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr,
1080 					    phy_data->phydev_mode);
1081 	if (ret) {
1082 		netdev_err(pdata->netdev,
1083 			   "mdio port/clause not compatible (%u/%u)\n",
1084 			   phy_data->mdio_addr, phy_data->phydev_mode);
1085 		return ret;
1086 	}
1087 
1088 	/* Create and connect to the PHY device */
1089 	phydev = get_phy_device(phy_data->mii, phy_data->mdio_addr,
1090 				(phy_data->phydev_mode == XGBE_MDIO_MODE_CL45));
1091 	if (IS_ERR(phydev)) {
1092 		netdev_err(pdata->netdev, "get_phy_device failed\n");
1093 		return -ENODEV;
1094 	}
1095 	netif_dbg(pdata, drv, pdata->netdev, "external PHY id is %#010x\n",
1096 		  phydev->phy_id);
1097 
1098 	/*TODO: If c45, add request_module based on one of the MMD ids? */
1099 
1100 	ret = phy_device_register(phydev);
1101 	if (ret) {
1102 		netdev_err(pdata->netdev, "phy_device_register failed\n");
1103 		phy_device_free(phydev);
1104 		return ret;
1105 	}
1106 
1107 	ret = phy_attach_direct(pdata->netdev, phydev, phydev->dev_flags,
1108 				PHY_INTERFACE_MODE_SGMII);
1109 	if (ret) {
1110 		netdev_err(pdata->netdev, "phy_attach_direct failed\n");
1111 		phy_device_remove(phydev);
1112 		phy_device_free(phydev);
1113 		return ret;
1114 	}
1115 	phy_data->phydev = phydev;
1116 
1117 	xgbe_phy_external_phy_quirks(pdata);
1118 
1119 	linkmode_and(phydev->advertising, phydev->advertising,
1120 		     lks->link_modes.advertising);
1121 
1122 	phy_start_aneg(phy_data->phydev);
1123 
1124 	return 0;
1125 }
1126 
1127 static void xgbe_phy_sfp_external_phy(struct xgbe_prv_data *pdata)
1128 {
1129 	struct xgbe_phy_data *phy_data = pdata->phy_data;
1130 	int ret;
1131 
1132 	if (!phy_data->sfp_changed)
1133 		return;
1134 
1135 	phy_data->sfp_phy_avail = 0;
1136 
1137 	if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
1138 		return;
1139 
1140 	/* Check access to the PHY by reading CTRL1 */
1141 	ret = xgbe_phy_i2c_mii_read(pdata, MII_BMCR);
1142 	if (ret < 0)
1143 		return;
1144 
1145 	/* Successfully accessed the PHY */
1146 	phy_data->sfp_phy_avail = 1;
1147 }
1148 
1149 static bool xgbe_phy_check_sfp_rx_los(struct xgbe_phy_data *phy_data)
1150 {
1151 	u8 *sfp_extd = phy_data->sfp_eeprom.extd;
1152 
1153 	if (!(sfp_extd[XGBE_SFP_EXTD_OPT1] & XGBE_SFP_EXTD_OPT1_RX_LOS))
1154 		return false;
1155 
1156 	if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_RX_LOS)
1157 		return false;
1158 
1159 	if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_rx_los))
1160 		return true;
1161 
1162 	return false;
1163 }
1164 
1165 static bool xgbe_phy_check_sfp_tx_fault(struct xgbe_phy_data *phy_data)
1166 {
1167 	u8 *sfp_extd = phy_data->sfp_eeprom.extd;
1168 
1169 	if (!(sfp_extd[XGBE_SFP_EXTD_OPT1] & XGBE_SFP_EXTD_OPT1_TX_FAULT))
1170 		return false;
1171 
1172 	if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_TX_FAULT)
1173 		return false;
1174 
1175 	if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_tx_fault))
1176 		return true;
1177 
1178 	return false;
1179 }
1180 
1181 static bool xgbe_phy_check_sfp_mod_absent(struct xgbe_phy_data *phy_data)
1182 {
1183 	if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_MOD_ABSENT)
1184 		return false;
1185 
1186 	if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_mod_absent))
1187 		return true;
1188 
1189 	return false;
1190 }
1191 
1192 static void xgbe_phy_sfp_parse_eeprom(struct xgbe_prv_data *pdata)
1193 {
1194 	struct xgbe_phy_data *phy_data = pdata->phy_data;
1195 	struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom;
1196 	u8 *sfp_base;
1197 
1198 	sfp_base = sfp_eeprom->base;
1199 
1200 	if (sfp_base[XGBE_SFP_BASE_ID] != XGBE_SFP_ID_SFP)
1201 		return;
1202 
1203 	if (sfp_base[XGBE_SFP_BASE_EXT_ID] != XGBE_SFP_EXT_ID_SFP)
1204 		return;
1205 
1206 	/* Update transceiver signals (eeprom extd/options) */
1207 	phy_data->sfp_tx_fault = xgbe_phy_check_sfp_tx_fault(phy_data);
1208 	phy_data->sfp_rx_los = xgbe_phy_check_sfp_rx_los(phy_data);
1209 
1210 	/* Assume FIBER cable unless told otherwise */
1211 	if (sfp_base[XGBE_SFP_BASE_CABLE] & XGBE_SFP_BASE_CABLE_PASSIVE) {
1212 		phy_data->sfp_cable = XGBE_SFP_CABLE_PASSIVE;
1213 		phy_data->sfp_cable_len = sfp_base[XGBE_SFP_BASE_CU_CABLE_LEN];
1214 	} else if (sfp_base[XGBE_SFP_BASE_CABLE] & XGBE_SFP_BASE_CABLE_ACTIVE) {
1215 		phy_data->sfp_cable = XGBE_SFP_CABLE_ACTIVE;
1216 	} else {
1217 		phy_data->sfp_cable = XGBE_SFP_CABLE_FIBER;
1218 	}
1219 
1220 	/* Determine the type of SFP */
1221 	if (phy_data->sfp_cable != XGBE_SFP_CABLE_FIBER &&
1222 	    xgbe_phy_sfp_bit_rate(sfp_eeprom, XGBE_SFP_SPEED_10000))
1223 		phy_data->sfp_base = XGBE_SFP_BASE_10000_CR;
1224 	else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_SR)
1225 		phy_data->sfp_base = XGBE_SFP_BASE_10000_SR;
1226 	else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LR)
1227 		phy_data->sfp_base = XGBE_SFP_BASE_10000_LR;
1228 	else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LRM)
1229 		phy_data->sfp_base = XGBE_SFP_BASE_10000_LRM;
1230 	else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_ER)
1231 		phy_data->sfp_base = XGBE_SFP_BASE_10000_ER;
1232 	else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_SX)
1233 		phy_data->sfp_base = XGBE_SFP_BASE_1000_SX;
1234 	else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_LX)
1235 		phy_data->sfp_base = XGBE_SFP_BASE_1000_LX;
1236 	else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_CX)
1237 		phy_data->sfp_base = XGBE_SFP_BASE_1000_CX;
1238 	else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_T)
1239 		phy_data->sfp_base = XGBE_SFP_BASE_1000_T;
1240 
1241 	switch (phy_data->sfp_base) {
1242 	case XGBE_SFP_BASE_1000_T:
1243 		phy_data->sfp_speed = XGBE_SFP_SPEED_100_1000;
1244 		break;
1245 	case XGBE_SFP_BASE_1000_SX:
1246 	case XGBE_SFP_BASE_1000_LX:
1247 	case XGBE_SFP_BASE_1000_CX:
1248 		phy_data->sfp_speed = XGBE_SFP_SPEED_1000;
1249 		break;
1250 	case XGBE_SFP_BASE_10000_SR:
1251 	case XGBE_SFP_BASE_10000_LR:
1252 	case XGBE_SFP_BASE_10000_LRM:
1253 	case XGBE_SFP_BASE_10000_ER:
1254 	case XGBE_SFP_BASE_10000_CR:
1255 		phy_data->sfp_speed = XGBE_SFP_SPEED_10000;
1256 		break;
1257 	default:
1258 		break;
1259 	}
1260 }
1261 
1262 static void xgbe_phy_sfp_eeprom_info(struct xgbe_prv_data *pdata,
1263 				     struct xgbe_sfp_eeprom *sfp_eeprom)
1264 {
1265 	struct xgbe_sfp_ascii sfp_ascii;
1266 	char *sfp_data = (char *)&sfp_ascii;
1267 
1268 	netif_dbg(pdata, drv, pdata->netdev, "SFP detected:\n");
1269 	memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME],
1270 	       XGBE_SFP_BASE_VENDOR_NAME_LEN);
1271 	sfp_data[XGBE_SFP_BASE_VENDOR_NAME_LEN] = '\0';
1272 	netif_dbg(pdata, drv, pdata->netdev, "  vendor:         %s\n",
1273 		  sfp_data);
1274 
1275 	memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN],
1276 	       XGBE_SFP_BASE_VENDOR_PN_LEN);
1277 	sfp_data[XGBE_SFP_BASE_VENDOR_PN_LEN] = '\0';
1278 	netif_dbg(pdata, drv, pdata->netdev, "  part number:    %s\n",
1279 		  sfp_data);
1280 
1281 	memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_REV],
1282 	       XGBE_SFP_BASE_VENDOR_REV_LEN);
1283 	sfp_data[XGBE_SFP_BASE_VENDOR_REV_LEN] = '\0';
1284 	netif_dbg(pdata, drv, pdata->netdev, "  revision level: %s\n",
1285 		  sfp_data);
1286 
1287 	memcpy(sfp_data, &sfp_eeprom->extd[XGBE_SFP_BASE_VENDOR_SN],
1288 	       XGBE_SFP_BASE_VENDOR_SN_LEN);
1289 	sfp_data[XGBE_SFP_BASE_VENDOR_SN_LEN] = '\0';
1290 	netif_dbg(pdata, drv, pdata->netdev, "  serial number:  %s\n",
1291 		  sfp_data);
1292 }
1293 
1294 static bool xgbe_phy_sfp_verify_eeprom(u8 cc_in, u8 *buf, unsigned int len)
1295 {
1296 	u8 cc;
1297 
1298 	for (cc = 0; len; buf++, len--)
1299 		cc += *buf;
1300 
1301 	return cc == cc_in;
1302 }
1303 
1304 static int xgbe_phy_sfp_read_eeprom(struct xgbe_prv_data *pdata)
1305 {
1306 	struct xgbe_phy_data *phy_data = pdata->phy_data;
1307 	struct xgbe_sfp_eeprom sfp_eeprom;
1308 	u8 eeprom_addr;
1309 	int ret;
1310 
1311 	ret = xgbe_phy_sfp_get_mux(pdata);
1312 	if (ret) {
1313 		dev_err_once(pdata->dev, "%s: I2C error setting SFP MUX\n",
1314 			     netdev_name(pdata->netdev));
1315 		return ret;
1316 	}
1317 
1318 	/* Read the SFP serial ID eeprom */
1319 	eeprom_addr = 0;
1320 	ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_SERIAL_ID_ADDRESS,
1321 				&eeprom_addr, sizeof(eeprom_addr),
1322 				&sfp_eeprom, sizeof(sfp_eeprom));
1323 	if (ret) {
1324 		dev_err_once(pdata->dev, "%s: I2C error reading SFP EEPROM\n",
1325 			     netdev_name(pdata->netdev));
1326 		goto put;
1327 	}
1328 
1329 	/* Validate the contents read */
1330 	if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.base[XGBE_SFP_BASE_CC],
1331 					sfp_eeprom.base,
1332 					sizeof(sfp_eeprom.base) - 1)) {
1333 		ret = -EINVAL;
1334 		goto put;
1335 	}
1336 
1337 	if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.extd[XGBE_SFP_EXTD_CC],
1338 					sfp_eeprom.extd,
1339 					sizeof(sfp_eeprom.extd) - 1)) {
1340 		ret = -EINVAL;
1341 		goto put;
1342 	}
1343 
1344 	/* Check for an added or changed SFP */
1345 	if (memcmp(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom))) {
1346 		phy_data->sfp_changed = 1;
1347 
1348 		if (netif_msg_drv(pdata))
1349 			xgbe_phy_sfp_eeprom_info(pdata, &sfp_eeprom);
1350 
1351 		memcpy(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom));
1352 
1353 		xgbe_phy_free_phy_device(pdata);
1354 	} else {
1355 		phy_data->sfp_changed = 0;
1356 	}
1357 
1358 put:
1359 	xgbe_phy_sfp_put_mux(pdata);
1360 
1361 	return ret;
1362 }
1363 
1364 static void xgbe_phy_sfp_signals(struct xgbe_prv_data *pdata)
1365 {
1366 	struct xgbe_phy_data *phy_data = pdata->phy_data;
1367 	u8 gpio_reg, gpio_ports[2];
1368 	int ret;
1369 
1370 	/* Read the input port registers */
1371 	gpio_reg = 0;
1372 	ret = xgbe_phy_i2c_read(pdata, phy_data->sfp_gpio_address,
1373 				&gpio_reg, sizeof(gpio_reg),
1374 				gpio_ports, sizeof(gpio_ports));
1375 	if (ret) {
1376 		dev_err_once(pdata->dev, "%s: I2C error reading SFP GPIOs\n",
1377 			     netdev_name(pdata->netdev));
1378 		return;
1379 	}
1380 
1381 	phy_data->sfp_gpio_inputs = (gpio_ports[1] << 8) | gpio_ports[0];
1382 
1383 	phy_data->sfp_mod_absent = xgbe_phy_check_sfp_mod_absent(phy_data);
1384 }
1385 
1386 static void xgbe_phy_sfp_mod_absent(struct xgbe_prv_data *pdata)
1387 {
1388 	struct xgbe_phy_data *phy_data = pdata->phy_data;
1389 
1390 	xgbe_phy_free_phy_device(pdata);
1391 
1392 	phy_data->sfp_mod_absent = 1;
1393 	phy_data->sfp_phy_avail = 0;
1394 	memset(&phy_data->sfp_eeprom, 0, sizeof(phy_data->sfp_eeprom));
1395 }
1396 
1397 static void xgbe_phy_sfp_reset(struct xgbe_phy_data *phy_data)
1398 {
1399 	phy_data->sfp_rx_los = 0;
1400 	phy_data->sfp_tx_fault = 0;
1401 	phy_data->sfp_mod_absent = 1;
1402 	phy_data->sfp_base = XGBE_SFP_BASE_UNKNOWN;
1403 	phy_data->sfp_cable = XGBE_SFP_CABLE_UNKNOWN;
1404 	phy_data->sfp_speed = XGBE_SFP_SPEED_UNKNOWN;
1405 }
1406 
1407 static void xgbe_phy_sfp_detect(struct xgbe_prv_data *pdata)
1408 {
1409 	struct xgbe_phy_data *phy_data = pdata->phy_data;
1410 	int ret;
1411 
1412 	/* Reset the SFP signals and info */
1413 	xgbe_phy_sfp_reset(phy_data);
1414 
1415 	ret = xgbe_phy_get_comm_ownership(pdata);
1416 	if (ret)
1417 		return;
1418 
1419 	/* Read the SFP signals and check for module presence */
1420 	xgbe_phy_sfp_signals(pdata);
1421 	if (phy_data->sfp_mod_absent) {
1422 		xgbe_phy_sfp_mod_absent(pdata);
1423 		goto put;
1424 	}
1425 
1426 	ret = xgbe_phy_sfp_read_eeprom(pdata);
1427 	if (ret) {
1428 		/* Treat any error as if there isn't an SFP plugged in */
1429 		xgbe_phy_sfp_reset(phy_data);
1430 		xgbe_phy_sfp_mod_absent(pdata);
1431 		goto put;
1432 	}
1433 
1434 	xgbe_phy_sfp_parse_eeprom(pdata);
1435 
1436 	xgbe_phy_sfp_external_phy(pdata);
1437 
1438 put:
1439 	xgbe_phy_sfp_phy_settings(pdata);
1440 
1441 	xgbe_phy_put_comm_ownership(pdata);
1442 }
1443 
1444 static int xgbe_phy_module_eeprom(struct xgbe_prv_data *pdata,
1445 				  struct ethtool_eeprom *eeprom, u8 *data)
1446 {
1447 	struct xgbe_phy_data *phy_data = pdata->phy_data;
1448 	u8 eeprom_addr, eeprom_data[XGBE_SFP_EEPROM_MAX];
1449 	struct xgbe_sfp_eeprom *sfp_eeprom;
1450 	unsigned int i, j, rem;
1451 	int ret;
1452 
1453 	rem = eeprom->len;
1454 
1455 	if (!eeprom->len) {
1456 		ret = -EINVAL;
1457 		goto done;
1458 	}
1459 
1460 	if ((eeprom->offset + eeprom->len) > XGBE_SFP_EEPROM_MAX) {
1461 		ret = -EINVAL;
1462 		goto done;
1463 	}
1464 
1465 	if (phy_data->port_mode != XGBE_PORT_MODE_SFP) {
1466 		ret = -ENXIO;
1467 		goto done;
1468 	}
1469 
1470 	if (!netif_running(pdata->netdev)) {
1471 		ret = -EIO;
1472 		goto done;
1473 	}
1474 
1475 	if (phy_data->sfp_mod_absent) {
1476 		ret = -EIO;
1477 		goto done;
1478 	}
1479 
1480 	ret = xgbe_phy_get_comm_ownership(pdata);
1481 	if (ret) {
1482 		ret = -EIO;
1483 		goto done;
1484 	}
1485 
1486 	ret = xgbe_phy_sfp_get_mux(pdata);
1487 	if (ret) {
1488 		netdev_err(pdata->netdev, "I2C error setting SFP MUX\n");
1489 		ret = -EIO;
1490 		goto put_own;
1491 	}
1492 
1493 	/* Read the SFP serial ID eeprom */
1494 	eeprom_addr = 0;
1495 	ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_SERIAL_ID_ADDRESS,
1496 				&eeprom_addr, sizeof(eeprom_addr),
1497 				eeprom_data, XGBE_SFP_EEPROM_BASE_LEN);
1498 	if (ret) {
1499 		netdev_err(pdata->netdev,
1500 			   "I2C error reading SFP EEPROM\n");
1501 		ret = -EIO;
1502 		goto put_mux;
1503 	}
1504 
1505 	sfp_eeprom = (struct xgbe_sfp_eeprom *)eeprom_data;
1506 
1507 	if (XGBE_SFP_DIAGS_SUPPORTED(sfp_eeprom)) {
1508 		/* Read the SFP diagnostic eeprom */
1509 		eeprom_addr = 0;
1510 		ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_DIAG_INFO_ADDRESS,
1511 					&eeprom_addr, sizeof(eeprom_addr),
1512 					eeprom_data + XGBE_SFP_EEPROM_BASE_LEN,
1513 					XGBE_SFP_EEPROM_DIAG_LEN);
1514 		if (ret) {
1515 			netdev_err(pdata->netdev,
1516 				   "I2C error reading SFP DIAGS\n");
1517 			ret = -EIO;
1518 			goto put_mux;
1519 		}
1520 	}
1521 
1522 	for (i = 0, j = eeprom->offset; i < eeprom->len; i++, j++) {
1523 		if ((j >= XGBE_SFP_EEPROM_BASE_LEN) &&
1524 		    !XGBE_SFP_DIAGS_SUPPORTED(sfp_eeprom))
1525 			break;
1526 
1527 		data[i] = eeprom_data[j];
1528 		rem--;
1529 	}
1530 
1531 put_mux:
1532 	xgbe_phy_sfp_put_mux(pdata);
1533 
1534 put_own:
1535 	xgbe_phy_put_comm_ownership(pdata);
1536 
1537 done:
1538 	eeprom->len -= rem;
1539 
1540 	return ret;
1541 }
1542 
1543 static int xgbe_phy_module_info(struct xgbe_prv_data *pdata,
1544 				struct ethtool_modinfo *modinfo)
1545 {
1546 	struct xgbe_phy_data *phy_data = pdata->phy_data;
1547 
1548 	if (phy_data->port_mode != XGBE_PORT_MODE_SFP)
1549 		return -ENXIO;
1550 
1551 	if (!netif_running(pdata->netdev))
1552 		return -EIO;
1553 
1554 	if (phy_data->sfp_mod_absent)
1555 		return -EIO;
1556 
1557 	if (XGBE_SFP_DIAGS_SUPPORTED(&phy_data->sfp_eeprom)) {
1558 		modinfo->type = ETH_MODULE_SFF_8472;
1559 		modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1560 	} else {
1561 		modinfo->type = ETH_MODULE_SFF_8079;
1562 		modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
1563 	}
1564 
1565 	return 0;
1566 }
1567 
1568 static void xgbe_phy_phydev_flowctrl(struct xgbe_prv_data *pdata)
1569 {
1570 	struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1571 	struct xgbe_phy_data *phy_data = pdata->phy_data;
1572 	u16 lcl_adv = 0, rmt_adv = 0;
1573 	u8 fc;
1574 
1575 	pdata->phy.tx_pause = 0;
1576 	pdata->phy.rx_pause = 0;
1577 
1578 	if (!phy_data->phydev)
1579 		return;
1580 
1581 	lcl_adv = linkmode_adv_to_lcl_adv_t(phy_data->phydev->advertising);
1582 
1583 	if (phy_data->phydev->pause) {
1584 		XGBE_SET_LP_ADV(lks, Pause);
1585 		rmt_adv |= LPA_PAUSE_CAP;
1586 	}
1587 	if (phy_data->phydev->asym_pause) {
1588 		XGBE_SET_LP_ADV(lks, Asym_Pause);
1589 		rmt_adv |= LPA_PAUSE_ASYM;
1590 	}
1591 
1592 	fc = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
1593 	if (fc & FLOW_CTRL_TX)
1594 		pdata->phy.tx_pause = 1;
1595 	if (fc & FLOW_CTRL_RX)
1596 		pdata->phy.rx_pause = 1;
1597 }
1598 
1599 static enum xgbe_mode xgbe_phy_an37_sgmii_outcome(struct xgbe_prv_data *pdata)
1600 {
1601 	struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1602 	enum xgbe_mode mode;
1603 
1604 	XGBE_SET_LP_ADV(lks, Autoneg);
1605 	XGBE_SET_LP_ADV(lks, TP);
1606 
1607 	/* Use external PHY to determine flow control */
1608 	if (pdata->phy.pause_autoneg)
1609 		xgbe_phy_phydev_flowctrl(pdata);
1610 
1611 	switch (pdata->an_status & XGBE_SGMII_AN_LINK_SPEED) {
1612 	case XGBE_SGMII_AN_LINK_SPEED_10:
1613 		if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) {
1614 			XGBE_SET_LP_ADV(lks, 10baseT_Full);
1615 			mode = XGBE_MODE_SGMII_10;
1616 		} else {
1617 			/* Half-duplex not supported */
1618 			XGBE_SET_LP_ADV(lks, 10baseT_Half);
1619 			mode = XGBE_MODE_UNKNOWN;
1620 		}
1621 		break;
1622 	case XGBE_SGMII_AN_LINK_SPEED_100:
1623 		if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) {
1624 			XGBE_SET_LP_ADV(lks, 100baseT_Full);
1625 			mode = XGBE_MODE_SGMII_100;
1626 		} else {
1627 			/* Half-duplex not supported */
1628 			XGBE_SET_LP_ADV(lks, 100baseT_Half);
1629 			mode = XGBE_MODE_UNKNOWN;
1630 		}
1631 		break;
1632 	case XGBE_SGMII_AN_LINK_SPEED_1000:
1633 		if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) {
1634 			XGBE_SET_LP_ADV(lks, 1000baseT_Full);
1635 			mode = XGBE_MODE_SGMII_1000;
1636 		} else {
1637 			/* Half-duplex not supported */
1638 			XGBE_SET_LP_ADV(lks, 1000baseT_Half);
1639 			mode = XGBE_MODE_UNKNOWN;
1640 		}
1641 		break;
1642 	default:
1643 		mode = XGBE_MODE_UNKNOWN;
1644 	}
1645 
1646 	return mode;
1647 }
1648 
1649 static enum xgbe_mode xgbe_phy_an37_outcome(struct xgbe_prv_data *pdata)
1650 {
1651 	struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1652 	enum xgbe_mode mode;
1653 	unsigned int ad_reg, lp_reg;
1654 
1655 	XGBE_SET_LP_ADV(lks, Autoneg);
1656 	XGBE_SET_LP_ADV(lks, FIBRE);
1657 
1658 	/* Compare Advertisement and Link Partner register */
1659 	ad_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE);
1660 	lp_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_LP_ABILITY);
1661 	if (lp_reg & 0x100)
1662 		XGBE_SET_LP_ADV(lks, Pause);
1663 	if (lp_reg & 0x80)
1664 		XGBE_SET_LP_ADV(lks, Asym_Pause);
1665 
1666 	if (pdata->phy.pause_autoneg) {
1667 		/* Set flow control based on auto-negotiation result */
1668 		pdata->phy.tx_pause = 0;
1669 		pdata->phy.rx_pause = 0;
1670 
1671 		if (ad_reg & lp_reg & 0x100) {
1672 			pdata->phy.tx_pause = 1;
1673 			pdata->phy.rx_pause = 1;
1674 		} else if (ad_reg & lp_reg & 0x80) {
1675 			if (ad_reg & 0x100)
1676 				pdata->phy.rx_pause = 1;
1677 			else if (lp_reg & 0x100)
1678 				pdata->phy.tx_pause = 1;
1679 		}
1680 	}
1681 
1682 	if (lp_reg & 0x20)
1683 		XGBE_SET_LP_ADV(lks, 1000baseX_Full);
1684 
1685 	/* Half duplex is not supported */
1686 	ad_reg &= lp_reg;
1687 	mode = (ad_reg & 0x20) ? XGBE_MODE_X : XGBE_MODE_UNKNOWN;
1688 
1689 	return mode;
1690 }
1691 
1692 static enum xgbe_mode xgbe_phy_an73_redrv_outcome(struct xgbe_prv_data *pdata)
1693 {
1694 	struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1695 	struct xgbe_phy_data *phy_data = pdata->phy_data;
1696 	enum xgbe_mode mode;
1697 	unsigned int ad_reg, lp_reg;
1698 
1699 	XGBE_SET_LP_ADV(lks, Autoneg);
1700 	XGBE_SET_LP_ADV(lks, Backplane);
1701 
1702 	/* Use external PHY to determine flow control */
1703 	if (pdata->phy.pause_autoneg)
1704 		xgbe_phy_phydev_flowctrl(pdata);
1705 
1706 	/* Compare Advertisement and Link Partner register 2 */
1707 	ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
1708 	lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
1709 	if (lp_reg & 0x80)
1710 		XGBE_SET_LP_ADV(lks, 10000baseKR_Full);
1711 	if (lp_reg & 0x20)
1712 		XGBE_SET_LP_ADV(lks, 1000baseKX_Full);
1713 
1714 	ad_reg &= lp_reg;
1715 	if (ad_reg & 0x80) {
1716 		switch (phy_data->port_mode) {
1717 		case XGBE_PORT_MODE_BACKPLANE:
1718 		case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
1719 			mode = XGBE_MODE_KR;
1720 			break;
1721 		default:
1722 			mode = XGBE_MODE_SFI;
1723 			break;
1724 		}
1725 	} else if (ad_reg & 0x20) {
1726 		switch (phy_data->port_mode) {
1727 		case XGBE_PORT_MODE_BACKPLANE:
1728 		case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
1729 			mode = XGBE_MODE_KX_1000;
1730 			break;
1731 		case XGBE_PORT_MODE_1000BASE_X:
1732 			mode = XGBE_MODE_X;
1733 			break;
1734 		case XGBE_PORT_MODE_SFP:
1735 			switch (phy_data->sfp_base) {
1736 			case XGBE_SFP_BASE_1000_T:
1737 				if (phy_data->phydev &&
1738 				    (phy_data->phydev->speed == SPEED_10))
1739 					mode = XGBE_MODE_SGMII_10;
1740 				else if (phy_data->phydev &&
1741 					 (phy_data->phydev->speed == SPEED_100))
1742 					mode = XGBE_MODE_SGMII_100;
1743 				else
1744 					mode = XGBE_MODE_SGMII_1000;
1745 				break;
1746 			case XGBE_SFP_BASE_1000_SX:
1747 			case XGBE_SFP_BASE_1000_LX:
1748 			case XGBE_SFP_BASE_1000_CX:
1749 			default:
1750 				mode = XGBE_MODE_X;
1751 				break;
1752 			}
1753 			break;
1754 		default:
1755 			if (phy_data->phydev &&
1756 			    (phy_data->phydev->speed == SPEED_10))
1757 				mode = XGBE_MODE_SGMII_10;
1758 			else if (phy_data->phydev &&
1759 				 (phy_data->phydev->speed == SPEED_100))
1760 				mode = XGBE_MODE_SGMII_100;
1761 			else
1762 				mode = XGBE_MODE_SGMII_1000;
1763 			break;
1764 		}
1765 	} else {
1766 		mode = XGBE_MODE_UNKNOWN;
1767 	}
1768 
1769 	/* Compare Advertisement and Link Partner register 3 */
1770 	ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
1771 	lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
1772 	if (lp_reg & 0xc000)
1773 		XGBE_SET_LP_ADV(lks, 10000baseR_FEC);
1774 
1775 	return mode;
1776 }
1777 
1778 static enum xgbe_mode xgbe_phy_an73_outcome(struct xgbe_prv_data *pdata)
1779 {
1780 	struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1781 	enum xgbe_mode mode;
1782 	unsigned int ad_reg, lp_reg;
1783 
1784 	XGBE_SET_LP_ADV(lks, Autoneg);
1785 	XGBE_SET_LP_ADV(lks, Backplane);
1786 
1787 	/* Compare Advertisement and Link Partner register 1 */
1788 	ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
1789 	lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA);
1790 	if (lp_reg & 0x400)
1791 		XGBE_SET_LP_ADV(lks, Pause);
1792 	if (lp_reg & 0x800)
1793 		XGBE_SET_LP_ADV(lks, Asym_Pause);
1794 
1795 	if (pdata->phy.pause_autoneg) {
1796 		/* Set flow control based on auto-negotiation result */
1797 		pdata->phy.tx_pause = 0;
1798 		pdata->phy.rx_pause = 0;
1799 
1800 		if (ad_reg & lp_reg & 0x400) {
1801 			pdata->phy.tx_pause = 1;
1802 			pdata->phy.rx_pause = 1;
1803 		} else if (ad_reg & lp_reg & 0x800) {
1804 			if (ad_reg & 0x400)
1805 				pdata->phy.rx_pause = 1;
1806 			else if (lp_reg & 0x400)
1807 				pdata->phy.tx_pause = 1;
1808 		}
1809 	}
1810 
1811 	/* Compare Advertisement and Link Partner register 2 */
1812 	ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
1813 	lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
1814 	if (lp_reg & 0x80)
1815 		XGBE_SET_LP_ADV(lks, 10000baseKR_Full);
1816 	if (lp_reg & 0x20)
1817 		XGBE_SET_LP_ADV(lks, 1000baseKX_Full);
1818 
1819 	ad_reg &= lp_reg;
1820 	if (ad_reg & 0x80)
1821 		mode = XGBE_MODE_KR;
1822 	else if (ad_reg & 0x20)
1823 		mode = XGBE_MODE_KX_1000;
1824 	else
1825 		mode = XGBE_MODE_UNKNOWN;
1826 
1827 	/* Compare Advertisement and Link Partner register 3 */
1828 	ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
1829 	lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
1830 	if (lp_reg & 0xc000)
1831 		XGBE_SET_LP_ADV(lks, 10000baseR_FEC);
1832 
1833 	return mode;
1834 }
1835 
1836 static enum xgbe_mode xgbe_phy_an_outcome(struct xgbe_prv_data *pdata)
1837 {
1838 	switch (pdata->an_mode) {
1839 	case XGBE_AN_MODE_CL73:
1840 		return xgbe_phy_an73_outcome(pdata);
1841 	case XGBE_AN_MODE_CL73_REDRV:
1842 		return xgbe_phy_an73_redrv_outcome(pdata);
1843 	case XGBE_AN_MODE_CL37:
1844 		return xgbe_phy_an37_outcome(pdata);
1845 	case XGBE_AN_MODE_CL37_SGMII:
1846 		return xgbe_phy_an37_sgmii_outcome(pdata);
1847 	default:
1848 		return XGBE_MODE_UNKNOWN;
1849 	}
1850 }
1851 
1852 static void xgbe_phy_an_advertising(struct xgbe_prv_data *pdata,
1853 				    struct ethtool_link_ksettings *dlks)
1854 {
1855 	struct ethtool_link_ksettings *slks = &pdata->phy.lks;
1856 	struct xgbe_phy_data *phy_data = pdata->phy_data;
1857 
1858 	XGBE_LM_COPY(dlks, advertising, slks, advertising);
1859 
1860 	/* Without a re-driver, just return current advertising */
1861 	if (!phy_data->redrv)
1862 		return;
1863 
1864 	/* With the KR re-driver we need to advertise a single speed */
1865 	XGBE_CLR_ADV(dlks, 1000baseKX_Full);
1866 	XGBE_CLR_ADV(dlks, 10000baseKR_Full);
1867 
1868 	/* Advertise FEC support is present */
1869 	if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
1870 		XGBE_SET_ADV(dlks, 10000baseR_FEC);
1871 
1872 	switch (phy_data->port_mode) {
1873 	case XGBE_PORT_MODE_BACKPLANE:
1874 	case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
1875 		XGBE_SET_ADV(dlks, 10000baseKR_Full);
1876 		break;
1877 	case XGBE_PORT_MODE_BACKPLANE_2500:
1878 		XGBE_SET_ADV(dlks, 1000baseKX_Full);
1879 		break;
1880 	case XGBE_PORT_MODE_1000BASE_T:
1881 	case XGBE_PORT_MODE_1000BASE_X:
1882 	case XGBE_PORT_MODE_NBASE_T:
1883 		XGBE_SET_ADV(dlks, 1000baseKX_Full);
1884 		break;
1885 	case XGBE_PORT_MODE_10GBASE_T:
1886 		if (phy_data->phydev &&
1887 		    (phy_data->phydev->speed == SPEED_10000))
1888 			XGBE_SET_ADV(dlks, 10000baseKR_Full);
1889 		else if (phy_data->phydev &&
1890 			 (phy_data->phydev->speed == SPEED_2500))
1891 			XGBE_SET_ADV(dlks, 2500baseX_Full);
1892 		else
1893 			XGBE_SET_ADV(dlks, 1000baseKX_Full);
1894 		break;
1895 	case XGBE_PORT_MODE_10GBASE_R:
1896 		XGBE_SET_ADV(dlks, 10000baseKR_Full);
1897 		break;
1898 	case XGBE_PORT_MODE_SFP:
1899 		switch (phy_data->sfp_base) {
1900 		case XGBE_SFP_BASE_1000_T:
1901 		case XGBE_SFP_BASE_1000_SX:
1902 		case XGBE_SFP_BASE_1000_LX:
1903 		case XGBE_SFP_BASE_1000_CX:
1904 			XGBE_SET_ADV(dlks, 1000baseKX_Full);
1905 			break;
1906 		default:
1907 			XGBE_SET_ADV(dlks, 10000baseKR_Full);
1908 			break;
1909 		}
1910 		break;
1911 	default:
1912 		XGBE_SET_ADV(dlks, 10000baseKR_Full);
1913 		break;
1914 	}
1915 }
1916 
1917 static int xgbe_phy_an_config(struct xgbe_prv_data *pdata)
1918 {
1919 	struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1920 	struct xgbe_phy_data *phy_data = pdata->phy_data;
1921 	int ret;
1922 
1923 	ret = xgbe_phy_find_phy_device(pdata);
1924 	if (ret)
1925 		return ret;
1926 
1927 	if (!phy_data->phydev)
1928 		return 0;
1929 
1930 	phy_data->phydev->autoneg = pdata->phy.autoneg;
1931 	linkmode_and(phy_data->phydev->advertising,
1932 		     phy_data->phydev->supported,
1933 		     lks->link_modes.advertising);
1934 
1935 	if (pdata->phy.autoneg != AUTONEG_ENABLE) {
1936 		phy_data->phydev->speed = pdata->phy.speed;
1937 		phy_data->phydev->duplex = pdata->phy.duplex;
1938 	}
1939 
1940 	ret = phy_start_aneg(phy_data->phydev);
1941 
1942 	return ret;
1943 }
1944 
1945 static enum xgbe_an_mode xgbe_phy_an_sfp_mode(struct xgbe_phy_data *phy_data)
1946 {
1947 	switch (phy_data->sfp_base) {
1948 	case XGBE_SFP_BASE_1000_T:
1949 		return XGBE_AN_MODE_CL37_SGMII;
1950 	case XGBE_SFP_BASE_1000_SX:
1951 	case XGBE_SFP_BASE_1000_LX:
1952 	case XGBE_SFP_BASE_1000_CX:
1953 		return XGBE_AN_MODE_CL37;
1954 	default:
1955 		return XGBE_AN_MODE_NONE;
1956 	}
1957 }
1958 
1959 static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata)
1960 {
1961 	struct xgbe_phy_data *phy_data = pdata->phy_data;
1962 
1963 	/* A KR re-driver will always require CL73 AN */
1964 	if (phy_data->redrv)
1965 		return XGBE_AN_MODE_CL73_REDRV;
1966 
1967 	switch (phy_data->port_mode) {
1968 	case XGBE_PORT_MODE_BACKPLANE:
1969 		return XGBE_AN_MODE_CL73;
1970 	case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
1971 	case XGBE_PORT_MODE_BACKPLANE_2500:
1972 		return XGBE_AN_MODE_NONE;
1973 	case XGBE_PORT_MODE_1000BASE_T:
1974 		return XGBE_AN_MODE_CL37_SGMII;
1975 	case XGBE_PORT_MODE_1000BASE_X:
1976 		return XGBE_AN_MODE_CL37;
1977 	case XGBE_PORT_MODE_NBASE_T:
1978 		return XGBE_AN_MODE_CL37_SGMII;
1979 	case XGBE_PORT_MODE_10GBASE_T:
1980 		return XGBE_AN_MODE_CL73;
1981 	case XGBE_PORT_MODE_10GBASE_R:
1982 		return XGBE_AN_MODE_NONE;
1983 	case XGBE_PORT_MODE_SFP:
1984 		return xgbe_phy_an_sfp_mode(phy_data);
1985 	default:
1986 		return XGBE_AN_MODE_NONE;
1987 	}
1988 }
1989 
1990 static int xgbe_phy_set_redrv_mode_mdio(struct xgbe_prv_data *pdata,
1991 					enum xgbe_phy_redrv_mode mode)
1992 {
1993 	struct xgbe_phy_data *phy_data = pdata->phy_data;
1994 	u16 redrv_reg, redrv_val;
1995 
1996 	redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000);
1997 	redrv_val = (u16)mode;
1998 
1999 	return pdata->hw_if.write_ext_mii_regs_c22(pdata, phy_data->redrv_addr,
2000 						   redrv_reg, redrv_val);
2001 }
2002 
2003 static int xgbe_phy_set_redrv_mode_i2c(struct xgbe_prv_data *pdata,
2004 				       enum xgbe_phy_redrv_mode mode)
2005 {
2006 	struct xgbe_phy_data *phy_data = pdata->phy_data;
2007 	unsigned int redrv_reg;
2008 	int ret;
2009 
2010 	/* Calculate the register to write */
2011 	redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000);
2012 
2013 	ret = xgbe_phy_redrv_write(pdata, redrv_reg, mode);
2014 
2015 	return ret;
2016 }
2017 
2018 static void xgbe_phy_set_redrv_mode(struct xgbe_prv_data *pdata)
2019 {
2020 	struct xgbe_phy_data *phy_data = pdata->phy_data;
2021 	enum xgbe_phy_redrv_mode mode;
2022 	int ret;
2023 
2024 	if (!phy_data->redrv)
2025 		return;
2026 
2027 	mode = XGBE_PHY_REDRV_MODE_CX;
2028 	if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) &&
2029 	    (phy_data->sfp_base != XGBE_SFP_BASE_1000_CX) &&
2030 	    (phy_data->sfp_base != XGBE_SFP_BASE_10000_CR))
2031 		mode = XGBE_PHY_REDRV_MODE_SR;
2032 
2033 	ret = xgbe_phy_get_comm_ownership(pdata);
2034 	if (ret)
2035 		return;
2036 
2037 	if (phy_data->redrv_if)
2038 		xgbe_phy_set_redrv_mode_i2c(pdata, mode);
2039 	else
2040 		xgbe_phy_set_redrv_mode_mdio(pdata, mode);
2041 
2042 	xgbe_phy_put_comm_ownership(pdata);
2043 }
2044 
2045 #define MAX_RX_ADAPT_RETRIES		1
2046 #define XGBE_PMA_RX_VAL_SIG_MASK	(XGBE_PMA_RX_SIG_DET_0_MASK | \
2047 					 XGBE_PMA_RX_VALID_0_MASK)
2048 
2049 static void xgbe_set_rx_adap_mode(struct xgbe_prv_data *pdata,
2050 				  enum xgbe_mode mode)
2051 {
2052 	if (pdata->rx_adapt_retries++ >= MAX_RX_ADAPT_RETRIES) {
2053 		pdata->rx_adapt_retries = 0;
2054 		return;
2055 	}
2056 
2057 	xgbe_phy_perform_ratechange(pdata,
2058 				    mode == XGBE_MODE_KR ?
2059 				    XGBE_MB_CMD_SET_10G_KR :
2060 				    XGBE_MB_CMD_SET_10G_SFI,
2061 				    XGBE_MB_SUBCMD_RX_ADAP);
2062 }
2063 
2064 static void xgbe_rx_adaptation(struct xgbe_prv_data *pdata)
2065 {
2066 	struct xgbe_phy_data *phy_data = pdata->phy_data;
2067 	unsigned int reg;
2068 
2069 	/* step 2: force PCS to send RX_ADAPT Req to PHY */
2070 	XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_EQ_CTRL4,
2071 			 XGBE_PMA_RX_AD_REQ_MASK, XGBE_PMA_RX_AD_REQ_ENABLE);
2072 
2073 	/* Step 3: Wait for RX_ADAPT ACK from the PHY */
2074 	msleep(200);
2075 
2076 	/* Software polls for coefficient update command (given by local PHY) */
2077 	reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_PHY_RX_EQ_CEU);
2078 
2079 	/* Clear the RX_AD_REQ bit */
2080 	XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_EQ_CTRL4,
2081 			 XGBE_PMA_RX_AD_REQ_MASK, XGBE_PMA_RX_AD_REQ_DISABLE);
2082 
2083 	/* Check if coefficient update command is set */
2084 	if ((reg & XGBE_PMA_CFF_UPDT_MASK) != XGBE_PMA_CFF_UPDT_MASK)
2085 		goto set_mode;
2086 
2087 	/* Step 4: Check for Block lock */
2088 
2089 	/* Link status is latched low, so read once to clear
2090 	 * and then read again to get current state
2091 	 */
2092 	reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
2093 	reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
2094 	if (reg & MDIO_STAT1_LSTATUS) {
2095 		/* If the block lock is found, update the helpers
2096 		 * and declare the link up
2097 		 */
2098 		netif_dbg(pdata, link, pdata->netdev, "Block_lock done");
2099 		pdata->rx_adapt_done = true;
2100 		pdata->mode_set = false;
2101 		return;
2102 	}
2103 
2104 set_mode:
2105 	xgbe_set_rx_adap_mode(pdata, phy_data->cur_mode);
2106 }
2107 
2108 static void xgbe_phy_rx_adaptation(struct xgbe_prv_data *pdata)
2109 {
2110 	unsigned int reg;
2111 
2112 rx_adapt_reinit:
2113 	reg = XMDIO_READ_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_LSTS,
2114 			      XGBE_PMA_RX_VAL_SIG_MASK);
2115 
2116 	/* step 1: Check for RX_VALID && LF_SIGDET */
2117 	if ((reg & XGBE_PMA_RX_VAL_SIG_MASK) != XGBE_PMA_RX_VAL_SIG_MASK) {
2118 		netif_dbg(pdata, link, pdata->netdev,
2119 			  "RX_VALID or LF_SIGDET is unset, issue rrc");
2120 		xgbe_phy_rrc(pdata);
2121 		if (pdata->rx_adapt_retries++ >= MAX_RX_ADAPT_RETRIES) {
2122 			pdata->rx_adapt_retries = 0;
2123 			return;
2124 		}
2125 		goto rx_adapt_reinit;
2126 	}
2127 
2128 	/* perform rx adaptation */
2129 	xgbe_rx_adaptation(pdata);
2130 }
2131 
2132 static void xgbe_phy_rx_reset(struct xgbe_prv_data *pdata)
2133 {
2134 	int reg;
2135 
2136 	reg = XMDIO_READ_BITS(pdata, MDIO_MMD_PCS, MDIO_PCS_DIGITAL_STAT,
2137 			      XGBE_PCS_PSEQ_STATE_MASK);
2138 	if (reg == XGBE_PCS_PSEQ_STATE_POWER_GOOD) {
2139 		/* Mailbox command timed out, reset of RX block is required.
2140 		 * This can be done by asseting the reset bit and wait for
2141 		 * its compeletion.
2142 		 */
2143 		XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_CTRL1,
2144 				 XGBE_PMA_RX_RST_0_MASK, XGBE_PMA_RX_RST_0_RESET_ON);
2145 		ndelay(20);
2146 		XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_CTRL1,
2147 				 XGBE_PMA_RX_RST_0_MASK, XGBE_PMA_RX_RST_0_RESET_OFF);
2148 		usleep_range(40, 50);
2149 		netif_err(pdata, link, pdata->netdev, "firmware mailbox reset performed\n");
2150 	}
2151 }
2152 
2153 static void xgbe_phy_pll_ctrl(struct xgbe_prv_data *pdata, bool enable)
2154 {
2155 	/* PLL_CTRL feature needs to be enabled for fixed PHY modes (Non-Autoneg) only */
2156 	if (pdata->phy.autoneg != AUTONEG_DISABLE)
2157 		return;
2158 
2159 	XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_MISC_CTRL0,
2160 			 XGBE_PMA_PLL_CTRL_MASK,
2161 			 enable ? XGBE_PMA_PLL_CTRL_ENABLE
2162 				: XGBE_PMA_PLL_CTRL_DISABLE);
2163 
2164 	/* Wait for command to complete */
2165 	usleep_range(100, 200);
2166 }
2167 
2168 static void xgbe_phy_perform_ratechange(struct xgbe_prv_data *pdata,
2169 					enum xgbe_mb_cmd cmd, enum xgbe_mb_subcmd sub_cmd)
2170 {
2171 	unsigned int s0 = 0;
2172 	unsigned int wait;
2173 
2174 	/* Disable PLL re-initialization during FW command processing */
2175 	xgbe_phy_pll_ctrl(pdata, false);
2176 
2177 	/* Log if a previous command did not complete */
2178 	if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) {
2179 		netif_dbg(pdata, link, pdata->netdev,
2180 			  "firmware mailbox not ready for command\n");
2181 		xgbe_phy_rx_reset(pdata);
2182 	}
2183 
2184 	/* Construct the command */
2185 	XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, cmd);
2186 	XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, sub_cmd);
2187 
2188 	/* Issue the command */
2189 	XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
2190 	XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
2191 	XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
2192 
2193 	/* Wait for command to complete */
2194 	wait = XGBE_RATECHANGE_COUNT;
2195 	while (wait--) {
2196 		if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
2197 			goto do_rx_adaptation;
2198 
2199 		usleep_range(1000, 2000);
2200 	}
2201 
2202 	netif_dbg(pdata, link, pdata->netdev,
2203 		  "firmware mailbox command did not complete\n");
2204 
2205 	/* Reset on error */
2206 	xgbe_phy_rx_reset(pdata);
2207 	goto reenable_pll;
2208 
2209 do_rx_adaptation:
2210 	if (pdata->en_rx_adap && sub_cmd == XGBE_MB_SUBCMD_RX_ADAP &&
2211 	    (cmd == XGBE_MB_CMD_SET_10G_KR || cmd == XGBE_MB_CMD_SET_10G_SFI)) {
2212 		netif_dbg(pdata, link, pdata->netdev,
2213 			  "Enabling RX adaptation\n");
2214 		pdata->mode_set = true;
2215 		xgbe_phy_rx_adaptation(pdata);
2216 		/* return from here to avoid enabling PLL ctrl
2217 		 * during adaptation phase
2218 		 */
2219 		return;
2220 	}
2221 
2222 reenable_pll:
2223 	/* Enable PLL re-initialization, not needed for PHY Power Off and RRC cmds */
2224 	if (cmd != XGBE_MB_CMD_POWER_OFF &&
2225 	    cmd != XGBE_MB_CMD_RRC)
2226 		xgbe_phy_pll_ctrl(pdata, true);
2227 }
2228 
2229 static void xgbe_phy_rrc(struct xgbe_prv_data *pdata)
2230 {
2231 	/* Receiver Reset Cycle */
2232 	xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_RRC, XGBE_MB_SUBCMD_NONE);
2233 
2234 	netif_dbg(pdata, link, pdata->netdev, "receiver reset complete\n");
2235 }
2236 
2237 static void xgbe_phy_power_off(struct xgbe_prv_data *pdata)
2238 {
2239 	struct xgbe_phy_data *phy_data = pdata->phy_data;
2240 
2241 	/* Power off */
2242 	xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_POWER_OFF, XGBE_MB_SUBCMD_NONE);
2243 
2244 	phy_data->cur_mode = XGBE_MODE_UNKNOWN;
2245 
2246 	netif_dbg(pdata, link, pdata->netdev, "phy powered off\n");
2247 }
2248 
2249 static bool enable_rx_adap(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2250 {
2251 	struct xgbe_phy_data *phy_data = pdata->phy_data;
2252 	unsigned int ver;
2253 
2254 	/* Rx-Adaptation is not supported on older platforms(< 0x30H) */
2255 	ver = XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER);
2256 	if (ver < 0x30)
2257 		return false;
2258 
2259 	/* Re-driver models 4223 && 4227 do not support Rx-Adaptation */
2260 	if (phy_data->redrv &&
2261 	    (phy_data->redrv_model == XGBE_PHY_REDRV_MODEL_4223 ||
2262 	     phy_data->redrv_model == XGBE_PHY_REDRV_MODEL_4227))
2263 		return false;
2264 
2265 	/* 10G KR mode with AN does not support Rx-Adaptation */
2266 	if (mode == XGBE_MODE_KR &&
2267 	    phy_data->port_mode != XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG)
2268 		return false;
2269 
2270 	pdata->en_rx_adap = 1;
2271 	return true;
2272 }
2273 
2274 static void xgbe_phy_sfi_mode(struct xgbe_prv_data *pdata)
2275 {
2276 	struct xgbe_phy_data *phy_data = pdata->phy_data;
2277 
2278 	xgbe_phy_set_redrv_mode(pdata);
2279 
2280 	/* 10G/SFI */
2281 	if (phy_data->sfp_cable != XGBE_SFP_CABLE_PASSIVE) {
2282 		pdata->en_rx_adap = 0;
2283 		xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_10G_SFI, XGBE_MB_SUBCMD_ACTIVE);
2284 	} else if ((phy_data->sfp_cable == XGBE_SFP_CABLE_PASSIVE) &&
2285 		   (enable_rx_adap(pdata, XGBE_MODE_SFI))) {
2286 		xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_10G_SFI,
2287 					    XGBE_MB_SUBCMD_RX_ADAP);
2288 	} else {
2289 		if (phy_data->sfp_cable_len <= 1)
2290 			xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_10G_SFI,
2291 						    XGBE_MB_SUBCMD_PASSIVE_1M);
2292 		else if (phy_data->sfp_cable_len <= 3)
2293 			xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_10G_SFI,
2294 						    XGBE_MB_SUBCMD_PASSIVE_3M);
2295 		else
2296 			xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_10G_SFI,
2297 						    XGBE_MB_SUBCMD_PASSIVE_OTHER);
2298 	}
2299 
2300 	phy_data->cur_mode = XGBE_MODE_SFI;
2301 
2302 	netif_dbg(pdata, link, pdata->netdev, "10GbE SFI mode set\n");
2303 }
2304 
2305 static void xgbe_phy_x_mode(struct xgbe_prv_data *pdata)
2306 {
2307 	struct xgbe_phy_data *phy_data = pdata->phy_data;
2308 
2309 	xgbe_phy_set_redrv_mode(pdata);
2310 
2311 	/* 1G/X */
2312 	xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_1G, XGBE_MB_SUBCMD_1G_KX);
2313 
2314 	phy_data->cur_mode = XGBE_MODE_X;
2315 
2316 	netif_dbg(pdata, link, pdata->netdev, "1GbE X mode set\n");
2317 }
2318 
2319 static void xgbe_phy_sgmii_1000_mode(struct xgbe_prv_data *pdata)
2320 {
2321 	struct xgbe_phy_data *phy_data = pdata->phy_data;
2322 
2323 	xgbe_phy_set_redrv_mode(pdata);
2324 
2325 	/* 1G/SGMII */
2326 	xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_1G, XGBE_MB_SUBCMD_1G_SGMII);
2327 
2328 	phy_data->cur_mode = XGBE_MODE_SGMII_1000;
2329 
2330 	netif_dbg(pdata, link, pdata->netdev, "1GbE SGMII mode set\n");
2331 }
2332 
2333 static void xgbe_phy_sgmii_100_mode(struct xgbe_prv_data *pdata)
2334 {
2335 	struct xgbe_phy_data *phy_data = pdata->phy_data;
2336 
2337 	xgbe_phy_set_redrv_mode(pdata);
2338 
2339 	/* 100M/SGMII */
2340 	xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_1G, XGBE_MB_SUBCMD_100MBITS);
2341 
2342 	phy_data->cur_mode = XGBE_MODE_SGMII_100;
2343 
2344 	netif_dbg(pdata, link, pdata->netdev, "100MbE SGMII mode set\n");
2345 }
2346 
2347 static void xgbe_phy_sgmii_10_mode(struct xgbe_prv_data *pdata)
2348 {
2349 	struct xgbe_phy_data *phy_data = pdata->phy_data;
2350 
2351 	xgbe_phy_set_redrv_mode(pdata);
2352 
2353 	/* 10M/SGMII */
2354 	xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_1G, XGBE_MB_SUBCMD_10MBITS);
2355 
2356 	phy_data->cur_mode = XGBE_MODE_SGMII_10;
2357 
2358 	netif_dbg(pdata, link, pdata->netdev, "10MbE SGMII mode set\n");
2359 }
2360 
2361 static void xgbe_phy_kr_mode(struct xgbe_prv_data *pdata)
2362 {
2363 	struct xgbe_phy_data *phy_data = pdata->phy_data;
2364 
2365 	xgbe_phy_set_redrv_mode(pdata);
2366 
2367 	/* 10G/KR */
2368 	if (enable_rx_adap(pdata, XGBE_MODE_KR))
2369 		xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_10G_KR,
2370 					    XGBE_MB_SUBCMD_RX_ADAP);
2371 	else
2372 		xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_10G_KR,
2373 					    XGBE_MB_SUBCMD_NONE);
2374 
2375 	phy_data->cur_mode = XGBE_MODE_KR;
2376 
2377 	netif_dbg(pdata, link, pdata->netdev, "10GbE KR mode set\n");
2378 }
2379 
2380 static void xgbe_phy_kx_2500_mode(struct xgbe_prv_data *pdata)
2381 {
2382 	struct xgbe_phy_data *phy_data = pdata->phy_data;
2383 
2384 	xgbe_phy_set_redrv_mode(pdata);
2385 
2386 	/* 2.5G/KX */
2387 	xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_2_5G, XGBE_MB_SUBCMD_NONE);
2388 
2389 	phy_data->cur_mode = XGBE_MODE_KX_2500;
2390 
2391 	netif_dbg(pdata, link, pdata->netdev, "2.5GbE KX mode set\n");
2392 }
2393 
2394 static void xgbe_phy_kx_1000_mode(struct xgbe_prv_data *pdata)
2395 {
2396 	struct xgbe_phy_data *phy_data = pdata->phy_data;
2397 
2398 	xgbe_phy_set_redrv_mode(pdata);
2399 
2400 	/* 1G/KX */
2401 	xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_1G, XGBE_MB_SUBCMD_1G_KX);
2402 
2403 	phy_data->cur_mode = XGBE_MODE_KX_1000;
2404 
2405 	netif_dbg(pdata, link, pdata->netdev, "1GbE KX mode set\n");
2406 }
2407 
2408 static enum xgbe_mode xgbe_phy_cur_mode(struct xgbe_prv_data *pdata)
2409 {
2410 	struct xgbe_phy_data *phy_data = pdata->phy_data;
2411 
2412 	return phy_data->cur_mode;
2413 }
2414 
2415 static enum xgbe_mode xgbe_phy_switch_baset_mode(struct xgbe_prv_data *pdata)
2416 {
2417 	struct xgbe_phy_data *phy_data = pdata->phy_data;
2418 
2419 	/* No switching if not 10GBase-T */
2420 	if (phy_data->port_mode != XGBE_PORT_MODE_10GBASE_T)
2421 		return xgbe_phy_cur_mode(pdata);
2422 
2423 	switch (xgbe_phy_cur_mode(pdata)) {
2424 	case XGBE_MODE_SGMII_10:
2425 	case XGBE_MODE_SGMII_100:
2426 	case XGBE_MODE_SGMII_1000:
2427 		return XGBE_MODE_KR;
2428 	case XGBE_MODE_KX_2500:
2429 		return XGBE_MODE_SGMII_1000;
2430 	case XGBE_MODE_KR:
2431 	default:
2432 		return XGBE_MODE_KX_2500;
2433 	}
2434 }
2435 
2436 static enum xgbe_mode xgbe_phy_switch_bp_2500_mode(struct xgbe_prv_data *pdata)
2437 {
2438 	return XGBE_MODE_KX_2500;
2439 }
2440 
2441 static enum xgbe_mode xgbe_phy_switch_bp_mode(struct xgbe_prv_data *pdata)
2442 {
2443 	/* If we are in KR switch to KX, and vice-versa */
2444 	switch (xgbe_phy_cur_mode(pdata)) {
2445 	case XGBE_MODE_KX_1000:
2446 		return XGBE_MODE_KR;
2447 	case XGBE_MODE_KR:
2448 	default:
2449 		return XGBE_MODE_KX_1000;
2450 	}
2451 }
2452 
2453 static enum xgbe_mode xgbe_phy_switch_mode(struct xgbe_prv_data *pdata)
2454 {
2455 	struct xgbe_phy_data *phy_data = pdata->phy_data;
2456 
2457 	switch (phy_data->port_mode) {
2458 	case XGBE_PORT_MODE_BACKPLANE:
2459 	case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
2460 		return xgbe_phy_switch_bp_mode(pdata);
2461 	case XGBE_PORT_MODE_BACKPLANE_2500:
2462 		return xgbe_phy_switch_bp_2500_mode(pdata);
2463 	case XGBE_PORT_MODE_1000BASE_T:
2464 	case XGBE_PORT_MODE_NBASE_T:
2465 	case XGBE_PORT_MODE_10GBASE_T:
2466 		return xgbe_phy_switch_baset_mode(pdata);
2467 	case XGBE_PORT_MODE_1000BASE_X:
2468 	case XGBE_PORT_MODE_10GBASE_R:
2469 	case XGBE_PORT_MODE_SFP:
2470 		/* No switching, so just return current mode */
2471 		return xgbe_phy_cur_mode(pdata);
2472 	default:
2473 		return XGBE_MODE_UNKNOWN;
2474 	}
2475 }
2476 
2477 static enum xgbe_mode xgbe_phy_get_basex_mode(struct xgbe_phy_data *phy_data,
2478 					      int speed)
2479 {
2480 	switch (speed) {
2481 	case SPEED_1000:
2482 		return XGBE_MODE_X;
2483 	case SPEED_10000:
2484 		return XGBE_MODE_KR;
2485 	default:
2486 		return XGBE_MODE_UNKNOWN;
2487 	}
2488 }
2489 
2490 static enum xgbe_mode xgbe_phy_get_baset_mode(struct xgbe_phy_data *phy_data,
2491 					      int speed)
2492 {
2493 	switch (speed) {
2494 	case SPEED_10:
2495 		return XGBE_MODE_SGMII_10;
2496 	case SPEED_100:
2497 		return XGBE_MODE_SGMII_100;
2498 	case SPEED_1000:
2499 		return XGBE_MODE_SGMII_1000;
2500 	case SPEED_2500:
2501 		return XGBE_MODE_KX_2500;
2502 	case SPEED_10000:
2503 		return XGBE_MODE_KR;
2504 	default:
2505 		return XGBE_MODE_UNKNOWN;
2506 	}
2507 }
2508 
2509 static enum xgbe_mode xgbe_phy_get_sfp_mode(struct xgbe_phy_data *phy_data,
2510 					    int speed)
2511 {
2512 	switch (speed) {
2513 	case SPEED_10:
2514 		return XGBE_MODE_SGMII_10;
2515 	case SPEED_100:
2516 		return XGBE_MODE_SGMII_100;
2517 	case SPEED_1000:
2518 		if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T)
2519 			return XGBE_MODE_SGMII_1000;
2520 		else
2521 			return XGBE_MODE_X;
2522 	case SPEED_10000:
2523 	case SPEED_UNKNOWN:
2524 		return XGBE_MODE_SFI;
2525 	default:
2526 		return XGBE_MODE_UNKNOWN;
2527 	}
2528 }
2529 
2530 static enum xgbe_mode xgbe_phy_get_bp_2500_mode(int speed)
2531 {
2532 	switch (speed) {
2533 	case SPEED_2500:
2534 		return XGBE_MODE_KX_2500;
2535 	default:
2536 		return XGBE_MODE_UNKNOWN;
2537 	}
2538 }
2539 
2540 static enum xgbe_mode xgbe_phy_get_bp_mode(int speed)
2541 {
2542 	switch (speed) {
2543 	case SPEED_1000:
2544 		return XGBE_MODE_KX_1000;
2545 	case SPEED_10000:
2546 		return XGBE_MODE_KR;
2547 	default:
2548 		return XGBE_MODE_UNKNOWN;
2549 	}
2550 }
2551 
2552 static enum xgbe_mode xgbe_phy_get_mode(struct xgbe_prv_data *pdata,
2553 					int speed)
2554 {
2555 	struct xgbe_phy_data *phy_data = pdata->phy_data;
2556 
2557 	switch (phy_data->port_mode) {
2558 	case XGBE_PORT_MODE_BACKPLANE:
2559 	case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
2560 		return xgbe_phy_get_bp_mode(speed);
2561 	case XGBE_PORT_MODE_BACKPLANE_2500:
2562 		return xgbe_phy_get_bp_2500_mode(speed);
2563 	case XGBE_PORT_MODE_1000BASE_T:
2564 	case XGBE_PORT_MODE_NBASE_T:
2565 	case XGBE_PORT_MODE_10GBASE_T:
2566 		return xgbe_phy_get_baset_mode(phy_data, speed);
2567 	case XGBE_PORT_MODE_1000BASE_X:
2568 	case XGBE_PORT_MODE_10GBASE_R:
2569 		return xgbe_phy_get_basex_mode(phy_data, speed);
2570 	case XGBE_PORT_MODE_SFP:
2571 		return xgbe_phy_get_sfp_mode(phy_data, speed);
2572 	default:
2573 		return XGBE_MODE_UNKNOWN;
2574 	}
2575 }
2576 
2577 static void xgbe_phy_set_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2578 {
2579 	switch (mode) {
2580 	case XGBE_MODE_KX_1000:
2581 		xgbe_phy_kx_1000_mode(pdata);
2582 		break;
2583 	case XGBE_MODE_KX_2500:
2584 		xgbe_phy_kx_2500_mode(pdata);
2585 		break;
2586 	case XGBE_MODE_KR:
2587 		xgbe_phy_kr_mode(pdata);
2588 		break;
2589 	case XGBE_MODE_SGMII_10:
2590 		xgbe_phy_sgmii_10_mode(pdata);
2591 		break;
2592 	case XGBE_MODE_SGMII_100:
2593 		xgbe_phy_sgmii_100_mode(pdata);
2594 		break;
2595 	case XGBE_MODE_SGMII_1000:
2596 		xgbe_phy_sgmii_1000_mode(pdata);
2597 		break;
2598 	case XGBE_MODE_X:
2599 		xgbe_phy_x_mode(pdata);
2600 		break;
2601 	case XGBE_MODE_SFI:
2602 		xgbe_phy_sfi_mode(pdata);
2603 		break;
2604 	default:
2605 		break;
2606 	}
2607 }
2608 
2609 static bool xgbe_phy_check_mode(struct xgbe_prv_data *pdata,
2610 				enum xgbe_mode mode, bool advert)
2611 {
2612 	if (pdata->phy.autoneg == AUTONEG_ENABLE) {
2613 		return advert;
2614 	} else {
2615 		enum xgbe_mode cur_mode;
2616 
2617 		cur_mode = xgbe_phy_get_mode(pdata, pdata->phy.speed);
2618 		if (cur_mode == mode)
2619 			return true;
2620 	}
2621 
2622 	return false;
2623 }
2624 
2625 static bool xgbe_phy_use_basex_mode(struct xgbe_prv_data *pdata,
2626 				    enum xgbe_mode mode)
2627 {
2628 	struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2629 
2630 	switch (mode) {
2631 	case XGBE_MODE_X:
2632 		return xgbe_phy_check_mode(pdata, mode,
2633 					   XGBE_ADV(lks, 1000baseX_Full));
2634 	case XGBE_MODE_KR:
2635 		return xgbe_phy_check_mode(pdata, mode,
2636 					   XGBE_ADV(lks, 10000baseKR_Full));
2637 	default:
2638 		return false;
2639 	}
2640 }
2641 
2642 static bool xgbe_phy_use_baset_mode(struct xgbe_prv_data *pdata,
2643 				    enum xgbe_mode mode)
2644 {
2645 	struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2646 
2647 	switch (mode) {
2648 	case XGBE_MODE_SGMII_10:
2649 		return xgbe_phy_check_mode(pdata, mode,
2650 					   XGBE_ADV(lks, 10baseT_Full));
2651 	case XGBE_MODE_SGMII_100:
2652 		return xgbe_phy_check_mode(pdata, mode,
2653 					   XGBE_ADV(lks, 100baseT_Full));
2654 	case XGBE_MODE_SGMII_1000:
2655 		return xgbe_phy_check_mode(pdata, mode,
2656 					   XGBE_ADV(lks, 1000baseT_Full));
2657 	case XGBE_MODE_KX_2500:
2658 		return xgbe_phy_check_mode(pdata, mode,
2659 					   XGBE_ADV(lks, 2500baseT_Full));
2660 	case XGBE_MODE_KR:
2661 		return xgbe_phy_check_mode(pdata, mode,
2662 					   XGBE_ADV(lks, 10000baseT_Full));
2663 	default:
2664 		return false;
2665 	}
2666 }
2667 
2668 static bool xgbe_phy_use_sfp_mode(struct xgbe_prv_data *pdata,
2669 				  enum xgbe_mode mode)
2670 {
2671 	struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2672 	struct xgbe_phy_data *phy_data = pdata->phy_data;
2673 
2674 	switch (mode) {
2675 	case XGBE_MODE_X:
2676 		if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T)
2677 			return false;
2678 		return xgbe_phy_check_mode(pdata, mode,
2679 					   XGBE_ADV(lks, 1000baseX_Full));
2680 	case XGBE_MODE_SGMII_10:
2681 		if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
2682 			return false;
2683 		return xgbe_phy_check_mode(pdata, mode,
2684 					   XGBE_ADV(lks, 10baseT_Full));
2685 	case XGBE_MODE_SGMII_100:
2686 		if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
2687 			return false;
2688 		return xgbe_phy_check_mode(pdata, mode,
2689 					   XGBE_ADV(lks, 100baseT_Full));
2690 	case XGBE_MODE_SGMII_1000:
2691 		if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
2692 			return false;
2693 		return xgbe_phy_check_mode(pdata, mode,
2694 					   XGBE_ADV(lks, 1000baseT_Full));
2695 	case XGBE_MODE_SFI:
2696 		if (phy_data->sfp_mod_absent)
2697 			return true;
2698 		return xgbe_phy_check_mode(pdata, mode,
2699 					   XGBE_ADV(lks, 10000baseSR_Full)  ||
2700 					   XGBE_ADV(lks, 10000baseLR_Full)  ||
2701 					   XGBE_ADV(lks, 10000baseLRM_Full) ||
2702 					   XGBE_ADV(lks, 10000baseER_Full)  ||
2703 					   XGBE_ADV(lks, 10000baseCR_Full));
2704 	default:
2705 		return false;
2706 	}
2707 }
2708 
2709 static bool xgbe_phy_use_bp_2500_mode(struct xgbe_prv_data *pdata,
2710 				      enum xgbe_mode mode)
2711 {
2712 	struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2713 
2714 	switch (mode) {
2715 	case XGBE_MODE_KX_2500:
2716 		return xgbe_phy_check_mode(pdata, mode,
2717 					   XGBE_ADV(lks, 2500baseX_Full));
2718 	default:
2719 		return false;
2720 	}
2721 }
2722 
2723 static bool xgbe_phy_use_bp_mode(struct xgbe_prv_data *pdata,
2724 				 enum xgbe_mode mode)
2725 {
2726 	struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2727 
2728 	switch (mode) {
2729 	case XGBE_MODE_KX_1000:
2730 		return xgbe_phy_check_mode(pdata, mode,
2731 					   XGBE_ADV(lks, 1000baseKX_Full));
2732 	case XGBE_MODE_KR:
2733 		return xgbe_phy_check_mode(pdata, mode,
2734 					   XGBE_ADV(lks, 10000baseKR_Full));
2735 	default:
2736 		return false;
2737 	}
2738 }
2739 
2740 static bool xgbe_phy_use_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2741 {
2742 	struct xgbe_phy_data *phy_data = pdata->phy_data;
2743 
2744 	switch (phy_data->port_mode) {
2745 	case XGBE_PORT_MODE_BACKPLANE:
2746 	case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
2747 		return xgbe_phy_use_bp_mode(pdata, mode);
2748 	case XGBE_PORT_MODE_BACKPLANE_2500:
2749 		return xgbe_phy_use_bp_2500_mode(pdata, mode);
2750 	case XGBE_PORT_MODE_1000BASE_T:
2751 	case XGBE_PORT_MODE_NBASE_T:
2752 	case XGBE_PORT_MODE_10GBASE_T:
2753 		return xgbe_phy_use_baset_mode(pdata, mode);
2754 	case XGBE_PORT_MODE_1000BASE_X:
2755 	case XGBE_PORT_MODE_10GBASE_R:
2756 		return xgbe_phy_use_basex_mode(pdata, mode);
2757 	case XGBE_PORT_MODE_SFP:
2758 		return xgbe_phy_use_sfp_mode(pdata, mode);
2759 	default:
2760 		return false;
2761 	}
2762 }
2763 
2764 static bool xgbe_phy_valid_speed_basex_mode(struct xgbe_phy_data *phy_data,
2765 					    int speed)
2766 {
2767 	switch (speed) {
2768 	case SPEED_1000:
2769 		return (phy_data->port_mode == XGBE_PORT_MODE_1000BASE_X);
2770 	case SPEED_10000:
2771 		return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_R);
2772 	default:
2773 		return false;
2774 	}
2775 }
2776 
2777 static bool xgbe_phy_valid_speed_baset_mode(struct xgbe_prv_data *pdata,
2778 					    int speed)
2779 {
2780 	struct xgbe_phy_data *phy_data = pdata->phy_data;
2781 	unsigned int ver;
2782 
2783 	switch (speed) {
2784 	case SPEED_10:
2785 		/* Supported in ver 21H and ver >= 30H */
2786 		ver = XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER);
2787 		return (ver == 0x21 || ver >= 0x30);
2788 	case SPEED_100:
2789 	case SPEED_1000:
2790 		return true;
2791 	case SPEED_2500:
2792 		return ((phy_data->port_mode == XGBE_PORT_MODE_10GBASE_T) ||
2793 			(phy_data->port_mode == XGBE_PORT_MODE_NBASE_T));
2794 	case SPEED_10000:
2795 		return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_T);
2796 	default:
2797 		return false;
2798 	}
2799 }
2800 
2801 static bool xgbe_phy_valid_speed_sfp_mode(struct xgbe_prv_data *pdata,
2802 					  int speed)
2803 {
2804 	struct xgbe_phy_data *phy_data = pdata->phy_data;
2805 	unsigned int ver;
2806 
2807 	switch (speed) {
2808 	case SPEED_10:
2809 		/* Supported in ver 21H and ver >= 30H */
2810 		ver = XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER);
2811 		return ((ver == 0x21 || ver >= 0x30) &&
2812 			(phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000));
2813 	case SPEED_100:
2814 		return (phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000);
2815 	case SPEED_1000:
2816 		return ((phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000) ||
2817 			(phy_data->sfp_speed == XGBE_SFP_SPEED_1000));
2818 	case SPEED_10000:
2819 		return (phy_data->sfp_speed == XGBE_SFP_SPEED_10000);
2820 	default:
2821 		return false;
2822 	}
2823 }
2824 
2825 static bool xgbe_phy_valid_speed_bp_2500_mode(int speed)
2826 {
2827 	switch (speed) {
2828 	case SPEED_2500:
2829 		return true;
2830 	default:
2831 		return false;
2832 	}
2833 }
2834 
2835 static bool xgbe_phy_valid_speed_bp_mode(int speed)
2836 {
2837 	switch (speed) {
2838 	case SPEED_1000:
2839 	case SPEED_10000:
2840 		return true;
2841 	default:
2842 		return false;
2843 	}
2844 }
2845 
2846 static bool xgbe_phy_valid_speed(struct xgbe_prv_data *pdata, int speed)
2847 {
2848 	struct xgbe_phy_data *phy_data = pdata->phy_data;
2849 
2850 	switch (phy_data->port_mode) {
2851 	case XGBE_PORT_MODE_BACKPLANE:
2852 	case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
2853 		return xgbe_phy_valid_speed_bp_mode(speed);
2854 	case XGBE_PORT_MODE_BACKPLANE_2500:
2855 		return xgbe_phy_valid_speed_bp_2500_mode(speed);
2856 	case XGBE_PORT_MODE_1000BASE_T:
2857 	case XGBE_PORT_MODE_NBASE_T:
2858 	case XGBE_PORT_MODE_10GBASE_T:
2859 		return xgbe_phy_valid_speed_baset_mode(pdata, speed);
2860 	case XGBE_PORT_MODE_1000BASE_X:
2861 	case XGBE_PORT_MODE_10GBASE_R:
2862 		return xgbe_phy_valid_speed_basex_mode(phy_data, speed);
2863 	case XGBE_PORT_MODE_SFP:
2864 		return xgbe_phy_valid_speed_sfp_mode(pdata, speed);
2865 	default:
2866 		return false;
2867 	}
2868 }
2869 
2870 static int xgbe_phy_link_status(struct xgbe_prv_data *pdata, int *an_restart)
2871 {
2872 	struct xgbe_phy_data *phy_data = pdata->phy_data;
2873 	unsigned int reg;
2874 	int ret;
2875 
2876 	*an_restart = 0;
2877 
2878 	if (phy_data->port_mode == XGBE_PORT_MODE_SFP) {
2879 		/* Check SFP signals */
2880 		xgbe_phy_sfp_detect(pdata);
2881 
2882 		if (phy_data->sfp_changed) {
2883 			*an_restart = 1;
2884 			return 0;
2885 		}
2886 
2887 		if (phy_data->sfp_mod_absent || phy_data->sfp_rx_los) {
2888 			if (pdata->en_rx_adap)
2889 				pdata->rx_adapt_done = false;
2890 			return 0;
2891 		}
2892 	}
2893 
2894 	if (phy_data->phydev) {
2895 		/* Check external PHY */
2896 		ret = phy_read_status(phy_data->phydev);
2897 		if (ret < 0)
2898 			return 0;
2899 
2900 		if ((pdata->phy.autoneg == AUTONEG_ENABLE) &&
2901 		    !phy_aneg_done(phy_data->phydev))
2902 			return 0;
2903 
2904 		if (!phy_data->phydev->link)
2905 			return 0;
2906 	}
2907 
2908 	/* Link status is latched low, so read once to clear
2909 	 * and then read again to get current state
2910 	 */
2911 	reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
2912 	reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
2913 
2914 	if (pdata->en_rx_adap) {
2915 		/* if the link is available and adaptation is done,
2916 		 * declare link up
2917 		 */
2918 		if ((reg & MDIO_STAT1_LSTATUS) && pdata->rx_adapt_done)
2919 			return 1;
2920 		/* If either link is not available or adaptation is not done,
2921 		 * retrigger the adaptation logic. (if the mode is not set,
2922 		 * then issue mailbox command first)
2923 		 */
2924 		if (pdata->mode_set) {
2925 			xgbe_phy_rx_adaptation(pdata);
2926 		} else {
2927 			pdata->rx_adapt_done = false;
2928 			xgbe_phy_set_mode(pdata, phy_data->cur_mode);
2929 		}
2930 
2931 		/* check again for the link and adaptation status */
2932 		reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
2933 		if ((reg & MDIO_STAT1_LSTATUS) && pdata->rx_adapt_done)
2934 			return 1;
2935 	} else if (reg & MDIO_STAT1_LSTATUS)
2936 		return 1;
2937 
2938 	if (pdata->phy.autoneg == AUTONEG_ENABLE &&
2939 	    phy_data->port_mode == XGBE_PORT_MODE_BACKPLANE) {
2940 		if (!test_bit(XGBE_LINK_INIT, &pdata->dev_state)) {
2941 			netif_carrier_off(pdata->netdev);
2942 			*an_restart = 1;
2943 		}
2944 	}
2945 
2946 	/* No link, attempt a receiver reset cycle */
2947 	if (pdata->vdata->enable_rrc && phy_data->rrc_count++ > XGBE_RRC_FREQUENCY) {
2948 		phy_data->rrc_count = 0;
2949 		xgbe_phy_rrc(pdata);
2950 	}
2951 
2952 	return 0;
2953 }
2954 
2955 static void xgbe_phy_sfp_gpio_setup(struct xgbe_prv_data *pdata)
2956 {
2957 	struct xgbe_phy_data *phy_data = pdata->phy_data;
2958 
2959 	phy_data->sfp_gpio_address = XGBE_GPIO_ADDRESS_PCA9555 +
2960 				     XP_GET_BITS(pdata->pp3, XP_PROP_3,
2961 						 GPIO_ADDR);
2962 
2963 	phy_data->sfp_gpio_mask = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2964 					      GPIO_MASK);
2965 
2966 	phy_data->sfp_gpio_rx_los = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2967 						GPIO_RX_LOS);
2968 	phy_data->sfp_gpio_tx_fault = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2969 						  GPIO_TX_FAULT);
2970 	phy_data->sfp_gpio_mod_absent = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2971 						    GPIO_MOD_ABS);
2972 	phy_data->sfp_gpio_rate_select = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2973 						     GPIO_RATE_SELECT);
2974 
2975 	if (netif_msg_probe(pdata)) {
2976 		dev_dbg(pdata->dev, "SFP: gpio_address=%#x\n",
2977 			phy_data->sfp_gpio_address);
2978 		dev_dbg(pdata->dev, "SFP: gpio_mask=%#x\n",
2979 			phy_data->sfp_gpio_mask);
2980 		dev_dbg(pdata->dev, "SFP: gpio_rx_los=%u\n",
2981 			phy_data->sfp_gpio_rx_los);
2982 		dev_dbg(pdata->dev, "SFP: gpio_tx_fault=%u\n",
2983 			phy_data->sfp_gpio_tx_fault);
2984 		dev_dbg(pdata->dev, "SFP: gpio_mod_absent=%u\n",
2985 			phy_data->sfp_gpio_mod_absent);
2986 		dev_dbg(pdata->dev, "SFP: gpio_rate_select=%u\n",
2987 			phy_data->sfp_gpio_rate_select);
2988 	}
2989 }
2990 
2991 static void xgbe_phy_sfp_comm_setup(struct xgbe_prv_data *pdata)
2992 {
2993 	struct xgbe_phy_data *phy_data = pdata->phy_data;
2994 	unsigned int mux_addr_hi, mux_addr_lo;
2995 
2996 	mux_addr_hi = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_HI);
2997 	mux_addr_lo = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_LO);
2998 	if (mux_addr_lo == XGBE_SFP_DIRECT)
2999 		return;
3000 
3001 	phy_data->sfp_comm = XGBE_SFP_COMM_PCA9545;
3002 	phy_data->sfp_mux_address = (mux_addr_hi << 2) + mux_addr_lo;
3003 	phy_data->sfp_mux_channel = XP_GET_BITS(pdata->pp4, XP_PROP_4,
3004 						MUX_CHAN);
3005 
3006 	if (netif_msg_probe(pdata)) {
3007 		dev_dbg(pdata->dev, "SFP: mux_address=%#x\n",
3008 			phy_data->sfp_mux_address);
3009 		dev_dbg(pdata->dev, "SFP: mux_channel=%u\n",
3010 			phy_data->sfp_mux_channel);
3011 	}
3012 }
3013 
3014 static void xgbe_phy_sfp_setup(struct xgbe_prv_data *pdata)
3015 {
3016 	xgbe_phy_sfp_comm_setup(pdata);
3017 	xgbe_phy_sfp_gpio_setup(pdata);
3018 }
3019 
3020 static int xgbe_phy_int_mdio_reset(struct xgbe_prv_data *pdata)
3021 {
3022 	struct xgbe_phy_data *phy_data = pdata->phy_data;
3023 	unsigned int ret;
3024 
3025 	ret = pdata->hw_if.set_gpio(pdata, phy_data->mdio_reset_gpio);
3026 	if (ret)
3027 		return ret;
3028 
3029 	ret = pdata->hw_if.clr_gpio(pdata, phy_data->mdio_reset_gpio);
3030 
3031 	return ret;
3032 }
3033 
3034 static int xgbe_phy_i2c_mdio_reset(struct xgbe_prv_data *pdata)
3035 {
3036 	struct xgbe_phy_data *phy_data = pdata->phy_data;
3037 	u8 gpio_reg, gpio_ports[2], gpio_data[3];
3038 	int ret;
3039 
3040 	/* Read the output port registers */
3041 	gpio_reg = 2;
3042 	ret = xgbe_phy_i2c_read(pdata, phy_data->mdio_reset_addr,
3043 				&gpio_reg, sizeof(gpio_reg),
3044 				gpio_ports, sizeof(gpio_ports));
3045 	if (ret)
3046 		return ret;
3047 
3048 	/* Prepare to write the GPIO data */
3049 	gpio_data[0] = 2;
3050 	gpio_data[1] = gpio_ports[0];
3051 	gpio_data[2] = gpio_ports[1];
3052 
3053 	/* Set the GPIO pin */
3054 	if (phy_data->mdio_reset_gpio < 8)
3055 		gpio_data[1] |= (1 << (phy_data->mdio_reset_gpio % 8));
3056 	else
3057 		gpio_data[2] |= (1 << (phy_data->mdio_reset_gpio % 8));
3058 
3059 	/* Write the output port registers */
3060 	ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr,
3061 				 gpio_data, sizeof(gpio_data));
3062 	if (ret)
3063 		return ret;
3064 
3065 	/* Clear the GPIO pin */
3066 	if (phy_data->mdio_reset_gpio < 8)
3067 		gpio_data[1] &= ~(1 << (phy_data->mdio_reset_gpio % 8));
3068 	else
3069 		gpio_data[2] &= ~(1 << (phy_data->mdio_reset_gpio % 8));
3070 
3071 	/* Write the output port registers */
3072 	ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr,
3073 				 gpio_data, sizeof(gpio_data));
3074 
3075 	return ret;
3076 }
3077 
3078 static int xgbe_phy_mdio_reset(struct xgbe_prv_data *pdata)
3079 {
3080 	struct xgbe_phy_data *phy_data = pdata->phy_data;
3081 	int ret;
3082 
3083 	if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO)
3084 		return 0;
3085 
3086 	ret = xgbe_phy_get_comm_ownership(pdata);
3087 	if (ret)
3088 		return ret;
3089 
3090 	if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO)
3091 		ret = xgbe_phy_i2c_mdio_reset(pdata);
3092 	else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO)
3093 		ret = xgbe_phy_int_mdio_reset(pdata);
3094 
3095 	xgbe_phy_put_comm_ownership(pdata);
3096 
3097 	return ret;
3098 }
3099 
3100 static bool xgbe_phy_redrv_error(struct xgbe_phy_data *phy_data)
3101 {
3102 	if (!phy_data->redrv)
3103 		return false;
3104 
3105 	if (phy_data->redrv_if >= XGBE_PHY_REDRV_IF_MAX)
3106 		return true;
3107 
3108 	switch (phy_data->redrv_model) {
3109 	case XGBE_PHY_REDRV_MODEL_4223:
3110 		if (phy_data->redrv_lane > 3)
3111 			return true;
3112 		break;
3113 	case XGBE_PHY_REDRV_MODEL_4227:
3114 		if (phy_data->redrv_lane > 1)
3115 			return true;
3116 		break;
3117 	default:
3118 		return true;
3119 	}
3120 
3121 	return false;
3122 }
3123 
3124 static int xgbe_phy_mdio_reset_setup(struct xgbe_prv_data *pdata)
3125 {
3126 	struct xgbe_phy_data *phy_data = pdata->phy_data;
3127 
3128 	if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO)
3129 		return 0;
3130 
3131 	phy_data->mdio_reset = XP_GET_BITS(pdata->pp3, XP_PROP_3, MDIO_RESET);
3132 	switch (phy_data->mdio_reset) {
3133 	case XGBE_MDIO_RESET_NONE:
3134 	case XGBE_MDIO_RESET_I2C_GPIO:
3135 	case XGBE_MDIO_RESET_INT_GPIO:
3136 		break;
3137 	default:
3138 		dev_err(pdata->dev, "unsupported MDIO reset (%#x)\n",
3139 			phy_data->mdio_reset);
3140 		return -EINVAL;
3141 	}
3142 
3143 	if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO) {
3144 		phy_data->mdio_reset_addr = XGBE_GPIO_ADDRESS_PCA9555 +
3145 					    XP_GET_BITS(pdata->pp3, XP_PROP_3,
3146 							MDIO_RESET_I2C_ADDR);
3147 		phy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3,
3148 							MDIO_RESET_I2C_GPIO);
3149 	} else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO) {
3150 		phy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3,
3151 							MDIO_RESET_INT_GPIO);
3152 	}
3153 
3154 	return 0;
3155 }
3156 
3157 static bool xgbe_phy_port_mode_mismatch(struct xgbe_prv_data *pdata)
3158 {
3159 	struct xgbe_phy_data *phy_data = pdata->phy_data;
3160 	unsigned int ver;
3161 
3162 	/* 10 Mbps speed is supported in ver 21H and ver >= 30H */
3163 	ver = XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER);
3164 	if ((ver < 0x30 && ver != 0x21) && (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10))
3165 		return true;
3166 
3167 	switch (phy_data->port_mode) {
3168 	case XGBE_PORT_MODE_BACKPLANE:
3169 	case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
3170 		if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
3171 		    (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
3172 			return false;
3173 		break;
3174 	case XGBE_PORT_MODE_BACKPLANE_2500:
3175 		if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500)
3176 			return false;
3177 		break;
3178 	case XGBE_PORT_MODE_1000BASE_T:
3179 		if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10) ||
3180 		    (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
3181 		    (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000))
3182 			return false;
3183 		break;
3184 	case XGBE_PORT_MODE_1000BASE_X:
3185 		if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
3186 			return false;
3187 		break;
3188 	case XGBE_PORT_MODE_NBASE_T:
3189 		if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10) ||
3190 		    (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
3191 		    (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
3192 		    (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500))
3193 			return false;
3194 		break;
3195 	case XGBE_PORT_MODE_10GBASE_T:
3196 		if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10) ||
3197 		    (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
3198 		    (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
3199 		    (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500) ||
3200 		    (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
3201 			return false;
3202 		break;
3203 	case XGBE_PORT_MODE_10GBASE_R:
3204 		if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)
3205 			return false;
3206 		break;
3207 	case XGBE_PORT_MODE_SFP:
3208 		if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10) ||
3209 		    (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
3210 		    (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
3211 		    (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
3212 			return false;
3213 		break;
3214 	default:
3215 		break;
3216 	}
3217 
3218 	return true;
3219 }
3220 
3221 static bool xgbe_phy_conn_type_mismatch(struct xgbe_prv_data *pdata)
3222 {
3223 	struct xgbe_phy_data *phy_data = pdata->phy_data;
3224 
3225 	switch (phy_data->port_mode) {
3226 	case XGBE_PORT_MODE_BACKPLANE:
3227 	case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
3228 	case XGBE_PORT_MODE_BACKPLANE_2500:
3229 		if (phy_data->conn_type == XGBE_CONN_TYPE_BACKPLANE)
3230 			return false;
3231 		break;
3232 	case XGBE_PORT_MODE_1000BASE_T:
3233 	case XGBE_PORT_MODE_1000BASE_X:
3234 	case XGBE_PORT_MODE_NBASE_T:
3235 	case XGBE_PORT_MODE_10GBASE_T:
3236 	case XGBE_PORT_MODE_10GBASE_R:
3237 		if (phy_data->conn_type == XGBE_CONN_TYPE_MDIO)
3238 			return false;
3239 		break;
3240 	case XGBE_PORT_MODE_SFP:
3241 		if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
3242 			return false;
3243 		break;
3244 	default:
3245 		break;
3246 	}
3247 
3248 	return true;
3249 }
3250 
3251 static bool xgbe_phy_port_enabled(struct xgbe_prv_data *pdata)
3252 {
3253 	if (!XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS))
3254 		return false;
3255 	if (!XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE))
3256 		return false;
3257 
3258 	return true;
3259 }
3260 
3261 static void xgbe_phy_cdr_track(struct xgbe_prv_data *pdata)
3262 {
3263 	struct xgbe_phy_data *phy_data = pdata->phy_data;
3264 
3265 	if (!pdata->debugfs_an_cdr_workaround)
3266 		return;
3267 
3268 	if (!phy_data->phy_cdr_notrack)
3269 		return;
3270 
3271 	usleep_range(phy_data->phy_cdr_delay,
3272 		     phy_data->phy_cdr_delay + 500);
3273 
3274 	XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL,
3275 			 XGBE_PMA_CDR_TRACK_EN_MASK,
3276 			 XGBE_PMA_CDR_TRACK_EN_ON);
3277 
3278 	phy_data->phy_cdr_notrack = 0;
3279 }
3280 
3281 static void xgbe_phy_cdr_notrack(struct xgbe_prv_data *pdata)
3282 {
3283 	struct xgbe_phy_data *phy_data = pdata->phy_data;
3284 
3285 	if (!pdata->debugfs_an_cdr_workaround)
3286 		return;
3287 
3288 	if (phy_data->phy_cdr_notrack)
3289 		return;
3290 
3291 	XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL,
3292 			 XGBE_PMA_CDR_TRACK_EN_MASK,
3293 			 XGBE_PMA_CDR_TRACK_EN_OFF);
3294 
3295 	xgbe_phy_rrc(pdata);
3296 
3297 	phy_data->phy_cdr_notrack = 1;
3298 }
3299 
3300 static void xgbe_phy_kr_training_post(struct xgbe_prv_data *pdata)
3301 {
3302 	if (!pdata->debugfs_an_cdr_track_early)
3303 		xgbe_phy_cdr_track(pdata);
3304 }
3305 
3306 static void xgbe_phy_kr_training_pre(struct xgbe_prv_data *pdata)
3307 {
3308 	if (pdata->debugfs_an_cdr_track_early)
3309 		xgbe_phy_cdr_track(pdata);
3310 }
3311 
3312 static void xgbe_phy_an_post(struct xgbe_prv_data *pdata)
3313 {
3314 	struct xgbe_phy_data *phy_data = pdata->phy_data;
3315 
3316 	switch (pdata->an_mode) {
3317 	case XGBE_AN_MODE_CL73:
3318 	case XGBE_AN_MODE_CL73_REDRV:
3319 		if (phy_data->cur_mode != XGBE_MODE_KR)
3320 			break;
3321 
3322 		xgbe_phy_cdr_track(pdata);
3323 
3324 		switch (pdata->an_result) {
3325 		case XGBE_AN_READY:
3326 		case XGBE_AN_COMPLETE:
3327 			break;
3328 		default:
3329 			if (phy_data->phy_cdr_delay < XGBE_CDR_DELAY_MAX)
3330 				phy_data->phy_cdr_delay += XGBE_CDR_DELAY_INC;
3331 			else
3332 				phy_data->phy_cdr_delay = XGBE_CDR_DELAY_INIT;
3333 			break;
3334 		}
3335 		break;
3336 	default:
3337 		break;
3338 	}
3339 }
3340 
3341 static void xgbe_phy_an_pre(struct xgbe_prv_data *pdata)
3342 {
3343 	struct xgbe_phy_data *phy_data = pdata->phy_data;
3344 
3345 	switch (pdata->an_mode) {
3346 	case XGBE_AN_MODE_CL73:
3347 	case XGBE_AN_MODE_CL73_REDRV:
3348 		if (phy_data->cur_mode != XGBE_MODE_KR)
3349 			break;
3350 
3351 		xgbe_phy_cdr_notrack(pdata);
3352 		break;
3353 	default:
3354 		break;
3355 	}
3356 }
3357 
3358 static void xgbe_phy_stop(struct xgbe_prv_data *pdata)
3359 {
3360 	struct xgbe_phy_data *phy_data = pdata->phy_data;
3361 
3362 	/* If we have an external PHY, free it */
3363 	xgbe_phy_free_phy_device(pdata);
3364 
3365 	/* Reset SFP data */
3366 	xgbe_phy_sfp_reset(phy_data);
3367 	xgbe_phy_sfp_mod_absent(pdata);
3368 
3369 	/* Reset CDR support */
3370 	xgbe_phy_cdr_track(pdata);
3371 
3372 	/* Power off the PHY */
3373 	xgbe_phy_power_off(pdata);
3374 
3375 	/* Stop the I2C controller */
3376 	pdata->i2c_if.i2c_stop(pdata);
3377 }
3378 
3379 static int xgbe_phy_start(struct xgbe_prv_data *pdata)
3380 {
3381 	struct xgbe_phy_data *phy_data = pdata->phy_data;
3382 	int ret;
3383 
3384 	/* Start the I2C controller */
3385 	ret = pdata->i2c_if.i2c_start(pdata);
3386 	if (ret)
3387 		return ret;
3388 
3389 	/* Set the proper MDIO mode for the re-driver */
3390 	if (phy_data->redrv && !phy_data->redrv_if) {
3391 		ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr,
3392 						    XGBE_MDIO_MODE_CL22);
3393 		if (ret) {
3394 			netdev_err(pdata->netdev,
3395 				   "redriver mdio port not compatible (%u)\n",
3396 				   phy_data->redrv_addr);
3397 			return ret;
3398 		}
3399 	}
3400 
3401 	/* Start in highest supported mode */
3402 	xgbe_phy_set_mode(pdata, phy_data->start_mode);
3403 
3404 	/* Reset CDR support */
3405 	xgbe_phy_cdr_track(pdata);
3406 
3407 	/* After starting the I2C controller, we can check for an SFP */
3408 	switch (phy_data->port_mode) {
3409 	case XGBE_PORT_MODE_SFP:
3410 		xgbe_phy_sfp_detect(pdata);
3411 		break;
3412 	default:
3413 		break;
3414 	}
3415 
3416 	/* If we have an external PHY, start it */
3417 	ret = xgbe_phy_find_phy_device(pdata);
3418 	if (ret)
3419 		goto err_i2c;
3420 
3421 	return 0;
3422 
3423 err_i2c:
3424 	pdata->i2c_if.i2c_stop(pdata);
3425 
3426 	return ret;
3427 }
3428 
3429 static int xgbe_phy_reset(struct xgbe_prv_data *pdata)
3430 {
3431 	struct xgbe_phy_data *phy_data = pdata->phy_data;
3432 	enum xgbe_mode cur_mode;
3433 	int ret;
3434 
3435 	/* Reset by power cycling the PHY */
3436 	cur_mode = phy_data->cur_mode;
3437 	xgbe_phy_power_off(pdata);
3438 	xgbe_phy_set_mode(pdata, cur_mode);
3439 
3440 	if (!phy_data->phydev)
3441 		return 0;
3442 
3443 	/* Reset the external PHY */
3444 	ret = xgbe_phy_mdio_reset(pdata);
3445 	if (ret)
3446 		return ret;
3447 
3448 	return phy_init_hw(phy_data->phydev);
3449 }
3450 
3451 static void xgbe_phy_exit(struct xgbe_prv_data *pdata)
3452 {
3453 	struct xgbe_phy_data *phy_data = pdata->phy_data;
3454 
3455 	/* Unregister for driving external PHYs */
3456 	mdiobus_unregister(phy_data->mii);
3457 }
3458 
3459 static int xgbe_phy_init(struct xgbe_prv_data *pdata)
3460 {
3461 	struct ethtool_link_ksettings *lks = &pdata->phy.lks;
3462 	struct xgbe_phy_data *phy_data;
3463 	struct mii_bus *mii;
3464 	int ret;
3465 
3466 	/* Check if enabled */
3467 	if (!xgbe_phy_port_enabled(pdata)) {
3468 		dev_info(pdata->dev, "device is not enabled\n");
3469 		return -ENODEV;
3470 	}
3471 
3472 	/* Initialize the I2C controller */
3473 	ret = pdata->i2c_if.i2c_init(pdata);
3474 	if (ret)
3475 		return ret;
3476 
3477 	phy_data = devm_kzalloc(pdata->dev, sizeof(*phy_data), GFP_KERNEL);
3478 	if (!phy_data)
3479 		return -ENOMEM;
3480 	pdata->phy_data = phy_data;
3481 
3482 	phy_data->port_mode = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_MODE);
3483 	phy_data->port_id = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_ID);
3484 	phy_data->port_speeds = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS);
3485 	phy_data->conn_type = XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE);
3486 	phy_data->mdio_addr = XP_GET_BITS(pdata->pp0, XP_PROP_0, MDIO_ADDR);
3487 	if (netif_msg_probe(pdata)) {
3488 		dev_dbg(pdata->dev, "port mode=%u\n", phy_data->port_mode);
3489 		dev_dbg(pdata->dev, "port id=%u\n", phy_data->port_id);
3490 		dev_dbg(pdata->dev, "port speeds=%#x\n", phy_data->port_speeds);
3491 		dev_dbg(pdata->dev, "conn type=%u\n", phy_data->conn_type);
3492 		dev_dbg(pdata->dev, "mdio addr=%u\n", phy_data->mdio_addr);
3493 	}
3494 
3495 	phy_data->redrv = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_PRESENT);
3496 	phy_data->redrv_if = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_IF);
3497 	phy_data->redrv_addr = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_ADDR);
3498 	phy_data->redrv_lane = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_LANE);
3499 	phy_data->redrv_model = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_MODEL);
3500 	if (phy_data->redrv && netif_msg_probe(pdata)) {
3501 		dev_dbg(pdata->dev, "redrv present\n");
3502 		dev_dbg(pdata->dev, "redrv i/f=%u\n", phy_data->redrv_if);
3503 		dev_dbg(pdata->dev, "redrv addr=%#x\n", phy_data->redrv_addr);
3504 		dev_dbg(pdata->dev, "redrv lane=%u\n", phy_data->redrv_lane);
3505 		dev_dbg(pdata->dev, "redrv model=%u\n", phy_data->redrv_model);
3506 	}
3507 
3508 	/* Validate the connection requested */
3509 	if (xgbe_phy_conn_type_mismatch(pdata)) {
3510 		dev_err(pdata->dev, "phy mode/connection mismatch (%#x/%#x)\n",
3511 			phy_data->port_mode, phy_data->conn_type);
3512 		return -EINVAL;
3513 	}
3514 
3515 	/* Validate the mode requested */
3516 	if (xgbe_phy_port_mode_mismatch(pdata)) {
3517 		dev_err(pdata->dev, "phy mode/speed mismatch (%#x/%#x)\n",
3518 			phy_data->port_mode, phy_data->port_speeds);
3519 		return -EINVAL;
3520 	}
3521 
3522 	/* Check for and validate MDIO reset support */
3523 	ret = xgbe_phy_mdio_reset_setup(pdata);
3524 	if (ret)
3525 		return ret;
3526 
3527 	/* Validate the re-driver information */
3528 	if (xgbe_phy_redrv_error(phy_data)) {
3529 		dev_err(pdata->dev, "phy re-driver settings error\n");
3530 		return -EINVAL;
3531 	}
3532 	pdata->kr_redrv = phy_data->redrv;
3533 
3534 	/* Indicate current mode is unknown */
3535 	phy_data->cur_mode = XGBE_MODE_UNKNOWN;
3536 
3537 	/* Initialize supported features */
3538 	XGBE_ZERO_SUP(lks);
3539 
3540 	switch (phy_data->port_mode) {
3541 	/* Backplane support */
3542 	case XGBE_PORT_MODE_BACKPLANE:
3543 		XGBE_SET_SUP(lks, Autoneg);
3544 		fallthrough;
3545 	case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
3546 		XGBE_SET_SUP(lks, Pause);
3547 		XGBE_SET_SUP(lks, Asym_Pause);
3548 		XGBE_SET_SUP(lks, Backplane);
3549 		if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3550 			XGBE_SET_SUP(lks, 1000baseKX_Full);
3551 			phy_data->start_mode = XGBE_MODE_KX_1000;
3552 		}
3553 		if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
3554 			XGBE_SET_SUP(lks, 10000baseKR_Full);
3555 			if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
3556 				XGBE_SET_SUP(lks, 10000baseR_FEC);
3557 			phy_data->start_mode = XGBE_MODE_KR;
3558 		}
3559 
3560 		phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
3561 		break;
3562 	case XGBE_PORT_MODE_BACKPLANE_2500:
3563 		XGBE_SET_SUP(lks, Pause);
3564 		XGBE_SET_SUP(lks, Asym_Pause);
3565 		XGBE_SET_SUP(lks, Backplane);
3566 		XGBE_SET_SUP(lks, 2500baseX_Full);
3567 		phy_data->start_mode = XGBE_MODE_KX_2500;
3568 
3569 		phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
3570 		break;
3571 
3572 	/* MDIO 1GBase-T support */
3573 	case XGBE_PORT_MODE_1000BASE_T:
3574 		XGBE_SET_SUP(lks, Autoneg);
3575 		XGBE_SET_SUP(lks, Pause);
3576 		XGBE_SET_SUP(lks, Asym_Pause);
3577 		XGBE_SET_SUP(lks, TP);
3578 		if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10) {
3579 			XGBE_SET_SUP(lks, 10baseT_Full);
3580 			phy_data->start_mode = XGBE_MODE_SGMII_10;
3581 		}
3582 		if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
3583 			XGBE_SET_SUP(lks, 100baseT_Full);
3584 			phy_data->start_mode = XGBE_MODE_SGMII_100;
3585 		}
3586 		if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3587 			XGBE_SET_SUP(lks, 1000baseT_Full);
3588 			phy_data->start_mode = XGBE_MODE_SGMII_1000;
3589 		}
3590 
3591 		phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
3592 		break;
3593 
3594 	/* MDIO Base-X support */
3595 	case XGBE_PORT_MODE_1000BASE_X:
3596 		XGBE_SET_SUP(lks, Autoneg);
3597 		XGBE_SET_SUP(lks, Pause);
3598 		XGBE_SET_SUP(lks, Asym_Pause);
3599 		XGBE_SET_SUP(lks, FIBRE);
3600 		XGBE_SET_SUP(lks, 1000baseX_Full);
3601 		phy_data->start_mode = XGBE_MODE_X;
3602 
3603 		phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
3604 		break;
3605 
3606 	/* MDIO NBase-T support */
3607 	case XGBE_PORT_MODE_NBASE_T:
3608 		XGBE_SET_SUP(lks, Autoneg);
3609 		XGBE_SET_SUP(lks, Pause);
3610 		XGBE_SET_SUP(lks, Asym_Pause);
3611 		XGBE_SET_SUP(lks, TP);
3612 		if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10) {
3613 			XGBE_SET_SUP(lks, 10baseT_Full);
3614 			phy_data->start_mode = XGBE_MODE_SGMII_10;
3615 		}
3616 		if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
3617 			XGBE_SET_SUP(lks, 100baseT_Full);
3618 			phy_data->start_mode = XGBE_MODE_SGMII_100;
3619 		}
3620 		if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3621 			XGBE_SET_SUP(lks, 1000baseT_Full);
3622 			phy_data->start_mode = XGBE_MODE_SGMII_1000;
3623 		}
3624 		if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500) {
3625 			XGBE_SET_SUP(lks, 2500baseT_Full);
3626 			phy_data->start_mode = XGBE_MODE_KX_2500;
3627 		}
3628 
3629 		phy_data->phydev_mode = XGBE_MDIO_MODE_CL45;
3630 		break;
3631 
3632 	/* 10GBase-T support */
3633 	case XGBE_PORT_MODE_10GBASE_T:
3634 		XGBE_SET_SUP(lks, Autoneg);
3635 		XGBE_SET_SUP(lks, Pause);
3636 		XGBE_SET_SUP(lks, Asym_Pause);
3637 		XGBE_SET_SUP(lks, TP);
3638 		if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10) {
3639 			XGBE_SET_SUP(lks, 10baseT_Full);
3640 			phy_data->start_mode = XGBE_MODE_SGMII_10;
3641 		}
3642 		if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
3643 			XGBE_SET_SUP(lks, 100baseT_Full);
3644 			phy_data->start_mode = XGBE_MODE_SGMII_100;
3645 		}
3646 		if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3647 			XGBE_SET_SUP(lks, 1000baseT_Full);
3648 			phy_data->start_mode = XGBE_MODE_SGMII_1000;
3649 		}
3650 		if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500) {
3651 			XGBE_SET_SUP(lks, 2500baseT_Full);
3652 			phy_data->start_mode = XGBE_MODE_KX_2500;
3653 		}
3654 		if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
3655 			XGBE_SET_SUP(lks, 10000baseT_Full);
3656 			phy_data->start_mode = XGBE_MODE_KR;
3657 		}
3658 
3659 		phy_data->phydev_mode = XGBE_MDIO_MODE_CL45;
3660 		break;
3661 
3662 	/* 10GBase-R support */
3663 	case XGBE_PORT_MODE_10GBASE_R:
3664 		XGBE_SET_SUP(lks, Autoneg);
3665 		XGBE_SET_SUP(lks, Pause);
3666 		XGBE_SET_SUP(lks, Asym_Pause);
3667 		XGBE_SET_SUP(lks, FIBRE);
3668 		XGBE_SET_SUP(lks, 10000baseSR_Full);
3669 		XGBE_SET_SUP(lks, 10000baseLR_Full);
3670 		XGBE_SET_SUP(lks, 10000baseLRM_Full);
3671 		XGBE_SET_SUP(lks, 10000baseER_Full);
3672 		if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
3673 			XGBE_SET_SUP(lks, 10000baseR_FEC);
3674 		phy_data->start_mode = XGBE_MODE_SFI;
3675 
3676 		phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
3677 		break;
3678 
3679 	/* SFP support */
3680 	case XGBE_PORT_MODE_SFP:
3681 		XGBE_SET_SUP(lks, Autoneg);
3682 		XGBE_SET_SUP(lks, Pause);
3683 		XGBE_SET_SUP(lks, Asym_Pause);
3684 		XGBE_SET_SUP(lks, TP);
3685 		XGBE_SET_SUP(lks, FIBRE);
3686 		if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10)
3687 			phy_data->start_mode = XGBE_MODE_SGMII_10;
3688 		if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100)
3689 			phy_data->start_mode = XGBE_MODE_SGMII_100;
3690 		if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
3691 			phy_data->start_mode = XGBE_MODE_SGMII_1000;
3692 		if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)
3693 			phy_data->start_mode = XGBE_MODE_SFI;
3694 
3695 		phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
3696 
3697 		xgbe_phy_sfp_setup(pdata);
3698 		break;
3699 	default:
3700 		return -EINVAL;
3701 	}
3702 
3703 	if (netif_msg_probe(pdata))
3704 		dev_dbg(pdata->dev, "phy supported=0x%*pb\n",
3705 			__ETHTOOL_LINK_MODE_MASK_NBITS,
3706 			lks->link_modes.supported);
3707 
3708 	if ((phy_data->conn_type & XGBE_CONN_TYPE_MDIO) &&
3709 	    (phy_data->phydev_mode != XGBE_MDIO_MODE_NONE)) {
3710 		ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr,
3711 						    phy_data->phydev_mode);
3712 		if (ret) {
3713 			dev_err(pdata->dev,
3714 				"mdio port/clause not compatible (%d/%u)\n",
3715 				phy_data->mdio_addr, phy_data->phydev_mode);
3716 			return -EINVAL;
3717 		}
3718 	}
3719 
3720 	if (phy_data->redrv && !phy_data->redrv_if) {
3721 		ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr,
3722 						    XGBE_MDIO_MODE_CL22);
3723 		if (ret) {
3724 			dev_err(pdata->dev,
3725 				"redriver mdio port not compatible (%u)\n",
3726 				phy_data->redrv_addr);
3727 			return -EINVAL;
3728 		}
3729 	}
3730 
3731 	phy_data->phy_cdr_delay = XGBE_CDR_DELAY_INIT;
3732 
3733 	/* Register for driving external PHYs */
3734 	mii = devm_mdiobus_alloc(pdata->dev);
3735 	if (!mii) {
3736 		dev_err(pdata->dev, "mdiobus_alloc failed\n");
3737 		return -ENOMEM;
3738 	}
3739 
3740 	mii->priv = pdata;
3741 	mii->name = "amd-xgbe-mii";
3742 	mii->read = xgbe_phy_mii_read_c22;
3743 	mii->write = xgbe_phy_mii_write_c22;
3744 	mii->read_c45 = xgbe_phy_mii_read_c45;
3745 	mii->write_c45 = xgbe_phy_mii_write_c45;
3746 	mii->parent = pdata->dev;
3747 	mii->phy_mask = ~0;
3748 	snprintf(mii->id, sizeof(mii->id), "%s", dev_name(pdata->dev));
3749 	ret = mdiobus_register(mii);
3750 	if (ret) {
3751 		dev_err(pdata->dev, "mdiobus_register failed\n");
3752 		return ret;
3753 	}
3754 	phy_data->mii = mii;
3755 
3756 	return 0;
3757 }
3758 
3759 void xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if *phy_if)
3760 {
3761 	struct xgbe_phy_impl_if *phy_impl = &phy_if->phy_impl;
3762 
3763 	phy_impl->init			= xgbe_phy_init;
3764 	phy_impl->exit			= xgbe_phy_exit;
3765 
3766 	phy_impl->reset			= xgbe_phy_reset;
3767 	phy_impl->start			= xgbe_phy_start;
3768 	phy_impl->stop			= xgbe_phy_stop;
3769 
3770 	phy_impl->link_status		= xgbe_phy_link_status;
3771 
3772 	phy_impl->valid_speed		= xgbe_phy_valid_speed;
3773 
3774 	phy_impl->use_mode		= xgbe_phy_use_mode;
3775 	phy_impl->set_mode		= xgbe_phy_set_mode;
3776 	phy_impl->get_mode		= xgbe_phy_get_mode;
3777 	phy_impl->switch_mode		= xgbe_phy_switch_mode;
3778 	phy_impl->cur_mode		= xgbe_phy_cur_mode;
3779 
3780 	phy_impl->an_mode		= xgbe_phy_an_mode;
3781 
3782 	phy_impl->an_config		= xgbe_phy_an_config;
3783 
3784 	phy_impl->an_advertising	= xgbe_phy_an_advertising;
3785 
3786 	phy_impl->an_outcome		= xgbe_phy_an_outcome;
3787 
3788 	phy_impl->an_pre		= xgbe_phy_an_pre;
3789 	phy_impl->an_post		= xgbe_phy_an_post;
3790 
3791 	phy_impl->kr_training_pre	= xgbe_phy_kr_training_pre;
3792 	phy_impl->kr_training_post	= xgbe_phy_kr_training_post;
3793 
3794 	phy_impl->module_info		= xgbe_phy_module_info;
3795 	phy_impl->module_eeprom		= xgbe_phy_module_eeprom;
3796 }
3797