1 /* 2 * AMD 10Gb Ethernet driver 3 * 4 * This file is available to you under your choice of the following two 5 * licenses: 6 * 7 * License 1: GPLv2 8 * 9 * Copyright (c) 2016 Advanced Micro Devices, Inc. 10 * 11 * This file is free software; you may copy, redistribute and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation, either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program. If not, see <http://www.gnu.org/licenses/>. 23 * 24 * This file incorporates work covered by the following copyright and 25 * permission notice: 26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 28 * Inc. unless otherwise expressly agreed to in writing between Synopsys 29 * and you. 30 * 31 * The Software IS NOT an item of Licensed Software or Licensed Product 32 * under any End User Software License Agreement or Agreement for Licensed 33 * Product with Synopsys or any supplement thereto. Permission is hereby 34 * granted, free of charge, to any person obtaining a copy of this software 35 * annotated with this license and the Software, to deal in the Software 36 * without restriction, including without limitation the rights to use, 37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 38 * of the Software, and to permit persons to whom the Software is furnished 39 * to do so, subject to the following conditions: 40 * 41 * The above copyright notice and this permission notice shall be included 42 * in all copies or substantial portions of the Software. 43 * 44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 54 * THE POSSIBILITY OF SUCH DAMAGE. 55 * 56 * 57 * License 2: Modified BSD 58 * 59 * Copyright (c) 2016 Advanced Micro Devices, Inc. 60 * All rights reserved. 61 * 62 * Redistribution and use in source and binary forms, with or without 63 * modification, are permitted provided that the following conditions are met: 64 * * Redistributions of source code must retain the above copyright 65 * notice, this list of conditions and the following disclaimer. 66 * * Redistributions in binary form must reproduce the above copyright 67 * notice, this list of conditions and the following disclaimer in the 68 * documentation and/or other materials provided with the distribution. 69 * * Neither the name of Advanced Micro Devices, Inc. nor the 70 * names of its contributors may be used to endorse or promote products 71 * derived from this software without specific prior written permission. 72 * 73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY 77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 83 * 84 * This file incorporates work covered by the following copyright and 85 * permission notice: 86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 88 * Inc. unless otherwise expressly agreed to in writing between Synopsys 89 * and you. 90 * 91 * The Software IS NOT an item of Licensed Software or Licensed Product 92 * under any End User Software License Agreement or Agreement for Licensed 93 * Product with Synopsys or any supplement thereto. Permission is hereby 94 * granted, free of charge, to any person obtaining a copy of this software 95 * annotated with this license and the Software, to deal in the Software 96 * without restriction, including without limitation the rights to use, 97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 98 * of the Software, and to permit persons to whom the Software is furnished 99 * to do so, subject to the following conditions: 100 * 101 * The above copyright notice and this permission notice shall be included 102 * in all copies or substantial portions of the Software. 103 * 104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 114 * THE POSSIBILITY OF SUCH DAMAGE. 115 */ 116 117 #include <linux/module.h> 118 #include <linux/device.h> 119 #include <linux/kmod.h> 120 #include <linux/mdio.h> 121 #include <linux/phy.h> 122 123 #include "xgbe.h" 124 #include "xgbe-common.h" 125 126 #define XGBE_PHY_PORT_SPEED_100 BIT(0) 127 #define XGBE_PHY_PORT_SPEED_1000 BIT(1) 128 #define XGBE_PHY_PORT_SPEED_2500 BIT(2) 129 #define XGBE_PHY_PORT_SPEED_10000 BIT(3) 130 131 #define XGBE_MUTEX_RELEASE 0x80000000 132 133 #define XGBE_SFP_DIRECT 7 134 135 /* I2C target addresses */ 136 #define XGBE_SFP_SERIAL_ID_ADDRESS 0x50 137 #define XGBE_SFP_DIAG_INFO_ADDRESS 0x51 138 #define XGBE_SFP_PHY_ADDRESS 0x56 139 #define XGBE_GPIO_ADDRESS_PCA9555 0x20 140 141 /* SFP sideband signal indicators */ 142 #define XGBE_GPIO_NO_TX_FAULT BIT(0) 143 #define XGBE_GPIO_NO_RATE_SELECT BIT(1) 144 #define XGBE_GPIO_NO_MOD_ABSENT BIT(2) 145 #define XGBE_GPIO_NO_RX_LOS BIT(3) 146 147 /* Rate-change complete wait/retry count */ 148 #define XGBE_RATECHANGE_COUNT 500 149 150 /* CDR delay values for KR support (in usec) */ 151 #define XGBE_CDR_DELAY_INIT 10000 152 #define XGBE_CDR_DELAY_INC 10000 153 #define XGBE_CDR_DELAY_MAX 100000 154 155 /* RRC frequency during link status check */ 156 #define XGBE_RRC_FREQUENCY 10 157 158 enum xgbe_port_mode { 159 XGBE_PORT_MODE_RSVD = 0, 160 XGBE_PORT_MODE_BACKPLANE, 161 XGBE_PORT_MODE_BACKPLANE_2500, 162 XGBE_PORT_MODE_1000BASE_T, 163 XGBE_PORT_MODE_1000BASE_X, 164 XGBE_PORT_MODE_NBASE_T, 165 XGBE_PORT_MODE_10GBASE_T, 166 XGBE_PORT_MODE_10GBASE_R, 167 XGBE_PORT_MODE_SFP, 168 XGBE_PORT_MODE_MAX, 169 }; 170 171 enum xgbe_conn_type { 172 XGBE_CONN_TYPE_NONE = 0, 173 XGBE_CONN_TYPE_SFP, 174 XGBE_CONN_TYPE_MDIO, 175 XGBE_CONN_TYPE_RSVD1, 176 XGBE_CONN_TYPE_BACKPLANE, 177 XGBE_CONN_TYPE_MAX, 178 }; 179 180 /* SFP/SFP+ related definitions */ 181 enum xgbe_sfp_comm { 182 XGBE_SFP_COMM_DIRECT = 0, 183 XGBE_SFP_COMM_PCA9545, 184 }; 185 186 enum xgbe_sfp_cable { 187 XGBE_SFP_CABLE_UNKNOWN = 0, 188 XGBE_SFP_CABLE_ACTIVE, 189 XGBE_SFP_CABLE_PASSIVE, 190 }; 191 192 enum xgbe_sfp_base { 193 XGBE_SFP_BASE_UNKNOWN = 0, 194 XGBE_SFP_BASE_1000_T, 195 XGBE_SFP_BASE_1000_SX, 196 XGBE_SFP_BASE_1000_LX, 197 XGBE_SFP_BASE_1000_CX, 198 XGBE_SFP_BASE_10000_SR, 199 XGBE_SFP_BASE_10000_LR, 200 XGBE_SFP_BASE_10000_LRM, 201 XGBE_SFP_BASE_10000_ER, 202 XGBE_SFP_BASE_10000_CR, 203 }; 204 205 enum xgbe_sfp_speed { 206 XGBE_SFP_SPEED_UNKNOWN = 0, 207 XGBE_SFP_SPEED_100_1000, 208 XGBE_SFP_SPEED_1000, 209 XGBE_SFP_SPEED_10000, 210 }; 211 212 /* SFP Serial ID Base ID values relative to an offset of 0 */ 213 #define XGBE_SFP_BASE_ID 0 214 #define XGBE_SFP_ID_SFP 0x03 215 216 #define XGBE_SFP_BASE_EXT_ID 1 217 #define XGBE_SFP_EXT_ID_SFP 0x04 218 219 #define XGBE_SFP_BASE_10GBE_CC 3 220 #define XGBE_SFP_BASE_10GBE_CC_SR BIT(4) 221 #define XGBE_SFP_BASE_10GBE_CC_LR BIT(5) 222 #define XGBE_SFP_BASE_10GBE_CC_LRM BIT(6) 223 #define XGBE_SFP_BASE_10GBE_CC_ER BIT(7) 224 225 #define XGBE_SFP_BASE_1GBE_CC 6 226 #define XGBE_SFP_BASE_1GBE_CC_SX BIT(0) 227 #define XGBE_SFP_BASE_1GBE_CC_LX BIT(1) 228 #define XGBE_SFP_BASE_1GBE_CC_CX BIT(2) 229 #define XGBE_SFP_BASE_1GBE_CC_T BIT(3) 230 231 #define XGBE_SFP_BASE_CABLE 8 232 #define XGBE_SFP_BASE_CABLE_PASSIVE BIT(2) 233 #define XGBE_SFP_BASE_CABLE_ACTIVE BIT(3) 234 235 #define XGBE_SFP_BASE_BR 12 236 #define XGBE_SFP_BASE_BR_1GBE_MIN 0x0a 237 #define XGBE_SFP_BASE_BR_1GBE_MAX 0x0d 238 #define XGBE_SFP_BASE_BR_10GBE_MIN 0x64 239 #define XGBE_SFP_BASE_BR_10GBE_MAX 0x68 240 241 #define XGBE_SFP_BASE_CU_CABLE_LEN 18 242 243 #define XGBE_SFP_BASE_VENDOR_NAME 20 244 #define XGBE_SFP_BASE_VENDOR_NAME_LEN 16 245 #define XGBE_SFP_BASE_VENDOR_PN 40 246 #define XGBE_SFP_BASE_VENDOR_PN_LEN 16 247 #define XGBE_SFP_BASE_VENDOR_REV 56 248 #define XGBE_SFP_BASE_VENDOR_REV_LEN 4 249 250 #define XGBE_SFP_BASE_CC 63 251 252 /* SFP Serial ID Extended ID values relative to an offset of 64 */ 253 #define XGBE_SFP_BASE_VENDOR_SN 4 254 #define XGBE_SFP_BASE_VENDOR_SN_LEN 16 255 256 #define XGBE_SFP_EXTD_OPT1 1 257 #define XGBE_SFP_EXTD_OPT1_RX_LOS BIT(1) 258 #define XGBE_SFP_EXTD_OPT1_TX_FAULT BIT(3) 259 260 #define XGBE_SFP_EXTD_DIAG 28 261 #define XGBE_SFP_EXTD_DIAG_ADDR_CHANGE BIT(2) 262 263 #define XGBE_SFP_EXTD_SFF_8472 30 264 265 #define XGBE_SFP_EXTD_CC 31 266 267 struct xgbe_sfp_eeprom { 268 u8 base[64]; 269 u8 extd[32]; 270 u8 vendor[32]; 271 }; 272 273 #define XGBE_BEL_FUSE_VENDOR "BEL-FUSE " 274 #define XGBE_BEL_FUSE_PARTNO "1GBT-SFP06 " 275 276 struct xgbe_sfp_ascii { 277 union { 278 char vendor[XGBE_SFP_BASE_VENDOR_NAME_LEN + 1]; 279 char partno[XGBE_SFP_BASE_VENDOR_PN_LEN + 1]; 280 char rev[XGBE_SFP_BASE_VENDOR_REV_LEN + 1]; 281 char serno[XGBE_SFP_BASE_VENDOR_SN_LEN + 1]; 282 } u; 283 }; 284 285 /* MDIO PHY reset types */ 286 enum xgbe_mdio_reset { 287 XGBE_MDIO_RESET_NONE = 0, 288 XGBE_MDIO_RESET_I2C_GPIO, 289 XGBE_MDIO_RESET_INT_GPIO, 290 XGBE_MDIO_RESET_MAX, 291 }; 292 293 /* Re-driver related definitions */ 294 enum xgbe_phy_redrv_if { 295 XGBE_PHY_REDRV_IF_MDIO = 0, 296 XGBE_PHY_REDRV_IF_I2C, 297 XGBE_PHY_REDRV_IF_MAX, 298 }; 299 300 enum xgbe_phy_redrv_model { 301 XGBE_PHY_REDRV_MODEL_4223 = 0, 302 XGBE_PHY_REDRV_MODEL_4227, 303 XGBE_PHY_REDRV_MODEL_MAX, 304 }; 305 306 enum xgbe_phy_redrv_mode { 307 XGBE_PHY_REDRV_MODE_CX = 5, 308 XGBE_PHY_REDRV_MODE_SR = 9, 309 }; 310 311 #define XGBE_PHY_REDRV_MODE_REG 0x12b0 312 313 /* PHY related configuration information */ 314 struct xgbe_phy_data { 315 enum xgbe_port_mode port_mode; 316 317 unsigned int port_id; 318 319 unsigned int port_speeds; 320 321 enum xgbe_conn_type conn_type; 322 323 enum xgbe_mode cur_mode; 324 enum xgbe_mode start_mode; 325 326 unsigned int rrc_count; 327 328 unsigned int mdio_addr; 329 330 unsigned int comm_owned; 331 332 /* SFP Support */ 333 enum xgbe_sfp_comm sfp_comm; 334 unsigned int sfp_mux_address; 335 unsigned int sfp_mux_channel; 336 337 unsigned int sfp_gpio_address; 338 unsigned int sfp_gpio_mask; 339 unsigned int sfp_gpio_inputs; 340 unsigned int sfp_gpio_rx_los; 341 unsigned int sfp_gpio_tx_fault; 342 unsigned int sfp_gpio_mod_absent; 343 unsigned int sfp_gpio_rate_select; 344 345 unsigned int sfp_rx_los; 346 unsigned int sfp_tx_fault; 347 unsigned int sfp_mod_absent; 348 unsigned int sfp_diags; 349 unsigned int sfp_changed; 350 unsigned int sfp_phy_avail; 351 unsigned int sfp_cable_len; 352 enum xgbe_sfp_base sfp_base; 353 enum xgbe_sfp_cable sfp_cable; 354 enum xgbe_sfp_speed sfp_speed; 355 struct xgbe_sfp_eeprom sfp_eeprom; 356 357 /* External PHY support */ 358 enum xgbe_mdio_mode phydev_mode; 359 struct mii_bus *mii; 360 struct phy_device *phydev; 361 enum xgbe_mdio_reset mdio_reset; 362 unsigned int mdio_reset_addr; 363 unsigned int mdio_reset_gpio; 364 365 /* Re-driver support */ 366 unsigned int redrv; 367 unsigned int redrv_if; 368 unsigned int redrv_addr; 369 unsigned int redrv_lane; 370 unsigned int redrv_model; 371 372 /* KR AN support */ 373 unsigned int phy_cdr_notrack; 374 unsigned int phy_cdr_delay; 375 }; 376 377 /* I2C, MDIO and GPIO lines are muxed, so only one device at a time */ 378 static DEFINE_MUTEX(xgbe_phy_comm_lock); 379 380 static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata); 381 382 static int xgbe_phy_i2c_xfer(struct xgbe_prv_data *pdata, 383 struct xgbe_i2c_op *i2c_op) 384 { 385 struct xgbe_phy_data *phy_data = pdata->phy_data; 386 387 /* Be sure we own the bus */ 388 if (WARN_ON(!phy_data->comm_owned)) 389 return -EIO; 390 391 return pdata->i2c_if.i2c_xfer(pdata, i2c_op); 392 } 393 394 static int xgbe_phy_redrv_write(struct xgbe_prv_data *pdata, unsigned int reg, 395 unsigned int val) 396 { 397 struct xgbe_phy_data *phy_data = pdata->phy_data; 398 struct xgbe_i2c_op i2c_op; 399 __be16 *redrv_val; 400 u8 redrv_data[5], csum; 401 unsigned int i, retry; 402 int ret; 403 404 /* High byte of register contains read/write indicator */ 405 redrv_data[0] = ((reg >> 8) & 0xff) << 1; 406 redrv_data[1] = reg & 0xff; 407 redrv_val = (__be16 *)&redrv_data[2]; 408 *redrv_val = cpu_to_be16(val); 409 410 /* Calculate 1 byte checksum */ 411 csum = 0; 412 for (i = 0; i < 4; i++) { 413 csum += redrv_data[i]; 414 if (redrv_data[i] > csum) 415 csum++; 416 } 417 redrv_data[4] = ~csum; 418 419 retry = 1; 420 again1: 421 i2c_op.cmd = XGBE_I2C_CMD_WRITE; 422 i2c_op.target = phy_data->redrv_addr; 423 i2c_op.len = sizeof(redrv_data); 424 i2c_op.buf = redrv_data; 425 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op); 426 if (ret) { 427 if ((ret == -EAGAIN) && retry--) 428 goto again1; 429 430 return ret; 431 } 432 433 retry = 1; 434 again2: 435 i2c_op.cmd = XGBE_I2C_CMD_READ; 436 i2c_op.target = phy_data->redrv_addr; 437 i2c_op.len = 1; 438 i2c_op.buf = redrv_data; 439 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op); 440 if (ret) { 441 if ((ret == -EAGAIN) && retry--) 442 goto again2; 443 444 return ret; 445 } 446 447 if (redrv_data[0] != 0xff) { 448 netif_dbg(pdata, drv, pdata->netdev, 449 "Redriver write checksum error\n"); 450 ret = -EIO; 451 } 452 453 return ret; 454 } 455 456 static int xgbe_phy_i2c_write(struct xgbe_prv_data *pdata, unsigned int target, 457 void *val, unsigned int val_len) 458 { 459 struct xgbe_i2c_op i2c_op; 460 int retry, ret; 461 462 retry = 1; 463 again: 464 /* Write the specfied register */ 465 i2c_op.cmd = XGBE_I2C_CMD_WRITE; 466 i2c_op.target = target; 467 i2c_op.len = val_len; 468 i2c_op.buf = val; 469 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op); 470 if ((ret == -EAGAIN) && retry--) 471 goto again; 472 473 return ret; 474 } 475 476 static int xgbe_phy_i2c_read(struct xgbe_prv_data *pdata, unsigned int target, 477 void *reg, unsigned int reg_len, 478 void *val, unsigned int val_len) 479 { 480 struct xgbe_i2c_op i2c_op; 481 int retry, ret; 482 483 retry = 1; 484 again1: 485 /* Set the specified register to read */ 486 i2c_op.cmd = XGBE_I2C_CMD_WRITE; 487 i2c_op.target = target; 488 i2c_op.len = reg_len; 489 i2c_op.buf = reg; 490 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op); 491 if (ret) { 492 if ((ret == -EAGAIN) && retry--) 493 goto again1; 494 495 return ret; 496 } 497 498 retry = 1; 499 again2: 500 /* Read the specfied register */ 501 i2c_op.cmd = XGBE_I2C_CMD_READ; 502 i2c_op.target = target; 503 i2c_op.len = val_len; 504 i2c_op.buf = val; 505 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op); 506 if ((ret == -EAGAIN) && retry--) 507 goto again2; 508 509 return ret; 510 } 511 512 static int xgbe_phy_sfp_put_mux(struct xgbe_prv_data *pdata) 513 { 514 struct xgbe_phy_data *phy_data = pdata->phy_data; 515 struct xgbe_i2c_op i2c_op; 516 u8 mux_channel; 517 518 if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT) 519 return 0; 520 521 /* Select no mux channels */ 522 mux_channel = 0; 523 i2c_op.cmd = XGBE_I2C_CMD_WRITE; 524 i2c_op.target = phy_data->sfp_mux_address; 525 i2c_op.len = sizeof(mux_channel); 526 i2c_op.buf = &mux_channel; 527 528 return xgbe_phy_i2c_xfer(pdata, &i2c_op); 529 } 530 531 static int xgbe_phy_sfp_get_mux(struct xgbe_prv_data *pdata) 532 { 533 struct xgbe_phy_data *phy_data = pdata->phy_data; 534 struct xgbe_i2c_op i2c_op; 535 u8 mux_channel; 536 537 if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT) 538 return 0; 539 540 /* Select desired mux channel */ 541 mux_channel = 1 << phy_data->sfp_mux_channel; 542 i2c_op.cmd = XGBE_I2C_CMD_WRITE; 543 i2c_op.target = phy_data->sfp_mux_address; 544 i2c_op.len = sizeof(mux_channel); 545 i2c_op.buf = &mux_channel; 546 547 return xgbe_phy_i2c_xfer(pdata, &i2c_op); 548 } 549 550 static void xgbe_phy_put_comm_ownership(struct xgbe_prv_data *pdata) 551 { 552 struct xgbe_phy_data *phy_data = pdata->phy_data; 553 554 phy_data->comm_owned = 0; 555 556 mutex_unlock(&xgbe_phy_comm_lock); 557 } 558 559 static int xgbe_phy_get_comm_ownership(struct xgbe_prv_data *pdata) 560 { 561 struct xgbe_phy_data *phy_data = pdata->phy_data; 562 unsigned long timeout; 563 unsigned int mutex_id; 564 565 if (phy_data->comm_owned) 566 return 0; 567 568 /* The I2C and MDIO/GPIO bus is multiplexed between multiple devices, 569 * the driver needs to take the software mutex and then the hardware 570 * mutexes before being able to use the busses. 571 */ 572 mutex_lock(&xgbe_phy_comm_lock); 573 574 /* Clear the mutexes */ 575 XP_IOWRITE(pdata, XP_I2C_MUTEX, XGBE_MUTEX_RELEASE); 576 XP_IOWRITE(pdata, XP_MDIO_MUTEX, XGBE_MUTEX_RELEASE); 577 578 /* Mutex formats are the same for I2C and MDIO/GPIO */ 579 mutex_id = 0; 580 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ID, phy_data->port_id); 581 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ACTIVE, 1); 582 583 timeout = jiffies + (5 * HZ); 584 while (time_before(jiffies, timeout)) { 585 /* Must be all zeroes in order to obtain the mutex */ 586 if (XP_IOREAD(pdata, XP_I2C_MUTEX) || 587 XP_IOREAD(pdata, XP_MDIO_MUTEX)) { 588 usleep_range(100, 200); 589 continue; 590 } 591 592 /* Obtain the mutex */ 593 XP_IOWRITE(pdata, XP_I2C_MUTEX, mutex_id); 594 XP_IOWRITE(pdata, XP_MDIO_MUTEX, mutex_id); 595 596 phy_data->comm_owned = 1; 597 return 0; 598 } 599 600 mutex_unlock(&xgbe_phy_comm_lock); 601 602 netdev_err(pdata->netdev, "unable to obtain hardware mutexes\n"); 603 604 return -ETIMEDOUT; 605 } 606 607 static int xgbe_phy_mdio_mii_write(struct xgbe_prv_data *pdata, int addr, 608 int reg, u16 val) 609 { 610 struct xgbe_phy_data *phy_data = pdata->phy_data; 611 612 if (reg & MII_ADDR_C45) { 613 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45) 614 return -ENOTSUPP; 615 } else { 616 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22) 617 return -ENOTSUPP; 618 } 619 620 return pdata->hw_if.write_ext_mii_regs(pdata, addr, reg, val); 621 } 622 623 static int xgbe_phy_i2c_mii_write(struct xgbe_prv_data *pdata, int reg, u16 val) 624 { 625 __be16 *mii_val; 626 u8 mii_data[3]; 627 int ret; 628 629 ret = xgbe_phy_sfp_get_mux(pdata); 630 if (ret) 631 return ret; 632 633 mii_data[0] = reg & 0xff; 634 mii_val = (__be16 *)&mii_data[1]; 635 *mii_val = cpu_to_be16(val); 636 637 ret = xgbe_phy_i2c_write(pdata, XGBE_SFP_PHY_ADDRESS, 638 mii_data, sizeof(mii_data)); 639 640 xgbe_phy_sfp_put_mux(pdata); 641 642 return ret; 643 } 644 645 static int xgbe_phy_mii_write(struct mii_bus *mii, int addr, int reg, u16 val) 646 { 647 struct xgbe_prv_data *pdata = mii->priv; 648 struct xgbe_phy_data *phy_data = pdata->phy_data; 649 int ret; 650 651 ret = xgbe_phy_get_comm_ownership(pdata); 652 if (ret) 653 return ret; 654 655 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP) 656 ret = xgbe_phy_i2c_mii_write(pdata, reg, val); 657 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO) 658 ret = xgbe_phy_mdio_mii_write(pdata, addr, reg, val); 659 else 660 ret = -ENOTSUPP; 661 662 xgbe_phy_put_comm_ownership(pdata); 663 664 return ret; 665 } 666 667 static int xgbe_phy_mdio_mii_read(struct xgbe_prv_data *pdata, int addr, 668 int reg) 669 { 670 struct xgbe_phy_data *phy_data = pdata->phy_data; 671 672 if (reg & MII_ADDR_C45) { 673 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45) 674 return -ENOTSUPP; 675 } else { 676 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22) 677 return -ENOTSUPP; 678 } 679 680 return pdata->hw_if.read_ext_mii_regs(pdata, addr, reg); 681 } 682 683 static int xgbe_phy_i2c_mii_read(struct xgbe_prv_data *pdata, int reg) 684 { 685 __be16 mii_val; 686 u8 mii_reg; 687 int ret; 688 689 ret = xgbe_phy_sfp_get_mux(pdata); 690 if (ret) 691 return ret; 692 693 mii_reg = reg; 694 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_PHY_ADDRESS, 695 &mii_reg, sizeof(mii_reg), 696 &mii_val, sizeof(mii_val)); 697 if (!ret) 698 ret = be16_to_cpu(mii_val); 699 700 xgbe_phy_sfp_put_mux(pdata); 701 702 return ret; 703 } 704 705 static int xgbe_phy_mii_read(struct mii_bus *mii, int addr, int reg) 706 { 707 struct xgbe_prv_data *pdata = mii->priv; 708 struct xgbe_phy_data *phy_data = pdata->phy_data; 709 int ret; 710 711 ret = xgbe_phy_get_comm_ownership(pdata); 712 if (ret) 713 return ret; 714 715 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP) 716 ret = xgbe_phy_i2c_mii_read(pdata, reg); 717 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO) 718 ret = xgbe_phy_mdio_mii_read(pdata, addr, reg); 719 else 720 ret = -ENOTSUPP; 721 722 xgbe_phy_put_comm_ownership(pdata); 723 724 return ret; 725 } 726 727 static void xgbe_phy_sfp_phy_settings(struct xgbe_prv_data *pdata) 728 { 729 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 730 struct xgbe_phy_data *phy_data = pdata->phy_data; 731 732 if (!phy_data->sfp_mod_absent && !phy_data->sfp_changed) 733 return; 734 735 XGBE_ZERO_SUP(lks); 736 737 if (phy_data->sfp_mod_absent) { 738 pdata->phy.speed = SPEED_UNKNOWN; 739 pdata->phy.duplex = DUPLEX_UNKNOWN; 740 pdata->phy.autoneg = AUTONEG_ENABLE; 741 pdata->phy.pause_autoneg = AUTONEG_ENABLE; 742 743 XGBE_SET_SUP(lks, Autoneg); 744 XGBE_SET_SUP(lks, Pause); 745 XGBE_SET_SUP(lks, Asym_Pause); 746 XGBE_SET_SUP(lks, TP); 747 XGBE_SET_SUP(lks, FIBRE); 748 749 XGBE_LM_COPY(lks, advertising, lks, supported); 750 751 return; 752 } 753 754 switch (phy_data->sfp_base) { 755 case XGBE_SFP_BASE_1000_T: 756 case XGBE_SFP_BASE_1000_SX: 757 case XGBE_SFP_BASE_1000_LX: 758 case XGBE_SFP_BASE_1000_CX: 759 pdata->phy.speed = SPEED_UNKNOWN; 760 pdata->phy.duplex = DUPLEX_UNKNOWN; 761 pdata->phy.autoneg = AUTONEG_ENABLE; 762 pdata->phy.pause_autoneg = AUTONEG_ENABLE; 763 XGBE_SET_SUP(lks, Autoneg); 764 XGBE_SET_SUP(lks, Pause); 765 XGBE_SET_SUP(lks, Asym_Pause); 766 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T) { 767 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) 768 XGBE_SET_SUP(lks, 100baseT_Full); 769 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) 770 XGBE_SET_SUP(lks, 1000baseT_Full); 771 } else { 772 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) 773 XGBE_SET_SUP(lks, 1000baseX_Full); 774 } 775 break; 776 case XGBE_SFP_BASE_10000_SR: 777 case XGBE_SFP_BASE_10000_LR: 778 case XGBE_SFP_BASE_10000_LRM: 779 case XGBE_SFP_BASE_10000_ER: 780 case XGBE_SFP_BASE_10000_CR: 781 pdata->phy.speed = SPEED_10000; 782 pdata->phy.duplex = DUPLEX_FULL; 783 pdata->phy.autoneg = AUTONEG_DISABLE; 784 pdata->phy.pause_autoneg = AUTONEG_DISABLE; 785 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) { 786 switch (phy_data->sfp_base) { 787 case XGBE_SFP_BASE_10000_SR: 788 XGBE_SET_SUP(lks, 10000baseSR_Full); 789 break; 790 case XGBE_SFP_BASE_10000_LR: 791 XGBE_SET_SUP(lks, 10000baseLR_Full); 792 break; 793 case XGBE_SFP_BASE_10000_LRM: 794 XGBE_SET_SUP(lks, 10000baseLRM_Full); 795 break; 796 case XGBE_SFP_BASE_10000_ER: 797 XGBE_SET_SUP(lks, 10000baseER_Full); 798 break; 799 case XGBE_SFP_BASE_10000_CR: 800 XGBE_SET_SUP(lks, 10000baseCR_Full); 801 break; 802 default: 803 break; 804 } 805 } 806 break; 807 default: 808 pdata->phy.speed = SPEED_UNKNOWN; 809 pdata->phy.duplex = DUPLEX_UNKNOWN; 810 pdata->phy.autoneg = AUTONEG_DISABLE; 811 pdata->phy.pause_autoneg = AUTONEG_DISABLE; 812 break; 813 } 814 815 switch (phy_data->sfp_base) { 816 case XGBE_SFP_BASE_1000_T: 817 case XGBE_SFP_BASE_1000_CX: 818 case XGBE_SFP_BASE_10000_CR: 819 XGBE_SET_SUP(lks, TP); 820 break; 821 default: 822 XGBE_SET_SUP(lks, FIBRE); 823 break; 824 } 825 826 XGBE_LM_COPY(lks, advertising, lks, supported); 827 } 828 829 static bool xgbe_phy_sfp_bit_rate(struct xgbe_sfp_eeprom *sfp_eeprom, 830 enum xgbe_sfp_speed sfp_speed) 831 { 832 u8 *sfp_base, min, max; 833 834 sfp_base = sfp_eeprom->base; 835 836 switch (sfp_speed) { 837 case XGBE_SFP_SPEED_1000: 838 min = XGBE_SFP_BASE_BR_1GBE_MIN; 839 max = XGBE_SFP_BASE_BR_1GBE_MAX; 840 break; 841 case XGBE_SFP_SPEED_10000: 842 min = XGBE_SFP_BASE_BR_10GBE_MIN; 843 max = XGBE_SFP_BASE_BR_10GBE_MAX; 844 break; 845 default: 846 return false; 847 } 848 849 return ((sfp_base[XGBE_SFP_BASE_BR] >= min) && 850 (sfp_base[XGBE_SFP_BASE_BR] <= max)); 851 } 852 853 static void xgbe_phy_free_phy_device(struct xgbe_prv_data *pdata) 854 { 855 struct xgbe_phy_data *phy_data = pdata->phy_data; 856 857 if (phy_data->phydev) { 858 phy_detach(phy_data->phydev); 859 phy_device_remove(phy_data->phydev); 860 phy_device_free(phy_data->phydev); 861 phy_data->phydev = NULL; 862 } 863 } 864 865 static bool xgbe_phy_finisar_phy_quirks(struct xgbe_prv_data *pdata) 866 { 867 struct xgbe_phy_data *phy_data = pdata->phy_data; 868 unsigned int phy_id = phy_data->phydev->phy_id; 869 870 if ((phy_id & 0xfffffff0) != 0x01ff0cc0) 871 return false; 872 873 /* Enable Base-T AN */ 874 phy_write(phy_data->phydev, 0x16, 0x0001); 875 phy_write(phy_data->phydev, 0x00, 0x9140); 876 phy_write(phy_data->phydev, 0x16, 0x0000); 877 878 /* Enable SGMII at 100Base-T/1000Base-T Full Duplex */ 879 phy_write(phy_data->phydev, 0x1b, 0x9084); 880 phy_write(phy_data->phydev, 0x09, 0x0e00); 881 phy_write(phy_data->phydev, 0x00, 0x8140); 882 phy_write(phy_data->phydev, 0x04, 0x0d01); 883 phy_write(phy_data->phydev, 0x00, 0x9140); 884 885 phy_data->phydev->supported = PHY_GBIT_FEATURES; 886 phy_data->phydev->supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 887 phy_data->phydev->advertising = phy_data->phydev->supported; 888 889 netif_dbg(pdata, drv, pdata->netdev, 890 "Finisar PHY quirk in place\n"); 891 892 return true; 893 } 894 895 static void xgbe_phy_external_phy_quirks(struct xgbe_prv_data *pdata) 896 { 897 if (xgbe_phy_finisar_phy_quirks(pdata)) 898 return; 899 } 900 901 static int xgbe_phy_find_phy_device(struct xgbe_prv_data *pdata) 902 { 903 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 904 struct xgbe_phy_data *phy_data = pdata->phy_data; 905 struct phy_device *phydev; 906 u32 advertising; 907 int ret; 908 909 /* If we already have a PHY, just return */ 910 if (phy_data->phydev) 911 return 0; 912 913 /* Check for the use of an external PHY */ 914 if (phy_data->phydev_mode == XGBE_MDIO_MODE_NONE) 915 return 0; 916 917 /* For SFP, only use an external PHY if available */ 918 if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) && 919 !phy_data->sfp_phy_avail) 920 return 0; 921 922 /* Set the proper MDIO mode for the PHY */ 923 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr, 924 phy_data->phydev_mode); 925 if (ret) { 926 netdev_err(pdata->netdev, 927 "mdio port/clause not compatible (%u/%u)\n", 928 phy_data->mdio_addr, phy_data->phydev_mode); 929 return ret; 930 } 931 932 /* Create and connect to the PHY device */ 933 phydev = get_phy_device(phy_data->mii, phy_data->mdio_addr, 934 (phy_data->phydev_mode == XGBE_MDIO_MODE_CL45)); 935 if (IS_ERR(phydev)) { 936 netdev_err(pdata->netdev, "get_phy_device failed\n"); 937 return -ENODEV; 938 } 939 netif_dbg(pdata, drv, pdata->netdev, "external PHY id is %#010x\n", 940 phydev->phy_id); 941 942 /*TODO: If c45, add request_module based on one of the MMD ids? */ 943 944 ret = phy_device_register(phydev); 945 if (ret) { 946 netdev_err(pdata->netdev, "phy_device_register failed\n"); 947 phy_device_free(phydev); 948 return ret; 949 } 950 951 ret = phy_attach_direct(pdata->netdev, phydev, phydev->dev_flags, 952 PHY_INTERFACE_MODE_SGMII); 953 if (ret) { 954 netdev_err(pdata->netdev, "phy_attach_direct failed\n"); 955 phy_device_remove(phydev); 956 phy_device_free(phydev); 957 return ret; 958 } 959 phy_data->phydev = phydev; 960 961 xgbe_phy_external_phy_quirks(pdata); 962 963 ethtool_convert_link_mode_to_legacy_u32(&advertising, 964 lks->link_modes.advertising); 965 phydev->advertising &= advertising; 966 967 phy_start_aneg(phy_data->phydev); 968 969 return 0; 970 } 971 972 static void xgbe_phy_sfp_external_phy(struct xgbe_prv_data *pdata) 973 { 974 struct xgbe_phy_data *phy_data = pdata->phy_data; 975 int ret; 976 977 if (!phy_data->sfp_changed) 978 return; 979 980 phy_data->sfp_phy_avail = 0; 981 982 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T) 983 return; 984 985 /* Check access to the PHY by reading CTRL1 */ 986 ret = xgbe_phy_i2c_mii_read(pdata, MII_BMCR); 987 if (ret < 0) 988 return; 989 990 /* Successfully accessed the PHY */ 991 phy_data->sfp_phy_avail = 1; 992 } 993 994 static bool xgbe_phy_check_sfp_rx_los(struct xgbe_phy_data *phy_data) 995 { 996 u8 *sfp_extd = phy_data->sfp_eeprom.extd; 997 998 if (!(sfp_extd[XGBE_SFP_EXTD_OPT1] & XGBE_SFP_EXTD_OPT1_RX_LOS)) 999 return false; 1000 1001 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_RX_LOS) 1002 return false; 1003 1004 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_rx_los)) 1005 return true; 1006 1007 return false; 1008 } 1009 1010 static bool xgbe_phy_check_sfp_tx_fault(struct xgbe_phy_data *phy_data) 1011 { 1012 u8 *sfp_extd = phy_data->sfp_eeprom.extd; 1013 1014 if (!(sfp_extd[XGBE_SFP_EXTD_OPT1] & XGBE_SFP_EXTD_OPT1_TX_FAULT)) 1015 return false; 1016 1017 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_TX_FAULT) 1018 return false; 1019 1020 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_tx_fault)) 1021 return true; 1022 1023 return false; 1024 } 1025 1026 static bool xgbe_phy_check_sfp_mod_absent(struct xgbe_phy_data *phy_data) 1027 { 1028 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_MOD_ABSENT) 1029 return false; 1030 1031 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_mod_absent)) 1032 return true; 1033 1034 return false; 1035 } 1036 1037 static bool xgbe_phy_belfuse_parse_quirks(struct xgbe_prv_data *pdata) 1038 { 1039 struct xgbe_phy_data *phy_data = pdata->phy_data; 1040 struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom; 1041 1042 if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME], 1043 XGBE_BEL_FUSE_VENDOR, XGBE_SFP_BASE_VENDOR_NAME_LEN)) 1044 return false; 1045 1046 if (!memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN], 1047 XGBE_BEL_FUSE_PARTNO, XGBE_SFP_BASE_VENDOR_PN_LEN)) { 1048 phy_data->sfp_base = XGBE_SFP_BASE_1000_SX; 1049 phy_data->sfp_cable = XGBE_SFP_CABLE_ACTIVE; 1050 phy_data->sfp_speed = XGBE_SFP_SPEED_1000; 1051 if (phy_data->sfp_changed) 1052 netif_dbg(pdata, drv, pdata->netdev, 1053 "Bel-Fuse SFP quirk in place\n"); 1054 return true; 1055 } 1056 1057 return false; 1058 } 1059 1060 static bool xgbe_phy_sfp_parse_quirks(struct xgbe_prv_data *pdata) 1061 { 1062 if (xgbe_phy_belfuse_parse_quirks(pdata)) 1063 return true; 1064 1065 return false; 1066 } 1067 1068 static void xgbe_phy_sfp_parse_eeprom(struct xgbe_prv_data *pdata) 1069 { 1070 struct xgbe_phy_data *phy_data = pdata->phy_data; 1071 struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom; 1072 u8 *sfp_base; 1073 1074 sfp_base = sfp_eeprom->base; 1075 1076 if (sfp_base[XGBE_SFP_BASE_ID] != XGBE_SFP_ID_SFP) 1077 return; 1078 1079 if (sfp_base[XGBE_SFP_BASE_EXT_ID] != XGBE_SFP_EXT_ID_SFP) 1080 return; 1081 1082 /* Update transceiver signals (eeprom extd/options) */ 1083 phy_data->sfp_tx_fault = xgbe_phy_check_sfp_tx_fault(phy_data); 1084 phy_data->sfp_rx_los = xgbe_phy_check_sfp_rx_los(phy_data); 1085 1086 if (xgbe_phy_sfp_parse_quirks(pdata)) 1087 return; 1088 1089 /* Assume ACTIVE cable unless told it is PASSIVE */ 1090 if (sfp_base[XGBE_SFP_BASE_CABLE] & XGBE_SFP_BASE_CABLE_PASSIVE) { 1091 phy_data->sfp_cable = XGBE_SFP_CABLE_PASSIVE; 1092 phy_data->sfp_cable_len = sfp_base[XGBE_SFP_BASE_CU_CABLE_LEN]; 1093 } else { 1094 phy_data->sfp_cable = XGBE_SFP_CABLE_ACTIVE; 1095 } 1096 1097 /* Determine the type of SFP */ 1098 if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_SR) 1099 phy_data->sfp_base = XGBE_SFP_BASE_10000_SR; 1100 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LR) 1101 phy_data->sfp_base = XGBE_SFP_BASE_10000_LR; 1102 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LRM) 1103 phy_data->sfp_base = XGBE_SFP_BASE_10000_LRM; 1104 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_ER) 1105 phy_data->sfp_base = XGBE_SFP_BASE_10000_ER; 1106 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_SX) 1107 phy_data->sfp_base = XGBE_SFP_BASE_1000_SX; 1108 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_LX) 1109 phy_data->sfp_base = XGBE_SFP_BASE_1000_LX; 1110 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_CX) 1111 phy_data->sfp_base = XGBE_SFP_BASE_1000_CX; 1112 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_T) 1113 phy_data->sfp_base = XGBE_SFP_BASE_1000_T; 1114 else if ((phy_data->sfp_cable == XGBE_SFP_CABLE_PASSIVE) && 1115 xgbe_phy_sfp_bit_rate(sfp_eeprom, XGBE_SFP_SPEED_10000)) 1116 phy_data->sfp_base = XGBE_SFP_BASE_10000_CR; 1117 1118 switch (phy_data->sfp_base) { 1119 case XGBE_SFP_BASE_1000_T: 1120 phy_data->sfp_speed = XGBE_SFP_SPEED_100_1000; 1121 break; 1122 case XGBE_SFP_BASE_1000_SX: 1123 case XGBE_SFP_BASE_1000_LX: 1124 case XGBE_SFP_BASE_1000_CX: 1125 phy_data->sfp_speed = XGBE_SFP_SPEED_1000; 1126 break; 1127 case XGBE_SFP_BASE_10000_SR: 1128 case XGBE_SFP_BASE_10000_LR: 1129 case XGBE_SFP_BASE_10000_LRM: 1130 case XGBE_SFP_BASE_10000_ER: 1131 case XGBE_SFP_BASE_10000_CR: 1132 phy_data->sfp_speed = XGBE_SFP_SPEED_10000; 1133 break; 1134 default: 1135 break; 1136 } 1137 } 1138 1139 static void xgbe_phy_sfp_eeprom_info(struct xgbe_prv_data *pdata, 1140 struct xgbe_sfp_eeprom *sfp_eeprom) 1141 { 1142 struct xgbe_sfp_ascii sfp_ascii; 1143 char *sfp_data = (char *)&sfp_ascii; 1144 1145 netif_dbg(pdata, drv, pdata->netdev, "SFP detected:\n"); 1146 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME], 1147 XGBE_SFP_BASE_VENDOR_NAME_LEN); 1148 sfp_data[XGBE_SFP_BASE_VENDOR_NAME_LEN] = '\0'; 1149 netif_dbg(pdata, drv, pdata->netdev, " vendor: %s\n", 1150 sfp_data); 1151 1152 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN], 1153 XGBE_SFP_BASE_VENDOR_PN_LEN); 1154 sfp_data[XGBE_SFP_BASE_VENDOR_PN_LEN] = '\0'; 1155 netif_dbg(pdata, drv, pdata->netdev, " part number: %s\n", 1156 sfp_data); 1157 1158 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_REV], 1159 XGBE_SFP_BASE_VENDOR_REV_LEN); 1160 sfp_data[XGBE_SFP_BASE_VENDOR_REV_LEN] = '\0'; 1161 netif_dbg(pdata, drv, pdata->netdev, " revision level: %s\n", 1162 sfp_data); 1163 1164 memcpy(sfp_data, &sfp_eeprom->extd[XGBE_SFP_BASE_VENDOR_SN], 1165 XGBE_SFP_BASE_VENDOR_SN_LEN); 1166 sfp_data[XGBE_SFP_BASE_VENDOR_SN_LEN] = '\0'; 1167 netif_dbg(pdata, drv, pdata->netdev, " serial number: %s\n", 1168 sfp_data); 1169 } 1170 1171 static bool xgbe_phy_sfp_verify_eeprom(u8 cc_in, u8 *buf, unsigned int len) 1172 { 1173 u8 cc; 1174 1175 for (cc = 0; len; buf++, len--) 1176 cc += *buf; 1177 1178 return (cc == cc_in) ? true : false; 1179 } 1180 1181 static int xgbe_phy_sfp_read_eeprom(struct xgbe_prv_data *pdata) 1182 { 1183 struct xgbe_phy_data *phy_data = pdata->phy_data; 1184 struct xgbe_sfp_eeprom sfp_eeprom; 1185 u8 eeprom_addr; 1186 int ret; 1187 1188 ret = xgbe_phy_sfp_get_mux(pdata); 1189 if (ret) { 1190 dev_err_once(pdata->dev, "%s: I2C error setting SFP MUX\n", 1191 netdev_name(pdata->netdev)); 1192 return ret; 1193 } 1194 1195 /* Read the SFP serial ID eeprom */ 1196 eeprom_addr = 0; 1197 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_SERIAL_ID_ADDRESS, 1198 &eeprom_addr, sizeof(eeprom_addr), 1199 &sfp_eeprom, sizeof(sfp_eeprom)); 1200 if (ret) { 1201 dev_err_once(pdata->dev, "%s: I2C error reading SFP EEPROM\n", 1202 netdev_name(pdata->netdev)); 1203 goto put; 1204 } 1205 1206 /* Validate the contents read */ 1207 if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.base[XGBE_SFP_BASE_CC], 1208 sfp_eeprom.base, 1209 sizeof(sfp_eeprom.base) - 1)) { 1210 ret = -EINVAL; 1211 goto put; 1212 } 1213 1214 if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.extd[XGBE_SFP_EXTD_CC], 1215 sfp_eeprom.extd, 1216 sizeof(sfp_eeprom.extd) - 1)) { 1217 ret = -EINVAL; 1218 goto put; 1219 } 1220 1221 /* Check for an added or changed SFP */ 1222 if (memcmp(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom))) { 1223 phy_data->sfp_changed = 1; 1224 1225 if (netif_msg_drv(pdata)) 1226 xgbe_phy_sfp_eeprom_info(pdata, &sfp_eeprom); 1227 1228 memcpy(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom)); 1229 1230 if (sfp_eeprom.extd[XGBE_SFP_EXTD_SFF_8472]) { 1231 u8 diag_type = sfp_eeprom.extd[XGBE_SFP_EXTD_DIAG]; 1232 1233 if (!(diag_type & XGBE_SFP_EXTD_DIAG_ADDR_CHANGE)) 1234 phy_data->sfp_diags = 1; 1235 } 1236 1237 xgbe_phy_free_phy_device(pdata); 1238 } else { 1239 phy_data->sfp_changed = 0; 1240 } 1241 1242 put: 1243 xgbe_phy_sfp_put_mux(pdata); 1244 1245 return ret; 1246 } 1247 1248 static void xgbe_phy_sfp_signals(struct xgbe_prv_data *pdata) 1249 { 1250 struct xgbe_phy_data *phy_data = pdata->phy_data; 1251 u8 gpio_reg, gpio_ports[2]; 1252 int ret; 1253 1254 /* Read the input port registers */ 1255 gpio_reg = 0; 1256 ret = xgbe_phy_i2c_read(pdata, phy_data->sfp_gpio_address, 1257 &gpio_reg, sizeof(gpio_reg), 1258 gpio_ports, sizeof(gpio_ports)); 1259 if (ret) { 1260 dev_err_once(pdata->dev, "%s: I2C error reading SFP GPIOs\n", 1261 netdev_name(pdata->netdev)); 1262 return; 1263 } 1264 1265 phy_data->sfp_gpio_inputs = (gpio_ports[1] << 8) | gpio_ports[0]; 1266 1267 phy_data->sfp_mod_absent = xgbe_phy_check_sfp_mod_absent(phy_data); 1268 } 1269 1270 static void xgbe_phy_sfp_mod_absent(struct xgbe_prv_data *pdata) 1271 { 1272 struct xgbe_phy_data *phy_data = pdata->phy_data; 1273 1274 xgbe_phy_free_phy_device(pdata); 1275 1276 phy_data->sfp_mod_absent = 1; 1277 phy_data->sfp_phy_avail = 0; 1278 memset(&phy_data->sfp_eeprom, 0, sizeof(phy_data->sfp_eeprom)); 1279 } 1280 1281 static void xgbe_phy_sfp_reset(struct xgbe_phy_data *phy_data) 1282 { 1283 phy_data->sfp_rx_los = 0; 1284 phy_data->sfp_tx_fault = 0; 1285 phy_data->sfp_mod_absent = 1; 1286 phy_data->sfp_diags = 0; 1287 phy_data->sfp_base = XGBE_SFP_BASE_UNKNOWN; 1288 phy_data->sfp_cable = XGBE_SFP_CABLE_UNKNOWN; 1289 phy_data->sfp_speed = XGBE_SFP_SPEED_UNKNOWN; 1290 } 1291 1292 static void xgbe_phy_sfp_detect(struct xgbe_prv_data *pdata) 1293 { 1294 struct xgbe_phy_data *phy_data = pdata->phy_data; 1295 int ret; 1296 1297 /* Reset the SFP signals and info */ 1298 xgbe_phy_sfp_reset(phy_data); 1299 1300 ret = xgbe_phy_get_comm_ownership(pdata); 1301 if (ret) 1302 return; 1303 1304 /* Read the SFP signals and check for module presence */ 1305 xgbe_phy_sfp_signals(pdata); 1306 if (phy_data->sfp_mod_absent) { 1307 xgbe_phy_sfp_mod_absent(pdata); 1308 goto put; 1309 } 1310 1311 ret = xgbe_phy_sfp_read_eeprom(pdata); 1312 if (ret) { 1313 /* Treat any error as if there isn't an SFP plugged in */ 1314 xgbe_phy_sfp_reset(phy_data); 1315 xgbe_phy_sfp_mod_absent(pdata); 1316 goto put; 1317 } 1318 1319 xgbe_phy_sfp_parse_eeprom(pdata); 1320 1321 xgbe_phy_sfp_external_phy(pdata); 1322 1323 put: 1324 xgbe_phy_sfp_phy_settings(pdata); 1325 1326 xgbe_phy_put_comm_ownership(pdata); 1327 } 1328 1329 static void xgbe_phy_phydev_flowctrl(struct xgbe_prv_data *pdata) 1330 { 1331 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 1332 struct xgbe_phy_data *phy_data = pdata->phy_data; 1333 u16 lcl_adv = 0, rmt_adv = 0; 1334 u8 fc; 1335 1336 pdata->phy.tx_pause = 0; 1337 pdata->phy.rx_pause = 0; 1338 1339 if (!phy_data->phydev) 1340 return; 1341 1342 if (phy_data->phydev->advertising & ADVERTISED_Pause) 1343 lcl_adv |= ADVERTISE_PAUSE_CAP; 1344 if (phy_data->phydev->advertising & ADVERTISED_Asym_Pause) 1345 lcl_adv |= ADVERTISE_PAUSE_ASYM; 1346 1347 if (phy_data->phydev->pause) { 1348 XGBE_SET_LP_ADV(lks, Pause); 1349 rmt_adv |= LPA_PAUSE_CAP; 1350 } 1351 if (phy_data->phydev->asym_pause) { 1352 XGBE_SET_LP_ADV(lks, Asym_Pause); 1353 rmt_adv |= LPA_PAUSE_ASYM; 1354 } 1355 1356 fc = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv); 1357 if (fc & FLOW_CTRL_TX) 1358 pdata->phy.tx_pause = 1; 1359 if (fc & FLOW_CTRL_RX) 1360 pdata->phy.rx_pause = 1; 1361 } 1362 1363 static enum xgbe_mode xgbe_phy_an37_sgmii_outcome(struct xgbe_prv_data *pdata) 1364 { 1365 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 1366 enum xgbe_mode mode; 1367 1368 XGBE_SET_LP_ADV(lks, Autoneg); 1369 XGBE_SET_LP_ADV(lks, TP); 1370 1371 /* Use external PHY to determine flow control */ 1372 if (pdata->phy.pause_autoneg) 1373 xgbe_phy_phydev_flowctrl(pdata); 1374 1375 switch (pdata->an_status & XGBE_SGMII_AN_LINK_SPEED) { 1376 case XGBE_SGMII_AN_LINK_SPEED_100: 1377 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) { 1378 XGBE_SET_LP_ADV(lks, 100baseT_Full); 1379 mode = XGBE_MODE_SGMII_100; 1380 } else { 1381 /* Half-duplex not supported */ 1382 XGBE_SET_LP_ADV(lks, 100baseT_Half); 1383 mode = XGBE_MODE_UNKNOWN; 1384 } 1385 break; 1386 case XGBE_SGMII_AN_LINK_SPEED_1000: 1387 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) { 1388 XGBE_SET_LP_ADV(lks, 1000baseT_Full); 1389 mode = XGBE_MODE_SGMII_1000; 1390 } else { 1391 /* Half-duplex not supported */ 1392 XGBE_SET_LP_ADV(lks, 1000baseT_Half); 1393 mode = XGBE_MODE_UNKNOWN; 1394 } 1395 break; 1396 default: 1397 mode = XGBE_MODE_UNKNOWN; 1398 } 1399 1400 return mode; 1401 } 1402 1403 static enum xgbe_mode xgbe_phy_an37_outcome(struct xgbe_prv_data *pdata) 1404 { 1405 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 1406 enum xgbe_mode mode; 1407 unsigned int ad_reg, lp_reg; 1408 1409 XGBE_SET_LP_ADV(lks, Autoneg); 1410 XGBE_SET_LP_ADV(lks, FIBRE); 1411 1412 /* Compare Advertisement and Link Partner register */ 1413 ad_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE); 1414 lp_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_LP_ABILITY); 1415 if (lp_reg & 0x100) 1416 XGBE_SET_LP_ADV(lks, Pause); 1417 if (lp_reg & 0x80) 1418 XGBE_SET_LP_ADV(lks, Asym_Pause); 1419 1420 if (pdata->phy.pause_autoneg) { 1421 /* Set flow control based on auto-negotiation result */ 1422 pdata->phy.tx_pause = 0; 1423 pdata->phy.rx_pause = 0; 1424 1425 if (ad_reg & lp_reg & 0x100) { 1426 pdata->phy.tx_pause = 1; 1427 pdata->phy.rx_pause = 1; 1428 } else if (ad_reg & lp_reg & 0x80) { 1429 if (ad_reg & 0x100) 1430 pdata->phy.rx_pause = 1; 1431 else if (lp_reg & 0x100) 1432 pdata->phy.tx_pause = 1; 1433 } 1434 } 1435 1436 if (lp_reg & 0x20) 1437 XGBE_SET_LP_ADV(lks, 1000baseX_Full); 1438 1439 /* Half duplex is not supported */ 1440 ad_reg &= lp_reg; 1441 mode = (ad_reg & 0x20) ? XGBE_MODE_X : XGBE_MODE_UNKNOWN; 1442 1443 return mode; 1444 } 1445 1446 static enum xgbe_mode xgbe_phy_an73_redrv_outcome(struct xgbe_prv_data *pdata) 1447 { 1448 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 1449 struct xgbe_phy_data *phy_data = pdata->phy_data; 1450 enum xgbe_mode mode; 1451 unsigned int ad_reg, lp_reg; 1452 1453 XGBE_SET_LP_ADV(lks, Autoneg); 1454 XGBE_SET_LP_ADV(lks, Backplane); 1455 1456 /* Use external PHY to determine flow control */ 1457 if (pdata->phy.pause_autoneg) 1458 xgbe_phy_phydev_flowctrl(pdata); 1459 1460 /* Compare Advertisement and Link Partner register 2 */ 1461 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); 1462 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); 1463 if (lp_reg & 0x80) 1464 XGBE_SET_LP_ADV(lks, 10000baseKR_Full); 1465 if (lp_reg & 0x20) 1466 XGBE_SET_LP_ADV(lks, 1000baseKX_Full); 1467 1468 ad_reg &= lp_reg; 1469 if (ad_reg & 0x80) { 1470 switch (phy_data->port_mode) { 1471 case XGBE_PORT_MODE_BACKPLANE: 1472 mode = XGBE_MODE_KR; 1473 break; 1474 default: 1475 mode = XGBE_MODE_SFI; 1476 break; 1477 } 1478 } else if (ad_reg & 0x20) { 1479 switch (phy_data->port_mode) { 1480 case XGBE_PORT_MODE_BACKPLANE: 1481 mode = XGBE_MODE_KX_1000; 1482 break; 1483 case XGBE_PORT_MODE_1000BASE_X: 1484 mode = XGBE_MODE_X; 1485 break; 1486 case XGBE_PORT_MODE_SFP: 1487 switch (phy_data->sfp_base) { 1488 case XGBE_SFP_BASE_1000_T: 1489 if (phy_data->phydev && 1490 (phy_data->phydev->speed == SPEED_100)) 1491 mode = XGBE_MODE_SGMII_100; 1492 else 1493 mode = XGBE_MODE_SGMII_1000; 1494 break; 1495 case XGBE_SFP_BASE_1000_SX: 1496 case XGBE_SFP_BASE_1000_LX: 1497 case XGBE_SFP_BASE_1000_CX: 1498 default: 1499 mode = XGBE_MODE_X; 1500 break; 1501 } 1502 break; 1503 default: 1504 if (phy_data->phydev && 1505 (phy_data->phydev->speed == SPEED_100)) 1506 mode = XGBE_MODE_SGMII_100; 1507 else 1508 mode = XGBE_MODE_SGMII_1000; 1509 break; 1510 } 1511 } else { 1512 mode = XGBE_MODE_UNKNOWN; 1513 } 1514 1515 /* Compare Advertisement and Link Partner register 3 */ 1516 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); 1517 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); 1518 if (lp_reg & 0xc000) 1519 XGBE_SET_LP_ADV(lks, 10000baseR_FEC); 1520 1521 return mode; 1522 } 1523 1524 static enum xgbe_mode xgbe_phy_an73_outcome(struct xgbe_prv_data *pdata) 1525 { 1526 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 1527 enum xgbe_mode mode; 1528 unsigned int ad_reg, lp_reg; 1529 1530 XGBE_SET_LP_ADV(lks, Autoneg); 1531 XGBE_SET_LP_ADV(lks, Backplane); 1532 1533 /* Compare Advertisement and Link Partner register 1 */ 1534 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE); 1535 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA); 1536 if (lp_reg & 0x400) 1537 XGBE_SET_LP_ADV(lks, Pause); 1538 if (lp_reg & 0x800) 1539 XGBE_SET_LP_ADV(lks, Asym_Pause); 1540 1541 if (pdata->phy.pause_autoneg) { 1542 /* Set flow control based on auto-negotiation result */ 1543 pdata->phy.tx_pause = 0; 1544 pdata->phy.rx_pause = 0; 1545 1546 if (ad_reg & lp_reg & 0x400) { 1547 pdata->phy.tx_pause = 1; 1548 pdata->phy.rx_pause = 1; 1549 } else if (ad_reg & lp_reg & 0x800) { 1550 if (ad_reg & 0x400) 1551 pdata->phy.rx_pause = 1; 1552 else if (lp_reg & 0x400) 1553 pdata->phy.tx_pause = 1; 1554 } 1555 } 1556 1557 /* Compare Advertisement and Link Partner register 2 */ 1558 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); 1559 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); 1560 if (lp_reg & 0x80) 1561 XGBE_SET_LP_ADV(lks, 10000baseKR_Full); 1562 if (lp_reg & 0x20) 1563 XGBE_SET_LP_ADV(lks, 1000baseKX_Full); 1564 1565 ad_reg &= lp_reg; 1566 if (ad_reg & 0x80) 1567 mode = XGBE_MODE_KR; 1568 else if (ad_reg & 0x20) 1569 mode = XGBE_MODE_KX_1000; 1570 else 1571 mode = XGBE_MODE_UNKNOWN; 1572 1573 /* Compare Advertisement and Link Partner register 3 */ 1574 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); 1575 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); 1576 if (lp_reg & 0xc000) 1577 XGBE_SET_LP_ADV(lks, 10000baseR_FEC); 1578 1579 return mode; 1580 } 1581 1582 static enum xgbe_mode xgbe_phy_an_outcome(struct xgbe_prv_data *pdata) 1583 { 1584 switch (pdata->an_mode) { 1585 case XGBE_AN_MODE_CL73: 1586 return xgbe_phy_an73_outcome(pdata); 1587 case XGBE_AN_MODE_CL73_REDRV: 1588 return xgbe_phy_an73_redrv_outcome(pdata); 1589 case XGBE_AN_MODE_CL37: 1590 return xgbe_phy_an37_outcome(pdata); 1591 case XGBE_AN_MODE_CL37_SGMII: 1592 return xgbe_phy_an37_sgmii_outcome(pdata); 1593 default: 1594 return XGBE_MODE_UNKNOWN; 1595 } 1596 } 1597 1598 static void xgbe_phy_an_advertising(struct xgbe_prv_data *pdata, 1599 struct ethtool_link_ksettings *dlks) 1600 { 1601 struct ethtool_link_ksettings *slks = &pdata->phy.lks; 1602 struct xgbe_phy_data *phy_data = pdata->phy_data; 1603 1604 XGBE_LM_COPY(dlks, advertising, slks, advertising); 1605 1606 /* Without a re-driver, just return current advertising */ 1607 if (!phy_data->redrv) 1608 return; 1609 1610 /* With the KR re-driver we need to advertise a single speed */ 1611 XGBE_CLR_ADV(dlks, 1000baseKX_Full); 1612 XGBE_CLR_ADV(dlks, 10000baseKR_Full); 1613 1614 switch (phy_data->port_mode) { 1615 case XGBE_PORT_MODE_BACKPLANE: 1616 XGBE_SET_ADV(dlks, 10000baseKR_Full); 1617 break; 1618 case XGBE_PORT_MODE_BACKPLANE_2500: 1619 XGBE_SET_ADV(dlks, 1000baseKX_Full); 1620 break; 1621 case XGBE_PORT_MODE_1000BASE_T: 1622 case XGBE_PORT_MODE_1000BASE_X: 1623 case XGBE_PORT_MODE_NBASE_T: 1624 XGBE_SET_ADV(dlks, 1000baseKX_Full); 1625 break; 1626 case XGBE_PORT_MODE_10GBASE_T: 1627 if (phy_data->phydev && 1628 (phy_data->phydev->speed == SPEED_10000)) 1629 XGBE_SET_ADV(dlks, 10000baseKR_Full); 1630 else 1631 XGBE_SET_ADV(dlks, 1000baseKX_Full); 1632 break; 1633 case XGBE_PORT_MODE_10GBASE_R: 1634 XGBE_SET_ADV(dlks, 10000baseKR_Full); 1635 break; 1636 case XGBE_PORT_MODE_SFP: 1637 switch (phy_data->sfp_base) { 1638 case XGBE_SFP_BASE_1000_T: 1639 case XGBE_SFP_BASE_1000_SX: 1640 case XGBE_SFP_BASE_1000_LX: 1641 case XGBE_SFP_BASE_1000_CX: 1642 XGBE_SET_ADV(dlks, 1000baseKX_Full); 1643 break; 1644 default: 1645 XGBE_SET_ADV(dlks, 10000baseKR_Full); 1646 break; 1647 } 1648 break; 1649 default: 1650 XGBE_SET_ADV(dlks, 10000baseKR_Full); 1651 break; 1652 } 1653 } 1654 1655 static int xgbe_phy_an_config(struct xgbe_prv_data *pdata) 1656 { 1657 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 1658 struct xgbe_phy_data *phy_data = pdata->phy_data; 1659 u32 advertising; 1660 int ret; 1661 1662 ret = xgbe_phy_find_phy_device(pdata); 1663 if (ret) 1664 return ret; 1665 1666 if (!phy_data->phydev) 1667 return 0; 1668 1669 ethtool_convert_link_mode_to_legacy_u32(&advertising, 1670 lks->link_modes.advertising); 1671 1672 phy_data->phydev->autoneg = pdata->phy.autoneg; 1673 phy_data->phydev->advertising = phy_data->phydev->supported & 1674 advertising; 1675 1676 if (pdata->phy.autoneg != AUTONEG_ENABLE) { 1677 phy_data->phydev->speed = pdata->phy.speed; 1678 phy_data->phydev->duplex = pdata->phy.duplex; 1679 } 1680 1681 ret = phy_start_aneg(phy_data->phydev); 1682 1683 return ret; 1684 } 1685 1686 static enum xgbe_an_mode xgbe_phy_an_sfp_mode(struct xgbe_phy_data *phy_data) 1687 { 1688 switch (phy_data->sfp_base) { 1689 case XGBE_SFP_BASE_1000_T: 1690 return XGBE_AN_MODE_CL37_SGMII; 1691 case XGBE_SFP_BASE_1000_SX: 1692 case XGBE_SFP_BASE_1000_LX: 1693 case XGBE_SFP_BASE_1000_CX: 1694 return XGBE_AN_MODE_CL37; 1695 default: 1696 return XGBE_AN_MODE_NONE; 1697 } 1698 } 1699 1700 static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata) 1701 { 1702 struct xgbe_phy_data *phy_data = pdata->phy_data; 1703 1704 /* A KR re-driver will always require CL73 AN */ 1705 if (phy_data->redrv) 1706 return XGBE_AN_MODE_CL73_REDRV; 1707 1708 switch (phy_data->port_mode) { 1709 case XGBE_PORT_MODE_BACKPLANE: 1710 return XGBE_AN_MODE_CL73; 1711 case XGBE_PORT_MODE_BACKPLANE_2500: 1712 return XGBE_AN_MODE_NONE; 1713 case XGBE_PORT_MODE_1000BASE_T: 1714 return XGBE_AN_MODE_CL37_SGMII; 1715 case XGBE_PORT_MODE_1000BASE_X: 1716 return XGBE_AN_MODE_CL37; 1717 case XGBE_PORT_MODE_NBASE_T: 1718 return XGBE_AN_MODE_CL37_SGMII; 1719 case XGBE_PORT_MODE_10GBASE_T: 1720 return XGBE_AN_MODE_CL73; 1721 case XGBE_PORT_MODE_10GBASE_R: 1722 return XGBE_AN_MODE_NONE; 1723 case XGBE_PORT_MODE_SFP: 1724 return xgbe_phy_an_sfp_mode(phy_data); 1725 default: 1726 return XGBE_AN_MODE_NONE; 1727 } 1728 } 1729 1730 static int xgbe_phy_set_redrv_mode_mdio(struct xgbe_prv_data *pdata, 1731 enum xgbe_phy_redrv_mode mode) 1732 { 1733 struct xgbe_phy_data *phy_data = pdata->phy_data; 1734 u16 redrv_reg, redrv_val; 1735 1736 redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000); 1737 redrv_val = (u16)mode; 1738 1739 return pdata->hw_if.write_ext_mii_regs(pdata, phy_data->redrv_addr, 1740 redrv_reg, redrv_val); 1741 } 1742 1743 static int xgbe_phy_set_redrv_mode_i2c(struct xgbe_prv_data *pdata, 1744 enum xgbe_phy_redrv_mode mode) 1745 { 1746 struct xgbe_phy_data *phy_data = pdata->phy_data; 1747 unsigned int redrv_reg; 1748 int ret; 1749 1750 /* Calculate the register to write */ 1751 redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000); 1752 1753 ret = xgbe_phy_redrv_write(pdata, redrv_reg, mode); 1754 1755 return ret; 1756 } 1757 1758 static void xgbe_phy_set_redrv_mode(struct xgbe_prv_data *pdata) 1759 { 1760 struct xgbe_phy_data *phy_data = pdata->phy_data; 1761 enum xgbe_phy_redrv_mode mode; 1762 int ret; 1763 1764 if (!phy_data->redrv) 1765 return; 1766 1767 mode = XGBE_PHY_REDRV_MODE_CX; 1768 if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) && 1769 (phy_data->sfp_base != XGBE_SFP_BASE_1000_CX) && 1770 (phy_data->sfp_base != XGBE_SFP_BASE_10000_CR)) 1771 mode = XGBE_PHY_REDRV_MODE_SR; 1772 1773 ret = xgbe_phy_get_comm_ownership(pdata); 1774 if (ret) 1775 return; 1776 1777 if (phy_data->redrv_if) 1778 xgbe_phy_set_redrv_mode_i2c(pdata, mode); 1779 else 1780 xgbe_phy_set_redrv_mode_mdio(pdata, mode); 1781 1782 xgbe_phy_put_comm_ownership(pdata); 1783 } 1784 1785 static void xgbe_phy_perform_ratechange(struct xgbe_prv_data *pdata, 1786 unsigned int cmd, unsigned int sub_cmd) 1787 { 1788 unsigned int s0 = 0; 1789 unsigned int wait; 1790 1791 /* Log if a previous command did not complete */ 1792 if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) 1793 netif_dbg(pdata, link, pdata->netdev, 1794 "firmware mailbox not ready for command\n"); 1795 1796 /* Construct the command */ 1797 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, cmd); 1798 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, sub_cmd); 1799 1800 /* Issue the command */ 1801 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0); 1802 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0); 1803 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1); 1804 1805 /* Wait for command to complete */ 1806 wait = XGBE_RATECHANGE_COUNT; 1807 while (wait--) { 1808 if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) 1809 return; 1810 1811 usleep_range(1000, 2000); 1812 } 1813 1814 netif_dbg(pdata, link, pdata->netdev, 1815 "firmware mailbox command did not complete\n"); 1816 } 1817 1818 static void xgbe_phy_rrc(struct xgbe_prv_data *pdata) 1819 { 1820 /* Receiver Reset Cycle */ 1821 xgbe_phy_perform_ratechange(pdata, 5, 0); 1822 1823 netif_dbg(pdata, link, pdata->netdev, "receiver reset complete\n"); 1824 } 1825 1826 static void xgbe_phy_power_off(struct xgbe_prv_data *pdata) 1827 { 1828 struct xgbe_phy_data *phy_data = pdata->phy_data; 1829 1830 /* Power off */ 1831 xgbe_phy_perform_ratechange(pdata, 0, 0); 1832 1833 phy_data->cur_mode = XGBE_MODE_UNKNOWN; 1834 1835 netif_dbg(pdata, link, pdata->netdev, "phy powered off\n"); 1836 } 1837 1838 static void xgbe_phy_sfi_mode(struct xgbe_prv_data *pdata) 1839 { 1840 struct xgbe_phy_data *phy_data = pdata->phy_data; 1841 1842 xgbe_phy_set_redrv_mode(pdata); 1843 1844 /* 10G/SFI */ 1845 if (phy_data->sfp_cable != XGBE_SFP_CABLE_PASSIVE) { 1846 xgbe_phy_perform_ratechange(pdata, 3, 0); 1847 } else { 1848 if (phy_data->sfp_cable_len <= 1) 1849 xgbe_phy_perform_ratechange(pdata, 3, 1); 1850 else if (phy_data->sfp_cable_len <= 3) 1851 xgbe_phy_perform_ratechange(pdata, 3, 2); 1852 else 1853 xgbe_phy_perform_ratechange(pdata, 3, 3); 1854 } 1855 1856 phy_data->cur_mode = XGBE_MODE_SFI; 1857 1858 netif_dbg(pdata, link, pdata->netdev, "10GbE SFI mode set\n"); 1859 } 1860 1861 static void xgbe_phy_x_mode(struct xgbe_prv_data *pdata) 1862 { 1863 struct xgbe_phy_data *phy_data = pdata->phy_data; 1864 1865 xgbe_phy_set_redrv_mode(pdata); 1866 1867 /* 1G/X */ 1868 xgbe_phy_perform_ratechange(pdata, 1, 3); 1869 1870 phy_data->cur_mode = XGBE_MODE_X; 1871 1872 netif_dbg(pdata, link, pdata->netdev, "1GbE X mode set\n"); 1873 } 1874 1875 static void xgbe_phy_sgmii_1000_mode(struct xgbe_prv_data *pdata) 1876 { 1877 struct xgbe_phy_data *phy_data = pdata->phy_data; 1878 1879 xgbe_phy_set_redrv_mode(pdata); 1880 1881 /* 1G/SGMII */ 1882 xgbe_phy_perform_ratechange(pdata, 1, 2); 1883 1884 phy_data->cur_mode = XGBE_MODE_SGMII_1000; 1885 1886 netif_dbg(pdata, link, pdata->netdev, "1GbE SGMII mode set\n"); 1887 } 1888 1889 static void xgbe_phy_sgmii_100_mode(struct xgbe_prv_data *pdata) 1890 { 1891 struct xgbe_phy_data *phy_data = pdata->phy_data; 1892 1893 xgbe_phy_set_redrv_mode(pdata); 1894 1895 /* 100M/SGMII */ 1896 xgbe_phy_perform_ratechange(pdata, 1, 1); 1897 1898 phy_data->cur_mode = XGBE_MODE_SGMII_100; 1899 1900 netif_dbg(pdata, link, pdata->netdev, "100MbE SGMII mode set\n"); 1901 } 1902 1903 static void xgbe_phy_kr_mode(struct xgbe_prv_data *pdata) 1904 { 1905 struct xgbe_phy_data *phy_data = pdata->phy_data; 1906 1907 xgbe_phy_set_redrv_mode(pdata); 1908 1909 /* 10G/KR */ 1910 xgbe_phy_perform_ratechange(pdata, 4, 0); 1911 1912 phy_data->cur_mode = XGBE_MODE_KR; 1913 1914 netif_dbg(pdata, link, pdata->netdev, "10GbE KR mode set\n"); 1915 } 1916 1917 static void xgbe_phy_kx_2500_mode(struct xgbe_prv_data *pdata) 1918 { 1919 struct xgbe_phy_data *phy_data = pdata->phy_data; 1920 1921 xgbe_phy_set_redrv_mode(pdata); 1922 1923 /* 2.5G/KX */ 1924 xgbe_phy_perform_ratechange(pdata, 2, 0); 1925 1926 phy_data->cur_mode = XGBE_MODE_KX_2500; 1927 1928 netif_dbg(pdata, link, pdata->netdev, "2.5GbE KX mode set\n"); 1929 } 1930 1931 static void xgbe_phy_kx_1000_mode(struct xgbe_prv_data *pdata) 1932 { 1933 struct xgbe_phy_data *phy_data = pdata->phy_data; 1934 1935 xgbe_phy_set_redrv_mode(pdata); 1936 1937 /* 1G/KX */ 1938 xgbe_phy_perform_ratechange(pdata, 1, 3); 1939 1940 phy_data->cur_mode = XGBE_MODE_KX_1000; 1941 1942 netif_dbg(pdata, link, pdata->netdev, "1GbE KX mode set\n"); 1943 } 1944 1945 static enum xgbe_mode xgbe_phy_cur_mode(struct xgbe_prv_data *pdata) 1946 { 1947 struct xgbe_phy_data *phy_data = pdata->phy_data; 1948 1949 return phy_data->cur_mode; 1950 } 1951 1952 static enum xgbe_mode xgbe_phy_switch_baset_mode(struct xgbe_prv_data *pdata) 1953 { 1954 struct xgbe_phy_data *phy_data = pdata->phy_data; 1955 1956 /* No switching if not 10GBase-T */ 1957 if (phy_data->port_mode != XGBE_PORT_MODE_10GBASE_T) 1958 return xgbe_phy_cur_mode(pdata); 1959 1960 switch (xgbe_phy_cur_mode(pdata)) { 1961 case XGBE_MODE_SGMII_100: 1962 case XGBE_MODE_SGMII_1000: 1963 return XGBE_MODE_KR; 1964 case XGBE_MODE_KR: 1965 default: 1966 return XGBE_MODE_SGMII_1000; 1967 } 1968 } 1969 1970 static enum xgbe_mode xgbe_phy_switch_bp_2500_mode(struct xgbe_prv_data *pdata) 1971 { 1972 return XGBE_MODE_KX_2500; 1973 } 1974 1975 static enum xgbe_mode xgbe_phy_switch_bp_mode(struct xgbe_prv_data *pdata) 1976 { 1977 /* If we are in KR switch to KX, and vice-versa */ 1978 switch (xgbe_phy_cur_mode(pdata)) { 1979 case XGBE_MODE_KX_1000: 1980 return XGBE_MODE_KR; 1981 case XGBE_MODE_KR: 1982 default: 1983 return XGBE_MODE_KX_1000; 1984 } 1985 } 1986 1987 static enum xgbe_mode xgbe_phy_switch_mode(struct xgbe_prv_data *pdata) 1988 { 1989 struct xgbe_phy_data *phy_data = pdata->phy_data; 1990 1991 switch (phy_data->port_mode) { 1992 case XGBE_PORT_MODE_BACKPLANE: 1993 return xgbe_phy_switch_bp_mode(pdata); 1994 case XGBE_PORT_MODE_BACKPLANE_2500: 1995 return xgbe_phy_switch_bp_2500_mode(pdata); 1996 case XGBE_PORT_MODE_1000BASE_T: 1997 case XGBE_PORT_MODE_NBASE_T: 1998 case XGBE_PORT_MODE_10GBASE_T: 1999 return xgbe_phy_switch_baset_mode(pdata); 2000 case XGBE_PORT_MODE_1000BASE_X: 2001 case XGBE_PORT_MODE_10GBASE_R: 2002 case XGBE_PORT_MODE_SFP: 2003 /* No switching, so just return current mode */ 2004 return xgbe_phy_cur_mode(pdata); 2005 default: 2006 return XGBE_MODE_UNKNOWN; 2007 } 2008 } 2009 2010 static enum xgbe_mode xgbe_phy_get_basex_mode(struct xgbe_phy_data *phy_data, 2011 int speed) 2012 { 2013 switch (speed) { 2014 case SPEED_1000: 2015 return XGBE_MODE_X; 2016 case SPEED_10000: 2017 return XGBE_MODE_KR; 2018 default: 2019 return XGBE_MODE_UNKNOWN; 2020 } 2021 } 2022 2023 static enum xgbe_mode xgbe_phy_get_baset_mode(struct xgbe_phy_data *phy_data, 2024 int speed) 2025 { 2026 switch (speed) { 2027 case SPEED_100: 2028 return XGBE_MODE_SGMII_100; 2029 case SPEED_1000: 2030 return XGBE_MODE_SGMII_1000; 2031 case SPEED_2500: 2032 return XGBE_MODE_KX_2500; 2033 case SPEED_10000: 2034 return XGBE_MODE_KR; 2035 default: 2036 return XGBE_MODE_UNKNOWN; 2037 } 2038 } 2039 2040 static enum xgbe_mode xgbe_phy_get_sfp_mode(struct xgbe_phy_data *phy_data, 2041 int speed) 2042 { 2043 switch (speed) { 2044 case SPEED_100: 2045 return XGBE_MODE_SGMII_100; 2046 case SPEED_1000: 2047 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T) 2048 return XGBE_MODE_SGMII_1000; 2049 else 2050 return XGBE_MODE_X; 2051 case SPEED_10000: 2052 case SPEED_UNKNOWN: 2053 return XGBE_MODE_SFI; 2054 default: 2055 return XGBE_MODE_UNKNOWN; 2056 } 2057 } 2058 2059 static enum xgbe_mode xgbe_phy_get_bp_2500_mode(int speed) 2060 { 2061 switch (speed) { 2062 case SPEED_2500: 2063 return XGBE_MODE_KX_2500; 2064 default: 2065 return XGBE_MODE_UNKNOWN; 2066 } 2067 } 2068 2069 static enum xgbe_mode xgbe_phy_get_bp_mode(int speed) 2070 { 2071 switch (speed) { 2072 case SPEED_1000: 2073 return XGBE_MODE_KX_1000; 2074 case SPEED_10000: 2075 return XGBE_MODE_KR; 2076 default: 2077 return XGBE_MODE_UNKNOWN; 2078 } 2079 } 2080 2081 static enum xgbe_mode xgbe_phy_get_mode(struct xgbe_prv_data *pdata, 2082 int speed) 2083 { 2084 struct xgbe_phy_data *phy_data = pdata->phy_data; 2085 2086 switch (phy_data->port_mode) { 2087 case XGBE_PORT_MODE_BACKPLANE: 2088 return xgbe_phy_get_bp_mode(speed); 2089 case XGBE_PORT_MODE_BACKPLANE_2500: 2090 return xgbe_phy_get_bp_2500_mode(speed); 2091 case XGBE_PORT_MODE_1000BASE_T: 2092 case XGBE_PORT_MODE_NBASE_T: 2093 case XGBE_PORT_MODE_10GBASE_T: 2094 return xgbe_phy_get_baset_mode(phy_data, speed); 2095 case XGBE_PORT_MODE_1000BASE_X: 2096 case XGBE_PORT_MODE_10GBASE_R: 2097 return xgbe_phy_get_basex_mode(phy_data, speed); 2098 case XGBE_PORT_MODE_SFP: 2099 return xgbe_phy_get_sfp_mode(phy_data, speed); 2100 default: 2101 return XGBE_MODE_UNKNOWN; 2102 } 2103 } 2104 2105 static void xgbe_phy_set_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode) 2106 { 2107 switch (mode) { 2108 case XGBE_MODE_KX_1000: 2109 xgbe_phy_kx_1000_mode(pdata); 2110 break; 2111 case XGBE_MODE_KX_2500: 2112 xgbe_phy_kx_2500_mode(pdata); 2113 break; 2114 case XGBE_MODE_KR: 2115 xgbe_phy_kr_mode(pdata); 2116 break; 2117 case XGBE_MODE_SGMII_100: 2118 xgbe_phy_sgmii_100_mode(pdata); 2119 break; 2120 case XGBE_MODE_SGMII_1000: 2121 xgbe_phy_sgmii_1000_mode(pdata); 2122 break; 2123 case XGBE_MODE_X: 2124 xgbe_phy_x_mode(pdata); 2125 break; 2126 case XGBE_MODE_SFI: 2127 xgbe_phy_sfi_mode(pdata); 2128 break; 2129 default: 2130 break; 2131 } 2132 } 2133 2134 static bool xgbe_phy_check_mode(struct xgbe_prv_data *pdata, 2135 enum xgbe_mode mode, bool advert) 2136 { 2137 if (pdata->phy.autoneg == AUTONEG_ENABLE) { 2138 return advert; 2139 } else { 2140 enum xgbe_mode cur_mode; 2141 2142 cur_mode = xgbe_phy_get_mode(pdata, pdata->phy.speed); 2143 if (cur_mode == mode) 2144 return true; 2145 } 2146 2147 return false; 2148 } 2149 2150 static bool xgbe_phy_use_basex_mode(struct xgbe_prv_data *pdata, 2151 enum xgbe_mode mode) 2152 { 2153 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 2154 2155 switch (mode) { 2156 case XGBE_MODE_X: 2157 return xgbe_phy_check_mode(pdata, mode, 2158 XGBE_ADV(lks, 1000baseX_Full)); 2159 case XGBE_MODE_KR: 2160 return xgbe_phy_check_mode(pdata, mode, 2161 XGBE_ADV(lks, 10000baseKR_Full)); 2162 default: 2163 return false; 2164 } 2165 } 2166 2167 static bool xgbe_phy_use_baset_mode(struct xgbe_prv_data *pdata, 2168 enum xgbe_mode mode) 2169 { 2170 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 2171 2172 switch (mode) { 2173 case XGBE_MODE_SGMII_100: 2174 return xgbe_phy_check_mode(pdata, mode, 2175 XGBE_ADV(lks, 100baseT_Full)); 2176 case XGBE_MODE_SGMII_1000: 2177 return xgbe_phy_check_mode(pdata, mode, 2178 XGBE_ADV(lks, 1000baseT_Full)); 2179 case XGBE_MODE_KX_2500: 2180 return xgbe_phy_check_mode(pdata, mode, 2181 XGBE_ADV(lks, 2500baseT_Full)); 2182 case XGBE_MODE_KR: 2183 return xgbe_phy_check_mode(pdata, mode, 2184 XGBE_ADV(lks, 10000baseT_Full)); 2185 default: 2186 return false; 2187 } 2188 } 2189 2190 static bool xgbe_phy_use_sfp_mode(struct xgbe_prv_data *pdata, 2191 enum xgbe_mode mode) 2192 { 2193 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 2194 struct xgbe_phy_data *phy_data = pdata->phy_data; 2195 2196 switch (mode) { 2197 case XGBE_MODE_X: 2198 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T) 2199 return false; 2200 return xgbe_phy_check_mode(pdata, mode, 2201 XGBE_ADV(lks, 1000baseX_Full)); 2202 case XGBE_MODE_SGMII_100: 2203 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T) 2204 return false; 2205 return xgbe_phy_check_mode(pdata, mode, 2206 XGBE_ADV(lks, 100baseT_Full)); 2207 case XGBE_MODE_SGMII_1000: 2208 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T) 2209 return false; 2210 return xgbe_phy_check_mode(pdata, mode, 2211 XGBE_ADV(lks, 1000baseT_Full)); 2212 case XGBE_MODE_SFI: 2213 if (phy_data->sfp_mod_absent) 2214 return true; 2215 return xgbe_phy_check_mode(pdata, mode, 2216 XGBE_ADV(lks, 10000baseSR_Full) || 2217 XGBE_ADV(lks, 10000baseLR_Full) || 2218 XGBE_ADV(lks, 10000baseLRM_Full) || 2219 XGBE_ADV(lks, 10000baseER_Full) || 2220 XGBE_ADV(lks, 10000baseCR_Full)); 2221 default: 2222 return false; 2223 } 2224 } 2225 2226 static bool xgbe_phy_use_bp_2500_mode(struct xgbe_prv_data *pdata, 2227 enum xgbe_mode mode) 2228 { 2229 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 2230 2231 switch (mode) { 2232 case XGBE_MODE_KX_2500: 2233 return xgbe_phy_check_mode(pdata, mode, 2234 XGBE_ADV(lks, 2500baseX_Full)); 2235 default: 2236 return false; 2237 } 2238 } 2239 2240 static bool xgbe_phy_use_bp_mode(struct xgbe_prv_data *pdata, 2241 enum xgbe_mode mode) 2242 { 2243 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 2244 2245 switch (mode) { 2246 case XGBE_MODE_KX_1000: 2247 return xgbe_phy_check_mode(pdata, mode, 2248 XGBE_ADV(lks, 1000baseKX_Full)); 2249 case XGBE_MODE_KR: 2250 return xgbe_phy_check_mode(pdata, mode, 2251 XGBE_ADV(lks, 10000baseKR_Full)); 2252 default: 2253 return false; 2254 } 2255 } 2256 2257 static bool xgbe_phy_use_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode) 2258 { 2259 struct xgbe_phy_data *phy_data = pdata->phy_data; 2260 2261 switch (phy_data->port_mode) { 2262 case XGBE_PORT_MODE_BACKPLANE: 2263 return xgbe_phy_use_bp_mode(pdata, mode); 2264 case XGBE_PORT_MODE_BACKPLANE_2500: 2265 return xgbe_phy_use_bp_2500_mode(pdata, mode); 2266 case XGBE_PORT_MODE_1000BASE_T: 2267 case XGBE_PORT_MODE_NBASE_T: 2268 case XGBE_PORT_MODE_10GBASE_T: 2269 return xgbe_phy_use_baset_mode(pdata, mode); 2270 case XGBE_PORT_MODE_1000BASE_X: 2271 case XGBE_PORT_MODE_10GBASE_R: 2272 return xgbe_phy_use_basex_mode(pdata, mode); 2273 case XGBE_PORT_MODE_SFP: 2274 return xgbe_phy_use_sfp_mode(pdata, mode); 2275 default: 2276 return false; 2277 } 2278 } 2279 2280 static bool xgbe_phy_valid_speed_basex_mode(struct xgbe_phy_data *phy_data, 2281 int speed) 2282 { 2283 switch (speed) { 2284 case SPEED_1000: 2285 return (phy_data->port_mode == XGBE_PORT_MODE_1000BASE_X); 2286 case SPEED_10000: 2287 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_R); 2288 default: 2289 return false; 2290 } 2291 } 2292 2293 static bool xgbe_phy_valid_speed_baset_mode(struct xgbe_phy_data *phy_data, 2294 int speed) 2295 { 2296 switch (speed) { 2297 case SPEED_100: 2298 case SPEED_1000: 2299 return true; 2300 case SPEED_2500: 2301 return (phy_data->port_mode == XGBE_PORT_MODE_NBASE_T); 2302 case SPEED_10000: 2303 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_T); 2304 default: 2305 return false; 2306 } 2307 } 2308 2309 static bool xgbe_phy_valid_speed_sfp_mode(struct xgbe_phy_data *phy_data, 2310 int speed) 2311 { 2312 switch (speed) { 2313 case SPEED_100: 2314 return (phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000); 2315 case SPEED_1000: 2316 return ((phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000) || 2317 (phy_data->sfp_speed == XGBE_SFP_SPEED_1000)); 2318 case SPEED_10000: 2319 return (phy_data->sfp_speed == XGBE_SFP_SPEED_10000); 2320 default: 2321 return false; 2322 } 2323 } 2324 2325 static bool xgbe_phy_valid_speed_bp_2500_mode(int speed) 2326 { 2327 switch (speed) { 2328 case SPEED_2500: 2329 return true; 2330 default: 2331 return false; 2332 } 2333 } 2334 2335 static bool xgbe_phy_valid_speed_bp_mode(int speed) 2336 { 2337 switch (speed) { 2338 case SPEED_1000: 2339 case SPEED_10000: 2340 return true; 2341 default: 2342 return false; 2343 } 2344 } 2345 2346 static bool xgbe_phy_valid_speed(struct xgbe_prv_data *pdata, int speed) 2347 { 2348 struct xgbe_phy_data *phy_data = pdata->phy_data; 2349 2350 switch (phy_data->port_mode) { 2351 case XGBE_PORT_MODE_BACKPLANE: 2352 return xgbe_phy_valid_speed_bp_mode(speed); 2353 case XGBE_PORT_MODE_BACKPLANE_2500: 2354 return xgbe_phy_valid_speed_bp_2500_mode(speed); 2355 case XGBE_PORT_MODE_1000BASE_T: 2356 case XGBE_PORT_MODE_NBASE_T: 2357 case XGBE_PORT_MODE_10GBASE_T: 2358 return xgbe_phy_valid_speed_baset_mode(phy_data, speed); 2359 case XGBE_PORT_MODE_1000BASE_X: 2360 case XGBE_PORT_MODE_10GBASE_R: 2361 return xgbe_phy_valid_speed_basex_mode(phy_data, speed); 2362 case XGBE_PORT_MODE_SFP: 2363 return xgbe_phy_valid_speed_sfp_mode(phy_data, speed); 2364 default: 2365 return false; 2366 } 2367 } 2368 2369 static int xgbe_phy_link_status(struct xgbe_prv_data *pdata, int *an_restart) 2370 { 2371 struct xgbe_phy_data *phy_data = pdata->phy_data; 2372 unsigned int reg; 2373 int ret; 2374 2375 *an_restart = 0; 2376 2377 if (phy_data->port_mode == XGBE_PORT_MODE_SFP) { 2378 /* Check SFP signals */ 2379 xgbe_phy_sfp_detect(pdata); 2380 2381 if (phy_data->sfp_changed) { 2382 *an_restart = 1; 2383 return 0; 2384 } 2385 2386 if (phy_data->sfp_mod_absent || phy_data->sfp_rx_los) 2387 return 0; 2388 } 2389 2390 if (phy_data->phydev) { 2391 /* Check external PHY */ 2392 ret = phy_read_status(phy_data->phydev); 2393 if (ret < 0) 2394 return 0; 2395 2396 if ((pdata->phy.autoneg == AUTONEG_ENABLE) && 2397 !phy_aneg_done(phy_data->phydev)) 2398 return 0; 2399 2400 if (!phy_data->phydev->link) 2401 return 0; 2402 } 2403 2404 /* Link status is latched low, so read once to clear 2405 * and then read again to get current state 2406 */ 2407 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); 2408 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); 2409 if (reg & MDIO_STAT1_LSTATUS) 2410 return 1; 2411 2412 /* No link, attempt a receiver reset cycle */ 2413 if (phy_data->rrc_count++ > XGBE_RRC_FREQUENCY) { 2414 phy_data->rrc_count = 0; 2415 xgbe_phy_rrc(pdata); 2416 } 2417 2418 return 0; 2419 } 2420 2421 static void xgbe_phy_sfp_gpio_setup(struct xgbe_prv_data *pdata) 2422 { 2423 struct xgbe_phy_data *phy_data = pdata->phy_data; 2424 unsigned int reg; 2425 2426 reg = XP_IOREAD(pdata, XP_PROP_3); 2427 2428 phy_data->sfp_gpio_address = XGBE_GPIO_ADDRESS_PCA9555 + 2429 XP_GET_BITS(reg, XP_PROP_3, GPIO_ADDR); 2430 2431 phy_data->sfp_gpio_mask = XP_GET_BITS(reg, XP_PROP_3, GPIO_MASK); 2432 2433 phy_data->sfp_gpio_rx_los = XP_GET_BITS(reg, XP_PROP_3, 2434 GPIO_RX_LOS); 2435 phy_data->sfp_gpio_tx_fault = XP_GET_BITS(reg, XP_PROP_3, 2436 GPIO_TX_FAULT); 2437 phy_data->sfp_gpio_mod_absent = XP_GET_BITS(reg, XP_PROP_3, 2438 GPIO_MOD_ABS); 2439 phy_data->sfp_gpio_rate_select = XP_GET_BITS(reg, XP_PROP_3, 2440 GPIO_RATE_SELECT); 2441 2442 if (netif_msg_probe(pdata)) { 2443 dev_dbg(pdata->dev, "SFP: gpio_address=%#x\n", 2444 phy_data->sfp_gpio_address); 2445 dev_dbg(pdata->dev, "SFP: gpio_mask=%#x\n", 2446 phy_data->sfp_gpio_mask); 2447 dev_dbg(pdata->dev, "SFP: gpio_rx_los=%u\n", 2448 phy_data->sfp_gpio_rx_los); 2449 dev_dbg(pdata->dev, "SFP: gpio_tx_fault=%u\n", 2450 phy_data->sfp_gpio_tx_fault); 2451 dev_dbg(pdata->dev, "SFP: gpio_mod_absent=%u\n", 2452 phy_data->sfp_gpio_mod_absent); 2453 dev_dbg(pdata->dev, "SFP: gpio_rate_select=%u\n", 2454 phy_data->sfp_gpio_rate_select); 2455 } 2456 } 2457 2458 static void xgbe_phy_sfp_comm_setup(struct xgbe_prv_data *pdata) 2459 { 2460 struct xgbe_phy_data *phy_data = pdata->phy_data; 2461 unsigned int reg, mux_addr_hi, mux_addr_lo; 2462 2463 reg = XP_IOREAD(pdata, XP_PROP_4); 2464 2465 mux_addr_hi = XP_GET_BITS(reg, XP_PROP_4, MUX_ADDR_HI); 2466 mux_addr_lo = XP_GET_BITS(reg, XP_PROP_4, MUX_ADDR_LO); 2467 if (mux_addr_lo == XGBE_SFP_DIRECT) 2468 return; 2469 2470 phy_data->sfp_comm = XGBE_SFP_COMM_PCA9545; 2471 phy_data->sfp_mux_address = (mux_addr_hi << 2) + mux_addr_lo; 2472 phy_data->sfp_mux_channel = XP_GET_BITS(reg, XP_PROP_4, MUX_CHAN); 2473 2474 if (netif_msg_probe(pdata)) { 2475 dev_dbg(pdata->dev, "SFP: mux_address=%#x\n", 2476 phy_data->sfp_mux_address); 2477 dev_dbg(pdata->dev, "SFP: mux_channel=%u\n", 2478 phy_data->sfp_mux_channel); 2479 } 2480 } 2481 2482 static void xgbe_phy_sfp_setup(struct xgbe_prv_data *pdata) 2483 { 2484 xgbe_phy_sfp_comm_setup(pdata); 2485 xgbe_phy_sfp_gpio_setup(pdata); 2486 } 2487 2488 static int xgbe_phy_int_mdio_reset(struct xgbe_prv_data *pdata) 2489 { 2490 struct xgbe_phy_data *phy_data = pdata->phy_data; 2491 unsigned int ret; 2492 2493 ret = pdata->hw_if.set_gpio(pdata, phy_data->mdio_reset_gpio); 2494 if (ret) 2495 return ret; 2496 2497 ret = pdata->hw_if.clr_gpio(pdata, phy_data->mdio_reset_gpio); 2498 2499 return ret; 2500 } 2501 2502 static int xgbe_phy_i2c_mdio_reset(struct xgbe_prv_data *pdata) 2503 { 2504 struct xgbe_phy_data *phy_data = pdata->phy_data; 2505 u8 gpio_reg, gpio_ports[2], gpio_data[3]; 2506 int ret; 2507 2508 /* Read the output port registers */ 2509 gpio_reg = 2; 2510 ret = xgbe_phy_i2c_read(pdata, phy_data->mdio_reset_addr, 2511 &gpio_reg, sizeof(gpio_reg), 2512 gpio_ports, sizeof(gpio_ports)); 2513 if (ret) 2514 return ret; 2515 2516 /* Prepare to write the GPIO data */ 2517 gpio_data[0] = 2; 2518 gpio_data[1] = gpio_ports[0]; 2519 gpio_data[2] = gpio_ports[1]; 2520 2521 /* Set the GPIO pin */ 2522 if (phy_data->mdio_reset_gpio < 8) 2523 gpio_data[1] |= (1 << (phy_data->mdio_reset_gpio % 8)); 2524 else 2525 gpio_data[2] |= (1 << (phy_data->mdio_reset_gpio % 8)); 2526 2527 /* Write the output port registers */ 2528 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr, 2529 gpio_data, sizeof(gpio_data)); 2530 if (ret) 2531 return ret; 2532 2533 /* Clear the GPIO pin */ 2534 if (phy_data->mdio_reset_gpio < 8) 2535 gpio_data[1] &= ~(1 << (phy_data->mdio_reset_gpio % 8)); 2536 else 2537 gpio_data[2] &= ~(1 << (phy_data->mdio_reset_gpio % 8)); 2538 2539 /* Write the output port registers */ 2540 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr, 2541 gpio_data, sizeof(gpio_data)); 2542 2543 return ret; 2544 } 2545 2546 static int xgbe_phy_mdio_reset(struct xgbe_prv_data *pdata) 2547 { 2548 struct xgbe_phy_data *phy_data = pdata->phy_data; 2549 int ret; 2550 2551 if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO) 2552 return 0; 2553 2554 ret = xgbe_phy_get_comm_ownership(pdata); 2555 if (ret) 2556 return ret; 2557 2558 if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO) 2559 ret = xgbe_phy_i2c_mdio_reset(pdata); 2560 else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO) 2561 ret = xgbe_phy_int_mdio_reset(pdata); 2562 2563 xgbe_phy_put_comm_ownership(pdata); 2564 2565 return ret; 2566 } 2567 2568 static bool xgbe_phy_redrv_error(struct xgbe_phy_data *phy_data) 2569 { 2570 if (!phy_data->redrv) 2571 return false; 2572 2573 if (phy_data->redrv_if >= XGBE_PHY_REDRV_IF_MAX) 2574 return true; 2575 2576 switch (phy_data->redrv_model) { 2577 case XGBE_PHY_REDRV_MODEL_4223: 2578 if (phy_data->redrv_lane > 3) 2579 return true; 2580 break; 2581 case XGBE_PHY_REDRV_MODEL_4227: 2582 if (phy_data->redrv_lane > 1) 2583 return true; 2584 break; 2585 default: 2586 return true; 2587 } 2588 2589 return false; 2590 } 2591 2592 static int xgbe_phy_mdio_reset_setup(struct xgbe_prv_data *pdata) 2593 { 2594 struct xgbe_phy_data *phy_data = pdata->phy_data; 2595 unsigned int reg; 2596 2597 if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO) 2598 return 0; 2599 2600 reg = XP_IOREAD(pdata, XP_PROP_3); 2601 phy_data->mdio_reset = XP_GET_BITS(reg, XP_PROP_3, MDIO_RESET); 2602 switch (phy_data->mdio_reset) { 2603 case XGBE_MDIO_RESET_NONE: 2604 case XGBE_MDIO_RESET_I2C_GPIO: 2605 case XGBE_MDIO_RESET_INT_GPIO: 2606 break; 2607 default: 2608 dev_err(pdata->dev, "unsupported MDIO reset (%#x)\n", 2609 phy_data->mdio_reset); 2610 return -EINVAL; 2611 } 2612 2613 if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO) { 2614 phy_data->mdio_reset_addr = XGBE_GPIO_ADDRESS_PCA9555 + 2615 XP_GET_BITS(reg, XP_PROP_3, 2616 MDIO_RESET_I2C_ADDR); 2617 phy_data->mdio_reset_gpio = XP_GET_BITS(reg, XP_PROP_3, 2618 MDIO_RESET_I2C_GPIO); 2619 } else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO) { 2620 phy_data->mdio_reset_gpio = XP_GET_BITS(reg, XP_PROP_3, 2621 MDIO_RESET_INT_GPIO); 2622 } 2623 2624 return 0; 2625 } 2626 2627 static bool xgbe_phy_port_mode_mismatch(struct xgbe_prv_data *pdata) 2628 { 2629 struct xgbe_phy_data *phy_data = pdata->phy_data; 2630 2631 switch (phy_data->port_mode) { 2632 case XGBE_PORT_MODE_BACKPLANE: 2633 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) || 2634 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)) 2635 return false; 2636 break; 2637 case XGBE_PORT_MODE_BACKPLANE_2500: 2638 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500) 2639 return false; 2640 break; 2641 case XGBE_PORT_MODE_1000BASE_T: 2642 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) || 2643 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)) 2644 return false; 2645 break; 2646 case XGBE_PORT_MODE_1000BASE_X: 2647 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) 2648 return false; 2649 break; 2650 case XGBE_PORT_MODE_NBASE_T: 2651 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) || 2652 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) || 2653 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500)) 2654 return false; 2655 break; 2656 case XGBE_PORT_MODE_10GBASE_T: 2657 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) || 2658 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) || 2659 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)) 2660 return false; 2661 break; 2662 case XGBE_PORT_MODE_10GBASE_R: 2663 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) 2664 return false; 2665 break; 2666 case XGBE_PORT_MODE_SFP: 2667 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) || 2668 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) || 2669 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)) 2670 return false; 2671 break; 2672 default: 2673 break; 2674 } 2675 2676 return true; 2677 } 2678 2679 static bool xgbe_phy_conn_type_mismatch(struct xgbe_prv_data *pdata) 2680 { 2681 struct xgbe_phy_data *phy_data = pdata->phy_data; 2682 2683 switch (phy_data->port_mode) { 2684 case XGBE_PORT_MODE_BACKPLANE: 2685 case XGBE_PORT_MODE_BACKPLANE_2500: 2686 if (phy_data->conn_type == XGBE_CONN_TYPE_BACKPLANE) 2687 return false; 2688 break; 2689 case XGBE_PORT_MODE_1000BASE_T: 2690 case XGBE_PORT_MODE_1000BASE_X: 2691 case XGBE_PORT_MODE_NBASE_T: 2692 case XGBE_PORT_MODE_10GBASE_T: 2693 case XGBE_PORT_MODE_10GBASE_R: 2694 if (phy_data->conn_type == XGBE_CONN_TYPE_MDIO) 2695 return false; 2696 break; 2697 case XGBE_PORT_MODE_SFP: 2698 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP) 2699 return false; 2700 break; 2701 default: 2702 break; 2703 } 2704 2705 return true; 2706 } 2707 2708 static bool xgbe_phy_port_enabled(struct xgbe_prv_data *pdata) 2709 { 2710 unsigned int reg; 2711 2712 reg = XP_IOREAD(pdata, XP_PROP_0); 2713 if (!XP_GET_BITS(reg, XP_PROP_0, PORT_SPEEDS)) 2714 return false; 2715 if (!XP_GET_BITS(reg, XP_PROP_0, CONN_TYPE)) 2716 return false; 2717 2718 return true; 2719 } 2720 2721 static void xgbe_phy_cdr_track(struct xgbe_prv_data *pdata) 2722 { 2723 struct xgbe_phy_data *phy_data = pdata->phy_data; 2724 2725 if (!pdata->debugfs_an_cdr_workaround) 2726 return; 2727 2728 if (!phy_data->phy_cdr_notrack) 2729 return; 2730 2731 usleep_range(phy_data->phy_cdr_delay, 2732 phy_data->phy_cdr_delay + 500); 2733 2734 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL, 2735 XGBE_PMA_CDR_TRACK_EN_MASK, 2736 XGBE_PMA_CDR_TRACK_EN_ON); 2737 2738 phy_data->phy_cdr_notrack = 0; 2739 } 2740 2741 static void xgbe_phy_cdr_notrack(struct xgbe_prv_data *pdata) 2742 { 2743 struct xgbe_phy_data *phy_data = pdata->phy_data; 2744 2745 if (!pdata->debugfs_an_cdr_workaround) 2746 return; 2747 2748 if (phy_data->phy_cdr_notrack) 2749 return; 2750 2751 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL, 2752 XGBE_PMA_CDR_TRACK_EN_MASK, 2753 XGBE_PMA_CDR_TRACK_EN_OFF); 2754 2755 xgbe_phy_rrc(pdata); 2756 2757 phy_data->phy_cdr_notrack = 1; 2758 } 2759 2760 static void xgbe_phy_kr_training_post(struct xgbe_prv_data *pdata) 2761 { 2762 if (!pdata->debugfs_an_cdr_track_early) 2763 xgbe_phy_cdr_track(pdata); 2764 } 2765 2766 static void xgbe_phy_kr_training_pre(struct xgbe_prv_data *pdata) 2767 { 2768 if (pdata->debugfs_an_cdr_track_early) 2769 xgbe_phy_cdr_track(pdata); 2770 } 2771 2772 static void xgbe_phy_an_post(struct xgbe_prv_data *pdata) 2773 { 2774 struct xgbe_phy_data *phy_data = pdata->phy_data; 2775 2776 switch (pdata->an_mode) { 2777 case XGBE_AN_MODE_CL73: 2778 case XGBE_AN_MODE_CL73_REDRV: 2779 if (phy_data->cur_mode != XGBE_MODE_KR) 2780 break; 2781 2782 xgbe_phy_cdr_track(pdata); 2783 2784 switch (pdata->an_result) { 2785 case XGBE_AN_READY: 2786 case XGBE_AN_COMPLETE: 2787 break; 2788 default: 2789 if (phy_data->phy_cdr_delay < XGBE_CDR_DELAY_MAX) 2790 phy_data->phy_cdr_delay += XGBE_CDR_DELAY_INC; 2791 else 2792 phy_data->phy_cdr_delay = XGBE_CDR_DELAY_INIT; 2793 break; 2794 } 2795 break; 2796 default: 2797 break; 2798 } 2799 } 2800 2801 static void xgbe_phy_an_pre(struct xgbe_prv_data *pdata) 2802 { 2803 struct xgbe_phy_data *phy_data = pdata->phy_data; 2804 2805 switch (pdata->an_mode) { 2806 case XGBE_AN_MODE_CL73: 2807 case XGBE_AN_MODE_CL73_REDRV: 2808 if (phy_data->cur_mode != XGBE_MODE_KR) 2809 break; 2810 2811 xgbe_phy_cdr_notrack(pdata); 2812 break; 2813 default: 2814 break; 2815 } 2816 } 2817 2818 static void xgbe_phy_stop(struct xgbe_prv_data *pdata) 2819 { 2820 struct xgbe_phy_data *phy_data = pdata->phy_data; 2821 2822 /* If we have an external PHY, free it */ 2823 xgbe_phy_free_phy_device(pdata); 2824 2825 /* Reset SFP data */ 2826 xgbe_phy_sfp_reset(phy_data); 2827 xgbe_phy_sfp_mod_absent(pdata); 2828 2829 /* Reset CDR support */ 2830 xgbe_phy_cdr_track(pdata); 2831 2832 /* Power off the PHY */ 2833 xgbe_phy_power_off(pdata); 2834 2835 /* Stop the I2C controller */ 2836 pdata->i2c_if.i2c_stop(pdata); 2837 } 2838 2839 static int xgbe_phy_start(struct xgbe_prv_data *pdata) 2840 { 2841 struct xgbe_phy_data *phy_data = pdata->phy_data; 2842 int ret; 2843 2844 /* Start the I2C controller */ 2845 ret = pdata->i2c_if.i2c_start(pdata); 2846 if (ret) 2847 return ret; 2848 2849 /* Set the proper MDIO mode for the re-driver */ 2850 if (phy_data->redrv && !phy_data->redrv_if) { 2851 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr, 2852 XGBE_MDIO_MODE_CL22); 2853 if (ret) { 2854 netdev_err(pdata->netdev, 2855 "redriver mdio port not compatible (%u)\n", 2856 phy_data->redrv_addr); 2857 return ret; 2858 } 2859 } 2860 2861 /* Start in highest supported mode */ 2862 xgbe_phy_set_mode(pdata, phy_data->start_mode); 2863 2864 /* Reset CDR support */ 2865 xgbe_phy_cdr_track(pdata); 2866 2867 /* After starting the I2C controller, we can check for an SFP */ 2868 switch (phy_data->port_mode) { 2869 case XGBE_PORT_MODE_SFP: 2870 xgbe_phy_sfp_detect(pdata); 2871 break; 2872 default: 2873 break; 2874 } 2875 2876 /* If we have an external PHY, start it */ 2877 ret = xgbe_phy_find_phy_device(pdata); 2878 if (ret) 2879 goto err_i2c; 2880 2881 return 0; 2882 2883 err_i2c: 2884 pdata->i2c_if.i2c_stop(pdata); 2885 2886 return ret; 2887 } 2888 2889 static int xgbe_phy_reset(struct xgbe_prv_data *pdata) 2890 { 2891 struct xgbe_phy_data *phy_data = pdata->phy_data; 2892 enum xgbe_mode cur_mode; 2893 int ret; 2894 2895 /* Reset by power cycling the PHY */ 2896 cur_mode = phy_data->cur_mode; 2897 xgbe_phy_power_off(pdata); 2898 xgbe_phy_set_mode(pdata, cur_mode); 2899 2900 if (!phy_data->phydev) 2901 return 0; 2902 2903 /* Reset the external PHY */ 2904 ret = xgbe_phy_mdio_reset(pdata); 2905 if (ret) 2906 return ret; 2907 2908 return phy_init_hw(phy_data->phydev); 2909 } 2910 2911 static void xgbe_phy_exit(struct xgbe_prv_data *pdata) 2912 { 2913 struct xgbe_phy_data *phy_data = pdata->phy_data; 2914 2915 /* Unregister for driving external PHYs */ 2916 mdiobus_unregister(phy_data->mii); 2917 } 2918 2919 static int xgbe_phy_init(struct xgbe_prv_data *pdata) 2920 { 2921 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 2922 struct xgbe_phy_data *phy_data; 2923 struct mii_bus *mii; 2924 unsigned int reg; 2925 int ret; 2926 2927 /* Check if enabled */ 2928 if (!xgbe_phy_port_enabled(pdata)) { 2929 dev_info(pdata->dev, "device is not enabled\n"); 2930 return -ENODEV; 2931 } 2932 2933 /* Initialize the I2C controller */ 2934 ret = pdata->i2c_if.i2c_init(pdata); 2935 if (ret) 2936 return ret; 2937 2938 phy_data = devm_kzalloc(pdata->dev, sizeof(*phy_data), GFP_KERNEL); 2939 if (!phy_data) 2940 return -ENOMEM; 2941 pdata->phy_data = phy_data; 2942 2943 reg = XP_IOREAD(pdata, XP_PROP_0); 2944 phy_data->port_mode = XP_GET_BITS(reg, XP_PROP_0, PORT_MODE); 2945 phy_data->port_id = XP_GET_BITS(reg, XP_PROP_0, PORT_ID); 2946 phy_data->port_speeds = XP_GET_BITS(reg, XP_PROP_0, PORT_SPEEDS); 2947 phy_data->conn_type = XP_GET_BITS(reg, XP_PROP_0, CONN_TYPE); 2948 phy_data->mdio_addr = XP_GET_BITS(reg, XP_PROP_0, MDIO_ADDR); 2949 if (netif_msg_probe(pdata)) { 2950 dev_dbg(pdata->dev, "port mode=%u\n", phy_data->port_mode); 2951 dev_dbg(pdata->dev, "port id=%u\n", phy_data->port_id); 2952 dev_dbg(pdata->dev, "port speeds=%#x\n", phy_data->port_speeds); 2953 dev_dbg(pdata->dev, "conn type=%u\n", phy_data->conn_type); 2954 dev_dbg(pdata->dev, "mdio addr=%u\n", phy_data->mdio_addr); 2955 } 2956 2957 reg = XP_IOREAD(pdata, XP_PROP_4); 2958 phy_data->redrv = XP_GET_BITS(reg, XP_PROP_4, REDRV_PRESENT); 2959 phy_data->redrv_if = XP_GET_BITS(reg, XP_PROP_4, REDRV_IF); 2960 phy_data->redrv_addr = XP_GET_BITS(reg, XP_PROP_4, REDRV_ADDR); 2961 phy_data->redrv_lane = XP_GET_BITS(reg, XP_PROP_4, REDRV_LANE); 2962 phy_data->redrv_model = XP_GET_BITS(reg, XP_PROP_4, REDRV_MODEL); 2963 if (phy_data->redrv && netif_msg_probe(pdata)) { 2964 dev_dbg(pdata->dev, "redrv present\n"); 2965 dev_dbg(pdata->dev, "redrv i/f=%u\n", phy_data->redrv_if); 2966 dev_dbg(pdata->dev, "redrv addr=%#x\n", phy_data->redrv_addr); 2967 dev_dbg(pdata->dev, "redrv lane=%u\n", phy_data->redrv_lane); 2968 dev_dbg(pdata->dev, "redrv model=%u\n", phy_data->redrv_model); 2969 } 2970 2971 /* Validate the connection requested */ 2972 if (xgbe_phy_conn_type_mismatch(pdata)) { 2973 dev_err(pdata->dev, "phy mode/connection mismatch (%#x/%#x)\n", 2974 phy_data->port_mode, phy_data->conn_type); 2975 return -EINVAL; 2976 } 2977 2978 /* Validate the mode requested */ 2979 if (xgbe_phy_port_mode_mismatch(pdata)) { 2980 dev_err(pdata->dev, "phy mode/speed mismatch (%#x/%#x)\n", 2981 phy_data->port_mode, phy_data->port_speeds); 2982 return -EINVAL; 2983 } 2984 2985 /* Check for and validate MDIO reset support */ 2986 ret = xgbe_phy_mdio_reset_setup(pdata); 2987 if (ret) 2988 return ret; 2989 2990 /* Validate the re-driver information */ 2991 if (xgbe_phy_redrv_error(phy_data)) { 2992 dev_err(pdata->dev, "phy re-driver settings error\n"); 2993 return -EINVAL; 2994 } 2995 pdata->kr_redrv = phy_data->redrv; 2996 2997 /* Indicate current mode is unknown */ 2998 phy_data->cur_mode = XGBE_MODE_UNKNOWN; 2999 3000 /* Initialize supported features */ 3001 XGBE_ZERO_SUP(lks); 3002 3003 switch (phy_data->port_mode) { 3004 /* Backplane support */ 3005 case XGBE_PORT_MODE_BACKPLANE: 3006 XGBE_SET_SUP(lks, Autoneg); 3007 XGBE_SET_SUP(lks, Pause); 3008 XGBE_SET_SUP(lks, Asym_Pause); 3009 XGBE_SET_SUP(lks, Backplane); 3010 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) { 3011 XGBE_SET_SUP(lks, 1000baseKX_Full); 3012 phy_data->start_mode = XGBE_MODE_KX_1000; 3013 } 3014 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) { 3015 XGBE_SET_SUP(lks, 10000baseKR_Full); 3016 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 3017 XGBE_SET_SUP(lks, 10000baseR_FEC); 3018 phy_data->start_mode = XGBE_MODE_KR; 3019 } 3020 3021 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE; 3022 break; 3023 case XGBE_PORT_MODE_BACKPLANE_2500: 3024 XGBE_SET_SUP(lks, Pause); 3025 XGBE_SET_SUP(lks, Asym_Pause); 3026 XGBE_SET_SUP(lks, Backplane); 3027 XGBE_SET_SUP(lks, 2500baseX_Full); 3028 phy_data->start_mode = XGBE_MODE_KX_2500; 3029 3030 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE; 3031 break; 3032 3033 /* MDIO 1GBase-T support */ 3034 case XGBE_PORT_MODE_1000BASE_T: 3035 XGBE_SET_SUP(lks, Autoneg); 3036 XGBE_SET_SUP(lks, Pause); 3037 XGBE_SET_SUP(lks, Asym_Pause); 3038 XGBE_SET_SUP(lks, TP); 3039 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) { 3040 XGBE_SET_SUP(lks, 100baseT_Full); 3041 phy_data->start_mode = XGBE_MODE_SGMII_100; 3042 } 3043 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) { 3044 XGBE_SET_SUP(lks, 1000baseT_Full); 3045 phy_data->start_mode = XGBE_MODE_SGMII_1000; 3046 } 3047 3048 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22; 3049 break; 3050 3051 /* MDIO Base-X support */ 3052 case XGBE_PORT_MODE_1000BASE_X: 3053 XGBE_SET_SUP(lks, Autoneg); 3054 XGBE_SET_SUP(lks, Pause); 3055 XGBE_SET_SUP(lks, Asym_Pause); 3056 XGBE_SET_SUP(lks, FIBRE); 3057 XGBE_SET_SUP(lks, 1000baseX_Full); 3058 phy_data->start_mode = XGBE_MODE_X; 3059 3060 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22; 3061 break; 3062 3063 /* MDIO NBase-T support */ 3064 case XGBE_PORT_MODE_NBASE_T: 3065 XGBE_SET_SUP(lks, Autoneg); 3066 XGBE_SET_SUP(lks, Pause); 3067 XGBE_SET_SUP(lks, Asym_Pause); 3068 XGBE_SET_SUP(lks, TP); 3069 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) { 3070 XGBE_SET_SUP(lks, 100baseT_Full); 3071 phy_data->start_mode = XGBE_MODE_SGMII_100; 3072 } 3073 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) { 3074 XGBE_SET_SUP(lks, 1000baseT_Full); 3075 phy_data->start_mode = XGBE_MODE_SGMII_1000; 3076 } 3077 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500) { 3078 XGBE_SET_SUP(lks, 2500baseT_Full); 3079 phy_data->start_mode = XGBE_MODE_KX_2500; 3080 } 3081 3082 phy_data->phydev_mode = XGBE_MDIO_MODE_CL45; 3083 break; 3084 3085 /* 10GBase-T support */ 3086 case XGBE_PORT_MODE_10GBASE_T: 3087 XGBE_SET_SUP(lks, Autoneg); 3088 XGBE_SET_SUP(lks, Pause); 3089 XGBE_SET_SUP(lks, Asym_Pause); 3090 XGBE_SET_SUP(lks, TP); 3091 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) { 3092 XGBE_SET_SUP(lks, 100baseT_Full); 3093 phy_data->start_mode = XGBE_MODE_SGMII_100; 3094 } 3095 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) { 3096 XGBE_SET_SUP(lks, 1000baseT_Full); 3097 phy_data->start_mode = XGBE_MODE_SGMII_1000; 3098 } 3099 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) { 3100 XGBE_SET_SUP(lks, 10000baseT_Full); 3101 phy_data->start_mode = XGBE_MODE_KR; 3102 } 3103 3104 phy_data->phydev_mode = XGBE_MDIO_MODE_CL45; 3105 break; 3106 3107 /* 10GBase-R support */ 3108 case XGBE_PORT_MODE_10GBASE_R: 3109 XGBE_SET_SUP(lks, Autoneg); 3110 XGBE_SET_SUP(lks, Pause); 3111 XGBE_SET_SUP(lks, Asym_Pause); 3112 XGBE_SET_SUP(lks, FIBRE); 3113 XGBE_SET_SUP(lks, 10000baseSR_Full); 3114 XGBE_SET_SUP(lks, 10000baseLR_Full); 3115 XGBE_SET_SUP(lks, 10000baseLRM_Full); 3116 XGBE_SET_SUP(lks, 10000baseER_Full); 3117 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 3118 XGBE_SET_SUP(lks, 10000baseR_FEC); 3119 phy_data->start_mode = XGBE_MODE_SFI; 3120 3121 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE; 3122 break; 3123 3124 /* SFP support */ 3125 case XGBE_PORT_MODE_SFP: 3126 XGBE_SET_SUP(lks, Autoneg); 3127 XGBE_SET_SUP(lks, Pause); 3128 XGBE_SET_SUP(lks, Asym_Pause); 3129 XGBE_SET_SUP(lks, TP); 3130 XGBE_SET_SUP(lks, FIBRE); 3131 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) 3132 phy_data->start_mode = XGBE_MODE_SGMII_100; 3133 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) 3134 phy_data->start_mode = XGBE_MODE_SGMII_1000; 3135 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) 3136 phy_data->start_mode = XGBE_MODE_SFI; 3137 3138 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22; 3139 3140 xgbe_phy_sfp_setup(pdata); 3141 break; 3142 default: 3143 return -EINVAL; 3144 } 3145 3146 if (netif_msg_probe(pdata)) 3147 dev_dbg(pdata->dev, "phy supported=0x%*pb\n", 3148 __ETHTOOL_LINK_MODE_MASK_NBITS, 3149 lks->link_modes.supported); 3150 3151 if ((phy_data->conn_type & XGBE_CONN_TYPE_MDIO) && 3152 (phy_data->phydev_mode != XGBE_MDIO_MODE_NONE)) { 3153 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr, 3154 phy_data->phydev_mode); 3155 if (ret) { 3156 dev_err(pdata->dev, 3157 "mdio port/clause not compatible (%d/%u)\n", 3158 phy_data->mdio_addr, phy_data->phydev_mode); 3159 return -EINVAL; 3160 } 3161 } 3162 3163 if (phy_data->redrv && !phy_data->redrv_if) { 3164 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr, 3165 XGBE_MDIO_MODE_CL22); 3166 if (ret) { 3167 dev_err(pdata->dev, 3168 "redriver mdio port not compatible (%u)\n", 3169 phy_data->redrv_addr); 3170 return -EINVAL; 3171 } 3172 } 3173 3174 phy_data->phy_cdr_delay = XGBE_CDR_DELAY_INIT; 3175 3176 /* Register for driving external PHYs */ 3177 mii = devm_mdiobus_alloc(pdata->dev); 3178 if (!mii) { 3179 dev_err(pdata->dev, "mdiobus_alloc failed\n"); 3180 return -ENOMEM; 3181 } 3182 3183 mii->priv = pdata; 3184 mii->name = "amd-xgbe-mii"; 3185 mii->read = xgbe_phy_mii_read; 3186 mii->write = xgbe_phy_mii_write; 3187 mii->parent = pdata->dev; 3188 mii->phy_mask = ~0; 3189 snprintf(mii->id, sizeof(mii->id), "%s", dev_name(pdata->dev)); 3190 ret = mdiobus_register(mii); 3191 if (ret) { 3192 dev_err(pdata->dev, "mdiobus_register failed\n"); 3193 return ret; 3194 } 3195 phy_data->mii = mii; 3196 3197 return 0; 3198 } 3199 3200 void xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if *phy_if) 3201 { 3202 struct xgbe_phy_impl_if *phy_impl = &phy_if->phy_impl; 3203 3204 phy_impl->init = xgbe_phy_init; 3205 phy_impl->exit = xgbe_phy_exit; 3206 3207 phy_impl->reset = xgbe_phy_reset; 3208 phy_impl->start = xgbe_phy_start; 3209 phy_impl->stop = xgbe_phy_stop; 3210 3211 phy_impl->link_status = xgbe_phy_link_status; 3212 3213 phy_impl->valid_speed = xgbe_phy_valid_speed; 3214 3215 phy_impl->use_mode = xgbe_phy_use_mode; 3216 phy_impl->set_mode = xgbe_phy_set_mode; 3217 phy_impl->get_mode = xgbe_phy_get_mode; 3218 phy_impl->switch_mode = xgbe_phy_switch_mode; 3219 phy_impl->cur_mode = xgbe_phy_cur_mode; 3220 3221 phy_impl->an_mode = xgbe_phy_an_mode; 3222 3223 phy_impl->an_config = xgbe_phy_an_config; 3224 3225 phy_impl->an_advertising = xgbe_phy_an_advertising; 3226 3227 phy_impl->an_outcome = xgbe_phy_an_outcome; 3228 3229 phy_impl->an_pre = xgbe_phy_an_pre; 3230 phy_impl->an_post = xgbe_phy_an_post; 3231 3232 phy_impl->kr_training_pre = xgbe_phy_kr_training_pre; 3233 phy_impl->kr_training_post = xgbe_phy_kr_training_post; 3234 } 3235