1 /* 2 * AMD 10Gb Ethernet driver 3 * 4 * This file is available to you under your choice of the following two 5 * licenses: 6 * 7 * License 1: GPLv2 8 * 9 * Copyright (c) 2016 Advanced Micro Devices, Inc. 10 * 11 * This file is free software; you may copy, redistribute and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation, either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program. If not, see <http://www.gnu.org/licenses/>. 23 * 24 * This file incorporates work covered by the following copyright and 25 * permission notice: 26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 28 * Inc. unless otherwise expressly agreed to in writing between Synopsys 29 * and you. 30 * 31 * The Software IS NOT an item of Licensed Software or Licensed Product 32 * under any End User Software License Agreement or Agreement for Licensed 33 * Product with Synopsys or any supplement thereto. Permission is hereby 34 * granted, free of charge, to any person obtaining a copy of this software 35 * annotated with this license and the Software, to deal in the Software 36 * without restriction, including without limitation the rights to use, 37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 38 * of the Software, and to permit persons to whom the Software is furnished 39 * to do so, subject to the following conditions: 40 * 41 * The above copyright notice and this permission notice shall be included 42 * in all copies or substantial portions of the Software. 43 * 44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 54 * THE POSSIBILITY OF SUCH DAMAGE. 55 * 56 * 57 * License 2: Modified BSD 58 * 59 * Copyright (c) 2016 Advanced Micro Devices, Inc. 60 * All rights reserved. 61 * 62 * Redistribution and use in source and binary forms, with or without 63 * modification, are permitted provided that the following conditions are met: 64 * * Redistributions of source code must retain the above copyright 65 * notice, this list of conditions and the following disclaimer. 66 * * Redistributions in binary form must reproduce the above copyright 67 * notice, this list of conditions and the following disclaimer in the 68 * documentation and/or other materials provided with the distribution. 69 * * Neither the name of Advanced Micro Devices, Inc. nor the 70 * names of its contributors may be used to endorse or promote products 71 * derived from this software without specific prior written permission. 72 * 73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY 77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 83 * 84 * This file incorporates work covered by the following copyright and 85 * permission notice: 86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 88 * Inc. unless otherwise expressly agreed to in writing between Synopsys 89 * and you. 90 * 91 * The Software IS NOT an item of Licensed Software or Licensed Product 92 * under any End User Software License Agreement or Agreement for Licensed 93 * Product with Synopsys or any supplement thereto. Permission is hereby 94 * granted, free of charge, to any person obtaining a copy of this software 95 * annotated with this license and the Software, to deal in the Software 96 * without restriction, including without limitation the rights to use, 97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 98 * of the Software, and to permit persons to whom the Software is furnished 99 * to do so, subject to the following conditions: 100 * 101 * The above copyright notice and this permission notice shall be included 102 * in all copies or substantial portions of the Software. 103 * 104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 114 * THE POSSIBILITY OF SUCH DAMAGE. 115 */ 116 117 #include <linux/module.h> 118 #include <linux/device.h> 119 #include <linux/kmod.h> 120 #include <linux/mdio.h> 121 #include <linux/phy.h> 122 123 #include "xgbe.h" 124 #include "xgbe-common.h" 125 126 #define XGBE_PHY_PORT_SPEED_100 BIT(0) 127 #define XGBE_PHY_PORT_SPEED_1000 BIT(1) 128 #define XGBE_PHY_PORT_SPEED_2500 BIT(2) 129 #define XGBE_PHY_PORT_SPEED_10000 BIT(3) 130 131 #define XGBE_MUTEX_RELEASE 0x80000000 132 133 #define XGBE_SFP_DIRECT 7 134 135 /* I2C target addresses */ 136 #define XGBE_SFP_SERIAL_ID_ADDRESS 0x50 137 #define XGBE_SFP_DIAG_INFO_ADDRESS 0x51 138 #define XGBE_SFP_PHY_ADDRESS 0x56 139 #define XGBE_GPIO_ADDRESS_PCA9555 0x20 140 141 /* SFP sideband signal indicators */ 142 #define XGBE_GPIO_NO_TX_FAULT BIT(0) 143 #define XGBE_GPIO_NO_RATE_SELECT BIT(1) 144 #define XGBE_GPIO_NO_MOD_ABSENT BIT(2) 145 #define XGBE_GPIO_NO_RX_LOS BIT(3) 146 147 /* Rate-change complete wait/retry count */ 148 #define XGBE_RATECHANGE_COUNT 500 149 150 enum xgbe_port_mode { 151 XGBE_PORT_MODE_RSVD = 0, 152 XGBE_PORT_MODE_BACKPLANE, 153 XGBE_PORT_MODE_BACKPLANE_2500, 154 XGBE_PORT_MODE_1000BASE_T, 155 XGBE_PORT_MODE_1000BASE_X, 156 XGBE_PORT_MODE_NBASE_T, 157 XGBE_PORT_MODE_10GBASE_T, 158 XGBE_PORT_MODE_10GBASE_R, 159 XGBE_PORT_MODE_SFP, 160 XGBE_PORT_MODE_MAX, 161 }; 162 163 enum xgbe_conn_type { 164 XGBE_CONN_TYPE_NONE = 0, 165 XGBE_CONN_TYPE_SFP, 166 XGBE_CONN_TYPE_MDIO, 167 XGBE_CONN_TYPE_RSVD1, 168 XGBE_CONN_TYPE_BACKPLANE, 169 XGBE_CONN_TYPE_MAX, 170 }; 171 172 /* SFP/SFP+ related definitions */ 173 enum xgbe_sfp_comm { 174 XGBE_SFP_COMM_DIRECT = 0, 175 XGBE_SFP_COMM_PCA9545, 176 }; 177 178 enum xgbe_sfp_cable { 179 XGBE_SFP_CABLE_UNKNOWN = 0, 180 XGBE_SFP_CABLE_ACTIVE, 181 XGBE_SFP_CABLE_PASSIVE, 182 }; 183 184 enum xgbe_sfp_base { 185 XGBE_SFP_BASE_UNKNOWN = 0, 186 XGBE_SFP_BASE_1000_T, 187 XGBE_SFP_BASE_1000_SX, 188 XGBE_SFP_BASE_1000_LX, 189 XGBE_SFP_BASE_1000_CX, 190 XGBE_SFP_BASE_10000_SR, 191 XGBE_SFP_BASE_10000_LR, 192 XGBE_SFP_BASE_10000_LRM, 193 XGBE_SFP_BASE_10000_ER, 194 XGBE_SFP_BASE_10000_CR, 195 }; 196 197 enum xgbe_sfp_speed { 198 XGBE_SFP_SPEED_UNKNOWN = 0, 199 XGBE_SFP_SPEED_100_1000, 200 XGBE_SFP_SPEED_1000, 201 XGBE_SFP_SPEED_10000, 202 }; 203 204 /* SFP Serial ID Base ID values relative to an offset of 0 */ 205 #define XGBE_SFP_BASE_ID 0 206 #define XGBE_SFP_ID_SFP 0x03 207 208 #define XGBE_SFP_BASE_EXT_ID 1 209 #define XGBE_SFP_EXT_ID_SFP 0x04 210 211 #define XGBE_SFP_BASE_10GBE_CC 3 212 #define XGBE_SFP_BASE_10GBE_CC_SR BIT(4) 213 #define XGBE_SFP_BASE_10GBE_CC_LR BIT(5) 214 #define XGBE_SFP_BASE_10GBE_CC_LRM BIT(6) 215 #define XGBE_SFP_BASE_10GBE_CC_ER BIT(7) 216 217 #define XGBE_SFP_BASE_1GBE_CC 6 218 #define XGBE_SFP_BASE_1GBE_CC_SX BIT(0) 219 #define XGBE_SFP_BASE_1GBE_CC_LX BIT(1) 220 #define XGBE_SFP_BASE_1GBE_CC_CX BIT(2) 221 #define XGBE_SFP_BASE_1GBE_CC_T BIT(3) 222 223 #define XGBE_SFP_BASE_CABLE 8 224 #define XGBE_SFP_BASE_CABLE_PASSIVE BIT(2) 225 #define XGBE_SFP_BASE_CABLE_ACTIVE BIT(3) 226 227 #define XGBE_SFP_BASE_BR 12 228 #define XGBE_SFP_BASE_BR_1GBE_MIN 0x0a 229 #define XGBE_SFP_BASE_BR_1GBE_MAX 0x0d 230 #define XGBE_SFP_BASE_BR_10GBE_MIN 0x64 231 #define XGBE_SFP_BASE_BR_10GBE_MAX 0x68 232 233 #define XGBE_SFP_BASE_CU_CABLE_LEN 18 234 235 #define XGBE_SFP_BASE_VENDOR_NAME 20 236 #define XGBE_SFP_BASE_VENDOR_NAME_LEN 16 237 #define XGBE_SFP_BASE_VENDOR_PN 40 238 #define XGBE_SFP_BASE_VENDOR_PN_LEN 16 239 #define XGBE_SFP_BASE_VENDOR_REV 56 240 #define XGBE_SFP_BASE_VENDOR_REV_LEN 4 241 242 #define XGBE_SFP_BASE_CC 63 243 244 /* SFP Serial ID Extended ID values relative to an offset of 64 */ 245 #define XGBE_SFP_BASE_VENDOR_SN 4 246 #define XGBE_SFP_BASE_VENDOR_SN_LEN 16 247 248 #define XGBE_SFP_EXTD_DIAG 28 249 #define XGBE_SFP_EXTD_DIAG_ADDR_CHANGE BIT(2) 250 251 #define XGBE_SFP_EXTD_SFF_8472 30 252 253 #define XGBE_SFP_EXTD_CC 31 254 255 struct xgbe_sfp_eeprom { 256 u8 base[64]; 257 u8 extd[32]; 258 u8 vendor[32]; 259 }; 260 261 #define XGBE_BEL_FUSE_VENDOR "BEL-FUSE " 262 #define XGBE_BEL_FUSE_PARTNO "1GBT-SFP06 " 263 264 struct xgbe_sfp_ascii { 265 union { 266 char vendor[XGBE_SFP_BASE_VENDOR_NAME_LEN + 1]; 267 char partno[XGBE_SFP_BASE_VENDOR_PN_LEN + 1]; 268 char rev[XGBE_SFP_BASE_VENDOR_REV_LEN + 1]; 269 char serno[XGBE_SFP_BASE_VENDOR_SN_LEN + 1]; 270 } u; 271 }; 272 273 /* MDIO PHY reset types */ 274 enum xgbe_mdio_reset { 275 XGBE_MDIO_RESET_NONE = 0, 276 XGBE_MDIO_RESET_I2C_GPIO, 277 XGBE_MDIO_RESET_INT_GPIO, 278 XGBE_MDIO_RESET_MAX, 279 }; 280 281 /* Re-driver related definitions */ 282 enum xgbe_phy_redrv_if { 283 XGBE_PHY_REDRV_IF_MDIO = 0, 284 XGBE_PHY_REDRV_IF_I2C, 285 XGBE_PHY_REDRV_IF_MAX, 286 }; 287 288 enum xgbe_phy_redrv_model { 289 XGBE_PHY_REDRV_MODEL_4223 = 0, 290 XGBE_PHY_REDRV_MODEL_4227, 291 XGBE_PHY_REDRV_MODEL_MAX, 292 }; 293 294 enum xgbe_phy_redrv_mode { 295 XGBE_PHY_REDRV_MODE_CX = 5, 296 XGBE_PHY_REDRV_MODE_SR = 9, 297 }; 298 299 #define XGBE_PHY_REDRV_MODE_REG 0x12b0 300 301 /* PHY related configuration information */ 302 struct xgbe_phy_data { 303 enum xgbe_port_mode port_mode; 304 305 unsigned int port_id; 306 307 unsigned int port_speeds; 308 309 enum xgbe_conn_type conn_type; 310 311 enum xgbe_mode cur_mode; 312 enum xgbe_mode start_mode; 313 314 unsigned int rrc_count; 315 316 unsigned int mdio_addr; 317 318 unsigned int comm_owned; 319 320 /* SFP Support */ 321 enum xgbe_sfp_comm sfp_comm; 322 unsigned int sfp_mux_address; 323 unsigned int sfp_mux_channel; 324 325 unsigned int sfp_gpio_address; 326 unsigned int sfp_gpio_mask; 327 unsigned int sfp_gpio_rx_los; 328 unsigned int sfp_gpio_tx_fault; 329 unsigned int sfp_gpio_mod_absent; 330 unsigned int sfp_gpio_rate_select; 331 332 unsigned int sfp_rx_los; 333 unsigned int sfp_tx_fault; 334 unsigned int sfp_mod_absent; 335 unsigned int sfp_diags; 336 unsigned int sfp_changed; 337 unsigned int sfp_phy_avail; 338 unsigned int sfp_cable_len; 339 enum xgbe_sfp_base sfp_base; 340 enum xgbe_sfp_cable sfp_cable; 341 enum xgbe_sfp_speed sfp_speed; 342 struct xgbe_sfp_eeprom sfp_eeprom; 343 344 /* External PHY support */ 345 enum xgbe_mdio_mode phydev_mode; 346 struct mii_bus *mii; 347 struct phy_device *phydev; 348 enum xgbe_mdio_reset mdio_reset; 349 unsigned int mdio_reset_addr; 350 unsigned int mdio_reset_gpio; 351 352 /* Re-driver support */ 353 unsigned int redrv; 354 unsigned int redrv_if; 355 unsigned int redrv_addr; 356 unsigned int redrv_lane; 357 unsigned int redrv_model; 358 }; 359 360 /* I2C, MDIO and GPIO lines are muxed, so only one device at a time */ 361 static DEFINE_MUTEX(xgbe_phy_comm_lock); 362 363 static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata); 364 365 static int xgbe_phy_i2c_xfer(struct xgbe_prv_data *pdata, 366 struct xgbe_i2c_op *i2c_op) 367 { 368 struct xgbe_phy_data *phy_data = pdata->phy_data; 369 370 /* Be sure we own the bus */ 371 if (WARN_ON(!phy_data->comm_owned)) 372 return -EIO; 373 374 return pdata->i2c_if.i2c_xfer(pdata, i2c_op); 375 } 376 377 static int xgbe_phy_redrv_write(struct xgbe_prv_data *pdata, unsigned int reg, 378 unsigned int val) 379 { 380 struct xgbe_phy_data *phy_data = pdata->phy_data; 381 struct xgbe_i2c_op i2c_op; 382 __be16 *redrv_val; 383 u8 redrv_data[5], csum; 384 unsigned int i, retry; 385 int ret; 386 387 /* High byte of register contains read/write indicator */ 388 redrv_data[0] = ((reg >> 8) & 0xff) << 1; 389 redrv_data[1] = reg & 0xff; 390 redrv_val = (__be16 *)&redrv_data[2]; 391 *redrv_val = cpu_to_be16(val); 392 393 /* Calculate 1 byte checksum */ 394 csum = 0; 395 for (i = 0; i < 4; i++) { 396 csum += redrv_data[i]; 397 if (redrv_data[i] > csum) 398 csum++; 399 } 400 redrv_data[4] = ~csum; 401 402 retry = 1; 403 again1: 404 i2c_op.cmd = XGBE_I2C_CMD_WRITE; 405 i2c_op.target = phy_data->redrv_addr; 406 i2c_op.len = sizeof(redrv_data); 407 i2c_op.buf = redrv_data; 408 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op); 409 if (ret) { 410 if ((ret == -EAGAIN) && retry--) 411 goto again1; 412 413 return ret; 414 } 415 416 retry = 1; 417 again2: 418 i2c_op.cmd = XGBE_I2C_CMD_READ; 419 i2c_op.target = phy_data->redrv_addr; 420 i2c_op.len = 1; 421 i2c_op.buf = redrv_data; 422 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op); 423 if (ret) { 424 if ((ret == -EAGAIN) && retry--) 425 goto again2; 426 427 return ret; 428 } 429 430 if (redrv_data[0] != 0xff) { 431 netif_dbg(pdata, drv, pdata->netdev, 432 "Redriver write checksum error\n"); 433 ret = -EIO; 434 } 435 436 return ret; 437 } 438 439 static int xgbe_phy_i2c_write(struct xgbe_prv_data *pdata, unsigned int target, 440 void *val, unsigned int val_len) 441 { 442 struct xgbe_i2c_op i2c_op; 443 int retry, ret; 444 445 retry = 1; 446 again: 447 /* Write the specfied register */ 448 i2c_op.cmd = XGBE_I2C_CMD_WRITE; 449 i2c_op.target = target; 450 i2c_op.len = val_len; 451 i2c_op.buf = val; 452 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op); 453 if ((ret == -EAGAIN) && retry--) 454 goto again; 455 456 return ret; 457 } 458 459 static int xgbe_phy_i2c_read(struct xgbe_prv_data *pdata, unsigned int target, 460 void *reg, unsigned int reg_len, 461 void *val, unsigned int val_len) 462 { 463 struct xgbe_i2c_op i2c_op; 464 int retry, ret; 465 466 retry = 1; 467 again1: 468 /* Set the specified register to read */ 469 i2c_op.cmd = XGBE_I2C_CMD_WRITE; 470 i2c_op.target = target; 471 i2c_op.len = reg_len; 472 i2c_op.buf = reg; 473 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op); 474 if (ret) { 475 if ((ret == -EAGAIN) && retry--) 476 goto again1; 477 478 return ret; 479 } 480 481 retry = 1; 482 again2: 483 /* Read the specfied register */ 484 i2c_op.cmd = XGBE_I2C_CMD_READ; 485 i2c_op.target = target; 486 i2c_op.len = val_len; 487 i2c_op.buf = val; 488 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op); 489 if ((ret == -EAGAIN) && retry--) 490 goto again2; 491 492 return ret; 493 } 494 495 static int xgbe_phy_sfp_put_mux(struct xgbe_prv_data *pdata) 496 { 497 struct xgbe_phy_data *phy_data = pdata->phy_data; 498 struct xgbe_i2c_op i2c_op; 499 u8 mux_channel; 500 501 if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT) 502 return 0; 503 504 /* Select no mux channels */ 505 mux_channel = 0; 506 i2c_op.cmd = XGBE_I2C_CMD_WRITE; 507 i2c_op.target = phy_data->sfp_mux_address; 508 i2c_op.len = sizeof(mux_channel); 509 i2c_op.buf = &mux_channel; 510 511 return xgbe_phy_i2c_xfer(pdata, &i2c_op); 512 } 513 514 static int xgbe_phy_sfp_get_mux(struct xgbe_prv_data *pdata) 515 { 516 struct xgbe_phy_data *phy_data = pdata->phy_data; 517 struct xgbe_i2c_op i2c_op; 518 u8 mux_channel; 519 520 if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT) 521 return 0; 522 523 /* Select desired mux channel */ 524 mux_channel = 1 << phy_data->sfp_mux_channel; 525 i2c_op.cmd = XGBE_I2C_CMD_WRITE; 526 i2c_op.target = phy_data->sfp_mux_address; 527 i2c_op.len = sizeof(mux_channel); 528 i2c_op.buf = &mux_channel; 529 530 return xgbe_phy_i2c_xfer(pdata, &i2c_op); 531 } 532 533 static void xgbe_phy_put_comm_ownership(struct xgbe_prv_data *pdata) 534 { 535 struct xgbe_phy_data *phy_data = pdata->phy_data; 536 537 phy_data->comm_owned = 0; 538 539 mutex_unlock(&xgbe_phy_comm_lock); 540 } 541 542 static int xgbe_phy_get_comm_ownership(struct xgbe_prv_data *pdata) 543 { 544 struct xgbe_phy_data *phy_data = pdata->phy_data; 545 unsigned long timeout; 546 unsigned int mutex_id; 547 548 if (phy_data->comm_owned) 549 return 0; 550 551 /* The I2C and MDIO/GPIO bus is multiplexed between multiple devices, 552 * the driver needs to take the software mutex and then the hardware 553 * mutexes before being able to use the busses. 554 */ 555 mutex_lock(&xgbe_phy_comm_lock); 556 557 /* Clear the mutexes */ 558 XP_IOWRITE(pdata, XP_I2C_MUTEX, XGBE_MUTEX_RELEASE); 559 XP_IOWRITE(pdata, XP_MDIO_MUTEX, XGBE_MUTEX_RELEASE); 560 561 /* Mutex formats are the same for I2C and MDIO/GPIO */ 562 mutex_id = 0; 563 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ID, phy_data->port_id); 564 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ACTIVE, 1); 565 566 timeout = jiffies + (5 * HZ); 567 while (time_before(jiffies, timeout)) { 568 /* Must be all zeroes in order to obtain the mutex */ 569 if (XP_IOREAD(pdata, XP_I2C_MUTEX) || 570 XP_IOREAD(pdata, XP_MDIO_MUTEX)) { 571 usleep_range(100, 200); 572 continue; 573 } 574 575 /* Obtain the mutex */ 576 XP_IOWRITE(pdata, XP_I2C_MUTEX, mutex_id); 577 XP_IOWRITE(pdata, XP_MDIO_MUTEX, mutex_id); 578 579 phy_data->comm_owned = 1; 580 return 0; 581 } 582 583 mutex_unlock(&xgbe_phy_comm_lock); 584 585 netdev_err(pdata->netdev, "unable to obtain hardware mutexes\n"); 586 587 return -ETIMEDOUT; 588 } 589 590 static int xgbe_phy_mdio_mii_write(struct xgbe_prv_data *pdata, int addr, 591 int reg, u16 val) 592 { 593 struct xgbe_phy_data *phy_data = pdata->phy_data; 594 595 if (reg & MII_ADDR_C45) { 596 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45) 597 return -ENOTSUPP; 598 } else { 599 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22) 600 return -ENOTSUPP; 601 } 602 603 return pdata->hw_if.write_ext_mii_regs(pdata, addr, reg, val); 604 } 605 606 static int xgbe_phy_i2c_mii_write(struct xgbe_prv_data *pdata, int reg, u16 val) 607 { 608 __be16 *mii_val; 609 u8 mii_data[3]; 610 int ret; 611 612 ret = xgbe_phy_sfp_get_mux(pdata); 613 if (ret) 614 return ret; 615 616 mii_data[0] = reg & 0xff; 617 mii_val = (__be16 *)&mii_data[1]; 618 *mii_val = cpu_to_be16(val); 619 620 ret = xgbe_phy_i2c_write(pdata, XGBE_SFP_PHY_ADDRESS, 621 mii_data, sizeof(mii_data)); 622 623 xgbe_phy_sfp_put_mux(pdata); 624 625 return ret; 626 } 627 628 static int xgbe_phy_mii_write(struct mii_bus *mii, int addr, int reg, u16 val) 629 { 630 struct xgbe_prv_data *pdata = mii->priv; 631 struct xgbe_phy_data *phy_data = pdata->phy_data; 632 int ret; 633 634 ret = xgbe_phy_get_comm_ownership(pdata); 635 if (ret) 636 return ret; 637 638 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP) 639 ret = xgbe_phy_i2c_mii_write(pdata, reg, val); 640 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO) 641 ret = xgbe_phy_mdio_mii_write(pdata, addr, reg, val); 642 else 643 ret = -ENOTSUPP; 644 645 xgbe_phy_put_comm_ownership(pdata); 646 647 return ret; 648 } 649 650 static int xgbe_phy_mdio_mii_read(struct xgbe_prv_data *pdata, int addr, 651 int reg) 652 { 653 struct xgbe_phy_data *phy_data = pdata->phy_data; 654 655 if (reg & MII_ADDR_C45) { 656 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45) 657 return -ENOTSUPP; 658 } else { 659 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22) 660 return -ENOTSUPP; 661 } 662 663 return pdata->hw_if.read_ext_mii_regs(pdata, addr, reg); 664 } 665 666 static int xgbe_phy_i2c_mii_read(struct xgbe_prv_data *pdata, int reg) 667 { 668 __be16 mii_val; 669 u8 mii_reg; 670 int ret; 671 672 ret = xgbe_phy_sfp_get_mux(pdata); 673 if (ret) 674 return ret; 675 676 mii_reg = reg; 677 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_PHY_ADDRESS, 678 &mii_reg, sizeof(mii_reg), 679 &mii_val, sizeof(mii_val)); 680 if (!ret) 681 ret = be16_to_cpu(mii_val); 682 683 xgbe_phy_sfp_put_mux(pdata); 684 685 return ret; 686 } 687 688 static int xgbe_phy_mii_read(struct mii_bus *mii, int addr, int reg) 689 { 690 struct xgbe_prv_data *pdata = mii->priv; 691 struct xgbe_phy_data *phy_data = pdata->phy_data; 692 int ret; 693 694 ret = xgbe_phy_get_comm_ownership(pdata); 695 if (ret) 696 return ret; 697 698 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP) 699 ret = xgbe_phy_i2c_mii_read(pdata, reg); 700 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO) 701 ret = xgbe_phy_mdio_mii_read(pdata, addr, reg); 702 else 703 ret = -ENOTSUPP; 704 705 xgbe_phy_put_comm_ownership(pdata); 706 707 return ret; 708 } 709 710 static void xgbe_phy_sfp_phy_settings(struct xgbe_prv_data *pdata) 711 { 712 struct xgbe_phy_data *phy_data = pdata->phy_data; 713 714 if (!phy_data->sfp_mod_absent && !phy_data->sfp_changed) 715 return; 716 717 pdata->phy.supported &= ~SUPPORTED_Autoneg; 718 pdata->phy.supported &= ~(SUPPORTED_Pause | SUPPORTED_Asym_Pause); 719 pdata->phy.supported &= ~SUPPORTED_TP; 720 pdata->phy.supported &= ~SUPPORTED_FIBRE; 721 pdata->phy.supported &= ~SUPPORTED_100baseT_Full; 722 pdata->phy.supported &= ~SUPPORTED_1000baseT_Full; 723 pdata->phy.supported &= ~SUPPORTED_10000baseT_Full; 724 725 if (phy_data->sfp_mod_absent) { 726 pdata->phy.speed = SPEED_UNKNOWN; 727 pdata->phy.duplex = DUPLEX_UNKNOWN; 728 pdata->phy.autoneg = AUTONEG_ENABLE; 729 pdata->phy.pause_autoneg = AUTONEG_ENABLE; 730 731 pdata->phy.supported |= SUPPORTED_Autoneg; 732 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 733 pdata->phy.supported |= SUPPORTED_TP; 734 pdata->phy.supported |= SUPPORTED_FIBRE; 735 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) 736 pdata->phy.supported |= SUPPORTED_100baseT_Full; 737 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) 738 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 739 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) 740 pdata->phy.supported |= SUPPORTED_10000baseT_Full; 741 742 pdata->phy.advertising = pdata->phy.supported; 743 744 return; 745 } 746 747 switch (phy_data->sfp_base) { 748 case XGBE_SFP_BASE_1000_T: 749 case XGBE_SFP_BASE_1000_SX: 750 case XGBE_SFP_BASE_1000_LX: 751 case XGBE_SFP_BASE_1000_CX: 752 pdata->phy.speed = SPEED_UNKNOWN; 753 pdata->phy.duplex = DUPLEX_UNKNOWN; 754 pdata->phy.autoneg = AUTONEG_ENABLE; 755 pdata->phy.pause_autoneg = AUTONEG_ENABLE; 756 pdata->phy.supported |= SUPPORTED_Autoneg; 757 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 758 break; 759 case XGBE_SFP_BASE_10000_SR: 760 case XGBE_SFP_BASE_10000_LR: 761 case XGBE_SFP_BASE_10000_LRM: 762 case XGBE_SFP_BASE_10000_ER: 763 case XGBE_SFP_BASE_10000_CR: 764 pdata->phy.speed = SPEED_10000; 765 pdata->phy.duplex = DUPLEX_FULL; 766 pdata->phy.autoneg = AUTONEG_DISABLE; 767 pdata->phy.pause_autoneg = AUTONEG_DISABLE; 768 break; 769 default: 770 pdata->phy.speed = SPEED_UNKNOWN; 771 pdata->phy.duplex = DUPLEX_UNKNOWN; 772 pdata->phy.autoneg = AUTONEG_DISABLE; 773 pdata->phy.pause_autoneg = AUTONEG_DISABLE; 774 break; 775 } 776 777 switch (phy_data->sfp_base) { 778 case XGBE_SFP_BASE_1000_T: 779 case XGBE_SFP_BASE_1000_CX: 780 case XGBE_SFP_BASE_10000_CR: 781 pdata->phy.supported |= SUPPORTED_TP; 782 break; 783 default: 784 pdata->phy.supported |= SUPPORTED_FIBRE; 785 } 786 787 switch (phy_data->sfp_speed) { 788 case XGBE_SFP_SPEED_100_1000: 789 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) 790 pdata->phy.supported |= SUPPORTED_100baseT_Full; 791 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) 792 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 793 break; 794 case XGBE_SFP_SPEED_1000: 795 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) 796 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 797 break; 798 case XGBE_SFP_SPEED_10000: 799 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) 800 pdata->phy.supported |= SUPPORTED_10000baseT_Full; 801 break; 802 default: 803 /* Choose the fastest supported speed */ 804 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) 805 pdata->phy.supported |= SUPPORTED_10000baseT_Full; 806 else if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) 807 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 808 else if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) 809 pdata->phy.supported |= SUPPORTED_100baseT_Full; 810 } 811 812 pdata->phy.advertising = pdata->phy.supported; 813 } 814 815 static bool xgbe_phy_sfp_bit_rate(struct xgbe_sfp_eeprom *sfp_eeprom, 816 enum xgbe_sfp_speed sfp_speed) 817 { 818 u8 *sfp_base, min, max; 819 820 sfp_base = sfp_eeprom->base; 821 822 switch (sfp_speed) { 823 case XGBE_SFP_SPEED_1000: 824 min = XGBE_SFP_BASE_BR_1GBE_MIN; 825 max = XGBE_SFP_BASE_BR_1GBE_MAX; 826 break; 827 case XGBE_SFP_SPEED_10000: 828 min = XGBE_SFP_BASE_BR_10GBE_MIN; 829 max = XGBE_SFP_BASE_BR_10GBE_MAX; 830 break; 831 default: 832 return false; 833 } 834 835 return ((sfp_base[XGBE_SFP_BASE_BR] >= min) && 836 (sfp_base[XGBE_SFP_BASE_BR] <= max)); 837 } 838 839 static void xgbe_phy_free_phy_device(struct xgbe_prv_data *pdata) 840 { 841 struct xgbe_phy_data *phy_data = pdata->phy_data; 842 843 if (phy_data->phydev) { 844 phy_detach(phy_data->phydev); 845 phy_device_remove(phy_data->phydev); 846 phy_device_free(phy_data->phydev); 847 phy_data->phydev = NULL; 848 } 849 } 850 851 static bool xgbe_phy_finisar_phy_quirks(struct xgbe_prv_data *pdata) 852 { 853 struct xgbe_phy_data *phy_data = pdata->phy_data; 854 unsigned int phy_id = phy_data->phydev->phy_id; 855 856 if ((phy_id & 0xfffffff0) != 0x01ff0cc0) 857 return false; 858 859 /* Enable Base-T AN */ 860 phy_write(phy_data->phydev, 0x16, 0x0001); 861 phy_write(phy_data->phydev, 0x00, 0x9140); 862 phy_write(phy_data->phydev, 0x16, 0x0000); 863 864 /* Enable SGMII at 100Base-T/1000Base-T Full Duplex */ 865 phy_write(phy_data->phydev, 0x1b, 0x9084); 866 phy_write(phy_data->phydev, 0x09, 0x0e00); 867 phy_write(phy_data->phydev, 0x00, 0x8140); 868 phy_write(phy_data->phydev, 0x04, 0x0d01); 869 phy_write(phy_data->phydev, 0x00, 0x9140); 870 871 phy_data->phydev->supported = PHY_GBIT_FEATURES; 872 phy_data->phydev->supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 873 phy_data->phydev->advertising = phy_data->phydev->supported; 874 875 netif_dbg(pdata, drv, pdata->netdev, 876 "Finisar PHY quirk in place\n"); 877 878 return true; 879 } 880 881 static void xgbe_phy_external_phy_quirks(struct xgbe_prv_data *pdata) 882 { 883 if (xgbe_phy_finisar_phy_quirks(pdata)) 884 return; 885 } 886 887 static int xgbe_phy_find_phy_device(struct xgbe_prv_data *pdata) 888 { 889 struct xgbe_phy_data *phy_data = pdata->phy_data; 890 struct phy_device *phydev; 891 int ret; 892 893 /* If we already have a PHY, just return */ 894 if (phy_data->phydev) 895 return 0; 896 897 /* Check for the use of an external PHY */ 898 if (phy_data->phydev_mode == XGBE_MDIO_MODE_NONE) 899 return 0; 900 901 /* For SFP, only use an external PHY if available */ 902 if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) && 903 !phy_data->sfp_phy_avail) 904 return 0; 905 906 /* Set the proper MDIO mode for the PHY */ 907 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr, 908 phy_data->phydev_mode); 909 if (ret) { 910 netdev_err(pdata->netdev, 911 "mdio port/clause not compatible (%u/%u)\n", 912 phy_data->mdio_addr, phy_data->phydev_mode); 913 return ret; 914 } 915 916 /* Create and connect to the PHY device */ 917 phydev = get_phy_device(phy_data->mii, phy_data->mdio_addr, 918 (phy_data->phydev_mode == XGBE_MDIO_MODE_CL45)); 919 if (IS_ERR(phydev)) { 920 netdev_err(pdata->netdev, "get_phy_device failed\n"); 921 return -ENODEV; 922 } 923 netif_dbg(pdata, drv, pdata->netdev, "external PHY id is %#010x\n", 924 phydev->phy_id); 925 926 /*TODO: If c45, add request_module based on one of the MMD ids? */ 927 928 ret = phy_device_register(phydev); 929 if (ret) { 930 netdev_err(pdata->netdev, "phy_device_register failed\n"); 931 phy_device_free(phydev); 932 return ret; 933 } 934 935 ret = phy_attach_direct(pdata->netdev, phydev, phydev->dev_flags, 936 PHY_INTERFACE_MODE_SGMII); 937 if (ret) { 938 netdev_err(pdata->netdev, "phy_attach_direct failed\n"); 939 phy_device_remove(phydev); 940 phy_device_free(phydev); 941 return ret; 942 } 943 phy_data->phydev = phydev; 944 945 xgbe_phy_external_phy_quirks(pdata); 946 phydev->advertising &= pdata->phy.advertising; 947 948 phy_start_aneg(phy_data->phydev); 949 950 return 0; 951 } 952 953 static void xgbe_phy_sfp_external_phy(struct xgbe_prv_data *pdata) 954 { 955 struct xgbe_phy_data *phy_data = pdata->phy_data; 956 int ret; 957 958 if (!phy_data->sfp_changed) 959 return; 960 961 phy_data->sfp_phy_avail = 0; 962 963 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T) 964 return; 965 966 /* Check access to the PHY by reading CTRL1 */ 967 ret = xgbe_phy_i2c_mii_read(pdata, MII_BMCR); 968 if (ret < 0) 969 return; 970 971 /* Successfully accessed the PHY */ 972 phy_data->sfp_phy_avail = 1; 973 } 974 975 static bool xgbe_phy_belfuse_parse_quirks(struct xgbe_prv_data *pdata) 976 { 977 struct xgbe_phy_data *phy_data = pdata->phy_data; 978 struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom; 979 980 if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME], 981 XGBE_BEL_FUSE_VENDOR, XGBE_SFP_BASE_VENDOR_NAME_LEN)) 982 return false; 983 984 if (!memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN], 985 XGBE_BEL_FUSE_PARTNO, XGBE_SFP_BASE_VENDOR_PN_LEN)) { 986 phy_data->sfp_base = XGBE_SFP_BASE_1000_SX; 987 phy_data->sfp_cable = XGBE_SFP_CABLE_ACTIVE; 988 phy_data->sfp_speed = XGBE_SFP_SPEED_1000; 989 if (phy_data->sfp_changed) 990 netif_dbg(pdata, drv, pdata->netdev, 991 "Bel-Fuse SFP quirk in place\n"); 992 return true; 993 } 994 995 return false; 996 } 997 998 static bool xgbe_phy_sfp_parse_quirks(struct xgbe_prv_data *pdata) 999 { 1000 if (xgbe_phy_belfuse_parse_quirks(pdata)) 1001 return true; 1002 1003 return false; 1004 } 1005 1006 static void xgbe_phy_sfp_parse_eeprom(struct xgbe_prv_data *pdata) 1007 { 1008 struct xgbe_phy_data *phy_data = pdata->phy_data; 1009 struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom; 1010 u8 *sfp_base; 1011 1012 sfp_base = sfp_eeprom->base; 1013 1014 if (sfp_base[XGBE_SFP_BASE_ID] != XGBE_SFP_ID_SFP) 1015 return; 1016 1017 if (sfp_base[XGBE_SFP_BASE_EXT_ID] != XGBE_SFP_EXT_ID_SFP) 1018 return; 1019 1020 if (xgbe_phy_sfp_parse_quirks(pdata)) 1021 return; 1022 1023 /* Assume ACTIVE cable unless told it is PASSIVE */ 1024 if (sfp_base[XGBE_SFP_BASE_CABLE] & XGBE_SFP_BASE_CABLE_PASSIVE) { 1025 phy_data->sfp_cable = XGBE_SFP_CABLE_PASSIVE; 1026 phy_data->sfp_cable_len = sfp_base[XGBE_SFP_BASE_CU_CABLE_LEN]; 1027 } else { 1028 phy_data->sfp_cable = XGBE_SFP_CABLE_ACTIVE; 1029 } 1030 1031 /* Determine the type of SFP */ 1032 if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_SR) 1033 phy_data->sfp_base = XGBE_SFP_BASE_10000_SR; 1034 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LR) 1035 phy_data->sfp_base = XGBE_SFP_BASE_10000_LR; 1036 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LRM) 1037 phy_data->sfp_base = XGBE_SFP_BASE_10000_LRM; 1038 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_ER) 1039 phy_data->sfp_base = XGBE_SFP_BASE_10000_ER; 1040 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_SX) 1041 phy_data->sfp_base = XGBE_SFP_BASE_1000_SX; 1042 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_LX) 1043 phy_data->sfp_base = XGBE_SFP_BASE_1000_LX; 1044 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_CX) 1045 phy_data->sfp_base = XGBE_SFP_BASE_1000_CX; 1046 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_T) 1047 phy_data->sfp_base = XGBE_SFP_BASE_1000_T; 1048 else if ((phy_data->sfp_cable == XGBE_SFP_CABLE_PASSIVE) && 1049 xgbe_phy_sfp_bit_rate(sfp_eeprom, XGBE_SFP_SPEED_10000)) 1050 phy_data->sfp_base = XGBE_SFP_BASE_10000_CR; 1051 1052 switch (phy_data->sfp_base) { 1053 case XGBE_SFP_BASE_1000_T: 1054 phy_data->sfp_speed = XGBE_SFP_SPEED_100_1000; 1055 break; 1056 case XGBE_SFP_BASE_1000_SX: 1057 case XGBE_SFP_BASE_1000_LX: 1058 case XGBE_SFP_BASE_1000_CX: 1059 phy_data->sfp_speed = XGBE_SFP_SPEED_1000; 1060 break; 1061 case XGBE_SFP_BASE_10000_SR: 1062 case XGBE_SFP_BASE_10000_LR: 1063 case XGBE_SFP_BASE_10000_LRM: 1064 case XGBE_SFP_BASE_10000_ER: 1065 case XGBE_SFP_BASE_10000_CR: 1066 phy_data->sfp_speed = XGBE_SFP_SPEED_10000; 1067 break; 1068 default: 1069 break; 1070 } 1071 } 1072 1073 static void xgbe_phy_sfp_eeprom_info(struct xgbe_prv_data *pdata, 1074 struct xgbe_sfp_eeprom *sfp_eeprom) 1075 { 1076 struct xgbe_sfp_ascii sfp_ascii; 1077 char *sfp_data = (char *)&sfp_ascii; 1078 1079 netif_dbg(pdata, drv, pdata->netdev, "SFP detected:\n"); 1080 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME], 1081 XGBE_SFP_BASE_VENDOR_NAME_LEN); 1082 sfp_data[XGBE_SFP_BASE_VENDOR_NAME_LEN] = '\0'; 1083 netif_dbg(pdata, drv, pdata->netdev, " vendor: %s\n", 1084 sfp_data); 1085 1086 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN], 1087 XGBE_SFP_BASE_VENDOR_PN_LEN); 1088 sfp_data[XGBE_SFP_BASE_VENDOR_PN_LEN] = '\0'; 1089 netif_dbg(pdata, drv, pdata->netdev, " part number: %s\n", 1090 sfp_data); 1091 1092 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_REV], 1093 XGBE_SFP_BASE_VENDOR_REV_LEN); 1094 sfp_data[XGBE_SFP_BASE_VENDOR_REV_LEN] = '\0'; 1095 netif_dbg(pdata, drv, pdata->netdev, " revision level: %s\n", 1096 sfp_data); 1097 1098 memcpy(sfp_data, &sfp_eeprom->extd[XGBE_SFP_BASE_VENDOR_SN], 1099 XGBE_SFP_BASE_VENDOR_SN_LEN); 1100 sfp_data[XGBE_SFP_BASE_VENDOR_SN_LEN] = '\0'; 1101 netif_dbg(pdata, drv, pdata->netdev, " serial number: %s\n", 1102 sfp_data); 1103 } 1104 1105 static bool xgbe_phy_sfp_verify_eeprom(u8 cc_in, u8 *buf, unsigned int len) 1106 { 1107 u8 cc; 1108 1109 for (cc = 0; len; buf++, len--) 1110 cc += *buf; 1111 1112 return (cc == cc_in) ? true : false; 1113 } 1114 1115 static int xgbe_phy_sfp_read_eeprom(struct xgbe_prv_data *pdata) 1116 { 1117 struct xgbe_phy_data *phy_data = pdata->phy_data; 1118 struct xgbe_sfp_eeprom sfp_eeprom; 1119 u8 eeprom_addr; 1120 int ret; 1121 1122 ret = xgbe_phy_sfp_get_mux(pdata); 1123 if (ret) { 1124 dev_err_once(pdata->dev, "%s: I2C error setting SFP MUX\n", 1125 netdev_name(pdata->netdev)); 1126 return ret; 1127 } 1128 1129 /* Read the SFP serial ID eeprom */ 1130 eeprom_addr = 0; 1131 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_SERIAL_ID_ADDRESS, 1132 &eeprom_addr, sizeof(eeprom_addr), 1133 &sfp_eeprom, sizeof(sfp_eeprom)); 1134 if (ret) { 1135 dev_err_once(pdata->dev, "%s: I2C error reading SFP EEPROM\n", 1136 netdev_name(pdata->netdev)); 1137 goto put; 1138 } 1139 1140 /* Validate the contents read */ 1141 if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.base[XGBE_SFP_BASE_CC], 1142 sfp_eeprom.base, 1143 sizeof(sfp_eeprom.base) - 1)) { 1144 ret = -EINVAL; 1145 goto put; 1146 } 1147 1148 if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.extd[XGBE_SFP_EXTD_CC], 1149 sfp_eeprom.extd, 1150 sizeof(sfp_eeprom.extd) - 1)) { 1151 ret = -EINVAL; 1152 goto put; 1153 } 1154 1155 /* Check for an added or changed SFP */ 1156 if (memcmp(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom))) { 1157 phy_data->sfp_changed = 1; 1158 1159 if (netif_msg_drv(pdata)) 1160 xgbe_phy_sfp_eeprom_info(pdata, &sfp_eeprom); 1161 1162 memcpy(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom)); 1163 1164 if (sfp_eeprom.extd[XGBE_SFP_EXTD_SFF_8472]) { 1165 u8 diag_type = sfp_eeprom.extd[XGBE_SFP_EXTD_DIAG]; 1166 1167 if (!(diag_type & XGBE_SFP_EXTD_DIAG_ADDR_CHANGE)) 1168 phy_data->sfp_diags = 1; 1169 } 1170 1171 xgbe_phy_free_phy_device(pdata); 1172 } else { 1173 phy_data->sfp_changed = 0; 1174 } 1175 1176 put: 1177 xgbe_phy_sfp_put_mux(pdata); 1178 1179 return ret; 1180 } 1181 1182 static void xgbe_phy_sfp_signals(struct xgbe_prv_data *pdata) 1183 { 1184 struct xgbe_phy_data *phy_data = pdata->phy_data; 1185 unsigned int gpio_input; 1186 u8 gpio_reg, gpio_ports[2]; 1187 int ret; 1188 1189 /* Read the input port registers */ 1190 gpio_reg = 0; 1191 ret = xgbe_phy_i2c_read(pdata, phy_data->sfp_gpio_address, 1192 &gpio_reg, sizeof(gpio_reg), 1193 gpio_ports, sizeof(gpio_ports)); 1194 if (ret) { 1195 dev_err_once(pdata->dev, "%s: I2C error reading SFP GPIOs\n", 1196 netdev_name(pdata->netdev)); 1197 return; 1198 } 1199 1200 gpio_input = (gpio_ports[1] << 8) | gpio_ports[0]; 1201 1202 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_MOD_ABSENT) { 1203 /* No GPIO, just assume the module is present for now */ 1204 phy_data->sfp_mod_absent = 0; 1205 } else { 1206 if (!(gpio_input & (1 << phy_data->sfp_gpio_mod_absent))) 1207 phy_data->sfp_mod_absent = 0; 1208 } 1209 1210 if (!(phy_data->sfp_gpio_mask & XGBE_GPIO_NO_RX_LOS) && 1211 (gpio_input & (1 << phy_data->sfp_gpio_rx_los))) 1212 phy_data->sfp_rx_los = 1; 1213 1214 if (!(phy_data->sfp_gpio_mask & XGBE_GPIO_NO_TX_FAULT) && 1215 (gpio_input & (1 << phy_data->sfp_gpio_tx_fault))) 1216 phy_data->sfp_tx_fault = 1; 1217 } 1218 1219 static void xgbe_phy_sfp_mod_absent(struct xgbe_prv_data *pdata) 1220 { 1221 struct xgbe_phy_data *phy_data = pdata->phy_data; 1222 1223 xgbe_phy_free_phy_device(pdata); 1224 1225 phy_data->sfp_mod_absent = 1; 1226 phy_data->sfp_phy_avail = 0; 1227 memset(&phy_data->sfp_eeprom, 0, sizeof(phy_data->sfp_eeprom)); 1228 } 1229 1230 static void xgbe_phy_sfp_reset(struct xgbe_phy_data *phy_data) 1231 { 1232 phy_data->sfp_rx_los = 0; 1233 phy_data->sfp_tx_fault = 0; 1234 phy_data->sfp_mod_absent = 1; 1235 phy_data->sfp_diags = 0; 1236 phy_data->sfp_base = XGBE_SFP_BASE_UNKNOWN; 1237 phy_data->sfp_cable = XGBE_SFP_CABLE_UNKNOWN; 1238 phy_data->sfp_speed = XGBE_SFP_SPEED_UNKNOWN; 1239 } 1240 1241 static void xgbe_phy_sfp_detect(struct xgbe_prv_data *pdata) 1242 { 1243 struct xgbe_phy_data *phy_data = pdata->phy_data; 1244 int ret; 1245 1246 /* Reset the SFP signals and info */ 1247 xgbe_phy_sfp_reset(phy_data); 1248 1249 ret = xgbe_phy_get_comm_ownership(pdata); 1250 if (ret) 1251 return; 1252 1253 /* Read the SFP signals and check for module presence */ 1254 xgbe_phy_sfp_signals(pdata); 1255 if (phy_data->sfp_mod_absent) { 1256 xgbe_phy_sfp_mod_absent(pdata); 1257 goto put; 1258 } 1259 1260 ret = xgbe_phy_sfp_read_eeprom(pdata); 1261 if (ret) { 1262 /* Treat any error as if there isn't an SFP plugged in */ 1263 xgbe_phy_sfp_reset(phy_data); 1264 xgbe_phy_sfp_mod_absent(pdata); 1265 goto put; 1266 } 1267 1268 xgbe_phy_sfp_parse_eeprom(pdata); 1269 1270 xgbe_phy_sfp_external_phy(pdata); 1271 1272 put: 1273 xgbe_phy_sfp_phy_settings(pdata); 1274 1275 xgbe_phy_put_comm_ownership(pdata); 1276 } 1277 1278 static void xgbe_phy_phydev_flowctrl(struct xgbe_prv_data *pdata) 1279 { 1280 struct xgbe_phy_data *phy_data = pdata->phy_data; 1281 u16 lcl_adv = 0, rmt_adv = 0; 1282 u8 fc; 1283 1284 pdata->phy.tx_pause = 0; 1285 pdata->phy.rx_pause = 0; 1286 1287 if (!phy_data->phydev) 1288 return; 1289 1290 if (phy_data->phydev->advertising & ADVERTISED_Pause) 1291 lcl_adv |= ADVERTISE_PAUSE_CAP; 1292 if (phy_data->phydev->advertising & ADVERTISED_Asym_Pause) 1293 lcl_adv |= ADVERTISE_PAUSE_ASYM; 1294 1295 if (phy_data->phydev->pause) { 1296 pdata->phy.lp_advertising |= ADVERTISED_Pause; 1297 rmt_adv |= LPA_PAUSE_CAP; 1298 } 1299 if (phy_data->phydev->asym_pause) { 1300 pdata->phy.lp_advertising |= ADVERTISED_Asym_Pause; 1301 rmt_adv |= LPA_PAUSE_ASYM; 1302 } 1303 1304 fc = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv); 1305 if (fc & FLOW_CTRL_TX) 1306 pdata->phy.tx_pause = 1; 1307 if (fc & FLOW_CTRL_RX) 1308 pdata->phy.rx_pause = 1; 1309 } 1310 1311 static enum xgbe_mode xgbe_phy_an37_sgmii_outcome(struct xgbe_prv_data *pdata) 1312 { 1313 enum xgbe_mode mode; 1314 1315 pdata->phy.lp_advertising |= ADVERTISED_Autoneg; 1316 pdata->phy.lp_advertising |= ADVERTISED_TP; 1317 1318 /* Use external PHY to determine flow control */ 1319 if (pdata->phy.pause_autoneg) 1320 xgbe_phy_phydev_flowctrl(pdata); 1321 1322 switch (pdata->an_status & XGBE_SGMII_AN_LINK_SPEED) { 1323 case XGBE_SGMII_AN_LINK_SPEED_100: 1324 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) { 1325 pdata->phy.lp_advertising |= ADVERTISED_100baseT_Full; 1326 mode = XGBE_MODE_SGMII_100; 1327 } else { 1328 /* Half-duplex not supported */ 1329 pdata->phy.lp_advertising |= ADVERTISED_100baseT_Half; 1330 mode = XGBE_MODE_UNKNOWN; 1331 } 1332 break; 1333 case XGBE_SGMII_AN_LINK_SPEED_1000: 1334 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) { 1335 pdata->phy.lp_advertising |= ADVERTISED_1000baseT_Full; 1336 mode = XGBE_MODE_SGMII_1000; 1337 } else { 1338 /* Half-duplex not supported */ 1339 pdata->phy.lp_advertising |= ADVERTISED_1000baseT_Half; 1340 mode = XGBE_MODE_UNKNOWN; 1341 } 1342 break; 1343 default: 1344 mode = XGBE_MODE_UNKNOWN; 1345 } 1346 1347 return mode; 1348 } 1349 1350 static enum xgbe_mode xgbe_phy_an37_outcome(struct xgbe_prv_data *pdata) 1351 { 1352 enum xgbe_mode mode; 1353 unsigned int ad_reg, lp_reg; 1354 1355 pdata->phy.lp_advertising |= ADVERTISED_Autoneg; 1356 pdata->phy.lp_advertising |= ADVERTISED_FIBRE; 1357 1358 /* Compare Advertisement and Link Partner register */ 1359 ad_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE); 1360 lp_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_LP_ABILITY); 1361 if (lp_reg & 0x100) 1362 pdata->phy.lp_advertising |= ADVERTISED_Pause; 1363 if (lp_reg & 0x80) 1364 pdata->phy.lp_advertising |= ADVERTISED_Asym_Pause; 1365 1366 if (pdata->phy.pause_autoneg) { 1367 /* Set flow control based on auto-negotiation result */ 1368 pdata->phy.tx_pause = 0; 1369 pdata->phy.rx_pause = 0; 1370 1371 if (ad_reg & lp_reg & 0x100) { 1372 pdata->phy.tx_pause = 1; 1373 pdata->phy.rx_pause = 1; 1374 } else if (ad_reg & lp_reg & 0x80) { 1375 if (ad_reg & 0x100) 1376 pdata->phy.rx_pause = 1; 1377 else if (lp_reg & 0x100) 1378 pdata->phy.tx_pause = 1; 1379 } 1380 } 1381 1382 if (lp_reg & 0x40) 1383 pdata->phy.lp_advertising |= ADVERTISED_1000baseT_Half; 1384 if (lp_reg & 0x20) 1385 pdata->phy.lp_advertising |= ADVERTISED_1000baseT_Full; 1386 1387 /* Half duplex is not supported */ 1388 ad_reg &= lp_reg; 1389 mode = (ad_reg & 0x20) ? XGBE_MODE_X : XGBE_MODE_UNKNOWN; 1390 1391 return mode; 1392 } 1393 1394 static enum xgbe_mode xgbe_phy_an73_redrv_outcome(struct xgbe_prv_data *pdata) 1395 { 1396 struct xgbe_phy_data *phy_data = pdata->phy_data; 1397 enum xgbe_mode mode; 1398 unsigned int ad_reg, lp_reg; 1399 1400 pdata->phy.lp_advertising |= ADVERTISED_Autoneg; 1401 pdata->phy.lp_advertising |= ADVERTISED_Backplane; 1402 1403 /* Use external PHY to determine flow control */ 1404 if (pdata->phy.pause_autoneg) 1405 xgbe_phy_phydev_flowctrl(pdata); 1406 1407 /* Compare Advertisement and Link Partner register 2 */ 1408 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); 1409 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); 1410 if (lp_reg & 0x80) 1411 pdata->phy.lp_advertising |= ADVERTISED_10000baseKR_Full; 1412 if (lp_reg & 0x20) 1413 pdata->phy.lp_advertising |= ADVERTISED_1000baseKX_Full; 1414 1415 ad_reg &= lp_reg; 1416 if (ad_reg & 0x80) { 1417 switch (phy_data->port_mode) { 1418 case XGBE_PORT_MODE_BACKPLANE: 1419 mode = XGBE_MODE_KR; 1420 break; 1421 default: 1422 mode = XGBE_MODE_SFI; 1423 break; 1424 } 1425 } else if (ad_reg & 0x20) { 1426 switch (phy_data->port_mode) { 1427 case XGBE_PORT_MODE_BACKPLANE: 1428 mode = XGBE_MODE_KX_1000; 1429 break; 1430 case XGBE_PORT_MODE_1000BASE_X: 1431 mode = XGBE_MODE_X; 1432 break; 1433 case XGBE_PORT_MODE_SFP: 1434 switch (phy_data->sfp_base) { 1435 case XGBE_SFP_BASE_1000_T: 1436 if (phy_data->phydev && 1437 (phy_data->phydev->speed == SPEED_100)) 1438 mode = XGBE_MODE_SGMII_100; 1439 else 1440 mode = XGBE_MODE_SGMII_1000; 1441 break; 1442 case XGBE_SFP_BASE_1000_SX: 1443 case XGBE_SFP_BASE_1000_LX: 1444 case XGBE_SFP_BASE_1000_CX: 1445 default: 1446 mode = XGBE_MODE_X; 1447 break; 1448 } 1449 break; 1450 default: 1451 if (phy_data->phydev && 1452 (phy_data->phydev->speed == SPEED_100)) 1453 mode = XGBE_MODE_SGMII_100; 1454 else 1455 mode = XGBE_MODE_SGMII_1000; 1456 break; 1457 } 1458 } else { 1459 mode = XGBE_MODE_UNKNOWN; 1460 } 1461 1462 /* Compare Advertisement and Link Partner register 3 */ 1463 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); 1464 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); 1465 if (lp_reg & 0xc000) 1466 pdata->phy.lp_advertising |= ADVERTISED_10000baseR_FEC; 1467 1468 return mode; 1469 } 1470 1471 static enum xgbe_mode xgbe_phy_an73_outcome(struct xgbe_prv_data *pdata) 1472 { 1473 enum xgbe_mode mode; 1474 unsigned int ad_reg, lp_reg; 1475 1476 pdata->phy.lp_advertising |= ADVERTISED_Autoneg; 1477 pdata->phy.lp_advertising |= ADVERTISED_Backplane; 1478 1479 /* Compare Advertisement and Link Partner register 1 */ 1480 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE); 1481 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA); 1482 if (lp_reg & 0x400) 1483 pdata->phy.lp_advertising |= ADVERTISED_Pause; 1484 if (lp_reg & 0x800) 1485 pdata->phy.lp_advertising |= ADVERTISED_Asym_Pause; 1486 1487 if (pdata->phy.pause_autoneg) { 1488 /* Set flow control based on auto-negotiation result */ 1489 pdata->phy.tx_pause = 0; 1490 pdata->phy.rx_pause = 0; 1491 1492 if (ad_reg & lp_reg & 0x400) { 1493 pdata->phy.tx_pause = 1; 1494 pdata->phy.rx_pause = 1; 1495 } else if (ad_reg & lp_reg & 0x800) { 1496 if (ad_reg & 0x400) 1497 pdata->phy.rx_pause = 1; 1498 else if (lp_reg & 0x400) 1499 pdata->phy.tx_pause = 1; 1500 } 1501 } 1502 1503 /* Compare Advertisement and Link Partner register 2 */ 1504 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); 1505 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); 1506 if (lp_reg & 0x80) 1507 pdata->phy.lp_advertising |= ADVERTISED_10000baseKR_Full; 1508 if (lp_reg & 0x20) 1509 pdata->phy.lp_advertising |= ADVERTISED_1000baseKX_Full; 1510 1511 ad_reg &= lp_reg; 1512 if (ad_reg & 0x80) 1513 mode = XGBE_MODE_KR; 1514 else if (ad_reg & 0x20) 1515 mode = XGBE_MODE_KX_1000; 1516 else 1517 mode = XGBE_MODE_UNKNOWN; 1518 1519 /* Compare Advertisement and Link Partner register 3 */ 1520 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); 1521 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); 1522 if (lp_reg & 0xc000) 1523 pdata->phy.lp_advertising |= ADVERTISED_10000baseR_FEC; 1524 1525 return mode; 1526 } 1527 1528 static enum xgbe_mode xgbe_phy_an_outcome(struct xgbe_prv_data *pdata) 1529 { 1530 switch (pdata->an_mode) { 1531 case XGBE_AN_MODE_CL73: 1532 return xgbe_phy_an73_outcome(pdata); 1533 case XGBE_AN_MODE_CL73_REDRV: 1534 return xgbe_phy_an73_redrv_outcome(pdata); 1535 case XGBE_AN_MODE_CL37: 1536 return xgbe_phy_an37_outcome(pdata); 1537 case XGBE_AN_MODE_CL37_SGMII: 1538 return xgbe_phy_an37_sgmii_outcome(pdata); 1539 default: 1540 return XGBE_MODE_UNKNOWN; 1541 } 1542 } 1543 1544 static unsigned int xgbe_phy_an_advertising(struct xgbe_prv_data *pdata) 1545 { 1546 struct xgbe_phy_data *phy_data = pdata->phy_data; 1547 unsigned int advertising; 1548 1549 /* Without a re-driver, just return current advertising */ 1550 if (!phy_data->redrv) 1551 return pdata->phy.advertising; 1552 1553 /* With the KR re-driver we need to advertise a single speed */ 1554 advertising = pdata->phy.advertising; 1555 advertising &= ~ADVERTISED_1000baseKX_Full; 1556 advertising &= ~ADVERTISED_10000baseKR_Full; 1557 1558 switch (phy_data->port_mode) { 1559 case XGBE_PORT_MODE_BACKPLANE: 1560 advertising |= ADVERTISED_10000baseKR_Full; 1561 break; 1562 case XGBE_PORT_MODE_BACKPLANE_2500: 1563 advertising |= ADVERTISED_1000baseKX_Full; 1564 break; 1565 case XGBE_PORT_MODE_1000BASE_T: 1566 case XGBE_PORT_MODE_1000BASE_X: 1567 case XGBE_PORT_MODE_NBASE_T: 1568 advertising |= ADVERTISED_1000baseKX_Full; 1569 break; 1570 case XGBE_PORT_MODE_10GBASE_T: 1571 if (phy_data->phydev && 1572 (phy_data->phydev->speed == SPEED_10000)) 1573 advertising |= ADVERTISED_10000baseKR_Full; 1574 else 1575 advertising |= ADVERTISED_1000baseKX_Full; 1576 break; 1577 case XGBE_PORT_MODE_10GBASE_R: 1578 advertising |= ADVERTISED_10000baseKR_Full; 1579 break; 1580 case XGBE_PORT_MODE_SFP: 1581 switch (phy_data->sfp_base) { 1582 case XGBE_SFP_BASE_1000_T: 1583 case XGBE_SFP_BASE_1000_SX: 1584 case XGBE_SFP_BASE_1000_LX: 1585 case XGBE_SFP_BASE_1000_CX: 1586 advertising |= ADVERTISED_1000baseKX_Full; 1587 break; 1588 default: 1589 advertising |= ADVERTISED_10000baseKR_Full; 1590 break; 1591 } 1592 break; 1593 default: 1594 advertising |= ADVERTISED_10000baseKR_Full; 1595 break; 1596 } 1597 1598 return advertising; 1599 } 1600 1601 static int xgbe_phy_an_config(struct xgbe_prv_data *pdata) 1602 { 1603 struct xgbe_phy_data *phy_data = pdata->phy_data; 1604 int ret; 1605 1606 ret = xgbe_phy_find_phy_device(pdata); 1607 if (ret) 1608 return ret; 1609 1610 if (!phy_data->phydev) 1611 return 0; 1612 1613 phy_data->phydev->autoneg = pdata->phy.autoneg; 1614 phy_data->phydev->advertising = phy_data->phydev->supported & 1615 pdata->phy.advertising; 1616 1617 if (pdata->phy.autoneg != AUTONEG_ENABLE) { 1618 phy_data->phydev->speed = pdata->phy.speed; 1619 phy_data->phydev->duplex = pdata->phy.duplex; 1620 } 1621 1622 ret = phy_start_aneg(phy_data->phydev); 1623 1624 return ret; 1625 } 1626 1627 static enum xgbe_an_mode xgbe_phy_an_sfp_mode(struct xgbe_phy_data *phy_data) 1628 { 1629 switch (phy_data->sfp_base) { 1630 case XGBE_SFP_BASE_1000_T: 1631 return XGBE_AN_MODE_CL37_SGMII; 1632 case XGBE_SFP_BASE_1000_SX: 1633 case XGBE_SFP_BASE_1000_LX: 1634 case XGBE_SFP_BASE_1000_CX: 1635 return XGBE_AN_MODE_CL37; 1636 default: 1637 return XGBE_AN_MODE_NONE; 1638 } 1639 } 1640 1641 static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata) 1642 { 1643 struct xgbe_phy_data *phy_data = pdata->phy_data; 1644 1645 /* A KR re-driver will always require CL73 AN */ 1646 if (phy_data->redrv) 1647 return XGBE_AN_MODE_CL73_REDRV; 1648 1649 switch (phy_data->port_mode) { 1650 case XGBE_PORT_MODE_BACKPLANE: 1651 return XGBE_AN_MODE_CL73; 1652 case XGBE_PORT_MODE_BACKPLANE_2500: 1653 return XGBE_AN_MODE_NONE; 1654 case XGBE_PORT_MODE_1000BASE_T: 1655 return XGBE_AN_MODE_CL37_SGMII; 1656 case XGBE_PORT_MODE_1000BASE_X: 1657 return XGBE_AN_MODE_CL37; 1658 case XGBE_PORT_MODE_NBASE_T: 1659 return XGBE_AN_MODE_CL37_SGMII; 1660 case XGBE_PORT_MODE_10GBASE_T: 1661 return XGBE_AN_MODE_CL73; 1662 case XGBE_PORT_MODE_10GBASE_R: 1663 return XGBE_AN_MODE_NONE; 1664 case XGBE_PORT_MODE_SFP: 1665 return xgbe_phy_an_sfp_mode(phy_data); 1666 default: 1667 return XGBE_AN_MODE_NONE; 1668 } 1669 } 1670 1671 static int xgbe_phy_set_redrv_mode_mdio(struct xgbe_prv_data *pdata, 1672 enum xgbe_phy_redrv_mode mode) 1673 { 1674 struct xgbe_phy_data *phy_data = pdata->phy_data; 1675 u16 redrv_reg, redrv_val; 1676 1677 redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000); 1678 redrv_val = (u16)mode; 1679 1680 return pdata->hw_if.write_ext_mii_regs(pdata, phy_data->redrv_addr, 1681 redrv_reg, redrv_val); 1682 } 1683 1684 static int xgbe_phy_set_redrv_mode_i2c(struct xgbe_prv_data *pdata, 1685 enum xgbe_phy_redrv_mode mode) 1686 { 1687 struct xgbe_phy_data *phy_data = pdata->phy_data; 1688 unsigned int redrv_reg; 1689 int ret; 1690 1691 /* Calculate the register to write */ 1692 redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000); 1693 1694 ret = xgbe_phy_redrv_write(pdata, redrv_reg, mode); 1695 1696 return ret; 1697 } 1698 1699 static void xgbe_phy_set_redrv_mode(struct xgbe_prv_data *pdata) 1700 { 1701 struct xgbe_phy_data *phy_data = pdata->phy_data; 1702 enum xgbe_phy_redrv_mode mode; 1703 int ret; 1704 1705 if (!phy_data->redrv) 1706 return; 1707 1708 mode = XGBE_PHY_REDRV_MODE_CX; 1709 if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) && 1710 (phy_data->sfp_base != XGBE_SFP_BASE_1000_CX) && 1711 (phy_data->sfp_base != XGBE_SFP_BASE_10000_CR)) 1712 mode = XGBE_PHY_REDRV_MODE_SR; 1713 1714 ret = xgbe_phy_get_comm_ownership(pdata); 1715 if (ret) 1716 return; 1717 1718 if (phy_data->redrv_if) 1719 xgbe_phy_set_redrv_mode_i2c(pdata, mode); 1720 else 1721 xgbe_phy_set_redrv_mode_mdio(pdata, mode); 1722 1723 xgbe_phy_put_comm_ownership(pdata); 1724 } 1725 1726 static void xgbe_phy_perform_ratechange(struct xgbe_prv_data *pdata, 1727 unsigned int cmd, unsigned int sub_cmd) 1728 { 1729 unsigned int s0 = 0; 1730 unsigned int wait; 1731 1732 /* Log if a previous command did not complete */ 1733 if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) 1734 netif_dbg(pdata, link, pdata->netdev, 1735 "firmware mailbox not ready for command\n"); 1736 1737 /* Construct the command */ 1738 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, cmd); 1739 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, sub_cmd); 1740 1741 /* Issue the command */ 1742 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0); 1743 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0); 1744 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1); 1745 1746 /* Wait for command to complete */ 1747 wait = XGBE_RATECHANGE_COUNT; 1748 while (wait--) { 1749 if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) 1750 return; 1751 1752 usleep_range(1000, 2000); 1753 } 1754 1755 netif_dbg(pdata, link, pdata->netdev, 1756 "firmware mailbox command did not complete\n"); 1757 } 1758 1759 static void xgbe_phy_rrc(struct xgbe_prv_data *pdata) 1760 { 1761 /* Receiver Reset Cycle */ 1762 xgbe_phy_perform_ratechange(pdata, 5, 0); 1763 1764 netif_dbg(pdata, link, pdata->netdev, "receiver reset complete\n"); 1765 } 1766 1767 static void xgbe_phy_power_off(struct xgbe_prv_data *pdata) 1768 { 1769 struct xgbe_phy_data *phy_data = pdata->phy_data; 1770 1771 /* Power off */ 1772 xgbe_phy_perform_ratechange(pdata, 0, 0); 1773 1774 phy_data->cur_mode = XGBE_MODE_UNKNOWN; 1775 1776 netif_dbg(pdata, link, pdata->netdev, "phy powered off\n"); 1777 } 1778 1779 static void xgbe_phy_sfi_mode(struct xgbe_prv_data *pdata) 1780 { 1781 struct xgbe_phy_data *phy_data = pdata->phy_data; 1782 1783 xgbe_phy_set_redrv_mode(pdata); 1784 1785 /* 10G/SFI */ 1786 if (phy_data->sfp_cable != XGBE_SFP_CABLE_PASSIVE) { 1787 xgbe_phy_perform_ratechange(pdata, 3, 0); 1788 } else { 1789 if (phy_data->sfp_cable_len <= 1) 1790 xgbe_phy_perform_ratechange(pdata, 3, 1); 1791 else if (phy_data->sfp_cable_len <= 3) 1792 xgbe_phy_perform_ratechange(pdata, 3, 2); 1793 else 1794 xgbe_phy_perform_ratechange(pdata, 3, 3); 1795 } 1796 1797 phy_data->cur_mode = XGBE_MODE_SFI; 1798 1799 netif_dbg(pdata, link, pdata->netdev, "10GbE SFI mode set\n"); 1800 } 1801 1802 static void xgbe_phy_x_mode(struct xgbe_prv_data *pdata) 1803 { 1804 struct xgbe_phy_data *phy_data = pdata->phy_data; 1805 1806 xgbe_phy_set_redrv_mode(pdata); 1807 1808 /* 1G/X */ 1809 xgbe_phy_perform_ratechange(pdata, 1, 3); 1810 1811 phy_data->cur_mode = XGBE_MODE_X; 1812 1813 netif_dbg(pdata, link, pdata->netdev, "1GbE X mode set\n"); 1814 } 1815 1816 static void xgbe_phy_sgmii_1000_mode(struct xgbe_prv_data *pdata) 1817 { 1818 struct xgbe_phy_data *phy_data = pdata->phy_data; 1819 1820 xgbe_phy_set_redrv_mode(pdata); 1821 1822 /* 1G/SGMII */ 1823 xgbe_phy_perform_ratechange(pdata, 1, 2); 1824 1825 phy_data->cur_mode = XGBE_MODE_SGMII_1000; 1826 1827 netif_dbg(pdata, link, pdata->netdev, "1GbE SGMII mode set\n"); 1828 } 1829 1830 static void xgbe_phy_sgmii_100_mode(struct xgbe_prv_data *pdata) 1831 { 1832 struct xgbe_phy_data *phy_data = pdata->phy_data; 1833 1834 xgbe_phy_set_redrv_mode(pdata); 1835 1836 /* 100M/SGMII */ 1837 xgbe_phy_perform_ratechange(pdata, 1, 1); 1838 1839 phy_data->cur_mode = XGBE_MODE_SGMII_100; 1840 1841 netif_dbg(pdata, link, pdata->netdev, "100MbE SGMII mode set\n"); 1842 } 1843 1844 static void xgbe_phy_kr_mode(struct xgbe_prv_data *pdata) 1845 { 1846 struct xgbe_phy_data *phy_data = pdata->phy_data; 1847 1848 xgbe_phy_set_redrv_mode(pdata); 1849 1850 /* 10G/KR */ 1851 xgbe_phy_perform_ratechange(pdata, 4, 0); 1852 1853 phy_data->cur_mode = XGBE_MODE_KR; 1854 1855 netif_dbg(pdata, link, pdata->netdev, "10GbE KR mode set\n"); 1856 } 1857 1858 static void xgbe_phy_kx_2500_mode(struct xgbe_prv_data *pdata) 1859 { 1860 struct xgbe_phy_data *phy_data = pdata->phy_data; 1861 1862 xgbe_phy_set_redrv_mode(pdata); 1863 1864 /* 2.5G/KX */ 1865 xgbe_phy_perform_ratechange(pdata, 2, 0); 1866 1867 phy_data->cur_mode = XGBE_MODE_KX_2500; 1868 1869 netif_dbg(pdata, link, pdata->netdev, "2.5GbE KX mode set\n"); 1870 } 1871 1872 static void xgbe_phy_kx_1000_mode(struct xgbe_prv_data *pdata) 1873 { 1874 struct xgbe_phy_data *phy_data = pdata->phy_data; 1875 1876 xgbe_phy_set_redrv_mode(pdata); 1877 1878 /* 1G/KX */ 1879 xgbe_phy_perform_ratechange(pdata, 1, 3); 1880 1881 phy_data->cur_mode = XGBE_MODE_KX_1000; 1882 1883 netif_dbg(pdata, link, pdata->netdev, "1GbE KX mode set\n"); 1884 } 1885 1886 static enum xgbe_mode xgbe_phy_cur_mode(struct xgbe_prv_data *pdata) 1887 { 1888 struct xgbe_phy_data *phy_data = pdata->phy_data; 1889 1890 return phy_data->cur_mode; 1891 } 1892 1893 static enum xgbe_mode xgbe_phy_switch_baset_mode(struct xgbe_prv_data *pdata) 1894 { 1895 struct xgbe_phy_data *phy_data = pdata->phy_data; 1896 1897 /* No switching if not 10GBase-T */ 1898 if (phy_data->port_mode != XGBE_PORT_MODE_10GBASE_T) 1899 return xgbe_phy_cur_mode(pdata); 1900 1901 switch (xgbe_phy_cur_mode(pdata)) { 1902 case XGBE_MODE_SGMII_100: 1903 case XGBE_MODE_SGMII_1000: 1904 return XGBE_MODE_KR; 1905 case XGBE_MODE_KR: 1906 default: 1907 return XGBE_MODE_SGMII_1000; 1908 } 1909 } 1910 1911 static enum xgbe_mode xgbe_phy_switch_bp_2500_mode(struct xgbe_prv_data *pdata) 1912 { 1913 return XGBE_MODE_KX_2500; 1914 } 1915 1916 static enum xgbe_mode xgbe_phy_switch_bp_mode(struct xgbe_prv_data *pdata) 1917 { 1918 /* If we are in KR switch to KX, and vice-versa */ 1919 switch (xgbe_phy_cur_mode(pdata)) { 1920 case XGBE_MODE_KX_1000: 1921 return XGBE_MODE_KR; 1922 case XGBE_MODE_KR: 1923 default: 1924 return XGBE_MODE_KX_1000; 1925 } 1926 } 1927 1928 static enum xgbe_mode xgbe_phy_switch_mode(struct xgbe_prv_data *pdata) 1929 { 1930 struct xgbe_phy_data *phy_data = pdata->phy_data; 1931 1932 switch (phy_data->port_mode) { 1933 case XGBE_PORT_MODE_BACKPLANE: 1934 return xgbe_phy_switch_bp_mode(pdata); 1935 case XGBE_PORT_MODE_BACKPLANE_2500: 1936 return xgbe_phy_switch_bp_2500_mode(pdata); 1937 case XGBE_PORT_MODE_1000BASE_T: 1938 case XGBE_PORT_MODE_NBASE_T: 1939 case XGBE_PORT_MODE_10GBASE_T: 1940 return xgbe_phy_switch_baset_mode(pdata); 1941 case XGBE_PORT_MODE_1000BASE_X: 1942 case XGBE_PORT_MODE_10GBASE_R: 1943 case XGBE_PORT_MODE_SFP: 1944 /* No switching, so just return current mode */ 1945 return xgbe_phy_cur_mode(pdata); 1946 default: 1947 return XGBE_MODE_UNKNOWN; 1948 } 1949 } 1950 1951 static enum xgbe_mode xgbe_phy_get_basex_mode(struct xgbe_phy_data *phy_data, 1952 int speed) 1953 { 1954 switch (speed) { 1955 case SPEED_1000: 1956 return XGBE_MODE_X; 1957 case SPEED_10000: 1958 return XGBE_MODE_KR; 1959 default: 1960 return XGBE_MODE_UNKNOWN; 1961 } 1962 } 1963 1964 static enum xgbe_mode xgbe_phy_get_baset_mode(struct xgbe_phy_data *phy_data, 1965 int speed) 1966 { 1967 switch (speed) { 1968 case SPEED_100: 1969 return XGBE_MODE_SGMII_100; 1970 case SPEED_1000: 1971 return XGBE_MODE_SGMII_1000; 1972 case SPEED_2500: 1973 return XGBE_MODE_KX_2500; 1974 case SPEED_10000: 1975 return XGBE_MODE_KR; 1976 default: 1977 return XGBE_MODE_UNKNOWN; 1978 } 1979 } 1980 1981 static enum xgbe_mode xgbe_phy_get_sfp_mode(struct xgbe_phy_data *phy_data, 1982 int speed) 1983 { 1984 switch (speed) { 1985 case SPEED_100: 1986 return XGBE_MODE_SGMII_100; 1987 case SPEED_1000: 1988 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T) 1989 return XGBE_MODE_SGMII_1000; 1990 else 1991 return XGBE_MODE_X; 1992 case SPEED_10000: 1993 case SPEED_UNKNOWN: 1994 return XGBE_MODE_SFI; 1995 default: 1996 return XGBE_MODE_UNKNOWN; 1997 } 1998 } 1999 2000 static enum xgbe_mode xgbe_phy_get_bp_2500_mode(int speed) 2001 { 2002 switch (speed) { 2003 case SPEED_2500: 2004 return XGBE_MODE_KX_2500; 2005 default: 2006 return XGBE_MODE_UNKNOWN; 2007 } 2008 } 2009 2010 static enum xgbe_mode xgbe_phy_get_bp_mode(int speed) 2011 { 2012 switch (speed) { 2013 case SPEED_1000: 2014 return XGBE_MODE_KX_1000; 2015 case SPEED_10000: 2016 return XGBE_MODE_KR; 2017 default: 2018 return XGBE_MODE_UNKNOWN; 2019 } 2020 } 2021 2022 static enum xgbe_mode xgbe_phy_get_mode(struct xgbe_prv_data *pdata, 2023 int speed) 2024 { 2025 struct xgbe_phy_data *phy_data = pdata->phy_data; 2026 2027 switch (phy_data->port_mode) { 2028 case XGBE_PORT_MODE_BACKPLANE: 2029 return xgbe_phy_get_bp_mode(speed); 2030 case XGBE_PORT_MODE_BACKPLANE_2500: 2031 return xgbe_phy_get_bp_2500_mode(speed); 2032 case XGBE_PORT_MODE_1000BASE_T: 2033 case XGBE_PORT_MODE_NBASE_T: 2034 case XGBE_PORT_MODE_10GBASE_T: 2035 return xgbe_phy_get_baset_mode(phy_data, speed); 2036 case XGBE_PORT_MODE_1000BASE_X: 2037 case XGBE_PORT_MODE_10GBASE_R: 2038 return xgbe_phy_get_basex_mode(phy_data, speed); 2039 case XGBE_PORT_MODE_SFP: 2040 return xgbe_phy_get_sfp_mode(phy_data, speed); 2041 default: 2042 return XGBE_MODE_UNKNOWN; 2043 } 2044 } 2045 2046 static void xgbe_phy_set_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode) 2047 { 2048 switch (mode) { 2049 case XGBE_MODE_KX_1000: 2050 xgbe_phy_kx_1000_mode(pdata); 2051 break; 2052 case XGBE_MODE_KX_2500: 2053 xgbe_phy_kx_2500_mode(pdata); 2054 break; 2055 case XGBE_MODE_KR: 2056 xgbe_phy_kr_mode(pdata); 2057 break; 2058 case XGBE_MODE_SGMII_100: 2059 xgbe_phy_sgmii_100_mode(pdata); 2060 break; 2061 case XGBE_MODE_SGMII_1000: 2062 xgbe_phy_sgmii_1000_mode(pdata); 2063 break; 2064 case XGBE_MODE_X: 2065 xgbe_phy_x_mode(pdata); 2066 break; 2067 case XGBE_MODE_SFI: 2068 xgbe_phy_sfi_mode(pdata); 2069 break; 2070 default: 2071 break; 2072 } 2073 } 2074 2075 static bool xgbe_phy_check_mode(struct xgbe_prv_data *pdata, 2076 enum xgbe_mode mode, u32 advert) 2077 { 2078 if (pdata->phy.autoneg == AUTONEG_ENABLE) { 2079 if (pdata->phy.advertising & advert) 2080 return true; 2081 } else { 2082 enum xgbe_mode cur_mode; 2083 2084 cur_mode = xgbe_phy_get_mode(pdata, pdata->phy.speed); 2085 if (cur_mode == mode) 2086 return true; 2087 } 2088 2089 return false; 2090 } 2091 2092 static bool xgbe_phy_use_basex_mode(struct xgbe_prv_data *pdata, 2093 enum xgbe_mode mode) 2094 { 2095 switch (mode) { 2096 case XGBE_MODE_X: 2097 return xgbe_phy_check_mode(pdata, mode, 2098 ADVERTISED_1000baseT_Full); 2099 case XGBE_MODE_KR: 2100 return xgbe_phy_check_mode(pdata, mode, 2101 ADVERTISED_10000baseT_Full); 2102 default: 2103 return false; 2104 } 2105 } 2106 2107 static bool xgbe_phy_use_baset_mode(struct xgbe_prv_data *pdata, 2108 enum xgbe_mode mode) 2109 { 2110 switch (mode) { 2111 case XGBE_MODE_SGMII_100: 2112 return xgbe_phy_check_mode(pdata, mode, 2113 ADVERTISED_100baseT_Full); 2114 case XGBE_MODE_SGMII_1000: 2115 return xgbe_phy_check_mode(pdata, mode, 2116 ADVERTISED_1000baseT_Full); 2117 case XGBE_MODE_KX_2500: 2118 return xgbe_phy_check_mode(pdata, mode, 2119 ADVERTISED_2500baseX_Full); 2120 case XGBE_MODE_KR: 2121 return xgbe_phy_check_mode(pdata, mode, 2122 ADVERTISED_10000baseT_Full); 2123 default: 2124 return false; 2125 } 2126 } 2127 2128 static bool xgbe_phy_use_sfp_mode(struct xgbe_prv_data *pdata, 2129 enum xgbe_mode mode) 2130 { 2131 struct xgbe_phy_data *phy_data = pdata->phy_data; 2132 2133 switch (mode) { 2134 case XGBE_MODE_X: 2135 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T) 2136 return false; 2137 return xgbe_phy_check_mode(pdata, mode, 2138 ADVERTISED_1000baseT_Full); 2139 case XGBE_MODE_SGMII_100: 2140 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T) 2141 return false; 2142 return xgbe_phy_check_mode(pdata, mode, 2143 ADVERTISED_100baseT_Full); 2144 case XGBE_MODE_SGMII_1000: 2145 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T) 2146 return false; 2147 return xgbe_phy_check_mode(pdata, mode, 2148 ADVERTISED_1000baseT_Full); 2149 case XGBE_MODE_SFI: 2150 if (phy_data->sfp_mod_absent) 2151 return true; 2152 return xgbe_phy_check_mode(pdata, mode, 2153 ADVERTISED_10000baseT_Full); 2154 default: 2155 return false; 2156 } 2157 } 2158 2159 static bool xgbe_phy_use_bp_2500_mode(struct xgbe_prv_data *pdata, 2160 enum xgbe_mode mode) 2161 { 2162 switch (mode) { 2163 case XGBE_MODE_KX_2500: 2164 return xgbe_phy_check_mode(pdata, mode, 2165 ADVERTISED_2500baseX_Full); 2166 default: 2167 return false; 2168 } 2169 } 2170 2171 static bool xgbe_phy_use_bp_mode(struct xgbe_prv_data *pdata, 2172 enum xgbe_mode mode) 2173 { 2174 switch (mode) { 2175 case XGBE_MODE_KX_1000: 2176 return xgbe_phy_check_mode(pdata, mode, 2177 ADVERTISED_1000baseKX_Full); 2178 case XGBE_MODE_KR: 2179 return xgbe_phy_check_mode(pdata, mode, 2180 ADVERTISED_10000baseKR_Full); 2181 default: 2182 return false; 2183 } 2184 } 2185 2186 static bool xgbe_phy_use_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode) 2187 { 2188 struct xgbe_phy_data *phy_data = pdata->phy_data; 2189 2190 switch (phy_data->port_mode) { 2191 case XGBE_PORT_MODE_BACKPLANE: 2192 return xgbe_phy_use_bp_mode(pdata, mode); 2193 case XGBE_PORT_MODE_BACKPLANE_2500: 2194 return xgbe_phy_use_bp_2500_mode(pdata, mode); 2195 case XGBE_PORT_MODE_1000BASE_T: 2196 case XGBE_PORT_MODE_NBASE_T: 2197 case XGBE_PORT_MODE_10GBASE_T: 2198 return xgbe_phy_use_baset_mode(pdata, mode); 2199 case XGBE_PORT_MODE_1000BASE_X: 2200 case XGBE_PORT_MODE_10GBASE_R: 2201 return xgbe_phy_use_basex_mode(pdata, mode); 2202 case XGBE_PORT_MODE_SFP: 2203 return xgbe_phy_use_sfp_mode(pdata, mode); 2204 default: 2205 return false; 2206 } 2207 } 2208 2209 static bool xgbe_phy_valid_speed_basex_mode(struct xgbe_phy_data *phy_data, 2210 int speed) 2211 { 2212 switch (speed) { 2213 case SPEED_1000: 2214 return (phy_data->port_mode == XGBE_PORT_MODE_1000BASE_X); 2215 case SPEED_10000: 2216 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_R); 2217 default: 2218 return false; 2219 } 2220 } 2221 2222 static bool xgbe_phy_valid_speed_baset_mode(struct xgbe_phy_data *phy_data, 2223 int speed) 2224 { 2225 switch (speed) { 2226 case SPEED_100: 2227 case SPEED_1000: 2228 return true; 2229 case SPEED_2500: 2230 return (phy_data->port_mode == XGBE_PORT_MODE_NBASE_T); 2231 case SPEED_10000: 2232 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_T); 2233 default: 2234 return false; 2235 } 2236 } 2237 2238 static bool xgbe_phy_valid_speed_sfp_mode(struct xgbe_phy_data *phy_data, 2239 int speed) 2240 { 2241 switch (speed) { 2242 case SPEED_100: 2243 return (phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000); 2244 case SPEED_1000: 2245 return ((phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000) || 2246 (phy_data->sfp_speed == XGBE_SFP_SPEED_1000)); 2247 case SPEED_10000: 2248 return (phy_data->sfp_speed == XGBE_SFP_SPEED_10000); 2249 default: 2250 return false; 2251 } 2252 } 2253 2254 static bool xgbe_phy_valid_speed_bp_2500_mode(int speed) 2255 { 2256 switch (speed) { 2257 case SPEED_2500: 2258 return true; 2259 default: 2260 return false; 2261 } 2262 } 2263 2264 static bool xgbe_phy_valid_speed_bp_mode(int speed) 2265 { 2266 switch (speed) { 2267 case SPEED_1000: 2268 case SPEED_10000: 2269 return true; 2270 default: 2271 return false; 2272 } 2273 } 2274 2275 static bool xgbe_phy_valid_speed(struct xgbe_prv_data *pdata, int speed) 2276 { 2277 struct xgbe_phy_data *phy_data = pdata->phy_data; 2278 2279 switch (phy_data->port_mode) { 2280 case XGBE_PORT_MODE_BACKPLANE: 2281 return xgbe_phy_valid_speed_bp_mode(speed); 2282 case XGBE_PORT_MODE_BACKPLANE_2500: 2283 return xgbe_phy_valid_speed_bp_2500_mode(speed); 2284 case XGBE_PORT_MODE_1000BASE_T: 2285 case XGBE_PORT_MODE_NBASE_T: 2286 case XGBE_PORT_MODE_10GBASE_T: 2287 return xgbe_phy_valid_speed_baset_mode(phy_data, speed); 2288 case XGBE_PORT_MODE_1000BASE_X: 2289 case XGBE_PORT_MODE_10GBASE_R: 2290 return xgbe_phy_valid_speed_basex_mode(phy_data, speed); 2291 case XGBE_PORT_MODE_SFP: 2292 return xgbe_phy_valid_speed_sfp_mode(phy_data, speed); 2293 default: 2294 return false; 2295 } 2296 } 2297 2298 static int xgbe_phy_link_status(struct xgbe_prv_data *pdata, int *an_restart) 2299 { 2300 struct xgbe_phy_data *phy_data = pdata->phy_data; 2301 unsigned int reg; 2302 int ret; 2303 2304 *an_restart = 0; 2305 2306 if (phy_data->port_mode == XGBE_PORT_MODE_SFP) { 2307 /* Check SFP signals */ 2308 xgbe_phy_sfp_detect(pdata); 2309 2310 if (phy_data->sfp_changed) { 2311 *an_restart = 1; 2312 return 0; 2313 } 2314 2315 if (phy_data->sfp_mod_absent || phy_data->sfp_rx_los) 2316 return 0; 2317 } 2318 2319 if (phy_data->phydev) { 2320 /* Check external PHY */ 2321 ret = phy_read_status(phy_data->phydev); 2322 if (ret < 0) 2323 return 0; 2324 2325 if ((pdata->phy.autoneg == AUTONEG_ENABLE) && 2326 !phy_aneg_done(phy_data->phydev)) 2327 return 0; 2328 2329 if (!phy_data->phydev->link) 2330 return 0; 2331 } 2332 2333 /* Link status is latched low, so read once to clear 2334 * and then read again to get current state 2335 */ 2336 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); 2337 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); 2338 if (reg & MDIO_STAT1_LSTATUS) 2339 return 1; 2340 2341 /* No link, attempt a receiver reset cycle */ 2342 if (phy_data->rrc_count++) { 2343 phy_data->rrc_count = 0; 2344 xgbe_phy_rrc(pdata); 2345 } 2346 2347 return 0; 2348 } 2349 2350 static void xgbe_phy_sfp_gpio_setup(struct xgbe_prv_data *pdata) 2351 { 2352 struct xgbe_phy_data *phy_data = pdata->phy_data; 2353 unsigned int reg; 2354 2355 reg = XP_IOREAD(pdata, XP_PROP_3); 2356 2357 phy_data->sfp_gpio_address = XGBE_GPIO_ADDRESS_PCA9555 + 2358 XP_GET_BITS(reg, XP_PROP_3, GPIO_ADDR); 2359 2360 phy_data->sfp_gpio_mask = XP_GET_BITS(reg, XP_PROP_3, GPIO_MASK); 2361 2362 phy_data->sfp_gpio_rx_los = XP_GET_BITS(reg, XP_PROP_3, 2363 GPIO_RX_LOS); 2364 phy_data->sfp_gpio_tx_fault = XP_GET_BITS(reg, XP_PROP_3, 2365 GPIO_TX_FAULT); 2366 phy_data->sfp_gpio_mod_absent = XP_GET_BITS(reg, XP_PROP_3, 2367 GPIO_MOD_ABS); 2368 phy_data->sfp_gpio_rate_select = XP_GET_BITS(reg, XP_PROP_3, 2369 GPIO_RATE_SELECT); 2370 2371 if (netif_msg_probe(pdata)) { 2372 dev_dbg(pdata->dev, "SFP: gpio_address=%#x\n", 2373 phy_data->sfp_gpio_address); 2374 dev_dbg(pdata->dev, "SFP: gpio_mask=%#x\n", 2375 phy_data->sfp_gpio_mask); 2376 dev_dbg(pdata->dev, "SFP: gpio_rx_los=%u\n", 2377 phy_data->sfp_gpio_rx_los); 2378 dev_dbg(pdata->dev, "SFP: gpio_tx_fault=%u\n", 2379 phy_data->sfp_gpio_tx_fault); 2380 dev_dbg(pdata->dev, "SFP: gpio_mod_absent=%u\n", 2381 phy_data->sfp_gpio_mod_absent); 2382 dev_dbg(pdata->dev, "SFP: gpio_rate_select=%u\n", 2383 phy_data->sfp_gpio_rate_select); 2384 } 2385 } 2386 2387 static void xgbe_phy_sfp_comm_setup(struct xgbe_prv_data *pdata) 2388 { 2389 struct xgbe_phy_data *phy_data = pdata->phy_data; 2390 unsigned int reg, mux_addr_hi, mux_addr_lo; 2391 2392 reg = XP_IOREAD(pdata, XP_PROP_4); 2393 2394 mux_addr_hi = XP_GET_BITS(reg, XP_PROP_4, MUX_ADDR_HI); 2395 mux_addr_lo = XP_GET_BITS(reg, XP_PROP_4, MUX_ADDR_LO); 2396 if (mux_addr_lo == XGBE_SFP_DIRECT) 2397 return; 2398 2399 phy_data->sfp_comm = XGBE_SFP_COMM_PCA9545; 2400 phy_data->sfp_mux_address = (mux_addr_hi << 2) + mux_addr_lo; 2401 phy_data->sfp_mux_channel = XP_GET_BITS(reg, XP_PROP_4, MUX_CHAN); 2402 2403 if (netif_msg_probe(pdata)) { 2404 dev_dbg(pdata->dev, "SFP: mux_address=%#x\n", 2405 phy_data->sfp_mux_address); 2406 dev_dbg(pdata->dev, "SFP: mux_channel=%u\n", 2407 phy_data->sfp_mux_channel); 2408 } 2409 } 2410 2411 static void xgbe_phy_sfp_setup(struct xgbe_prv_data *pdata) 2412 { 2413 xgbe_phy_sfp_comm_setup(pdata); 2414 xgbe_phy_sfp_gpio_setup(pdata); 2415 } 2416 2417 static int xgbe_phy_int_mdio_reset(struct xgbe_prv_data *pdata) 2418 { 2419 struct xgbe_phy_data *phy_data = pdata->phy_data; 2420 unsigned int ret; 2421 2422 ret = pdata->hw_if.set_gpio(pdata, phy_data->mdio_reset_gpio); 2423 if (ret) 2424 return ret; 2425 2426 ret = pdata->hw_if.clr_gpio(pdata, phy_data->mdio_reset_gpio); 2427 2428 return ret; 2429 } 2430 2431 static int xgbe_phy_i2c_mdio_reset(struct xgbe_prv_data *pdata) 2432 { 2433 struct xgbe_phy_data *phy_data = pdata->phy_data; 2434 u8 gpio_reg, gpio_ports[2], gpio_data[3]; 2435 int ret; 2436 2437 /* Read the output port registers */ 2438 gpio_reg = 2; 2439 ret = xgbe_phy_i2c_read(pdata, phy_data->mdio_reset_addr, 2440 &gpio_reg, sizeof(gpio_reg), 2441 gpio_ports, sizeof(gpio_ports)); 2442 if (ret) 2443 return ret; 2444 2445 /* Prepare to write the GPIO data */ 2446 gpio_data[0] = 2; 2447 gpio_data[1] = gpio_ports[0]; 2448 gpio_data[2] = gpio_ports[1]; 2449 2450 /* Set the GPIO pin */ 2451 if (phy_data->mdio_reset_gpio < 8) 2452 gpio_data[1] |= (1 << (phy_data->mdio_reset_gpio % 8)); 2453 else 2454 gpio_data[2] |= (1 << (phy_data->mdio_reset_gpio % 8)); 2455 2456 /* Write the output port registers */ 2457 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr, 2458 gpio_data, sizeof(gpio_data)); 2459 if (ret) 2460 return ret; 2461 2462 /* Clear the GPIO pin */ 2463 if (phy_data->mdio_reset_gpio < 8) 2464 gpio_data[1] &= ~(1 << (phy_data->mdio_reset_gpio % 8)); 2465 else 2466 gpio_data[2] &= ~(1 << (phy_data->mdio_reset_gpio % 8)); 2467 2468 /* Write the output port registers */ 2469 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr, 2470 gpio_data, sizeof(gpio_data)); 2471 2472 return ret; 2473 } 2474 2475 static int xgbe_phy_mdio_reset(struct xgbe_prv_data *pdata) 2476 { 2477 struct xgbe_phy_data *phy_data = pdata->phy_data; 2478 int ret; 2479 2480 if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO) 2481 return 0; 2482 2483 ret = xgbe_phy_get_comm_ownership(pdata); 2484 if (ret) 2485 return ret; 2486 2487 if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO) 2488 ret = xgbe_phy_i2c_mdio_reset(pdata); 2489 else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO) 2490 ret = xgbe_phy_int_mdio_reset(pdata); 2491 2492 xgbe_phy_put_comm_ownership(pdata); 2493 2494 return ret; 2495 } 2496 2497 static bool xgbe_phy_redrv_error(struct xgbe_phy_data *phy_data) 2498 { 2499 if (!phy_data->redrv) 2500 return false; 2501 2502 if (phy_data->redrv_if >= XGBE_PHY_REDRV_IF_MAX) 2503 return true; 2504 2505 switch (phy_data->redrv_model) { 2506 case XGBE_PHY_REDRV_MODEL_4223: 2507 if (phy_data->redrv_lane > 3) 2508 return true; 2509 break; 2510 case XGBE_PHY_REDRV_MODEL_4227: 2511 if (phy_data->redrv_lane > 1) 2512 return true; 2513 break; 2514 default: 2515 return true; 2516 } 2517 2518 return false; 2519 } 2520 2521 static int xgbe_phy_mdio_reset_setup(struct xgbe_prv_data *pdata) 2522 { 2523 struct xgbe_phy_data *phy_data = pdata->phy_data; 2524 unsigned int reg; 2525 2526 if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO) 2527 return 0; 2528 2529 reg = XP_IOREAD(pdata, XP_PROP_3); 2530 phy_data->mdio_reset = XP_GET_BITS(reg, XP_PROP_3, MDIO_RESET); 2531 switch (phy_data->mdio_reset) { 2532 case XGBE_MDIO_RESET_NONE: 2533 case XGBE_MDIO_RESET_I2C_GPIO: 2534 case XGBE_MDIO_RESET_INT_GPIO: 2535 break; 2536 default: 2537 dev_err(pdata->dev, "unsupported MDIO reset (%#x)\n", 2538 phy_data->mdio_reset); 2539 return -EINVAL; 2540 } 2541 2542 if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO) { 2543 phy_data->mdio_reset_addr = XGBE_GPIO_ADDRESS_PCA9555 + 2544 XP_GET_BITS(reg, XP_PROP_3, 2545 MDIO_RESET_I2C_ADDR); 2546 phy_data->mdio_reset_gpio = XP_GET_BITS(reg, XP_PROP_3, 2547 MDIO_RESET_I2C_GPIO); 2548 } else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO) { 2549 phy_data->mdio_reset_gpio = XP_GET_BITS(reg, XP_PROP_3, 2550 MDIO_RESET_INT_GPIO); 2551 } 2552 2553 return 0; 2554 } 2555 2556 static bool xgbe_phy_port_mode_mismatch(struct xgbe_prv_data *pdata) 2557 { 2558 struct xgbe_phy_data *phy_data = pdata->phy_data; 2559 2560 switch (phy_data->port_mode) { 2561 case XGBE_PORT_MODE_BACKPLANE: 2562 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) || 2563 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)) 2564 return false; 2565 break; 2566 case XGBE_PORT_MODE_BACKPLANE_2500: 2567 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500) 2568 return false; 2569 break; 2570 case XGBE_PORT_MODE_1000BASE_T: 2571 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) || 2572 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)) 2573 return false; 2574 break; 2575 case XGBE_PORT_MODE_1000BASE_X: 2576 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) 2577 return false; 2578 break; 2579 case XGBE_PORT_MODE_NBASE_T: 2580 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) || 2581 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) || 2582 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500)) 2583 return false; 2584 break; 2585 case XGBE_PORT_MODE_10GBASE_T: 2586 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) || 2587 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) || 2588 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)) 2589 return false; 2590 break; 2591 case XGBE_PORT_MODE_10GBASE_R: 2592 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) 2593 return false; 2594 break; 2595 case XGBE_PORT_MODE_SFP: 2596 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) || 2597 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) || 2598 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)) 2599 return false; 2600 break; 2601 default: 2602 break; 2603 } 2604 2605 return true; 2606 } 2607 2608 static bool xgbe_phy_conn_type_mismatch(struct xgbe_prv_data *pdata) 2609 { 2610 struct xgbe_phy_data *phy_data = pdata->phy_data; 2611 2612 switch (phy_data->port_mode) { 2613 case XGBE_PORT_MODE_BACKPLANE: 2614 case XGBE_PORT_MODE_BACKPLANE_2500: 2615 if (phy_data->conn_type == XGBE_CONN_TYPE_BACKPLANE) 2616 return false; 2617 break; 2618 case XGBE_PORT_MODE_1000BASE_T: 2619 case XGBE_PORT_MODE_1000BASE_X: 2620 case XGBE_PORT_MODE_NBASE_T: 2621 case XGBE_PORT_MODE_10GBASE_T: 2622 case XGBE_PORT_MODE_10GBASE_R: 2623 if (phy_data->conn_type == XGBE_CONN_TYPE_MDIO) 2624 return false; 2625 break; 2626 case XGBE_PORT_MODE_SFP: 2627 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP) 2628 return false; 2629 break; 2630 default: 2631 break; 2632 } 2633 2634 return true; 2635 } 2636 2637 static bool xgbe_phy_port_enabled(struct xgbe_prv_data *pdata) 2638 { 2639 unsigned int reg; 2640 2641 reg = XP_IOREAD(pdata, XP_PROP_0); 2642 if (!XP_GET_BITS(reg, XP_PROP_0, PORT_SPEEDS)) 2643 return false; 2644 if (!XP_GET_BITS(reg, XP_PROP_0, CONN_TYPE)) 2645 return false; 2646 2647 return true; 2648 } 2649 2650 static void xgbe_phy_stop(struct xgbe_prv_data *pdata) 2651 { 2652 struct xgbe_phy_data *phy_data = pdata->phy_data; 2653 2654 /* If we have an external PHY, free it */ 2655 xgbe_phy_free_phy_device(pdata); 2656 2657 /* Reset SFP data */ 2658 xgbe_phy_sfp_reset(phy_data); 2659 xgbe_phy_sfp_mod_absent(pdata); 2660 2661 /* Power off the PHY */ 2662 xgbe_phy_power_off(pdata); 2663 2664 /* Stop the I2C controller */ 2665 pdata->i2c_if.i2c_stop(pdata); 2666 } 2667 2668 static int xgbe_phy_start(struct xgbe_prv_data *pdata) 2669 { 2670 struct xgbe_phy_data *phy_data = pdata->phy_data; 2671 int ret; 2672 2673 /* Start the I2C controller */ 2674 ret = pdata->i2c_if.i2c_start(pdata); 2675 if (ret) 2676 return ret; 2677 2678 /* Set the proper MDIO mode for the re-driver */ 2679 if (phy_data->redrv && !phy_data->redrv_if) { 2680 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr, 2681 XGBE_MDIO_MODE_CL22); 2682 if (ret) { 2683 netdev_err(pdata->netdev, 2684 "redriver mdio port not compatible (%u)\n", 2685 phy_data->redrv_addr); 2686 return ret; 2687 } 2688 } 2689 2690 /* Start in highest supported mode */ 2691 xgbe_phy_set_mode(pdata, phy_data->start_mode); 2692 2693 /* After starting the I2C controller, we can check for an SFP */ 2694 switch (phy_data->port_mode) { 2695 case XGBE_PORT_MODE_SFP: 2696 xgbe_phy_sfp_detect(pdata); 2697 break; 2698 default: 2699 break; 2700 } 2701 2702 /* If we have an external PHY, start it */ 2703 ret = xgbe_phy_find_phy_device(pdata); 2704 if (ret) 2705 goto err_i2c; 2706 2707 return 0; 2708 2709 err_i2c: 2710 pdata->i2c_if.i2c_stop(pdata); 2711 2712 return ret; 2713 } 2714 2715 static int xgbe_phy_reset(struct xgbe_prv_data *pdata) 2716 { 2717 struct xgbe_phy_data *phy_data = pdata->phy_data; 2718 enum xgbe_mode cur_mode; 2719 int ret; 2720 2721 /* Reset by power cycling the PHY */ 2722 cur_mode = phy_data->cur_mode; 2723 xgbe_phy_power_off(pdata); 2724 xgbe_phy_set_mode(pdata, cur_mode); 2725 2726 if (!phy_data->phydev) 2727 return 0; 2728 2729 /* Reset the external PHY */ 2730 ret = xgbe_phy_mdio_reset(pdata); 2731 if (ret) 2732 return ret; 2733 2734 return phy_init_hw(phy_data->phydev); 2735 } 2736 2737 static void xgbe_phy_exit(struct xgbe_prv_data *pdata) 2738 { 2739 struct xgbe_phy_data *phy_data = pdata->phy_data; 2740 2741 /* Unregister for driving external PHYs */ 2742 mdiobus_unregister(phy_data->mii); 2743 } 2744 2745 static int xgbe_phy_init(struct xgbe_prv_data *pdata) 2746 { 2747 struct xgbe_phy_data *phy_data; 2748 struct mii_bus *mii; 2749 unsigned int reg; 2750 int ret; 2751 2752 /* Check if enabled */ 2753 if (!xgbe_phy_port_enabled(pdata)) { 2754 dev_info(pdata->dev, "device is not enabled\n"); 2755 return -ENODEV; 2756 } 2757 2758 /* Initialize the I2C controller */ 2759 ret = pdata->i2c_if.i2c_init(pdata); 2760 if (ret) 2761 return ret; 2762 2763 phy_data = devm_kzalloc(pdata->dev, sizeof(*phy_data), GFP_KERNEL); 2764 if (!phy_data) 2765 return -ENOMEM; 2766 pdata->phy_data = phy_data; 2767 2768 reg = XP_IOREAD(pdata, XP_PROP_0); 2769 phy_data->port_mode = XP_GET_BITS(reg, XP_PROP_0, PORT_MODE); 2770 phy_data->port_id = XP_GET_BITS(reg, XP_PROP_0, PORT_ID); 2771 phy_data->port_speeds = XP_GET_BITS(reg, XP_PROP_0, PORT_SPEEDS); 2772 phy_data->conn_type = XP_GET_BITS(reg, XP_PROP_0, CONN_TYPE); 2773 phy_data->mdio_addr = XP_GET_BITS(reg, XP_PROP_0, MDIO_ADDR); 2774 if (netif_msg_probe(pdata)) { 2775 dev_dbg(pdata->dev, "port mode=%u\n", phy_data->port_mode); 2776 dev_dbg(pdata->dev, "port id=%u\n", phy_data->port_id); 2777 dev_dbg(pdata->dev, "port speeds=%#x\n", phy_data->port_speeds); 2778 dev_dbg(pdata->dev, "conn type=%u\n", phy_data->conn_type); 2779 dev_dbg(pdata->dev, "mdio addr=%u\n", phy_data->mdio_addr); 2780 } 2781 2782 reg = XP_IOREAD(pdata, XP_PROP_4); 2783 phy_data->redrv = XP_GET_BITS(reg, XP_PROP_4, REDRV_PRESENT); 2784 phy_data->redrv_if = XP_GET_BITS(reg, XP_PROP_4, REDRV_IF); 2785 phy_data->redrv_addr = XP_GET_BITS(reg, XP_PROP_4, REDRV_ADDR); 2786 phy_data->redrv_lane = XP_GET_BITS(reg, XP_PROP_4, REDRV_LANE); 2787 phy_data->redrv_model = XP_GET_BITS(reg, XP_PROP_4, REDRV_MODEL); 2788 if (phy_data->redrv && netif_msg_probe(pdata)) { 2789 dev_dbg(pdata->dev, "redrv present\n"); 2790 dev_dbg(pdata->dev, "redrv i/f=%u\n", phy_data->redrv_if); 2791 dev_dbg(pdata->dev, "redrv addr=%#x\n", phy_data->redrv_addr); 2792 dev_dbg(pdata->dev, "redrv lane=%u\n", phy_data->redrv_lane); 2793 dev_dbg(pdata->dev, "redrv model=%u\n", phy_data->redrv_model); 2794 } 2795 2796 /* Validate the connection requested */ 2797 if (xgbe_phy_conn_type_mismatch(pdata)) { 2798 dev_err(pdata->dev, "phy mode/connection mismatch (%#x/%#x)\n", 2799 phy_data->port_mode, phy_data->conn_type); 2800 return -EINVAL; 2801 } 2802 2803 /* Validate the mode requested */ 2804 if (xgbe_phy_port_mode_mismatch(pdata)) { 2805 dev_err(pdata->dev, "phy mode/speed mismatch (%#x/%#x)\n", 2806 phy_data->port_mode, phy_data->port_speeds); 2807 return -EINVAL; 2808 } 2809 2810 /* Check for and validate MDIO reset support */ 2811 ret = xgbe_phy_mdio_reset_setup(pdata); 2812 if (ret) 2813 return ret; 2814 2815 /* Validate the re-driver information */ 2816 if (xgbe_phy_redrv_error(phy_data)) { 2817 dev_err(pdata->dev, "phy re-driver settings error\n"); 2818 return -EINVAL; 2819 } 2820 pdata->kr_redrv = phy_data->redrv; 2821 2822 /* Indicate current mode is unknown */ 2823 phy_data->cur_mode = XGBE_MODE_UNKNOWN; 2824 2825 /* Initialize supported features */ 2826 pdata->phy.supported = 0; 2827 2828 switch (phy_data->port_mode) { 2829 /* Backplane support */ 2830 case XGBE_PORT_MODE_BACKPLANE: 2831 pdata->phy.supported |= SUPPORTED_Autoneg; 2832 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2833 pdata->phy.supported |= SUPPORTED_Backplane; 2834 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) { 2835 pdata->phy.supported |= SUPPORTED_1000baseKX_Full; 2836 phy_data->start_mode = XGBE_MODE_KX_1000; 2837 } 2838 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) { 2839 pdata->phy.supported |= SUPPORTED_10000baseKR_Full; 2840 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 2841 pdata->phy.supported |= 2842 SUPPORTED_10000baseR_FEC; 2843 phy_data->start_mode = XGBE_MODE_KR; 2844 } 2845 2846 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE; 2847 break; 2848 case XGBE_PORT_MODE_BACKPLANE_2500: 2849 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2850 pdata->phy.supported |= SUPPORTED_Backplane; 2851 pdata->phy.supported |= SUPPORTED_2500baseX_Full; 2852 phy_data->start_mode = XGBE_MODE_KX_2500; 2853 2854 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE; 2855 break; 2856 2857 /* MDIO 1GBase-T support */ 2858 case XGBE_PORT_MODE_1000BASE_T: 2859 pdata->phy.supported |= SUPPORTED_Autoneg; 2860 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2861 pdata->phy.supported |= SUPPORTED_TP; 2862 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) { 2863 pdata->phy.supported |= SUPPORTED_100baseT_Full; 2864 phy_data->start_mode = XGBE_MODE_SGMII_100; 2865 } 2866 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) { 2867 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 2868 phy_data->start_mode = XGBE_MODE_SGMII_1000; 2869 } 2870 2871 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22; 2872 break; 2873 2874 /* MDIO Base-X support */ 2875 case XGBE_PORT_MODE_1000BASE_X: 2876 pdata->phy.supported |= SUPPORTED_Autoneg; 2877 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2878 pdata->phy.supported |= SUPPORTED_FIBRE; 2879 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 2880 phy_data->start_mode = XGBE_MODE_X; 2881 2882 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22; 2883 break; 2884 2885 /* MDIO NBase-T support */ 2886 case XGBE_PORT_MODE_NBASE_T: 2887 pdata->phy.supported |= SUPPORTED_Autoneg; 2888 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2889 pdata->phy.supported |= SUPPORTED_TP; 2890 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) { 2891 pdata->phy.supported |= SUPPORTED_100baseT_Full; 2892 phy_data->start_mode = XGBE_MODE_SGMII_100; 2893 } 2894 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) { 2895 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 2896 phy_data->start_mode = XGBE_MODE_SGMII_1000; 2897 } 2898 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500) { 2899 pdata->phy.supported |= SUPPORTED_2500baseX_Full; 2900 phy_data->start_mode = XGBE_MODE_KX_2500; 2901 } 2902 2903 phy_data->phydev_mode = XGBE_MDIO_MODE_CL45; 2904 break; 2905 2906 /* 10GBase-T support */ 2907 case XGBE_PORT_MODE_10GBASE_T: 2908 pdata->phy.supported |= SUPPORTED_Autoneg; 2909 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2910 pdata->phy.supported |= SUPPORTED_TP; 2911 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) { 2912 pdata->phy.supported |= SUPPORTED_100baseT_Full; 2913 phy_data->start_mode = XGBE_MODE_SGMII_100; 2914 } 2915 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) { 2916 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 2917 phy_data->start_mode = XGBE_MODE_SGMII_1000; 2918 } 2919 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) { 2920 pdata->phy.supported |= SUPPORTED_10000baseT_Full; 2921 phy_data->start_mode = XGBE_MODE_KR; 2922 } 2923 2924 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE; 2925 break; 2926 2927 /* 10GBase-R support */ 2928 case XGBE_PORT_MODE_10GBASE_R: 2929 pdata->phy.supported |= SUPPORTED_Autoneg; 2930 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2931 pdata->phy.supported |= SUPPORTED_TP; 2932 pdata->phy.supported |= SUPPORTED_10000baseT_Full; 2933 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 2934 pdata->phy.supported |= SUPPORTED_10000baseR_FEC; 2935 phy_data->start_mode = XGBE_MODE_SFI; 2936 2937 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE; 2938 break; 2939 2940 /* SFP support */ 2941 case XGBE_PORT_MODE_SFP: 2942 pdata->phy.supported |= SUPPORTED_Autoneg; 2943 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2944 pdata->phy.supported |= SUPPORTED_TP; 2945 pdata->phy.supported |= SUPPORTED_FIBRE; 2946 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) { 2947 pdata->phy.supported |= SUPPORTED_100baseT_Full; 2948 phy_data->start_mode = XGBE_MODE_SGMII_100; 2949 } 2950 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) { 2951 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 2952 phy_data->start_mode = XGBE_MODE_SGMII_1000; 2953 } 2954 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) { 2955 pdata->phy.supported |= SUPPORTED_10000baseT_Full; 2956 phy_data->start_mode = XGBE_MODE_SFI; 2957 } 2958 2959 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22; 2960 2961 xgbe_phy_sfp_setup(pdata); 2962 break; 2963 default: 2964 return -EINVAL; 2965 } 2966 2967 if (netif_msg_probe(pdata)) 2968 dev_dbg(pdata->dev, "phy supported=%#x\n", 2969 pdata->phy.supported); 2970 2971 if ((phy_data->conn_type & XGBE_CONN_TYPE_MDIO) && 2972 (phy_data->phydev_mode != XGBE_MDIO_MODE_NONE)) { 2973 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr, 2974 phy_data->phydev_mode); 2975 if (ret) { 2976 dev_err(pdata->dev, 2977 "mdio port/clause not compatible (%d/%u)\n", 2978 phy_data->mdio_addr, phy_data->phydev_mode); 2979 return -EINVAL; 2980 } 2981 } 2982 2983 if (phy_data->redrv && !phy_data->redrv_if) { 2984 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr, 2985 XGBE_MDIO_MODE_CL22); 2986 if (ret) { 2987 dev_err(pdata->dev, 2988 "redriver mdio port not compatible (%u)\n", 2989 phy_data->redrv_addr); 2990 return -EINVAL; 2991 } 2992 } 2993 2994 /* Register for driving external PHYs */ 2995 mii = devm_mdiobus_alloc(pdata->dev); 2996 if (!mii) { 2997 dev_err(pdata->dev, "mdiobus_alloc failed\n"); 2998 return -ENOMEM; 2999 } 3000 3001 mii->priv = pdata; 3002 mii->name = "amd-xgbe-mii"; 3003 mii->read = xgbe_phy_mii_read; 3004 mii->write = xgbe_phy_mii_write; 3005 mii->parent = pdata->dev; 3006 mii->phy_mask = ~0; 3007 snprintf(mii->id, sizeof(mii->id), "%s", dev_name(pdata->dev)); 3008 ret = mdiobus_register(mii); 3009 if (ret) { 3010 dev_err(pdata->dev, "mdiobus_register failed\n"); 3011 return ret; 3012 } 3013 phy_data->mii = mii; 3014 3015 return 0; 3016 } 3017 3018 void xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if *phy_if) 3019 { 3020 struct xgbe_phy_impl_if *phy_impl = &phy_if->phy_impl; 3021 3022 phy_impl->init = xgbe_phy_init; 3023 phy_impl->exit = xgbe_phy_exit; 3024 3025 phy_impl->reset = xgbe_phy_reset; 3026 phy_impl->start = xgbe_phy_start; 3027 phy_impl->stop = xgbe_phy_stop; 3028 3029 phy_impl->link_status = xgbe_phy_link_status; 3030 3031 phy_impl->valid_speed = xgbe_phy_valid_speed; 3032 3033 phy_impl->use_mode = xgbe_phy_use_mode; 3034 phy_impl->set_mode = xgbe_phy_set_mode; 3035 phy_impl->get_mode = xgbe_phy_get_mode; 3036 phy_impl->switch_mode = xgbe_phy_switch_mode; 3037 phy_impl->cur_mode = xgbe_phy_cur_mode; 3038 3039 phy_impl->an_mode = xgbe_phy_an_mode; 3040 3041 phy_impl->an_config = xgbe_phy_an_config; 3042 3043 phy_impl->an_advertising = xgbe_phy_an_advertising; 3044 3045 phy_impl->an_outcome = xgbe_phy_an_outcome; 3046 } 3047