1 /* 2 * AMD 10Gb Ethernet driver 3 * 4 * This file is available to you under your choice of the following two 5 * licenses: 6 * 7 * License 1: GPLv2 8 * 9 * Copyright (c) 2016 Advanced Micro Devices, Inc. 10 * 11 * This file is free software; you may copy, redistribute and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation, either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program. If not, see <http://www.gnu.org/licenses/>. 23 * 24 * This file incorporates work covered by the following copyright and 25 * permission notice: 26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 28 * Inc. unless otherwise expressly agreed to in writing between Synopsys 29 * and you. 30 * 31 * The Software IS NOT an item of Licensed Software or Licensed Product 32 * under any End User Software License Agreement or Agreement for Licensed 33 * Product with Synopsys or any supplement thereto. Permission is hereby 34 * granted, free of charge, to any person obtaining a copy of this software 35 * annotated with this license and the Software, to deal in the Software 36 * without restriction, including without limitation the rights to use, 37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 38 * of the Software, and to permit persons to whom the Software is furnished 39 * to do so, subject to the following conditions: 40 * 41 * The above copyright notice and this permission notice shall be included 42 * in all copies or substantial portions of the Software. 43 * 44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 54 * THE POSSIBILITY OF SUCH DAMAGE. 55 * 56 * 57 * License 2: Modified BSD 58 * 59 * Copyright (c) 2016 Advanced Micro Devices, Inc. 60 * All rights reserved. 61 * 62 * Redistribution and use in source and binary forms, with or without 63 * modification, are permitted provided that the following conditions are met: 64 * * Redistributions of source code must retain the above copyright 65 * notice, this list of conditions and the following disclaimer. 66 * * Redistributions in binary form must reproduce the above copyright 67 * notice, this list of conditions and the following disclaimer in the 68 * documentation and/or other materials provided with the distribution. 69 * * Neither the name of Advanced Micro Devices, Inc. nor the 70 * names of its contributors may be used to endorse or promote products 71 * derived from this software without specific prior written permission. 72 * 73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY 77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 83 * 84 * This file incorporates work covered by the following copyright and 85 * permission notice: 86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 88 * Inc. unless otherwise expressly agreed to in writing between Synopsys 89 * and you. 90 * 91 * The Software IS NOT an item of Licensed Software or Licensed Product 92 * under any End User Software License Agreement or Agreement for Licensed 93 * Product with Synopsys or any supplement thereto. Permission is hereby 94 * granted, free of charge, to any person obtaining a copy of this software 95 * annotated with this license and the Software, to deal in the Software 96 * without restriction, including without limitation the rights to use, 97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 98 * of the Software, and to permit persons to whom the Software is furnished 99 * to do so, subject to the following conditions: 100 * 101 * The above copyright notice and this permission notice shall be included 102 * in all copies or substantial portions of the Software. 103 * 104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 114 * THE POSSIBILITY OF SUCH DAMAGE. 115 */ 116 117 #include <linux/module.h> 118 #include <linux/device.h> 119 #include <linux/kmod.h> 120 #include <linux/mdio.h> 121 #include <linux/phy.h> 122 #include <linux/ethtool.h> 123 124 #include "xgbe.h" 125 #include "xgbe-common.h" 126 127 #define XGBE_PHY_PORT_SPEED_100 BIT(0) 128 #define XGBE_PHY_PORT_SPEED_1000 BIT(1) 129 #define XGBE_PHY_PORT_SPEED_2500 BIT(2) 130 #define XGBE_PHY_PORT_SPEED_10000 BIT(3) 131 132 #define XGBE_MUTEX_RELEASE 0x80000000 133 134 #define XGBE_SFP_DIRECT 7 135 136 /* I2C target addresses */ 137 #define XGBE_SFP_SERIAL_ID_ADDRESS 0x50 138 #define XGBE_SFP_DIAG_INFO_ADDRESS 0x51 139 #define XGBE_SFP_PHY_ADDRESS 0x56 140 #define XGBE_GPIO_ADDRESS_PCA9555 0x20 141 142 /* SFP sideband signal indicators */ 143 #define XGBE_GPIO_NO_TX_FAULT BIT(0) 144 #define XGBE_GPIO_NO_RATE_SELECT BIT(1) 145 #define XGBE_GPIO_NO_MOD_ABSENT BIT(2) 146 #define XGBE_GPIO_NO_RX_LOS BIT(3) 147 148 /* Rate-change complete wait/retry count */ 149 #define XGBE_RATECHANGE_COUNT 500 150 151 /* CDR delay values for KR support (in usec) */ 152 #define XGBE_CDR_DELAY_INIT 10000 153 #define XGBE_CDR_DELAY_INC 10000 154 #define XGBE_CDR_DELAY_MAX 100000 155 156 /* RRC frequency during link status check */ 157 #define XGBE_RRC_FREQUENCY 10 158 159 enum xgbe_port_mode { 160 XGBE_PORT_MODE_RSVD = 0, 161 XGBE_PORT_MODE_BACKPLANE, 162 XGBE_PORT_MODE_BACKPLANE_2500, 163 XGBE_PORT_MODE_1000BASE_T, 164 XGBE_PORT_MODE_1000BASE_X, 165 XGBE_PORT_MODE_NBASE_T, 166 XGBE_PORT_MODE_10GBASE_T, 167 XGBE_PORT_MODE_10GBASE_R, 168 XGBE_PORT_MODE_SFP, 169 XGBE_PORT_MODE_MAX, 170 }; 171 172 enum xgbe_conn_type { 173 XGBE_CONN_TYPE_NONE = 0, 174 XGBE_CONN_TYPE_SFP, 175 XGBE_CONN_TYPE_MDIO, 176 XGBE_CONN_TYPE_RSVD1, 177 XGBE_CONN_TYPE_BACKPLANE, 178 XGBE_CONN_TYPE_MAX, 179 }; 180 181 /* SFP/SFP+ related definitions */ 182 enum xgbe_sfp_comm { 183 XGBE_SFP_COMM_DIRECT = 0, 184 XGBE_SFP_COMM_PCA9545, 185 }; 186 187 enum xgbe_sfp_cable { 188 XGBE_SFP_CABLE_UNKNOWN = 0, 189 XGBE_SFP_CABLE_ACTIVE, 190 XGBE_SFP_CABLE_PASSIVE, 191 }; 192 193 enum xgbe_sfp_base { 194 XGBE_SFP_BASE_UNKNOWN = 0, 195 XGBE_SFP_BASE_1000_T, 196 XGBE_SFP_BASE_1000_SX, 197 XGBE_SFP_BASE_1000_LX, 198 XGBE_SFP_BASE_1000_CX, 199 XGBE_SFP_BASE_10000_SR, 200 XGBE_SFP_BASE_10000_LR, 201 XGBE_SFP_BASE_10000_LRM, 202 XGBE_SFP_BASE_10000_ER, 203 XGBE_SFP_BASE_10000_CR, 204 }; 205 206 enum xgbe_sfp_speed { 207 XGBE_SFP_SPEED_UNKNOWN = 0, 208 XGBE_SFP_SPEED_100_1000, 209 XGBE_SFP_SPEED_1000, 210 XGBE_SFP_SPEED_10000, 211 }; 212 213 /* SFP Serial ID Base ID values relative to an offset of 0 */ 214 #define XGBE_SFP_BASE_ID 0 215 #define XGBE_SFP_ID_SFP 0x03 216 217 #define XGBE_SFP_BASE_EXT_ID 1 218 #define XGBE_SFP_EXT_ID_SFP 0x04 219 220 #define XGBE_SFP_BASE_10GBE_CC 3 221 #define XGBE_SFP_BASE_10GBE_CC_SR BIT(4) 222 #define XGBE_SFP_BASE_10GBE_CC_LR BIT(5) 223 #define XGBE_SFP_BASE_10GBE_CC_LRM BIT(6) 224 #define XGBE_SFP_BASE_10GBE_CC_ER BIT(7) 225 226 #define XGBE_SFP_BASE_1GBE_CC 6 227 #define XGBE_SFP_BASE_1GBE_CC_SX BIT(0) 228 #define XGBE_SFP_BASE_1GBE_CC_LX BIT(1) 229 #define XGBE_SFP_BASE_1GBE_CC_CX BIT(2) 230 #define XGBE_SFP_BASE_1GBE_CC_T BIT(3) 231 232 #define XGBE_SFP_BASE_CABLE 8 233 #define XGBE_SFP_BASE_CABLE_PASSIVE BIT(2) 234 #define XGBE_SFP_BASE_CABLE_ACTIVE BIT(3) 235 236 #define XGBE_SFP_BASE_BR 12 237 #define XGBE_SFP_BASE_BR_1GBE_MIN 0x0a 238 #define XGBE_SFP_BASE_BR_1GBE_MAX 0x0d 239 #define XGBE_SFP_BASE_BR_10GBE_MIN 0x64 240 #define XGBE_SFP_BASE_BR_10GBE_MAX 0x68 241 242 #define XGBE_SFP_BASE_CU_CABLE_LEN 18 243 244 #define XGBE_SFP_BASE_VENDOR_NAME 20 245 #define XGBE_SFP_BASE_VENDOR_NAME_LEN 16 246 #define XGBE_SFP_BASE_VENDOR_PN 40 247 #define XGBE_SFP_BASE_VENDOR_PN_LEN 16 248 #define XGBE_SFP_BASE_VENDOR_REV 56 249 #define XGBE_SFP_BASE_VENDOR_REV_LEN 4 250 251 #define XGBE_SFP_BASE_CC 63 252 253 /* SFP Serial ID Extended ID values relative to an offset of 64 */ 254 #define XGBE_SFP_BASE_VENDOR_SN 4 255 #define XGBE_SFP_BASE_VENDOR_SN_LEN 16 256 257 #define XGBE_SFP_EXTD_OPT1 1 258 #define XGBE_SFP_EXTD_OPT1_RX_LOS BIT(1) 259 #define XGBE_SFP_EXTD_OPT1_TX_FAULT BIT(3) 260 261 #define XGBE_SFP_EXTD_DIAG 28 262 #define XGBE_SFP_EXTD_DIAG_ADDR_CHANGE BIT(2) 263 264 #define XGBE_SFP_EXTD_SFF_8472 30 265 266 #define XGBE_SFP_EXTD_CC 31 267 268 struct xgbe_sfp_eeprom { 269 u8 base[64]; 270 u8 extd[32]; 271 u8 vendor[32]; 272 }; 273 274 #define XGBE_SFP_DIAGS_SUPPORTED(_x) \ 275 ((_x)->extd[XGBE_SFP_EXTD_SFF_8472] && \ 276 !((_x)->extd[XGBE_SFP_EXTD_DIAG] & XGBE_SFP_EXTD_DIAG_ADDR_CHANGE)) 277 278 #define XGBE_SFP_EEPROM_BASE_LEN 256 279 #define XGBE_SFP_EEPROM_DIAG_LEN 256 280 #define XGBE_SFP_EEPROM_MAX (XGBE_SFP_EEPROM_BASE_LEN + \ 281 XGBE_SFP_EEPROM_DIAG_LEN) 282 283 #define XGBE_BEL_FUSE_VENDOR "BEL-FUSE " 284 #define XGBE_BEL_FUSE_PARTNO "1GBT-SFP06 " 285 286 struct xgbe_sfp_ascii { 287 union { 288 char vendor[XGBE_SFP_BASE_VENDOR_NAME_LEN + 1]; 289 char partno[XGBE_SFP_BASE_VENDOR_PN_LEN + 1]; 290 char rev[XGBE_SFP_BASE_VENDOR_REV_LEN + 1]; 291 char serno[XGBE_SFP_BASE_VENDOR_SN_LEN + 1]; 292 } u; 293 }; 294 295 /* MDIO PHY reset types */ 296 enum xgbe_mdio_reset { 297 XGBE_MDIO_RESET_NONE = 0, 298 XGBE_MDIO_RESET_I2C_GPIO, 299 XGBE_MDIO_RESET_INT_GPIO, 300 XGBE_MDIO_RESET_MAX, 301 }; 302 303 /* Re-driver related definitions */ 304 enum xgbe_phy_redrv_if { 305 XGBE_PHY_REDRV_IF_MDIO = 0, 306 XGBE_PHY_REDRV_IF_I2C, 307 XGBE_PHY_REDRV_IF_MAX, 308 }; 309 310 enum xgbe_phy_redrv_model { 311 XGBE_PHY_REDRV_MODEL_4223 = 0, 312 XGBE_PHY_REDRV_MODEL_4227, 313 XGBE_PHY_REDRV_MODEL_MAX, 314 }; 315 316 enum xgbe_phy_redrv_mode { 317 XGBE_PHY_REDRV_MODE_CX = 5, 318 XGBE_PHY_REDRV_MODE_SR = 9, 319 }; 320 321 #define XGBE_PHY_REDRV_MODE_REG 0x12b0 322 323 /* PHY related configuration information */ 324 struct xgbe_phy_data { 325 enum xgbe_port_mode port_mode; 326 327 unsigned int port_id; 328 329 unsigned int port_speeds; 330 331 enum xgbe_conn_type conn_type; 332 333 enum xgbe_mode cur_mode; 334 enum xgbe_mode start_mode; 335 336 unsigned int rrc_count; 337 338 unsigned int mdio_addr; 339 340 /* SFP Support */ 341 enum xgbe_sfp_comm sfp_comm; 342 unsigned int sfp_mux_address; 343 unsigned int sfp_mux_channel; 344 345 unsigned int sfp_gpio_address; 346 unsigned int sfp_gpio_mask; 347 unsigned int sfp_gpio_inputs; 348 unsigned int sfp_gpio_rx_los; 349 unsigned int sfp_gpio_tx_fault; 350 unsigned int sfp_gpio_mod_absent; 351 unsigned int sfp_gpio_rate_select; 352 353 unsigned int sfp_rx_los; 354 unsigned int sfp_tx_fault; 355 unsigned int sfp_mod_absent; 356 unsigned int sfp_changed; 357 unsigned int sfp_phy_avail; 358 unsigned int sfp_cable_len; 359 enum xgbe_sfp_base sfp_base; 360 enum xgbe_sfp_cable sfp_cable; 361 enum xgbe_sfp_speed sfp_speed; 362 struct xgbe_sfp_eeprom sfp_eeprom; 363 364 /* External PHY support */ 365 enum xgbe_mdio_mode phydev_mode; 366 struct mii_bus *mii; 367 struct phy_device *phydev; 368 enum xgbe_mdio_reset mdio_reset; 369 unsigned int mdio_reset_addr; 370 unsigned int mdio_reset_gpio; 371 372 /* Re-driver support */ 373 unsigned int redrv; 374 unsigned int redrv_if; 375 unsigned int redrv_addr; 376 unsigned int redrv_lane; 377 unsigned int redrv_model; 378 379 /* KR AN support */ 380 unsigned int phy_cdr_notrack; 381 unsigned int phy_cdr_delay; 382 }; 383 384 /* I2C, MDIO and GPIO lines are muxed, so only one device at a time */ 385 static DEFINE_MUTEX(xgbe_phy_comm_lock); 386 387 static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata); 388 389 static int xgbe_phy_i2c_xfer(struct xgbe_prv_data *pdata, 390 struct xgbe_i2c_op *i2c_op) 391 { 392 return pdata->i2c_if.i2c_xfer(pdata, i2c_op); 393 } 394 395 static int xgbe_phy_redrv_write(struct xgbe_prv_data *pdata, unsigned int reg, 396 unsigned int val) 397 { 398 struct xgbe_phy_data *phy_data = pdata->phy_data; 399 struct xgbe_i2c_op i2c_op; 400 __be16 *redrv_val; 401 u8 redrv_data[5], csum; 402 unsigned int i, retry; 403 int ret; 404 405 /* High byte of register contains read/write indicator */ 406 redrv_data[0] = ((reg >> 8) & 0xff) << 1; 407 redrv_data[1] = reg & 0xff; 408 redrv_val = (__be16 *)&redrv_data[2]; 409 *redrv_val = cpu_to_be16(val); 410 411 /* Calculate 1 byte checksum */ 412 csum = 0; 413 for (i = 0; i < 4; i++) { 414 csum += redrv_data[i]; 415 if (redrv_data[i] > csum) 416 csum++; 417 } 418 redrv_data[4] = ~csum; 419 420 retry = 1; 421 again1: 422 i2c_op.cmd = XGBE_I2C_CMD_WRITE; 423 i2c_op.target = phy_data->redrv_addr; 424 i2c_op.len = sizeof(redrv_data); 425 i2c_op.buf = redrv_data; 426 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op); 427 if (ret) { 428 if ((ret == -EAGAIN) && retry--) 429 goto again1; 430 431 return ret; 432 } 433 434 retry = 1; 435 again2: 436 i2c_op.cmd = XGBE_I2C_CMD_READ; 437 i2c_op.target = phy_data->redrv_addr; 438 i2c_op.len = 1; 439 i2c_op.buf = redrv_data; 440 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op); 441 if (ret) { 442 if ((ret == -EAGAIN) && retry--) 443 goto again2; 444 445 return ret; 446 } 447 448 if (redrv_data[0] != 0xff) { 449 netif_dbg(pdata, drv, pdata->netdev, 450 "Redriver write checksum error\n"); 451 ret = -EIO; 452 } 453 454 return ret; 455 } 456 457 static int xgbe_phy_i2c_write(struct xgbe_prv_data *pdata, unsigned int target, 458 void *val, unsigned int val_len) 459 { 460 struct xgbe_i2c_op i2c_op; 461 int retry, ret; 462 463 retry = 1; 464 again: 465 /* Write the specfied register */ 466 i2c_op.cmd = XGBE_I2C_CMD_WRITE; 467 i2c_op.target = target; 468 i2c_op.len = val_len; 469 i2c_op.buf = val; 470 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op); 471 if ((ret == -EAGAIN) && retry--) 472 goto again; 473 474 return ret; 475 } 476 477 static int xgbe_phy_i2c_read(struct xgbe_prv_data *pdata, unsigned int target, 478 void *reg, unsigned int reg_len, 479 void *val, unsigned int val_len) 480 { 481 struct xgbe_i2c_op i2c_op; 482 int retry, ret; 483 484 retry = 1; 485 again1: 486 /* Set the specified register to read */ 487 i2c_op.cmd = XGBE_I2C_CMD_WRITE; 488 i2c_op.target = target; 489 i2c_op.len = reg_len; 490 i2c_op.buf = reg; 491 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op); 492 if (ret) { 493 if ((ret == -EAGAIN) && retry--) 494 goto again1; 495 496 return ret; 497 } 498 499 retry = 1; 500 again2: 501 /* Read the specfied register */ 502 i2c_op.cmd = XGBE_I2C_CMD_READ; 503 i2c_op.target = target; 504 i2c_op.len = val_len; 505 i2c_op.buf = val; 506 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op); 507 if ((ret == -EAGAIN) && retry--) 508 goto again2; 509 510 return ret; 511 } 512 513 static int xgbe_phy_sfp_put_mux(struct xgbe_prv_data *pdata) 514 { 515 struct xgbe_phy_data *phy_data = pdata->phy_data; 516 struct xgbe_i2c_op i2c_op; 517 u8 mux_channel; 518 519 if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT) 520 return 0; 521 522 /* Select no mux channels */ 523 mux_channel = 0; 524 i2c_op.cmd = XGBE_I2C_CMD_WRITE; 525 i2c_op.target = phy_data->sfp_mux_address; 526 i2c_op.len = sizeof(mux_channel); 527 i2c_op.buf = &mux_channel; 528 529 return xgbe_phy_i2c_xfer(pdata, &i2c_op); 530 } 531 532 static int xgbe_phy_sfp_get_mux(struct xgbe_prv_data *pdata) 533 { 534 struct xgbe_phy_data *phy_data = pdata->phy_data; 535 struct xgbe_i2c_op i2c_op; 536 u8 mux_channel; 537 538 if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT) 539 return 0; 540 541 /* Select desired mux channel */ 542 mux_channel = 1 << phy_data->sfp_mux_channel; 543 i2c_op.cmd = XGBE_I2C_CMD_WRITE; 544 i2c_op.target = phy_data->sfp_mux_address; 545 i2c_op.len = sizeof(mux_channel); 546 i2c_op.buf = &mux_channel; 547 548 return xgbe_phy_i2c_xfer(pdata, &i2c_op); 549 } 550 551 static void xgbe_phy_put_comm_ownership(struct xgbe_prv_data *pdata) 552 { 553 mutex_unlock(&xgbe_phy_comm_lock); 554 } 555 556 static int xgbe_phy_get_comm_ownership(struct xgbe_prv_data *pdata) 557 { 558 struct xgbe_phy_data *phy_data = pdata->phy_data; 559 unsigned long timeout; 560 unsigned int mutex_id; 561 562 /* The I2C and MDIO/GPIO bus is multiplexed between multiple devices, 563 * the driver needs to take the software mutex and then the hardware 564 * mutexes before being able to use the busses. 565 */ 566 mutex_lock(&xgbe_phy_comm_lock); 567 568 /* Clear the mutexes */ 569 XP_IOWRITE(pdata, XP_I2C_MUTEX, XGBE_MUTEX_RELEASE); 570 XP_IOWRITE(pdata, XP_MDIO_MUTEX, XGBE_MUTEX_RELEASE); 571 572 /* Mutex formats are the same for I2C and MDIO/GPIO */ 573 mutex_id = 0; 574 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ID, phy_data->port_id); 575 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ACTIVE, 1); 576 577 timeout = jiffies + (5 * HZ); 578 while (time_before(jiffies, timeout)) { 579 /* Must be all zeroes in order to obtain the mutex */ 580 if (XP_IOREAD(pdata, XP_I2C_MUTEX) || 581 XP_IOREAD(pdata, XP_MDIO_MUTEX)) { 582 usleep_range(100, 200); 583 continue; 584 } 585 586 /* Obtain the mutex */ 587 XP_IOWRITE(pdata, XP_I2C_MUTEX, mutex_id); 588 XP_IOWRITE(pdata, XP_MDIO_MUTEX, mutex_id); 589 590 return 0; 591 } 592 593 mutex_unlock(&xgbe_phy_comm_lock); 594 595 netdev_err(pdata->netdev, "unable to obtain hardware mutexes\n"); 596 597 return -ETIMEDOUT; 598 } 599 600 static int xgbe_phy_mdio_mii_write(struct xgbe_prv_data *pdata, int addr, 601 int reg, u16 val) 602 { 603 struct xgbe_phy_data *phy_data = pdata->phy_data; 604 605 if (reg & MII_ADDR_C45) { 606 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45) 607 return -ENOTSUPP; 608 } else { 609 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22) 610 return -ENOTSUPP; 611 } 612 613 return pdata->hw_if.write_ext_mii_regs(pdata, addr, reg, val); 614 } 615 616 static int xgbe_phy_i2c_mii_write(struct xgbe_prv_data *pdata, int reg, u16 val) 617 { 618 __be16 *mii_val; 619 u8 mii_data[3]; 620 int ret; 621 622 ret = xgbe_phy_sfp_get_mux(pdata); 623 if (ret) 624 return ret; 625 626 mii_data[0] = reg & 0xff; 627 mii_val = (__be16 *)&mii_data[1]; 628 *mii_val = cpu_to_be16(val); 629 630 ret = xgbe_phy_i2c_write(pdata, XGBE_SFP_PHY_ADDRESS, 631 mii_data, sizeof(mii_data)); 632 633 xgbe_phy_sfp_put_mux(pdata); 634 635 return ret; 636 } 637 638 static int xgbe_phy_mii_write(struct mii_bus *mii, int addr, int reg, u16 val) 639 { 640 struct xgbe_prv_data *pdata = mii->priv; 641 struct xgbe_phy_data *phy_data = pdata->phy_data; 642 int ret; 643 644 ret = xgbe_phy_get_comm_ownership(pdata); 645 if (ret) 646 return ret; 647 648 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP) 649 ret = xgbe_phy_i2c_mii_write(pdata, reg, val); 650 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO) 651 ret = xgbe_phy_mdio_mii_write(pdata, addr, reg, val); 652 else 653 ret = -ENOTSUPP; 654 655 xgbe_phy_put_comm_ownership(pdata); 656 657 return ret; 658 } 659 660 static int xgbe_phy_mdio_mii_read(struct xgbe_prv_data *pdata, int addr, 661 int reg) 662 { 663 struct xgbe_phy_data *phy_data = pdata->phy_data; 664 665 if (reg & MII_ADDR_C45) { 666 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45) 667 return -ENOTSUPP; 668 } else { 669 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22) 670 return -ENOTSUPP; 671 } 672 673 return pdata->hw_if.read_ext_mii_regs(pdata, addr, reg); 674 } 675 676 static int xgbe_phy_i2c_mii_read(struct xgbe_prv_data *pdata, int reg) 677 { 678 __be16 mii_val; 679 u8 mii_reg; 680 int ret; 681 682 ret = xgbe_phy_sfp_get_mux(pdata); 683 if (ret) 684 return ret; 685 686 mii_reg = reg; 687 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_PHY_ADDRESS, 688 &mii_reg, sizeof(mii_reg), 689 &mii_val, sizeof(mii_val)); 690 if (!ret) 691 ret = be16_to_cpu(mii_val); 692 693 xgbe_phy_sfp_put_mux(pdata); 694 695 return ret; 696 } 697 698 static int xgbe_phy_mii_read(struct mii_bus *mii, int addr, int reg) 699 { 700 struct xgbe_prv_data *pdata = mii->priv; 701 struct xgbe_phy_data *phy_data = pdata->phy_data; 702 int ret; 703 704 ret = xgbe_phy_get_comm_ownership(pdata); 705 if (ret) 706 return ret; 707 708 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP) 709 ret = xgbe_phy_i2c_mii_read(pdata, reg); 710 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO) 711 ret = xgbe_phy_mdio_mii_read(pdata, addr, reg); 712 else 713 ret = -ENOTSUPP; 714 715 xgbe_phy_put_comm_ownership(pdata); 716 717 return ret; 718 } 719 720 static void xgbe_phy_sfp_phy_settings(struct xgbe_prv_data *pdata) 721 { 722 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 723 struct xgbe_phy_data *phy_data = pdata->phy_data; 724 725 if (!phy_data->sfp_mod_absent && !phy_data->sfp_changed) 726 return; 727 728 XGBE_ZERO_SUP(lks); 729 730 if (phy_data->sfp_mod_absent) { 731 pdata->phy.speed = SPEED_UNKNOWN; 732 pdata->phy.duplex = DUPLEX_UNKNOWN; 733 pdata->phy.autoneg = AUTONEG_ENABLE; 734 pdata->phy.pause_autoneg = AUTONEG_ENABLE; 735 736 XGBE_SET_SUP(lks, Autoneg); 737 XGBE_SET_SUP(lks, Pause); 738 XGBE_SET_SUP(lks, Asym_Pause); 739 XGBE_SET_SUP(lks, TP); 740 XGBE_SET_SUP(lks, FIBRE); 741 742 XGBE_LM_COPY(lks, advertising, lks, supported); 743 744 return; 745 } 746 747 switch (phy_data->sfp_base) { 748 case XGBE_SFP_BASE_1000_T: 749 case XGBE_SFP_BASE_1000_SX: 750 case XGBE_SFP_BASE_1000_LX: 751 case XGBE_SFP_BASE_1000_CX: 752 pdata->phy.speed = SPEED_UNKNOWN; 753 pdata->phy.duplex = DUPLEX_UNKNOWN; 754 pdata->phy.autoneg = AUTONEG_ENABLE; 755 pdata->phy.pause_autoneg = AUTONEG_ENABLE; 756 XGBE_SET_SUP(lks, Autoneg); 757 XGBE_SET_SUP(lks, Pause); 758 XGBE_SET_SUP(lks, Asym_Pause); 759 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T) { 760 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) 761 XGBE_SET_SUP(lks, 100baseT_Full); 762 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) 763 XGBE_SET_SUP(lks, 1000baseT_Full); 764 } else { 765 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) 766 XGBE_SET_SUP(lks, 1000baseX_Full); 767 } 768 break; 769 case XGBE_SFP_BASE_10000_SR: 770 case XGBE_SFP_BASE_10000_LR: 771 case XGBE_SFP_BASE_10000_LRM: 772 case XGBE_SFP_BASE_10000_ER: 773 case XGBE_SFP_BASE_10000_CR: 774 pdata->phy.speed = SPEED_10000; 775 pdata->phy.duplex = DUPLEX_FULL; 776 pdata->phy.autoneg = AUTONEG_DISABLE; 777 pdata->phy.pause_autoneg = AUTONEG_DISABLE; 778 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) { 779 switch (phy_data->sfp_base) { 780 case XGBE_SFP_BASE_10000_SR: 781 XGBE_SET_SUP(lks, 10000baseSR_Full); 782 break; 783 case XGBE_SFP_BASE_10000_LR: 784 XGBE_SET_SUP(lks, 10000baseLR_Full); 785 break; 786 case XGBE_SFP_BASE_10000_LRM: 787 XGBE_SET_SUP(lks, 10000baseLRM_Full); 788 break; 789 case XGBE_SFP_BASE_10000_ER: 790 XGBE_SET_SUP(lks, 10000baseER_Full); 791 break; 792 case XGBE_SFP_BASE_10000_CR: 793 XGBE_SET_SUP(lks, 10000baseCR_Full); 794 break; 795 default: 796 break; 797 } 798 } 799 break; 800 default: 801 pdata->phy.speed = SPEED_UNKNOWN; 802 pdata->phy.duplex = DUPLEX_UNKNOWN; 803 pdata->phy.autoneg = AUTONEG_DISABLE; 804 pdata->phy.pause_autoneg = AUTONEG_DISABLE; 805 break; 806 } 807 808 switch (phy_data->sfp_base) { 809 case XGBE_SFP_BASE_1000_T: 810 case XGBE_SFP_BASE_1000_CX: 811 case XGBE_SFP_BASE_10000_CR: 812 XGBE_SET_SUP(lks, TP); 813 break; 814 default: 815 XGBE_SET_SUP(lks, FIBRE); 816 break; 817 } 818 819 XGBE_LM_COPY(lks, advertising, lks, supported); 820 } 821 822 static bool xgbe_phy_sfp_bit_rate(struct xgbe_sfp_eeprom *sfp_eeprom, 823 enum xgbe_sfp_speed sfp_speed) 824 { 825 u8 *sfp_base, min, max; 826 827 sfp_base = sfp_eeprom->base; 828 829 switch (sfp_speed) { 830 case XGBE_SFP_SPEED_1000: 831 min = XGBE_SFP_BASE_BR_1GBE_MIN; 832 max = XGBE_SFP_BASE_BR_1GBE_MAX; 833 break; 834 case XGBE_SFP_SPEED_10000: 835 min = XGBE_SFP_BASE_BR_10GBE_MIN; 836 max = XGBE_SFP_BASE_BR_10GBE_MAX; 837 break; 838 default: 839 return false; 840 } 841 842 return ((sfp_base[XGBE_SFP_BASE_BR] >= min) && 843 (sfp_base[XGBE_SFP_BASE_BR] <= max)); 844 } 845 846 static void xgbe_phy_free_phy_device(struct xgbe_prv_data *pdata) 847 { 848 struct xgbe_phy_data *phy_data = pdata->phy_data; 849 850 if (phy_data->phydev) { 851 phy_detach(phy_data->phydev); 852 phy_device_remove(phy_data->phydev); 853 phy_device_free(phy_data->phydev); 854 phy_data->phydev = NULL; 855 } 856 } 857 858 static bool xgbe_phy_finisar_phy_quirks(struct xgbe_prv_data *pdata) 859 { 860 struct xgbe_phy_data *phy_data = pdata->phy_data; 861 unsigned int phy_id = phy_data->phydev->phy_id; 862 863 if (phy_data->port_mode != XGBE_PORT_MODE_SFP) 864 return false; 865 866 if ((phy_id & 0xfffffff0) != 0x01ff0cc0) 867 return false; 868 869 /* Enable Base-T AN */ 870 phy_write(phy_data->phydev, 0x16, 0x0001); 871 phy_write(phy_data->phydev, 0x00, 0x9140); 872 phy_write(phy_data->phydev, 0x16, 0x0000); 873 874 /* Enable SGMII at 100Base-T/1000Base-T Full Duplex */ 875 phy_write(phy_data->phydev, 0x1b, 0x9084); 876 phy_write(phy_data->phydev, 0x09, 0x0e00); 877 phy_write(phy_data->phydev, 0x00, 0x8140); 878 phy_write(phy_data->phydev, 0x04, 0x0d01); 879 phy_write(phy_data->phydev, 0x00, 0x9140); 880 881 phy_data->phydev->supported = PHY_10BT_FEATURES | 882 PHY_100BT_FEATURES | 883 PHY_1000BT_FEATURES; 884 phy_support_asym_pause(phy_data->phydev); 885 886 netif_dbg(pdata, drv, pdata->netdev, 887 "Finisar PHY quirk in place\n"); 888 889 return true; 890 } 891 892 static bool xgbe_phy_belfuse_phy_quirks(struct xgbe_prv_data *pdata) 893 { 894 struct xgbe_phy_data *phy_data = pdata->phy_data; 895 struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom; 896 unsigned int phy_id = phy_data->phydev->phy_id; 897 int reg; 898 899 if (phy_data->port_mode != XGBE_PORT_MODE_SFP) 900 return false; 901 902 if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME], 903 XGBE_BEL_FUSE_VENDOR, XGBE_SFP_BASE_VENDOR_NAME_LEN)) 904 return false; 905 906 /* For Bel-Fuse, use the extra AN flag */ 907 pdata->an_again = 1; 908 909 if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN], 910 XGBE_BEL_FUSE_PARTNO, XGBE_SFP_BASE_VENDOR_PN_LEN)) 911 return false; 912 913 if ((phy_id & 0xfffffff0) != 0x03625d10) 914 return false; 915 916 /* Disable RGMII mode */ 917 phy_write(phy_data->phydev, 0x18, 0x7007); 918 reg = phy_read(phy_data->phydev, 0x18); 919 phy_write(phy_data->phydev, 0x18, reg & ~0x0080); 920 921 /* Enable fiber register bank */ 922 phy_write(phy_data->phydev, 0x1c, 0x7c00); 923 reg = phy_read(phy_data->phydev, 0x1c); 924 reg &= 0x03ff; 925 reg &= ~0x0001; 926 phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg | 0x0001); 927 928 /* Power down SerDes */ 929 reg = phy_read(phy_data->phydev, 0x00); 930 phy_write(phy_data->phydev, 0x00, reg | 0x00800); 931 932 /* Configure SGMII-to-Copper mode */ 933 phy_write(phy_data->phydev, 0x1c, 0x7c00); 934 reg = phy_read(phy_data->phydev, 0x1c); 935 reg &= 0x03ff; 936 reg &= ~0x0006; 937 phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg | 0x0004); 938 939 /* Power up SerDes */ 940 reg = phy_read(phy_data->phydev, 0x00); 941 phy_write(phy_data->phydev, 0x00, reg & ~0x00800); 942 943 /* Enable copper register bank */ 944 phy_write(phy_data->phydev, 0x1c, 0x7c00); 945 reg = phy_read(phy_data->phydev, 0x1c); 946 reg &= 0x03ff; 947 reg &= ~0x0001; 948 phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg); 949 950 /* Power up SerDes */ 951 reg = phy_read(phy_data->phydev, 0x00); 952 phy_write(phy_data->phydev, 0x00, reg & ~0x00800); 953 954 phy_data->phydev->supported = (PHY_10BT_FEATURES | 955 PHY_100BT_FEATURES | 956 PHY_1000BT_FEATURES); 957 phy_support_asym_pause(phy_data->phydev); 958 959 netif_dbg(pdata, drv, pdata->netdev, 960 "BelFuse PHY quirk in place\n"); 961 962 return true; 963 } 964 965 static void xgbe_phy_external_phy_quirks(struct xgbe_prv_data *pdata) 966 { 967 if (xgbe_phy_belfuse_phy_quirks(pdata)) 968 return; 969 970 if (xgbe_phy_finisar_phy_quirks(pdata)) 971 return; 972 } 973 974 static int xgbe_phy_find_phy_device(struct xgbe_prv_data *pdata) 975 { 976 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 977 struct xgbe_phy_data *phy_data = pdata->phy_data; 978 struct phy_device *phydev; 979 u32 advertising; 980 int ret; 981 982 /* If we already have a PHY, just return */ 983 if (phy_data->phydev) 984 return 0; 985 986 /* Clear the extra AN flag */ 987 pdata->an_again = 0; 988 989 /* Check for the use of an external PHY */ 990 if (phy_data->phydev_mode == XGBE_MDIO_MODE_NONE) 991 return 0; 992 993 /* For SFP, only use an external PHY if available */ 994 if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) && 995 !phy_data->sfp_phy_avail) 996 return 0; 997 998 /* Set the proper MDIO mode for the PHY */ 999 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr, 1000 phy_data->phydev_mode); 1001 if (ret) { 1002 netdev_err(pdata->netdev, 1003 "mdio port/clause not compatible (%u/%u)\n", 1004 phy_data->mdio_addr, phy_data->phydev_mode); 1005 return ret; 1006 } 1007 1008 /* Create and connect to the PHY device */ 1009 phydev = get_phy_device(phy_data->mii, phy_data->mdio_addr, 1010 (phy_data->phydev_mode == XGBE_MDIO_MODE_CL45)); 1011 if (IS_ERR(phydev)) { 1012 netdev_err(pdata->netdev, "get_phy_device failed\n"); 1013 return -ENODEV; 1014 } 1015 netif_dbg(pdata, drv, pdata->netdev, "external PHY id is %#010x\n", 1016 phydev->phy_id); 1017 1018 /*TODO: If c45, add request_module based on one of the MMD ids? */ 1019 1020 ret = phy_device_register(phydev); 1021 if (ret) { 1022 netdev_err(pdata->netdev, "phy_device_register failed\n"); 1023 phy_device_free(phydev); 1024 return ret; 1025 } 1026 1027 ret = phy_attach_direct(pdata->netdev, phydev, phydev->dev_flags, 1028 PHY_INTERFACE_MODE_SGMII); 1029 if (ret) { 1030 netdev_err(pdata->netdev, "phy_attach_direct failed\n"); 1031 phy_device_remove(phydev); 1032 phy_device_free(phydev); 1033 return ret; 1034 } 1035 phy_data->phydev = phydev; 1036 1037 xgbe_phy_external_phy_quirks(pdata); 1038 1039 ethtool_convert_link_mode_to_legacy_u32(&advertising, 1040 lks->link_modes.advertising); 1041 phydev->advertising &= advertising; 1042 1043 phy_start_aneg(phy_data->phydev); 1044 1045 return 0; 1046 } 1047 1048 static void xgbe_phy_sfp_external_phy(struct xgbe_prv_data *pdata) 1049 { 1050 struct xgbe_phy_data *phy_data = pdata->phy_data; 1051 int ret; 1052 1053 if (!phy_data->sfp_changed) 1054 return; 1055 1056 phy_data->sfp_phy_avail = 0; 1057 1058 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T) 1059 return; 1060 1061 /* Check access to the PHY by reading CTRL1 */ 1062 ret = xgbe_phy_i2c_mii_read(pdata, MII_BMCR); 1063 if (ret < 0) 1064 return; 1065 1066 /* Successfully accessed the PHY */ 1067 phy_data->sfp_phy_avail = 1; 1068 } 1069 1070 static bool xgbe_phy_check_sfp_rx_los(struct xgbe_phy_data *phy_data) 1071 { 1072 u8 *sfp_extd = phy_data->sfp_eeprom.extd; 1073 1074 if (!(sfp_extd[XGBE_SFP_EXTD_OPT1] & XGBE_SFP_EXTD_OPT1_RX_LOS)) 1075 return false; 1076 1077 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_RX_LOS) 1078 return false; 1079 1080 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_rx_los)) 1081 return true; 1082 1083 return false; 1084 } 1085 1086 static bool xgbe_phy_check_sfp_tx_fault(struct xgbe_phy_data *phy_data) 1087 { 1088 u8 *sfp_extd = phy_data->sfp_eeprom.extd; 1089 1090 if (!(sfp_extd[XGBE_SFP_EXTD_OPT1] & XGBE_SFP_EXTD_OPT1_TX_FAULT)) 1091 return false; 1092 1093 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_TX_FAULT) 1094 return false; 1095 1096 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_tx_fault)) 1097 return true; 1098 1099 return false; 1100 } 1101 1102 static bool xgbe_phy_check_sfp_mod_absent(struct xgbe_phy_data *phy_data) 1103 { 1104 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_MOD_ABSENT) 1105 return false; 1106 1107 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_mod_absent)) 1108 return true; 1109 1110 return false; 1111 } 1112 1113 static void xgbe_phy_sfp_parse_eeprom(struct xgbe_prv_data *pdata) 1114 { 1115 struct xgbe_phy_data *phy_data = pdata->phy_data; 1116 struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom; 1117 u8 *sfp_base; 1118 1119 sfp_base = sfp_eeprom->base; 1120 1121 if (sfp_base[XGBE_SFP_BASE_ID] != XGBE_SFP_ID_SFP) 1122 return; 1123 1124 if (sfp_base[XGBE_SFP_BASE_EXT_ID] != XGBE_SFP_EXT_ID_SFP) 1125 return; 1126 1127 /* Update transceiver signals (eeprom extd/options) */ 1128 phy_data->sfp_tx_fault = xgbe_phy_check_sfp_tx_fault(phy_data); 1129 phy_data->sfp_rx_los = xgbe_phy_check_sfp_rx_los(phy_data); 1130 1131 /* Assume ACTIVE cable unless told it is PASSIVE */ 1132 if (sfp_base[XGBE_SFP_BASE_CABLE] & XGBE_SFP_BASE_CABLE_PASSIVE) { 1133 phy_data->sfp_cable = XGBE_SFP_CABLE_PASSIVE; 1134 phy_data->sfp_cable_len = sfp_base[XGBE_SFP_BASE_CU_CABLE_LEN]; 1135 } else { 1136 phy_data->sfp_cable = XGBE_SFP_CABLE_ACTIVE; 1137 } 1138 1139 /* Determine the type of SFP */ 1140 if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_SR) 1141 phy_data->sfp_base = XGBE_SFP_BASE_10000_SR; 1142 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LR) 1143 phy_data->sfp_base = XGBE_SFP_BASE_10000_LR; 1144 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LRM) 1145 phy_data->sfp_base = XGBE_SFP_BASE_10000_LRM; 1146 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_ER) 1147 phy_data->sfp_base = XGBE_SFP_BASE_10000_ER; 1148 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_SX) 1149 phy_data->sfp_base = XGBE_SFP_BASE_1000_SX; 1150 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_LX) 1151 phy_data->sfp_base = XGBE_SFP_BASE_1000_LX; 1152 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_CX) 1153 phy_data->sfp_base = XGBE_SFP_BASE_1000_CX; 1154 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_T) 1155 phy_data->sfp_base = XGBE_SFP_BASE_1000_T; 1156 else if ((phy_data->sfp_cable == XGBE_SFP_CABLE_PASSIVE) && 1157 xgbe_phy_sfp_bit_rate(sfp_eeprom, XGBE_SFP_SPEED_10000)) 1158 phy_data->sfp_base = XGBE_SFP_BASE_10000_CR; 1159 1160 switch (phy_data->sfp_base) { 1161 case XGBE_SFP_BASE_1000_T: 1162 phy_data->sfp_speed = XGBE_SFP_SPEED_100_1000; 1163 break; 1164 case XGBE_SFP_BASE_1000_SX: 1165 case XGBE_SFP_BASE_1000_LX: 1166 case XGBE_SFP_BASE_1000_CX: 1167 phy_data->sfp_speed = XGBE_SFP_SPEED_1000; 1168 break; 1169 case XGBE_SFP_BASE_10000_SR: 1170 case XGBE_SFP_BASE_10000_LR: 1171 case XGBE_SFP_BASE_10000_LRM: 1172 case XGBE_SFP_BASE_10000_ER: 1173 case XGBE_SFP_BASE_10000_CR: 1174 phy_data->sfp_speed = XGBE_SFP_SPEED_10000; 1175 break; 1176 default: 1177 break; 1178 } 1179 } 1180 1181 static void xgbe_phy_sfp_eeprom_info(struct xgbe_prv_data *pdata, 1182 struct xgbe_sfp_eeprom *sfp_eeprom) 1183 { 1184 struct xgbe_sfp_ascii sfp_ascii; 1185 char *sfp_data = (char *)&sfp_ascii; 1186 1187 netif_dbg(pdata, drv, pdata->netdev, "SFP detected:\n"); 1188 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME], 1189 XGBE_SFP_BASE_VENDOR_NAME_LEN); 1190 sfp_data[XGBE_SFP_BASE_VENDOR_NAME_LEN] = '\0'; 1191 netif_dbg(pdata, drv, pdata->netdev, " vendor: %s\n", 1192 sfp_data); 1193 1194 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN], 1195 XGBE_SFP_BASE_VENDOR_PN_LEN); 1196 sfp_data[XGBE_SFP_BASE_VENDOR_PN_LEN] = '\0'; 1197 netif_dbg(pdata, drv, pdata->netdev, " part number: %s\n", 1198 sfp_data); 1199 1200 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_REV], 1201 XGBE_SFP_BASE_VENDOR_REV_LEN); 1202 sfp_data[XGBE_SFP_BASE_VENDOR_REV_LEN] = '\0'; 1203 netif_dbg(pdata, drv, pdata->netdev, " revision level: %s\n", 1204 sfp_data); 1205 1206 memcpy(sfp_data, &sfp_eeprom->extd[XGBE_SFP_BASE_VENDOR_SN], 1207 XGBE_SFP_BASE_VENDOR_SN_LEN); 1208 sfp_data[XGBE_SFP_BASE_VENDOR_SN_LEN] = '\0'; 1209 netif_dbg(pdata, drv, pdata->netdev, " serial number: %s\n", 1210 sfp_data); 1211 } 1212 1213 static bool xgbe_phy_sfp_verify_eeprom(u8 cc_in, u8 *buf, unsigned int len) 1214 { 1215 u8 cc; 1216 1217 for (cc = 0; len; buf++, len--) 1218 cc += *buf; 1219 1220 return (cc == cc_in) ? true : false; 1221 } 1222 1223 static int xgbe_phy_sfp_read_eeprom(struct xgbe_prv_data *pdata) 1224 { 1225 struct xgbe_phy_data *phy_data = pdata->phy_data; 1226 struct xgbe_sfp_eeprom sfp_eeprom; 1227 u8 eeprom_addr; 1228 int ret; 1229 1230 ret = xgbe_phy_sfp_get_mux(pdata); 1231 if (ret) { 1232 dev_err_once(pdata->dev, "%s: I2C error setting SFP MUX\n", 1233 netdev_name(pdata->netdev)); 1234 return ret; 1235 } 1236 1237 /* Read the SFP serial ID eeprom */ 1238 eeprom_addr = 0; 1239 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_SERIAL_ID_ADDRESS, 1240 &eeprom_addr, sizeof(eeprom_addr), 1241 &sfp_eeprom, sizeof(sfp_eeprom)); 1242 if (ret) { 1243 dev_err_once(pdata->dev, "%s: I2C error reading SFP EEPROM\n", 1244 netdev_name(pdata->netdev)); 1245 goto put; 1246 } 1247 1248 /* Validate the contents read */ 1249 if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.base[XGBE_SFP_BASE_CC], 1250 sfp_eeprom.base, 1251 sizeof(sfp_eeprom.base) - 1)) { 1252 ret = -EINVAL; 1253 goto put; 1254 } 1255 1256 if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.extd[XGBE_SFP_EXTD_CC], 1257 sfp_eeprom.extd, 1258 sizeof(sfp_eeprom.extd) - 1)) { 1259 ret = -EINVAL; 1260 goto put; 1261 } 1262 1263 /* Check for an added or changed SFP */ 1264 if (memcmp(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom))) { 1265 phy_data->sfp_changed = 1; 1266 1267 if (netif_msg_drv(pdata)) 1268 xgbe_phy_sfp_eeprom_info(pdata, &sfp_eeprom); 1269 1270 memcpy(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom)); 1271 1272 xgbe_phy_free_phy_device(pdata); 1273 } else { 1274 phy_data->sfp_changed = 0; 1275 } 1276 1277 put: 1278 xgbe_phy_sfp_put_mux(pdata); 1279 1280 return ret; 1281 } 1282 1283 static void xgbe_phy_sfp_signals(struct xgbe_prv_data *pdata) 1284 { 1285 struct xgbe_phy_data *phy_data = pdata->phy_data; 1286 u8 gpio_reg, gpio_ports[2]; 1287 int ret; 1288 1289 /* Read the input port registers */ 1290 gpio_reg = 0; 1291 ret = xgbe_phy_i2c_read(pdata, phy_data->sfp_gpio_address, 1292 &gpio_reg, sizeof(gpio_reg), 1293 gpio_ports, sizeof(gpio_ports)); 1294 if (ret) { 1295 dev_err_once(pdata->dev, "%s: I2C error reading SFP GPIOs\n", 1296 netdev_name(pdata->netdev)); 1297 return; 1298 } 1299 1300 phy_data->sfp_gpio_inputs = (gpio_ports[1] << 8) | gpio_ports[0]; 1301 1302 phy_data->sfp_mod_absent = xgbe_phy_check_sfp_mod_absent(phy_data); 1303 } 1304 1305 static void xgbe_phy_sfp_mod_absent(struct xgbe_prv_data *pdata) 1306 { 1307 struct xgbe_phy_data *phy_data = pdata->phy_data; 1308 1309 xgbe_phy_free_phy_device(pdata); 1310 1311 phy_data->sfp_mod_absent = 1; 1312 phy_data->sfp_phy_avail = 0; 1313 memset(&phy_data->sfp_eeprom, 0, sizeof(phy_data->sfp_eeprom)); 1314 } 1315 1316 static void xgbe_phy_sfp_reset(struct xgbe_phy_data *phy_data) 1317 { 1318 phy_data->sfp_rx_los = 0; 1319 phy_data->sfp_tx_fault = 0; 1320 phy_data->sfp_mod_absent = 1; 1321 phy_data->sfp_base = XGBE_SFP_BASE_UNKNOWN; 1322 phy_data->sfp_cable = XGBE_SFP_CABLE_UNKNOWN; 1323 phy_data->sfp_speed = XGBE_SFP_SPEED_UNKNOWN; 1324 } 1325 1326 static void xgbe_phy_sfp_detect(struct xgbe_prv_data *pdata) 1327 { 1328 struct xgbe_phy_data *phy_data = pdata->phy_data; 1329 int ret; 1330 1331 /* Reset the SFP signals and info */ 1332 xgbe_phy_sfp_reset(phy_data); 1333 1334 ret = xgbe_phy_get_comm_ownership(pdata); 1335 if (ret) 1336 return; 1337 1338 /* Read the SFP signals and check for module presence */ 1339 xgbe_phy_sfp_signals(pdata); 1340 if (phy_data->sfp_mod_absent) { 1341 xgbe_phy_sfp_mod_absent(pdata); 1342 goto put; 1343 } 1344 1345 ret = xgbe_phy_sfp_read_eeprom(pdata); 1346 if (ret) { 1347 /* Treat any error as if there isn't an SFP plugged in */ 1348 xgbe_phy_sfp_reset(phy_data); 1349 xgbe_phy_sfp_mod_absent(pdata); 1350 goto put; 1351 } 1352 1353 xgbe_phy_sfp_parse_eeprom(pdata); 1354 1355 xgbe_phy_sfp_external_phy(pdata); 1356 1357 put: 1358 xgbe_phy_sfp_phy_settings(pdata); 1359 1360 xgbe_phy_put_comm_ownership(pdata); 1361 } 1362 1363 static int xgbe_phy_module_eeprom(struct xgbe_prv_data *pdata, 1364 struct ethtool_eeprom *eeprom, u8 *data) 1365 { 1366 struct xgbe_phy_data *phy_data = pdata->phy_data; 1367 u8 eeprom_addr, eeprom_data[XGBE_SFP_EEPROM_MAX]; 1368 struct xgbe_sfp_eeprom *sfp_eeprom; 1369 unsigned int i, j, rem; 1370 int ret; 1371 1372 rem = eeprom->len; 1373 1374 if (!eeprom->len) { 1375 ret = -EINVAL; 1376 goto done; 1377 } 1378 1379 if ((eeprom->offset + eeprom->len) > XGBE_SFP_EEPROM_MAX) { 1380 ret = -EINVAL; 1381 goto done; 1382 } 1383 1384 if (phy_data->port_mode != XGBE_PORT_MODE_SFP) { 1385 ret = -ENXIO; 1386 goto done; 1387 } 1388 1389 if (!netif_running(pdata->netdev)) { 1390 ret = -EIO; 1391 goto done; 1392 } 1393 1394 if (phy_data->sfp_mod_absent) { 1395 ret = -EIO; 1396 goto done; 1397 } 1398 1399 ret = xgbe_phy_get_comm_ownership(pdata); 1400 if (ret) { 1401 ret = -EIO; 1402 goto done; 1403 } 1404 1405 ret = xgbe_phy_sfp_get_mux(pdata); 1406 if (ret) { 1407 netdev_err(pdata->netdev, "I2C error setting SFP MUX\n"); 1408 ret = -EIO; 1409 goto put_own; 1410 } 1411 1412 /* Read the SFP serial ID eeprom */ 1413 eeprom_addr = 0; 1414 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_SERIAL_ID_ADDRESS, 1415 &eeprom_addr, sizeof(eeprom_addr), 1416 eeprom_data, XGBE_SFP_EEPROM_BASE_LEN); 1417 if (ret) { 1418 netdev_err(pdata->netdev, 1419 "I2C error reading SFP EEPROM\n"); 1420 ret = -EIO; 1421 goto put_mux; 1422 } 1423 1424 sfp_eeprom = (struct xgbe_sfp_eeprom *)eeprom_data; 1425 1426 if (XGBE_SFP_DIAGS_SUPPORTED(sfp_eeprom)) { 1427 /* Read the SFP diagnostic eeprom */ 1428 eeprom_addr = 0; 1429 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_DIAG_INFO_ADDRESS, 1430 &eeprom_addr, sizeof(eeprom_addr), 1431 eeprom_data + XGBE_SFP_EEPROM_BASE_LEN, 1432 XGBE_SFP_EEPROM_DIAG_LEN); 1433 if (ret) { 1434 netdev_err(pdata->netdev, 1435 "I2C error reading SFP DIAGS\n"); 1436 ret = -EIO; 1437 goto put_mux; 1438 } 1439 } 1440 1441 for (i = 0, j = eeprom->offset; i < eeprom->len; i++, j++) { 1442 if ((j >= XGBE_SFP_EEPROM_BASE_LEN) && 1443 !XGBE_SFP_DIAGS_SUPPORTED(sfp_eeprom)) 1444 break; 1445 1446 data[i] = eeprom_data[j]; 1447 rem--; 1448 } 1449 1450 put_mux: 1451 xgbe_phy_sfp_put_mux(pdata); 1452 1453 put_own: 1454 xgbe_phy_put_comm_ownership(pdata); 1455 1456 done: 1457 eeprom->len -= rem; 1458 1459 return ret; 1460 } 1461 1462 static int xgbe_phy_module_info(struct xgbe_prv_data *pdata, 1463 struct ethtool_modinfo *modinfo) 1464 { 1465 struct xgbe_phy_data *phy_data = pdata->phy_data; 1466 1467 if (phy_data->port_mode != XGBE_PORT_MODE_SFP) 1468 return -ENXIO; 1469 1470 if (!netif_running(pdata->netdev)) 1471 return -EIO; 1472 1473 if (phy_data->sfp_mod_absent) 1474 return -EIO; 1475 1476 if (XGBE_SFP_DIAGS_SUPPORTED(&phy_data->sfp_eeprom)) { 1477 modinfo->type = ETH_MODULE_SFF_8472; 1478 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 1479 } else { 1480 modinfo->type = ETH_MODULE_SFF_8079; 1481 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN; 1482 } 1483 1484 return 0; 1485 } 1486 1487 static void xgbe_phy_phydev_flowctrl(struct xgbe_prv_data *pdata) 1488 { 1489 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 1490 struct xgbe_phy_data *phy_data = pdata->phy_data; 1491 u16 lcl_adv = 0, rmt_adv = 0; 1492 u8 fc; 1493 1494 pdata->phy.tx_pause = 0; 1495 pdata->phy.rx_pause = 0; 1496 1497 if (!phy_data->phydev) 1498 return; 1499 1500 lcl_adv = ethtool_adv_to_lcl_adv_t(phy_data->phydev->advertising); 1501 1502 if (phy_data->phydev->pause) { 1503 XGBE_SET_LP_ADV(lks, Pause); 1504 rmt_adv |= LPA_PAUSE_CAP; 1505 } 1506 if (phy_data->phydev->asym_pause) { 1507 XGBE_SET_LP_ADV(lks, Asym_Pause); 1508 rmt_adv |= LPA_PAUSE_ASYM; 1509 } 1510 1511 fc = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv); 1512 if (fc & FLOW_CTRL_TX) 1513 pdata->phy.tx_pause = 1; 1514 if (fc & FLOW_CTRL_RX) 1515 pdata->phy.rx_pause = 1; 1516 } 1517 1518 static enum xgbe_mode xgbe_phy_an37_sgmii_outcome(struct xgbe_prv_data *pdata) 1519 { 1520 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 1521 enum xgbe_mode mode; 1522 1523 XGBE_SET_LP_ADV(lks, Autoneg); 1524 XGBE_SET_LP_ADV(lks, TP); 1525 1526 /* Use external PHY to determine flow control */ 1527 if (pdata->phy.pause_autoneg) 1528 xgbe_phy_phydev_flowctrl(pdata); 1529 1530 switch (pdata->an_status & XGBE_SGMII_AN_LINK_SPEED) { 1531 case XGBE_SGMII_AN_LINK_SPEED_100: 1532 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) { 1533 XGBE_SET_LP_ADV(lks, 100baseT_Full); 1534 mode = XGBE_MODE_SGMII_100; 1535 } else { 1536 /* Half-duplex not supported */ 1537 XGBE_SET_LP_ADV(lks, 100baseT_Half); 1538 mode = XGBE_MODE_UNKNOWN; 1539 } 1540 break; 1541 case XGBE_SGMII_AN_LINK_SPEED_1000: 1542 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) { 1543 XGBE_SET_LP_ADV(lks, 1000baseT_Full); 1544 mode = XGBE_MODE_SGMII_1000; 1545 } else { 1546 /* Half-duplex not supported */ 1547 XGBE_SET_LP_ADV(lks, 1000baseT_Half); 1548 mode = XGBE_MODE_UNKNOWN; 1549 } 1550 break; 1551 default: 1552 mode = XGBE_MODE_UNKNOWN; 1553 } 1554 1555 return mode; 1556 } 1557 1558 static enum xgbe_mode xgbe_phy_an37_outcome(struct xgbe_prv_data *pdata) 1559 { 1560 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 1561 enum xgbe_mode mode; 1562 unsigned int ad_reg, lp_reg; 1563 1564 XGBE_SET_LP_ADV(lks, Autoneg); 1565 XGBE_SET_LP_ADV(lks, FIBRE); 1566 1567 /* Compare Advertisement and Link Partner register */ 1568 ad_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE); 1569 lp_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_LP_ABILITY); 1570 if (lp_reg & 0x100) 1571 XGBE_SET_LP_ADV(lks, Pause); 1572 if (lp_reg & 0x80) 1573 XGBE_SET_LP_ADV(lks, Asym_Pause); 1574 1575 if (pdata->phy.pause_autoneg) { 1576 /* Set flow control based on auto-negotiation result */ 1577 pdata->phy.tx_pause = 0; 1578 pdata->phy.rx_pause = 0; 1579 1580 if (ad_reg & lp_reg & 0x100) { 1581 pdata->phy.tx_pause = 1; 1582 pdata->phy.rx_pause = 1; 1583 } else if (ad_reg & lp_reg & 0x80) { 1584 if (ad_reg & 0x100) 1585 pdata->phy.rx_pause = 1; 1586 else if (lp_reg & 0x100) 1587 pdata->phy.tx_pause = 1; 1588 } 1589 } 1590 1591 if (lp_reg & 0x20) 1592 XGBE_SET_LP_ADV(lks, 1000baseX_Full); 1593 1594 /* Half duplex is not supported */ 1595 ad_reg &= lp_reg; 1596 mode = (ad_reg & 0x20) ? XGBE_MODE_X : XGBE_MODE_UNKNOWN; 1597 1598 return mode; 1599 } 1600 1601 static enum xgbe_mode xgbe_phy_an73_redrv_outcome(struct xgbe_prv_data *pdata) 1602 { 1603 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 1604 struct xgbe_phy_data *phy_data = pdata->phy_data; 1605 enum xgbe_mode mode; 1606 unsigned int ad_reg, lp_reg; 1607 1608 XGBE_SET_LP_ADV(lks, Autoneg); 1609 XGBE_SET_LP_ADV(lks, Backplane); 1610 1611 /* Use external PHY to determine flow control */ 1612 if (pdata->phy.pause_autoneg) 1613 xgbe_phy_phydev_flowctrl(pdata); 1614 1615 /* Compare Advertisement and Link Partner register 2 */ 1616 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); 1617 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); 1618 if (lp_reg & 0x80) 1619 XGBE_SET_LP_ADV(lks, 10000baseKR_Full); 1620 if (lp_reg & 0x20) 1621 XGBE_SET_LP_ADV(lks, 1000baseKX_Full); 1622 1623 ad_reg &= lp_reg; 1624 if (ad_reg & 0x80) { 1625 switch (phy_data->port_mode) { 1626 case XGBE_PORT_MODE_BACKPLANE: 1627 mode = XGBE_MODE_KR; 1628 break; 1629 default: 1630 mode = XGBE_MODE_SFI; 1631 break; 1632 } 1633 } else if (ad_reg & 0x20) { 1634 switch (phy_data->port_mode) { 1635 case XGBE_PORT_MODE_BACKPLANE: 1636 mode = XGBE_MODE_KX_1000; 1637 break; 1638 case XGBE_PORT_MODE_1000BASE_X: 1639 mode = XGBE_MODE_X; 1640 break; 1641 case XGBE_PORT_MODE_SFP: 1642 switch (phy_data->sfp_base) { 1643 case XGBE_SFP_BASE_1000_T: 1644 if (phy_data->phydev && 1645 (phy_data->phydev->speed == SPEED_100)) 1646 mode = XGBE_MODE_SGMII_100; 1647 else 1648 mode = XGBE_MODE_SGMII_1000; 1649 break; 1650 case XGBE_SFP_BASE_1000_SX: 1651 case XGBE_SFP_BASE_1000_LX: 1652 case XGBE_SFP_BASE_1000_CX: 1653 default: 1654 mode = XGBE_MODE_X; 1655 break; 1656 } 1657 break; 1658 default: 1659 if (phy_data->phydev && 1660 (phy_data->phydev->speed == SPEED_100)) 1661 mode = XGBE_MODE_SGMII_100; 1662 else 1663 mode = XGBE_MODE_SGMII_1000; 1664 break; 1665 } 1666 } else { 1667 mode = XGBE_MODE_UNKNOWN; 1668 } 1669 1670 /* Compare Advertisement and Link Partner register 3 */ 1671 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); 1672 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); 1673 if (lp_reg & 0xc000) 1674 XGBE_SET_LP_ADV(lks, 10000baseR_FEC); 1675 1676 return mode; 1677 } 1678 1679 static enum xgbe_mode xgbe_phy_an73_outcome(struct xgbe_prv_data *pdata) 1680 { 1681 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 1682 enum xgbe_mode mode; 1683 unsigned int ad_reg, lp_reg; 1684 1685 XGBE_SET_LP_ADV(lks, Autoneg); 1686 XGBE_SET_LP_ADV(lks, Backplane); 1687 1688 /* Compare Advertisement and Link Partner register 1 */ 1689 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE); 1690 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA); 1691 if (lp_reg & 0x400) 1692 XGBE_SET_LP_ADV(lks, Pause); 1693 if (lp_reg & 0x800) 1694 XGBE_SET_LP_ADV(lks, Asym_Pause); 1695 1696 if (pdata->phy.pause_autoneg) { 1697 /* Set flow control based on auto-negotiation result */ 1698 pdata->phy.tx_pause = 0; 1699 pdata->phy.rx_pause = 0; 1700 1701 if (ad_reg & lp_reg & 0x400) { 1702 pdata->phy.tx_pause = 1; 1703 pdata->phy.rx_pause = 1; 1704 } else if (ad_reg & lp_reg & 0x800) { 1705 if (ad_reg & 0x400) 1706 pdata->phy.rx_pause = 1; 1707 else if (lp_reg & 0x400) 1708 pdata->phy.tx_pause = 1; 1709 } 1710 } 1711 1712 /* Compare Advertisement and Link Partner register 2 */ 1713 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); 1714 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); 1715 if (lp_reg & 0x80) 1716 XGBE_SET_LP_ADV(lks, 10000baseKR_Full); 1717 if (lp_reg & 0x20) 1718 XGBE_SET_LP_ADV(lks, 1000baseKX_Full); 1719 1720 ad_reg &= lp_reg; 1721 if (ad_reg & 0x80) 1722 mode = XGBE_MODE_KR; 1723 else if (ad_reg & 0x20) 1724 mode = XGBE_MODE_KX_1000; 1725 else 1726 mode = XGBE_MODE_UNKNOWN; 1727 1728 /* Compare Advertisement and Link Partner register 3 */ 1729 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); 1730 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); 1731 if (lp_reg & 0xc000) 1732 XGBE_SET_LP_ADV(lks, 10000baseR_FEC); 1733 1734 return mode; 1735 } 1736 1737 static enum xgbe_mode xgbe_phy_an_outcome(struct xgbe_prv_data *pdata) 1738 { 1739 switch (pdata->an_mode) { 1740 case XGBE_AN_MODE_CL73: 1741 return xgbe_phy_an73_outcome(pdata); 1742 case XGBE_AN_MODE_CL73_REDRV: 1743 return xgbe_phy_an73_redrv_outcome(pdata); 1744 case XGBE_AN_MODE_CL37: 1745 return xgbe_phy_an37_outcome(pdata); 1746 case XGBE_AN_MODE_CL37_SGMII: 1747 return xgbe_phy_an37_sgmii_outcome(pdata); 1748 default: 1749 return XGBE_MODE_UNKNOWN; 1750 } 1751 } 1752 1753 static void xgbe_phy_an_advertising(struct xgbe_prv_data *pdata, 1754 struct ethtool_link_ksettings *dlks) 1755 { 1756 struct ethtool_link_ksettings *slks = &pdata->phy.lks; 1757 struct xgbe_phy_data *phy_data = pdata->phy_data; 1758 1759 XGBE_LM_COPY(dlks, advertising, slks, advertising); 1760 1761 /* Without a re-driver, just return current advertising */ 1762 if (!phy_data->redrv) 1763 return; 1764 1765 /* With the KR re-driver we need to advertise a single speed */ 1766 XGBE_CLR_ADV(dlks, 1000baseKX_Full); 1767 XGBE_CLR_ADV(dlks, 10000baseKR_Full); 1768 1769 /* Advertise FEC support is present */ 1770 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 1771 XGBE_SET_ADV(dlks, 10000baseR_FEC); 1772 1773 switch (phy_data->port_mode) { 1774 case XGBE_PORT_MODE_BACKPLANE: 1775 XGBE_SET_ADV(dlks, 10000baseKR_Full); 1776 break; 1777 case XGBE_PORT_MODE_BACKPLANE_2500: 1778 XGBE_SET_ADV(dlks, 1000baseKX_Full); 1779 break; 1780 case XGBE_PORT_MODE_1000BASE_T: 1781 case XGBE_PORT_MODE_1000BASE_X: 1782 case XGBE_PORT_MODE_NBASE_T: 1783 XGBE_SET_ADV(dlks, 1000baseKX_Full); 1784 break; 1785 case XGBE_PORT_MODE_10GBASE_T: 1786 if (phy_data->phydev && 1787 (phy_data->phydev->speed == SPEED_10000)) 1788 XGBE_SET_ADV(dlks, 10000baseKR_Full); 1789 else 1790 XGBE_SET_ADV(dlks, 1000baseKX_Full); 1791 break; 1792 case XGBE_PORT_MODE_10GBASE_R: 1793 XGBE_SET_ADV(dlks, 10000baseKR_Full); 1794 break; 1795 case XGBE_PORT_MODE_SFP: 1796 switch (phy_data->sfp_base) { 1797 case XGBE_SFP_BASE_1000_T: 1798 case XGBE_SFP_BASE_1000_SX: 1799 case XGBE_SFP_BASE_1000_LX: 1800 case XGBE_SFP_BASE_1000_CX: 1801 XGBE_SET_ADV(dlks, 1000baseKX_Full); 1802 break; 1803 default: 1804 XGBE_SET_ADV(dlks, 10000baseKR_Full); 1805 break; 1806 } 1807 break; 1808 default: 1809 XGBE_SET_ADV(dlks, 10000baseKR_Full); 1810 break; 1811 } 1812 } 1813 1814 static int xgbe_phy_an_config(struct xgbe_prv_data *pdata) 1815 { 1816 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 1817 struct xgbe_phy_data *phy_data = pdata->phy_data; 1818 u32 advertising; 1819 int ret; 1820 1821 ret = xgbe_phy_find_phy_device(pdata); 1822 if (ret) 1823 return ret; 1824 1825 if (!phy_data->phydev) 1826 return 0; 1827 1828 ethtool_convert_link_mode_to_legacy_u32(&advertising, 1829 lks->link_modes.advertising); 1830 1831 phy_data->phydev->autoneg = pdata->phy.autoneg; 1832 phy_data->phydev->advertising = phy_data->phydev->supported & 1833 advertising; 1834 1835 if (pdata->phy.autoneg != AUTONEG_ENABLE) { 1836 phy_data->phydev->speed = pdata->phy.speed; 1837 phy_data->phydev->duplex = pdata->phy.duplex; 1838 } 1839 1840 ret = phy_start_aneg(phy_data->phydev); 1841 1842 return ret; 1843 } 1844 1845 static enum xgbe_an_mode xgbe_phy_an_sfp_mode(struct xgbe_phy_data *phy_data) 1846 { 1847 switch (phy_data->sfp_base) { 1848 case XGBE_SFP_BASE_1000_T: 1849 return XGBE_AN_MODE_CL37_SGMII; 1850 case XGBE_SFP_BASE_1000_SX: 1851 case XGBE_SFP_BASE_1000_LX: 1852 case XGBE_SFP_BASE_1000_CX: 1853 return XGBE_AN_MODE_CL37; 1854 default: 1855 return XGBE_AN_MODE_NONE; 1856 } 1857 } 1858 1859 static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata) 1860 { 1861 struct xgbe_phy_data *phy_data = pdata->phy_data; 1862 1863 /* A KR re-driver will always require CL73 AN */ 1864 if (phy_data->redrv) 1865 return XGBE_AN_MODE_CL73_REDRV; 1866 1867 switch (phy_data->port_mode) { 1868 case XGBE_PORT_MODE_BACKPLANE: 1869 return XGBE_AN_MODE_CL73; 1870 case XGBE_PORT_MODE_BACKPLANE_2500: 1871 return XGBE_AN_MODE_NONE; 1872 case XGBE_PORT_MODE_1000BASE_T: 1873 return XGBE_AN_MODE_CL37_SGMII; 1874 case XGBE_PORT_MODE_1000BASE_X: 1875 return XGBE_AN_MODE_CL37; 1876 case XGBE_PORT_MODE_NBASE_T: 1877 return XGBE_AN_MODE_CL37_SGMII; 1878 case XGBE_PORT_MODE_10GBASE_T: 1879 return XGBE_AN_MODE_CL73; 1880 case XGBE_PORT_MODE_10GBASE_R: 1881 return XGBE_AN_MODE_NONE; 1882 case XGBE_PORT_MODE_SFP: 1883 return xgbe_phy_an_sfp_mode(phy_data); 1884 default: 1885 return XGBE_AN_MODE_NONE; 1886 } 1887 } 1888 1889 static int xgbe_phy_set_redrv_mode_mdio(struct xgbe_prv_data *pdata, 1890 enum xgbe_phy_redrv_mode mode) 1891 { 1892 struct xgbe_phy_data *phy_data = pdata->phy_data; 1893 u16 redrv_reg, redrv_val; 1894 1895 redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000); 1896 redrv_val = (u16)mode; 1897 1898 return pdata->hw_if.write_ext_mii_regs(pdata, phy_data->redrv_addr, 1899 redrv_reg, redrv_val); 1900 } 1901 1902 static int xgbe_phy_set_redrv_mode_i2c(struct xgbe_prv_data *pdata, 1903 enum xgbe_phy_redrv_mode mode) 1904 { 1905 struct xgbe_phy_data *phy_data = pdata->phy_data; 1906 unsigned int redrv_reg; 1907 int ret; 1908 1909 /* Calculate the register to write */ 1910 redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000); 1911 1912 ret = xgbe_phy_redrv_write(pdata, redrv_reg, mode); 1913 1914 return ret; 1915 } 1916 1917 static void xgbe_phy_set_redrv_mode(struct xgbe_prv_data *pdata) 1918 { 1919 struct xgbe_phy_data *phy_data = pdata->phy_data; 1920 enum xgbe_phy_redrv_mode mode; 1921 int ret; 1922 1923 if (!phy_data->redrv) 1924 return; 1925 1926 mode = XGBE_PHY_REDRV_MODE_CX; 1927 if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) && 1928 (phy_data->sfp_base != XGBE_SFP_BASE_1000_CX) && 1929 (phy_data->sfp_base != XGBE_SFP_BASE_10000_CR)) 1930 mode = XGBE_PHY_REDRV_MODE_SR; 1931 1932 ret = xgbe_phy_get_comm_ownership(pdata); 1933 if (ret) 1934 return; 1935 1936 if (phy_data->redrv_if) 1937 xgbe_phy_set_redrv_mode_i2c(pdata, mode); 1938 else 1939 xgbe_phy_set_redrv_mode_mdio(pdata, mode); 1940 1941 xgbe_phy_put_comm_ownership(pdata); 1942 } 1943 1944 static void xgbe_phy_perform_ratechange(struct xgbe_prv_data *pdata, 1945 unsigned int cmd, unsigned int sub_cmd) 1946 { 1947 unsigned int s0 = 0; 1948 unsigned int wait; 1949 1950 /* Log if a previous command did not complete */ 1951 if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) 1952 netif_dbg(pdata, link, pdata->netdev, 1953 "firmware mailbox not ready for command\n"); 1954 1955 /* Construct the command */ 1956 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, cmd); 1957 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, sub_cmd); 1958 1959 /* Issue the command */ 1960 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0); 1961 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0); 1962 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1); 1963 1964 /* Wait for command to complete */ 1965 wait = XGBE_RATECHANGE_COUNT; 1966 while (wait--) { 1967 if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) 1968 return; 1969 1970 usleep_range(1000, 2000); 1971 } 1972 1973 netif_dbg(pdata, link, pdata->netdev, 1974 "firmware mailbox command did not complete\n"); 1975 } 1976 1977 static void xgbe_phy_rrc(struct xgbe_prv_data *pdata) 1978 { 1979 /* Receiver Reset Cycle */ 1980 xgbe_phy_perform_ratechange(pdata, 5, 0); 1981 1982 netif_dbg(pdata, link, pdata->netdev, "receiver reset complete\n"); 1983 } 1984 1985 static void xgbe_phy_power_off(struct xgbe_prv_data *pdata) 1986 { 1987 struct xgbe_phy_data *phy_data = pdata->phy_data; 1988 1989 /* Power off */ 1990 xgbe_phy_perform_ratechange(pdata, 0, 0); 1991 1992 phy_data->cur_mode = XGBE_MODE_UNKNOWN; 1993 1994 netif_dbg(pdata, link, pdata->netdev, "phy powered off\n"); 1995 } 1996 1997 static void xgbe_phy_sfi_mode(struct xgbe_prv_data *pdata) 1998 { 1999 struct xgbe_phy_data *phy_data = pdata->phy_data; 2000 2001 xgbe_phy_set_redrv_mode(pdata); 2002 2003 /* 10G/SFI */ 2004 if (phy_data->sfp_cable != XGBE_SFP_CABLE_PASSIVE) { 2005 xgbe_phy_perform_ratechange(pdata, 3, 0); 2006 } else { 2007 if (phy_data->sfp_cable_len <= 1) 2008 xgbe_phy_perform_ratechange(pdata, 3, 1); 2009 else if (phy_data->sfp_cable_len <= 3) 2010 xgbe_phy_perform_ratechange(pdata, 3, 2); 2011 else 2012 xgbe_phy_perform_ratechange(pdata, 3, 3); 2013 } 2014 2015 phy_data->cur_mode = XGBE_MODE_SFI; 2016 2017 netif_dbg(pdata, link, pdata->netdev, "10GbE SFI mode set\n"); 2018 } 2019 2020 static void xgbe_phy_x_mode(struct xgbe_prv_data *pdata) 2021 { 2022 struct xgbe_phy_data *phy_data = pdata->phy_data; 2023 2024 xgbe_phy_set_redrv_mode(pdata); 2025 2026 /* 1G/X */ 2027 xgbe_phy_perform_ratechange(pdata, 1, 3); 2028 2029 phy_data->cur_mode = XGBE_MODE_X; 2030 2031 netif_dbg(pdata, link, pdata->netdev, "1GbE X mode set\n"); 2032 } 2033 2034 static void xgbe_phy_sgmii_1000_mode(struct xgbe_prv_data *pdata) 2035 { 2036 struct xgbe_phy_data *phy_data = pdata->phy_data; 2037 2038 xgbe_phy_set_redrv_mode(pdata); 2039 2040 /* 1G/SGMII */ 2041 xgbe_phy_perform_ratechange(pdata, 1, 2); 2042 2043 phy_data->cur_mode = XGBE_MODE_SGMII_1000; 2044 2045 netif_dbg(pdata, link, pdata->netdev, "1GbE SGMII mode set\n"); 2046 } 2047 2048 static void xgbe_phy_sgmii_100_mode(struct xgbe_prv_data *pdata) 2049 { 2050 struct xgbe_phy_data *phy_data = pdata->phy_data; 2051 2052 xgbe_phy_set_redrv_mode(pdata); 2053 2054 /* 100M/SGMII */ 2055 xgbe_phy_perform_ratechange(pdata, 1, 1); 2056 2057 phy_data->cur_mode = XGBE_MODE_SGMII_100; 2058 2059 netif_dbg(pdata, link, pdata->netdev, "100MbE SGMII mode set\n"); 2060 } 2061 2062 static void xgbe_phy_kr_mode(struct xgbe_prv_data *pdata) 2063 { 2064 struct xgbe_phy_data *phy_data = pdata->phy_data; 2065 2066 xgbe_phy_set_redrv_mode(pdata); 2067 2068 /* 10G/KR */ 2069 xgbe_phy_perform_ratechange(pdata, 4, 0); 2070 2071 phy_data->cur_mode = XGBE_MODE_KR; 2072 2073 netif_dbg(pdata, link, pdata->netdev, "10GbE KR mode set\n"); 2074 } 2075 2076 static void xgbe_phy_kx_2500_mode(struct xgbe_prv_data *pdata) 2077 { 2078 struct xgbe_phy_data *phy_data = pdata->phy_data; 2079 2080 xgbe_phy_set_redrv_mode(pdata); 2081 2082 /* 2.5G/KX */ 2083 xgbe_phy_perform_ratechange(pdata, 2, 0); 2084 2085 phy_data->cur_mode = XGBE_MODE_KX_2500; 2086 2087 netif_dbg(pdata, link, pdata->netdev, "2.5GbE KX mode set\n"); 2088 } 2089 2090 static void xgbe_phy_kx_1000_mode(struct xgbe_prv_data *pdata) 2091 { 2092 struct xgbe_phy_data *phy_data = pdata->phy_data; 2093 2094 xgbe_phy_set_redrv_mode(pdata); 2095 2096 /* 1G/KX */ 2097 xgbe_phy_perform_ratechange(pdata, 1, 3); 2098 2099 phy_data->cur_mode = XGBE_MODE_KX_1000; 2100 2101 netif_dbg(pdata, link, pdata->netdev, "1GbE KX mode set\n"); 2102 } 2103 2104 static enum xgbe_mode xgbe_phy_cur_mode(struct xgbe_prv_data *pdata) 2105 { 2106 struct xgbe_phy_data *phy_data = pdata->phy_data; 2107 2108 return phy_data->cur_mode; 2109 } 2110 2111 static enum xgbe_mode xgbe_phy_switch_baset_mode(struct xgbe_prv_data *pdata) 2112 { 2113 struct xgbe_phy_data *phy_data = pdata->phy_data; 2114 2115 /* No switching if not 10GBase-T */ 2116 if (phy_data->port_mode != XGBE_PORT_MODE_10GBASE_T) 2117 return xgbe_phy_cur_mode(pdata); 2118 2119 switch (xgbe_phy_cur_mode(pdata)) { 2120 case XGBE_MODE_SGMII_100: 2121 case XGBE_MODE_SGMII_1000: 2122 return XGBE_MODE_KR; 2123 case XGBE_MODE_KR: 2124 default: 2125 return XGBE_MODE_SGMII_1000; 2126 } 2127 } 2128 2129 static enum xgbe_mode xgbe_phy_switch_bp_2500_mode(struct xgbe_prv_data *pdata) 2130 { 2131 return XGBE_MODE_KX_2500; 2132 } 2133 2134 static enum xgbe_mode xgbe_phy_switch_bp_mode(struct xgbe_prv_data *pdata) 2135 { 2136 /* If we are in KR switch to KX, and vice-versa */ 2137 switch (xgbe_phy_cur_mode(pdata)) { 2138 case XGBE_MODE_KX_1000: 2139 return XGBE_MODE_KR; 2140 case XGBE_MODE_KR: 2141 default: 2142 return XGBE_MODE_KX_1000; 2143 } 2144 } 2145 2146 static enum xgbe_mode xgbe_phy_switch_mode(struct xgbe_prv_data *pdata) 2147 { 2148 struct xgbe_phy_data *phy_data = pdata->phy_data; 2149 2150 switch (phy_data->port_mode) { 2151 case XGBE_PORT_MODE_BACKPLANE: 2152 return xgbe_phy_switch_bp_mode(pdata); 2153 case XGBE_PORT_MODE_BACKPLANE_2500: 2154 return xgbe_phy_switch_bp_2500_mode(pdata); 2155 case XGBE_PORT_MODE_1000BASE_T: 2156 case XGBE_PORT_MODE_NBASE_T: 2157 case XGBE_PORT_MODE_10GBASE_T: 2158 return xgbe_phy_switch_baset_mode(pdata); 2159 case XGBE_PORT_MODE_1000BASE_X: 2160 case XGBE_PORT_MODE_10GBASE_R: 2161 case XGBE_PORT_MODE_SFP: 2162 /* No switching, so just return current mode */ 2163 return xgbe_phy_cur_mode(pdata); 2164 default: 2165 return XGBE_MODE_UNKNOWN; 2166 } 2167 } 2168 2169 static enum xgbe_mode xgbe_phy_get_basex_mode(struct xgbe_phy_data *phy_data, 2170 int speed) 2171 { 2172 switch (speed) { 2173 case SPEED_1000: 2174 return XGBE_MODE_X; 2175 case SPEED_10000: 2176 return XGBE_MODE_KR; 2177 default: 2178 return XGBE_MODE_UNKNOWN; 2179 } 2180 } 2181 2182 static enum xgbe_mode xgbe_phy_get_baset_mode(struct xgbe_phy_data *phy_data, 2183 int speed) 2184 { 2185 switch (speed) { 2186 case SPEED_100: 2187 return XGBE_MODE_SGMII_100; 2188 case SPEED_1000: 2189 return XGBE_MODE_SGMII_1000; 2190 case SPEED_2500: 2191 return XGBE_MODE_KX_2500; 2192 case SPEED_10000: 2193 return XGBE_MODE_KR; 2194 default: 2195 return XGBE_MODE_UNKNOWN; 2196 } 2197 } 2198 2199 static enum xgbe_mode xgbe_phy_get_sfp_mode(struct xgbe_phy_data *phy_data, 2200 int speed) 2201 { 2202 switch (speed) { 2203 case SPEED_100: 2204 return XGBE_MODE_SGMII_100; 2205 case SPEED_1000: 2206 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T) 2207 return XGBE_MODE_SGMII_1000; 2208 else 2209 return XGBE_MODE_X; 2210 case SPEED_10000: 2211 case SPEED_UNKNOWN: 2212 return XGBE_MODE_SFI; 2213 default: 2214 return XGBE_MODE_UNKNOWN; 2215 } 2216 } 2217 2218 static enum xgbe_mode xgbe_phy_get_bp_2500_mode(int speed) 2219 { 2220 switch (speed) { 2221 case SPEED_2500: 2222 return XGBE_MODE_KX_2500; 2223 default: 2224 return XGBE_MODE_UNKNOWN; 2225 } 2226 } 2227 2228 static enum xgbe_mode xgbe_phy_get_bp_mode(int speed) 2229 { 2230 switch (speed) { 2231 case SPEED_1000: 2232 return XGBE_MODE_KX_1000; 2233 case SPEED_10000: 2234 return XGBE_MODE_KR; 2235 default: 2236 return XGBE_MODE_UNKNOWN; 2237 } 2238 } 2239 2240 static enum xgbe_mode xgbe_phy_get_mode(struct xgbe_prv_data *pdata, 2241 int speed) 2242 { 2243 struct xgbe_phy_data *phy_data = pdata->phy_data; 2244 2245 switch (phy_data->port_mode) { 2246 case XGBE_PORT_MODE_BACKPLANE: 2247 return xgbe_phy_get_bp_mode(speed); 2248 case XGBE_PORT_MODE_BACKPLANE_2500: 2249 return xgbe_phy_get_bp_2500_mode(speed); 2250 case XGBE_PORT_MODE_1000BASE_T: 2251 case XGBE_PORT_MODE_NBASE_T: 2252 case XGBE_PORT_MODE_10GBASE_T: 2253 return xgbe_phy_get_baset_mode(phy_data, speed); 2254 case XGBE_PORT_MODE_1000BASE_X: 2255 case XGBE_PORT_MODE_10GBASE_R: 2256 return xgbe_phy_get_basex_mode(phy_data, speed); 2257 case XGBE_PORT_MODE_SFP: 2258 return xgbe_phy_get_sfp_mode(phy_data, speed); 2259 default: 2260 return XGBE_MODE_UNKNOWN; 2261 } 2262 } 2263 2264 static void xgbe_phy_set_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode) 2265 { 2266 switch (mode) { 2267 case XGBE_MODE_KX_1000: 2268 xgbe_phy_kx_1000_mode(pdata); 2269 break; 2270 case XGBE_MODE_KX_2500: 2271 xgbe_phy_kx_2500_mode(pdata); 2272 break; 2273 case XGBE_MODE_KR: 2274 xgbe_phy_kr_mode(pdata); 2275 break; 2276 case XGBE_MODE_SGMII_100: 2277 xgbe_phy_sgmii_100_mode(pdata); 2278 break; 2279 case XGBE_MODE_SGMII_1000: 2280 xgbe_phy_sgmii_1000_mode(pdata); 2281 break; 2282 case XGBE_MODE_X: 2283 xgbe_phy_x_mode(pdata); 2284 break; 2285 case XGBE_MODE_SFI: 2286 xgbe_phy_sfi_mode(pdata); 2287 break; 2288 default: 2289 break; 2290 } 2291 } 2292 2293 static bool xgbe_phy_check_mode(struct xgbe_prv_data *pdata, 2294 enum xgbe_mode mode, bool advert) 2295 { 2296 if (pdata->phy.autoneg == AUTONEG_ENABLE) { 2297 return advert; 2298 } else { 2299 enum xgbe_mode cur_mode; 2300 2301 cur_mode = xgbe_phy_get_mode(pdata, pdata->phy.speed); 2302 if (cur_mode == mode) 2303 return true; 2304 } 2305 2306 return false; 2307 } 2308 2309 static bool xgbe_phy_use_basex_mode(struct xgbe_prv_data *pdata, 2310 enum xgbe_mode mode) 2311 { 2312 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 2313 2314 switch (mode) { 2315 case XGBE_MODE_X: 2316 return xgbe_phy_check_mode(pdata, mode, 2317 XGBE_ADV(lks, 1000baseX_Full)); 2318 case XGBE_MODE_KR: 2319 return xgbe_phy_check_mode(pdata, mode, 2320 XGBE_ADV(lks, 10000baseKR_Full)); 2321 default: 2322 return false; 2323 } 2324 } 2325 2326 static bool xgbe_phy_use_baset_mode(struct xgbe_prv_data *pdata, 2327 enum xgbe_mode mode) 2328 { 2329 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 2330 2331 switch (mode) { 2332 case XGBE_MODE_SGMII_100: 2333 return xgbe_phy_check_mode(pdata, mode, 2334 XGBE_ADV(lks, 100baseT_Full)); 2335 case XGBE_MODE_SGMII_1000: 2336 return xgbe_phy_check_mode(pdata, mode, 2337 XGBE_ADV(lks, 1000baseT_Full)); 2338 case XGBE_MODE_KX_2500: 2339 return xgbe_phy_check_mode(pdata, mode, 2340 XGBE_ADV(lks, 2500baseT_Full)); 2341 case XGBE_MODE_KR: 2342 return xgbe_phy_check_mode(pdata, mode, 2343 XGBE_ADV(lks, 10000baseT_Full)); 2344 default: 2345 return false; 2346 } 2347 } 2348 2349 static bool xgbe_phy_use_sfp_mode(struct xgbe_prv_data *pdata, 2350 enum xgbe_mode mode) 2351 { 2352 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 2353 struct xgbe_phy_data *phy_data = pdata->phy_data; 2354 2355 switch (mode) { 2356 case XGBE_MODE_X: 2357 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T) 2358 return false; 2359 return xgbe_phy_check_mode(pdata, mode, 2360 XGBE_ADV(lks, 1000baseX_Full)); 2361 case XGBE_MODE_SGMII_100: 2362 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T) 2363 return false; 2364 return xgbe_phy_check_mode(pdata, mode, 2365 XGBE_ADV(lks, 100baseT_Full)); 2366 case XGBE_MODE_SGMII_1000: 2367 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T) 2368 return false; 2369 return xgbe_phy_check_mode(pdata, mode, 2370 XGBE_ADV(lks, 1000baseT_Full)); 2371 case XGBE_MODE_SFI: 2372 if (phy_data->sfp_mod_absent) 2373 return true; 2374 return xgbe_phy_check_mode(pdata, mode, 2375 XGBE_ADV(lks, 10000baseSR_Full) || 2376 XGBE_ADV(lks, 10000baseLR_Full) || 2377 XGBE_ADV(lks, 10000baseLRM_Full) || 2378 XGBE_ADV(lks, 10000baseER_Full) || 2379 XGBE_ADV(lks, 10000baseCR_Full)); 2380 default: 2381 return false; 2382 } 2383 } 2384 2385 static bool xgbe_phy_use_bp_2500_mode(struct xgbe_prv_data *pdata, 2386 enum xgbe_mode mode) 2387 { 2388 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 2389 2390 switch (mode) { 2391 case XGBE_MODE_KX_2500: 2392 return xgbe_phy_check_mode(pdata, mode, 2393 XGBE_ADV(lks, 2500baseX_Full)); 2394 default: 2395 return false; 2396 } 2397 } 2398 2399 static bool xgbe_phy_use_bp_mode(struct xgbe_prv_data *pdata, 2400 enum xgbe_mode mode) 2401 { 2402 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 2403 2404 switch (mode) { 2405 case XGBE_MODE_KX_1000: 2406 return xgbe_phy_check_mode(pdata, mode, 2407 XGBE_ADV(lks, 1000baseKX_Full)); 2408 case XGBE_MODE_KR: 2409 return xgbe_phy_check_mode(pdata, mode, 2410 XGBE_ADV(lks, 10000baseKR_Full)); 2411 default: 2412 return false; 2413 } 2414 } 2415 2416 static bool xgbe_phy_use_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode) 2417 { 2418 struct xgbe_phy_data *phy_data = pdata->phy_data; 2419 2420 switch (phy_data->port_mode) { 2421 case XGBE_PORT_MODE_BACKPLANE: 2422 return xgbe_phy_use_bp_mode(pdata, mode); 2423 case XGBE_PORT_MODE_BACKPLANE_2500: 2424 return xgbe_phy_use_bp_2500_mode(pdata, mode); 2425 case XGBE_PORT_MODE_1000BASE_T: 2426 case XGBE_PORT_MODE_NBASE_T: 2427 case XGBE_PORT_MODE_10GBASE_T: 2428 return xgbe_phy_use_baset_mode(pdata, mode); 2429 case XGBE_PORT_MODE_1000BASE_X: 2430 case XGBE_PORT_MODE_10GBASE_R: 2431 return xgbe_phy_use_basex_mode(pdata, mode); 2432 case XGBE_PORT_MODE_SFP: 2433 return xgbe_phy_use_sfp_mode(pdata, mode); 2434 default: 2435 return false; 2436 } 2437 } 2438 2439 static bool xgbe_phy_valid_speed_basex_mode(struct xgbe_phy_data *phy_data, 2440 int speed) 2441 { 2442 switch (speed) { 2443 case SPEED_1000: 2444 return (phy_data->port_mode == XGBE_PORT_MODE_1000BASE_X); 2445 case SPEED_10000: 2446 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_R); 2447 default: 2448 return false; 2449 } 2450 } 2451 2452 static bool xgbe_phy_valid_speed_baset_mode(struct xgbe_phy_data *phy_data, 2453 int speed) 2454 { 2455 switch (speed) { 2456 case SPEED_100: 2457 case SPEED_1000: 2458 return true; 2459 case SPEED_2500: 2460 return (phy_data->port_mode == XGBE_PORT_MODE_NBASE_T); 2461 case SPEED_10000: 2462 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_T); 2463 default: 2464 return false; 2465 } 2466 } 2467 2468 static bool xgbe_phy_valid_speed_sfp_mode(struct xgbe_phy_data *phy_data, 2469 int speed) 2470 { 2471 switch (speed) { 2472 case SPEED_100: 2473 return (phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000); 2474 case SPEED_1000: 2475 return ((phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000) || 2476 (phy_data->sfp_speed == XGBE_SFP_SPEED_1000)); 2477 case SPEED_10000: 2478 return (phy_data->sfp_speed == XGBE_SFP_SPEED_10000); 2479 default: 2480 return false; 2481 } 2482 } 2483 2484 static bool xgbe_phy_valid_speed_bp_2500_mode(int speed) 2485 { 2486 switch (speed) { 2487 case SPEED_2500: 2488 return true; 2489 default: 2490 return false; 2491 } 2492 } 2493 2494 static bool xgbe_phy_valid_speed_bp_mode(int speed) 2495 { 2496 switch (speed) { 2497 case SPEED_1000: 2498 case SPEED_10000: 2499 return true; 2500 default: 2501 return false; 2502 } 2503 } 2504 2505 static bool xgbe_phy_valid_speed(struct xgbe_prv_data *pdata, int speed) 2506 { 2507 struct xgbe_phy_data *phy_data = pdata->phy_data; 2508 2509 switch (phy_data->port_mode) { 2510 case XGBE_PORT_MODE_BACKPLANE: 2511 return xgbe_phy_valid_speed_bp_mode(speed); 2512 case XGBE_PORT_MODE_BACKPLANE_2500: 2513 return xgbe_phy_valid_speed_bp_2500_mode(speed); 2514 case XGBE_PORT_MODE_1000BASE_T: 2515 case XGBE_PORT_MODE_NBASE_T: 2516 case XGBE_PORT_MODE_10GBASE_T: 2517 return xgbe_phy_valid_speed_baset_mode(phy_data, speed); 2518 case XGBE_PORT_MODE_1000BASE_X: 2519 case XGBE_PORT_MODE_10GBASE_R: 2520 return xgbe_phy_valid_speed_basex_mode(phy_data, speed); 2521 case XGBE_PORT_MODE_SFP: 2522 return xgbe_phy_valid_speed_sfp_mode(phy_data, speed); 2523 default: 2524 return false; 2525 } 2526 } 2527 2528 static int xgbe_phy_link_status(struct xgbe_prv_data *pdata, int *an_restart) 2529 { 2530 struct xgbe_phy_data *phy_data = pdata->phy_data; 2531 unsigned int reg; 2532 int ret; 2533 2534 *an_restart = 0; 2535 2536 if (phy_data->port_mode == XGBE_PORT_MODE_SFP) { 2537 /* Check SFP signals */ 2538 xgbe_phy_sfp_detect(pdata); 2539 2540 if (phy_data->sfp_changed) { 2541 *an_restart = 1; 2542 return 0; 2543 } 2544 2545 if (phy_data->sfp_mod_absent || phy_data->sfp_rx_los) 2546 return 0; 2547 } 2548 2549 if (phy_data->phydev) { 2550 /* Check external PHY */ 2551 ret = phy_read_status(phy_data->phydev); 2552 if (ret < 0) 2553 return 0; 2554 2555 if ((pdata->phy.autoneg == AUTONEG_ENABLE) && 2556 !phy_aneg_done(phy_data->phydev)) 2557 return 0; 2558 2559 if (!phy_data->phydev->link) 2560 return 0; 2561 } 2562 2563 /* Link status is latched low, so read once to clear 2564 * and then read again to get current state 2565 */ 2566 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); 2567 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); 2568 if (reg & MDIO_STAT1_LSTATUS) 2569 return 1; 2570 2571 /* No link, attempt a receiver reset cycle */ 2572 if (phy_data->rrc_count++ > XGBE_RRC_FREQUENCY) { 2573 phy_data->rrc_count = 0; 2574 xgbe_phy_rrc(pdata); 2575 } 2576 2577 return 0; 2578 } 2579 2580 static void xgbe_phy_sfp_gpio_setup(struct xgbe_prv_data *pdata) 2581 { 2582 struct xgbe_phy_data *phy_data = pdata->phy_data; 2583 2584 phy_data->sfp_gpio_address = XGBE_GPIO_ADDRESS_PCA9555 + 2585 XP_GET_BITS(pdata->pp3, XP_PROP_3, 2586 GPIO_ADDR); 2587 2588 phy_data->sfp_gpio_mask = XP_GET_BITS(pdata->pp3, XP_PROP_3, 2589 GPIO_MASK); 2590 2591 phy_data->sfp_gpio_rx_los = XP_GET_BITS(pdata->pp3, XP_PROP_3, 2592 GPIO_RX_LOS); 2593 phy_data->sfp_gpio_tx_fault = XP_GET_BITS(pdata->pp3, XP_PROP_3, 2594 GPIO_TX_FAULT); 2595 phy_data->sfp_gpio_mod_absent = XP_GET_BITS(pdata->pp3, XP_PROP_3, 2596 GPIO_MOD_ABS); 2597 phy_data->sfp_gpio_rate_select = XP_GET_BITS(pdata->pp3, XP_PROP_3, 2598 GPIO_RATE_SELECT); 2599 2600 if (netif_msg_probe(pdata)) { 2601 dev_dbg(pdata->dev, "SFP: gpio_address=%#x\n", 2602 phy_data->sfp_gpio_address); 2603 dev_dbg(pdata->dev, "SFP: gpio_mask=%#x\n", 2604 phy_data->sfp_gpio_mask); 2605 dev_dbg(pdata->dev, "SFP: gpio_rx_los=%u\n", 2606 phy_data->sfp_gpio_rx_los); 2607 dev_dbg(pdata->dev, "SFP: gpio_tx_fault=%u\n", 2608 phy_data->sfp_gpio_tx_fault); 2609 dev_dbg(pdata->dev, "SFP: gpio_mod_absent=%u\n", 2610 phy_data->sfp_gpio_mod_absent); 2611 dev_dbg(pdata->dev, "SFP: gpio_rate_select=%u\n", 2612 phy_data->sfp_gpio_rate_select); 2613 } 2614 } 2615 2616 static void xgbe_phy_sfp_comm_setup(struct xgbe_prv_data *pdata) 2617 { 2618 struct xgbe_phy_data *phy_data = pdata->phy_data; 2619 unsigned int mux_addr_hi, mux_addr_lo; 2620 2621 mux_addr_hi = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_HI); 2622 mux_addr_lo = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_LO); 2623 if (mux_addr_lo == XGBE_SFP_DIRECT) 2624 return; 2625 2626 phy_data->sfp_comm = XGBE_SFP_COMM_PCA9545; 2627 phy_data->sfp_mux_address = (mux_addr_hi << 2) + mux_addr_lo; 2628 phy_data->sfp_mux_channel = XP_GET_BITS(pdata->pp4, XP_PROP_4, 2629 MUX_CHAN); 2630 2631 if (netif_msg_probe(pdata)) { 2632 dev_dbg(pdata->dev, "SFP: mux_address=%#x\n", 2633 phy_data->sfp_mux_address); 2634 dev_dbg(pdata->dev, "SFP: mux_channel=%u\n", 2635 phy_data->sfp_mux_channel); 2636 } 2637 } 2638 2639 static void xgbe_phy_sfp_setup(struct xgbe_prv_data *pdata) 2640 { 2641 xgbe_phy_sfp_comm_setup(pdata); 2642 xgbe_phy_sfp_gpio_setup(pdata); 2643 } 2644 2645 static int xgbe_phy_int_mdio_reset(struct xgbe_prv_data *pdata) 2646 { 2647 struct xgbe_phy_data *phy_data = pdata->phy_data; 2648 unsigned int ret; 2649 2650 ret = pdata->hw_if.set_gpio(pdata, phy_data->mdio_reset_gpio); 2651 if (ret) 2652 return ret; 2653 2654 ret = pdata->hw_if.clr_gpio(pdata, phy_data->mdio_reset_gpio); 2655 2656 return ret; 2657 } 2658 2659 static int xgbe_phy_i2c_mdio_reset(struct xgbe_prv_data *pdata) 2660 { 2661 struct xgbe_phy_data *phy_data = pdata->phy_data; 2662 u8 gpio_reg, gpio_ports[2], gpio_data[3]; 2663 int ret; 2664 2665 /* Read the output port registers */ 2666 gpio_reg = 2; 2667 ret = xgbe_phy_i2c_read(pdata, phy_data->mdio_reset_addr, 2668 &gpio_reg, sizeof(gpio_reg), 2669 gpio_ports, sizeof(gpio_ports)); 2670 if (ret) 2671 return ret; 2672 2673 /* Prepare to write the GPIO data */ 2674 gpio_data[0] = 2; 2675 gpio_data[1] = gpio_ports[0]; 2676 gpio_data[2] = gpio_ports[1]; 2677 2678 /* Set the GPIO pin */ 2679 if (phy_data->mdio_reset_gpio < 8) 2680 gpio_data[1] |= (1 << (phy_data->mdio_reset_gpio % 8)); 2681 else 2682 gpio_data[2] |= (1 << (phy_data->mdio_reset_gpio % 8)); 2683 2684 /* Write the output port registers */ 2685 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr, 2686 gpio_data, sizeof(gpio_data)); 2687 if (ret) 2688 return ret; 2689 2690 /* Clear the GPIO pin */ 2691 if (phy_data->mdio_reset_gpio < 8) 2692 gpio_data[1] &= ~(1 << (phy_data->mdio_reset_gpio % 8)); 2693 else 2694 gpio_data[2] &= ~(1 << (phy_data->mdio_reset_gpio % 8)); 2695 2696 /* Write the output port registers */ 2697 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr, 2698 gpio_data, sizeof(gpio_data)); 2699 2700 return ret; 2701 } 2702 2703 static int xgbe_phy_mdio_reset(struct xgbe_prv_data *pdata) 2704 { 2705 struct xgbe_phy_data *phy_data = pdata->phy_data; 2706 int ret; 2707 2708 if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO) 2709 return 0; 2710 2711 ret = xgbe_phy_get_comm_ownership(pdata); 2712 if (ret) 2713 return ret; 2714 2715 if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO) 2716 ret = xgbe_phy_i2c_mdio_reset(pdata); 2717 else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO) 2718 ret = xgbe_phy_int_mdio_reset(pdata); 2719 2720 xgbe_phy_put_comm_ownership(pdata); 2721 2722 return ret; 2723 } 2724 2725 static bool xgbe_phy_redrv_error(struct xgbe_phy_data *phy_data) 2726 { 2727 if (!phy_data->redrv) 2728 return false; 2729 2730 if (phy_data->redrv_if >= XGBE_PHY_REDRV_IF_MAX) 2731 return true; 2732 2733 switch (phy_data->redrv_model) { 2734 case XGBE_PHY_REDRV_MODEL_4223: 2735 if (phy_data->redrv_lane > 3) 2736 return true; 2737 break; 2738 case XGBE_PHY_REDRV_MODEL_4227: 2739 if (phy_data->redrv_lane > 1) 2740 return true; 2741 break; 2742 default: 2743 return true; 2744 } 2745 2746 return false; 2747 } 2748 2749 static int xgbe_phy_mdio_reset_setup(struct xgbe_prv_data *pdata) 2750 { 2751 struct xgbe_phy_data *phy_data = pdata->phy_data; 2752 2753 if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO) 2754 return 0; 2755 2756 phy_data->mdio_reset = XP_GET_BITS(pdata->pp3, XP_PROP_3, MDIO_RESET); 2757 switch (phy_data->mdio_reset) { 2758 case XGBE_MDIO_RESET_NONE: 2759 case XGBE_MDIO_RESET_I2C_GPIO: 2760 case XGBE_MDIO_RESET_INT_GPIO: 2761 break; 2762 default: 2763 dev_err(pdata->dev, "unsupported MDIO reset (%#x)\n", 2764 phy_data->mdio_reset); 2765 return -EINVAL; 2766 } 2767 2768 if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO) { 2769 phy_data->mdio_reset_addr = XGBE_GPIO_ADDRESS_PCA9555 + 2770 XP_GET_BITS(pdata->pp3, XP_PROP_3, 2771 MDIO_RESET_I2C_ADDR); 2772 phy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3, 2773 MDIO_RESET_I2C_GPIO); 2774 } else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO) { 2775 phy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3, 2776 MDIO_RESET_INT_GPIO); 2777 } 2778 2779 return 0; 2780 } 2781 2782 static bool xgbe_phy_port_mode_mismatch(struct xgbe_prv_data *pdata) 2783 { 2784 struct xgbe_phy_data *phy_data = pdata->phy_data; 2785 2786 switch (phy_data->port_mode) { 2787 case XGBE_PORT_MODE_BACKPLANE: 2788 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) || 2789 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)) 2790 return false; 2791 break; 2792 case XGBE_PORT_MODE_BACKPLANE_2500: 2793 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500) 2794 return false; 2795 break; 2796 case XGBE_PORT_MODE_1000BASE_T: 2797 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) || 2798 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)) 2799 return false; 2800 break; 2801 case XGBE_PORT_MODE_1000BASE_X: 2802 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) 2803 return false; 2804 break; 2805 case XGBE_PORT_MODE_NBASE_T: 2806 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) || 2807 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) || 2808 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500)) 2809 return false; 2810 break; 2811 case XGBE_PORT_MODE_10GBASE_T: 2812 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) || 2813 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) || 2814 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)) 2815 return false; 2816 break; 2817 case XGBE_PORT_MODE_10GBASE_R: 2818 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) 2819 return false; 2820 break; 2821 case XGBE_PORT_MODE_SFP: 2822 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) || 2823 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) || 2824 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)) 2825 return false; 2826 break; 2827 default: 2828 break; 2829 } 2830 2831 return true; 2832 } 2833 2834 static bool xgbe_phy_conn_type_mismatch(struct xgbe_prv_data *pdata) 2835 { 2836 struct xgbe_phy_data *phy_data = pdata->phy_data; 2837 2838 switch (phy_data->port_mode) { 2839 case XGBE_PORT_MODE_BACKPLANE: 2840 case XGBE_PORT_MODE_BACKPLANE_2500: 2841 if (phy_data->conn_type == XGBE_CONN_TYPE_BACKPLANE) 2842 return false; 2843 break; 2844 case XGBE_PORT_MODE_1000BASE_T: 2845 case XGBE_PORT_MODE_1000BASE_X: 2846 case XGBE_PORT_MODE_NBASE_T: 2847 case XGBE_PORT_MODE_10GBASE_T: 2848 case XGBE_PORT_MODE_10GBASE_R: 2849 if (phy_data->conn_type == XGBE_CONN_TYPE_MDIO) 2850 return false; 2851 break; 2852 case XGBE_PORT_MODE_SFP: 2853 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP) 2854 return false; 2855 break; 2856 default: 2857 break; 2858 } 2859 2860 return true; 2861 } 2862 2863 static bool xgbe_phy_port_enabled(struct xgbe_prv_data *pdata) 2864 { 2865 if (!XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS)) 2866 return false; 2867 if (!XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE)) 2868 return false; 2869 2870 return true; 2871 } 2872 2873 static void xgbe_phy_cdr_track(struct xgbe_prv_data *pdata) 2874 { 2875 struct xgbe_phy_data *phy_data = pdata->phy_data; 2876 2877 if (!pdata->debugfs_an_cdr_workaround) 2878 return; 2879 2880 if (!phy_data->phy_cdr_notrack) 2881 return; 2882 2883 usleep_range(phy_data->phy_cdr_delay, 2884 phy_data->phy_cdr_delay + 500); 2885 2886 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL, 2887 XGBE_PMA_CDR_TRACK_EN_MASK, 2888 XGBE_PMA_CDR_TRACK_EN_ON); 2889 2890 phy_data->phy_cdr_notrack = 0; 2891 } 2892 2893 static void xgbe_phy_cdr_notrack(struct xgbe_prv_data *pdata) 2894 { 2895 struct xgbe_phy_data *phy_data = pdata->phy_data; 2896 2897 if (!pdata->debugfs_an_cdr_workaround) 2898 return; 2899 2900 if (phy_data->phy_cdr_notrack) 2901 return; 2902 2903 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL, 2904 XGBE_PMA_CDR_TRACK_EN_MASK, 2905 XGBE_PMA_CDR_TRACK_EN_OFF); 2906 2907 xgbe_phy_rrc(pdata); 2908 2909 phy_data->phy_cdr_notrack = 1; 2910 } 2911 2912 static void xgbe_phy_kr_training_post(struct xgbe_prv_data *pdata) 2913 { 2914 if (!pdata->debugfs_an_cdr_track_early) 2915 xgbe_phy_cdr_track(pdata); 2916 } 2917 2918 static void xgbe_phy_kr_training_pre(struct xgbe_prv_data *pdata) 2919 { 2920 if (pdata->debugfs_an_cdr_track_early) 2921 xgbe_phy_cdr_track(pdata); 2922 } 2923 2924 static void xgbe_phy_an_post(struct xgbe_prv_data *pdata) 2925 { 2926 struct xgbe_phy_data *phy_data = pdata->phy_data; 2927 2928 switch (pdata->an_mode) { 2929 case XGBE_AN_MODE_CL73: 2930 case XGBE_AN_MODE_CL73_REDRV: 2931 if (phy_data->cur_mode != XGBE_MODE_KR) 2932 break; 2933 2934 xgbe_phy_cdr_track(pdata); 2935 2936 switch (pdata->an_result) { 2937 case XGBE_AN_READY: 2938 case XGBE_AN_COMPLETE: 2939 break; 2940 default: 2941 if (phy_data->phy_cdr_delay < XGBE_CDR_DELAY_MAX) 2942 phy_data->phy_cdr_delay += XGBE_CDR_DELAY_INC; 2943 else 2944 phy_data->phy_cdr_delay = XGBE_CDR_DELAY_INIT; 2945 break; 2946 } 2947 break; 2948 default: 2949 break; 2950 } 2951 } 2952 2953 static void xgbe_phy_an_pre(struct xgbe_prv_data *pdata) 2954 { 2955 struct xgbe_phy_data *phy_data = pdata->phy_data; 2956 2957 switch (pdata->an_mode) { 2958 case XGBE_AN_MODE_CL73: 2959 case XGBE_AN_MODE_CL73_REDRV: 2960 if (phy_data->cur_mode != XGBE_MODE_KR) 2961 break; 2962 2963 xgbe_phy_cdr_notrack(pdata); 2964 break; 2965 default: 2966 break; 2967 } 2968 } 2969 2970 static void xgbe_phy_stop(struct xgbe_prv_data *pdata) 2971 { 2972 struct xgbe_phy_data *phy_data = pdata->phy_data; 2973 2974 /* If we have an external PHY, free it */ 2975 xgbe_phy_free_phy_device(pdata); 2976 2977 /* Reset SFP data */ 2978 xgbe_phy_sfp_reset(phy_data); 2979 xgbe_phy_sfp_mod_absent(pdata); 2980 2981 /* Reset CDR support */ 2982 xgbe_phy_cdr_track(pdata); 2983 2984 /* Power off the PHY */ 2985 xgbe_phy_power_off(pdata); 2986 2987 /* Stop the I2C controller */ 2988 pdata->i2c_if.i2c_stop(pdata); 2989 } 2990 2991 static int xgbe_phy_start(struct xgbe_prv_data *pdata) 2992 { 2993 struct xgbe_phy_data *phy_data = pdata->phy_data; 2994 int ret; 2995 2996 /* Start the I2C controller */ 2997 ret = pdata->i2c_if.i2c_start(pdata); 2998 if (ret) 2999 return ret; 3000 3001 /* Set the proper MDIO mode for the re-driver */ 3002 if (phy_data->redrv && !phy_data->redrv_if) { 3003 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr, 3004 XGBE_MDIO_MODE_CL22); 3005 if (ret) { 3006 netdev_err(pdata->netdev, 3007 "redriver mdio port not compatible (%u)\n", 3008 phy_data->redrv_addr); 3009 return ret; 3010 } 3011 } 3012 3013 /* Start in highest supported mode */ 3014 xgbe_phy_set_mode(pdata, phy_data->start_mode); 3015 3016 /* Reset CDR support */ 3017 xgbe_phy_cdr_track(pdata); 3018 3019 /* After starting the I2C controller, we can check for an SFP */ 3020 switch (phy_data->port_mode) { 3021 case XGBE_PORT_MODE_SFP: 3022 xgbe_phy_sfp_detect(pdata); 3023 break; 3024 default: 3025 break; 3026 } 3027 3028 /* If we have an external PHY, start it */ 3029 ret = xgbe_phy_find_phy_device(pdata); 3030 if (ret) 3031 goto err_i2c; 3032 3033 return 0; 3034 3035 err_i2c: 3036 pdata->i2c_if.i2c_stop(pdata); 3037 3038 return ret; 3039 } 3040 3041 static int xgbe_phy_reset(struct xgbe_prv_data *pdata) 3042 { 3043 struct xgbe_phy_data *phy_data = pdata->phy_data; 3044 enum xgbe_mode cur_mode; 3045 int ret; 3046 3047 /* Reset by power cycling the PHY */ 3048 cur_mode = phy_data->cur_mode; 3049 xgbe_phy_power_off(pdata); 3050 xgbe_phy_set_mode(pdata, cur_mode); 3051 3052 if (!phy_data->phydev) 3053 return 0; 3054 3055 /* Reset the external PHY */ 3056 ret = xgbe_phy_mdio_reset(pdata); 3057 if (ret) 3058 return ret; 3059 3060 return phy_init_hw(phy_data->phydev); 3061 } 3062 3063 static void xgbe_phy_exit(struct xgbe_prv_data *pdata) 3064 { 3065 struct xgbe_phy_data *phy_data = pdata->phy_data; 3066 3067 /* Unregister for driving external PHYs */ 3068 mdiobus_unregister(phy_data->mii); 3069 } 3070 3071 static int xgbe_phy_init(struct xgbe_prv_data *pdata) 3072 { 3073 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 3074 struct xgbe_phy_data *phy_data; 3075 struct mii_bus *mii; 3076 int ret; 3077 3078 /* Check if enabled */ 3079 if (!xgbe_phy_port_enabled(pdata)) { 3080 dev_info(pdata->dev, "device is not enabled\n"); 3081 return -ENODEV; 3082 } 3083 3084 /* Initialize the I2C controller */ 3085 ret = pdata->i2c_if.i2c_init(pdata); 3086 if (ret) 3087 return ret; 3088 3089 phy_data = devm_kzalloc(pdata->dev, sizeof(*phy_data), GFP_KERNEL); 3090 if (!phy_data) 3091 return -ENOMEM; 3092 pdata->phy_data = phy_data; 3093 3094 phy_data->port_mode = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_MODE); 3095 phy_data->port_id = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_ID); 3096 phy_data->port_speeds = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS); 3097 phy_data->conn_type = XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE); 3098 phy_data->mdio_addr = XP_GET_BITS(pdata->pp0, XP_PROP_0, MDIO_ADDR); 3099 if (netif_msg_probe(pdata)) { 3100 dev_dbg(pdata->dev, "port mode=%u\n", phy_data->port_mode); 3101 dev_dbg(pdata->dev, "port id=%u\n", phy_data->port_id); 3102 dev_dbg(pdata->dev, "port speeds=%#x\n", phy_data->port_speeds); 3103 dev_dbg(pdata->dev, "conn type=%u\n", phy_data->conn_type); 3104 dev_dbg(pdata->dev, "mdio addr=%u\n", phy_data->mdio_addr); 3105 } 3106 3107 phy_data->redrv = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_PRESENT); 3108 phy_data->redrv_if = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_IF); 3109 phy_data->redrv_addr = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_ADDR); 3110 phy_data->redrv_lane = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_LANE); 3111 phy_data->redrv_model = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_MODEL); 3112 if (phy_data->redrv && netif_msg_probe(pdata)) { 3113 dev_dbg(pdata->dev, "redrv present\n"); 3114 dev_dbg(pdata->dev, "redrv i/f=%u\n", phy_data->redrv_if); 3115 dev_dbg(pdata->dev, "redrv addr=%#x\n", phy_data->redrv_addr); 3116 dev_dbg(pdata->dev, "redrv lane=%u\n", phy_data->redrv_lane); 3117 dev_dbg(pdata->dev, "redrv model=%u\n", phy_data->redrv_model); 3118 } 3119 3120 /* Validate the connection requested */ 3121 if (xgbe_phy_conn_type_mismatch(pdata)) { 3122 dev_err(pdata->dev, "phy mode/connection mismatch (%#x/%#x)\n", 3123 phy_data->port_mode, phy_data->conn_type); 3124 return -EINVAL; 3125 } 3126 3127 /* Validate the mode requested */ 3128 if (xgbe_phy_port_mode_mismatch(pdata)) { 3129 dev_err(pdata->dev, "phy mode/speed mismatch (%#x/%#x)\n", 3130 phy_data->port_mode, phy_data->port_speeds); 3131 return -EINVAL; 3132 } 3133 3134 /* Check for and validate MDIO reset support */ 3135 ret = xgbe_phy_mdio_reset_setup(pdata); 3136 if (ret) 3137 return ret; 3138 3139 /* Validate the re-driver information */ 3140 if (xgbe_phy_redrv_error(phy_data)) { 3141 dev_err(pdata->dev, "phy re-driver settings error\n"); 3142 return -EINVAL; 3143 } 3144 pdata->kr_redrv = phy_data->redrv; 3145 3146 /* Indicate current mode is unknown */ 3147 phy_data->cur_mode = XGBE_MODE_UNKNOWN; 3148 3149 /* Initialize supported features */ 3150 XGBE_ZERO_SUP(lks); 3151 3152 switch (phy_data->port_mode) { 3153 /* Backplane support */ 3154 case XGBE_PORT_MODE_BACKPLANE: 3155 XGBE_SET_SUP(lks, Autoneg); 3156 XGBE_SET_SUP(lks, Pause); 3157 XGBE_SET_SUP(lks, Asym_Pause); 3158 XGBE_SET_SUP(lks, Backplane); 3159 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) { 3160 XGBE_SET_SUP(lks, 1000baseKX_Full); 3161 phy_data->start_mode = XGBE_MODE_KX_1000; 3162 } 3163 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) { 3164 XGBE_SET_SUP(lks, 10000baseKR_Full); 3165 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 3166 XGBE_SET_SUP(lks, 10000baseR_FEC); 3167 phy_data->start_mode = XGBE_MODE_KR; 3168 } 3169 3170 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE; 3171 break; 3172 case XGBE_PORT_MODE_BACKPLANE_2500: 3173 XGBE_SET_SUP(lks, Pause); 3174 XGBE_SET_SUP(lks, Asym_Pause); 3175 XGBE_SET_SUP(lks, Backplane); 3176 XGBE_SET_SUP(lks, 2500baseX_Full); 3177 phy_data->start_mode = XGBE_MODE_KX_2500; 3178 3179 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE; 3180 break; 3181 3182 /* MDIO 1GBase-T support */ 3183 case XGBE_PORT_MODE_1000BASE_T: 3184 XGBE_SET_SUP(lks, Autoneg); 3185 XGBE_SET_SUP(lks, Pause); 3186 XGBE_SET_SUP(lks, Asym_Pause); 3187 XGBE_SET_SUP(lks, TP); 3188 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) { 3189 XGBE_SET_SUP(lks, 100baseT_Full); 3190 phy_data->start_mode = XGBE_MODE_SGMII_100; 3191 } 3192 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) { 3193 XGBE_SET_SUP(lks, 1000baseT_Full); 3194 phy_data->start_mode = XGBE_MODE_SGMII_1000; 3195 } 3196 3197 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22; 3198 break; 3199 3200 /* MDIO Base-X support */ 3201 case XGBE_PORT_MODE_1000BASE_X: 3202 XGBE_SET_SUP(lks, Autoneg); 3203 XGBE_SET_SUP(lks, Pause); 3204 XGBE_SET_SUP(lks, Asym_Pause); 3205 XGBE_SET_SUP(lks, FIBRE); 3206 XGBE_SET_SUP(lks, 1000baseX_Full); 3207 phy_data->start_mode = XGBE_MODE_X; 3208 3209 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22; 3210 break; 3211 3212 /* MDIO NBase-T support */ 3213 case XGBE_PORT_MODE_NBASE_T: 3214 XGBE_SET_SUP(lks, Autoneg); 3215 XGBE_SET_SUP(lks, Pause); 3216 XGBE_SET_SUP(lks, Asym_Pause); 3217 XGBE_SET_SUP(lks, TP); 3218 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) { 3219 XGBE_SET_SUP(lks, 100baseT_Full); 3220 phy_data->start_mode = XGBE_MODE_SGMII_100; 3221 } 3222 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) { 3223 XGBE_SET_SUP(lks, 1000baseT_Full); 3224 phy_data->start_mode = XGBE_MODE_SGMII_1000; 3225 } 3226 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500) { 3227 XGBE_SET_SUP(lks, 2500baseT_Full); 3228 phy_data->start_mode = XGBE_MODE_KX_2500; 3229 } 3230 3231 phy_data->phydev_mode = XGBE_MDIO_MODE_CL45; 3232 break; 3233 3234 /* 10GBase-T support */ 3235 case XGBE_PORT_MODE_10GBASE_T: 3236 XGBE_SET_SUP(lks, Autoneg); 3237 XGBE_SET_SUP(lks, Pause); 3238 XGBE_SET_SUP(lks, Asym_Pause); 3239 XGBE_SET_SUP(lks, TP); 3240 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) { 3241 XGBE_SET_SUP(lks, 100baseT_Full); 3242 phy_data->start_mode = XGBE_MODE_SGMII_100; 3243 } 3244 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) { 3245 XGBE_SET_SUP(lks, 1000baseT_Full); 3246 phy_data->start_mode = XGBE_MODE_SGMII_1000; 3247 } 3248 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) { 3249 XGBE_SET_SUP(lks, 10000baseT_Full); 3250 phy_data->start_mode = XGBE_MODE_KR; 3251 } 3252 3253 phy_data->phydev_mode = XGBE_MDIO_MODE_CL45; 3254 break; 3255 3256 /* 10GBase-R support */ 3257 case XGBE_PORT_MODE_10GBASE_R: 3258 XGBE_SET_SUP(lks, Autoneg); 3259 XGBE_SET_SUP(lks, Pause); 3260 XGBE_SET_SUP(lks, Asym_Pause); 3261 XGBE_SET_SUP(lks, FIBRE); 3262 XGBE_SET_SUP(lks, 10000baseSR_Full); 3263 XGBE_SET_SUP(lks, 10000baseLR_Full); 3264 XGBE_SET_SUP(lks, 10000baseLRM_Full); 3265 XGBE_SET_SUP(lks, 10000baseER_Full); 3266 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 3267 XGBE_SET_SUP(lks, 10000baseR_FEC); 3268 phy_data->start_mode = XGBE_MODE_SFI; 3269 3270 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE; 3271 break; 3272 3273 /* SFP support */ 3274 case XGBE_PORT_MODE_SFP: 3275 XGBE_SET_SUP(lks, Autoneg); 3276 XGBE_SET_SUP(lks, Pause); 3277 XGBE_SET_SUP(lks, Asym_Pause); 3278 XGBE_SET_SUP(lks, TP); 3279 XGBE_SET_SUP(lks, FIBRE); 3280 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) 3281 phy_data->start_mode = XGBE_MODE_SGMII_100; 3282 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) 3283 phy_data->start_mode = XGBE_MODE_SGMII_1000; 3284 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) 3285 phy_data->start_mode = XGBE_MODE_SFI; 3286 3287 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22; 3288 3289 xgbe_phy_sfp_setup(pdata); 3290 break; 3291 default: 3292 return -EINVAL; 3293 } 3294 3295 if (netif_msg_probe(pdata)) 3296 dev_dbg(pdata->dev, "phy supported=0x%*pb\n", 3297 __ETHTOOL_LINK_MODE_MASK_NBITS, 3298 lks->link_modes.supported); 3299 3300 if ((phy_data->conn_type & XGBE_CONN_TYPE_MDIO) && 3301 (phy_data->phydev_mode != XGBE_MDIO_MODE_NONE)) { 3302 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr, 3303 phy_data->phydev_mode); 3304 if (ret) { 3305 dev_err(pdata->dev, 3306 "mdio port/clause not compatible (%d/%u)\n", 3307 phy_data->mdio_addr, phy_data->phydev_mode); 3308 return -EINVAL; 3309 } 3310 } 3311 3312 if (phy_data->redrv && !phy_data->redrv_if) { 3313 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr, 3314 XGBE_MDIO_MODE_CL22); 3315 if (ret) { 3316 dev_err(pdata->dev, 3317 "redriver mdio port not compatible (%u)\n", 3318 phy_data->redrv_addr); 3319 return -EINVAL; 3320 } 3321 } 3322 3323 phy_data->phy_cdr_delay = XGBE_CDR_DELAY_INIT; 3324 3325 /* Register for driving external PHYs */ 3326 mii = devm_mdiobus_alloc(pdata->dev); 3327 if (!mii) { 3328 dev_err(pdata->dev, "mdiobus_alloc failed\n"); 3329 return -ENOMEM; 3330 } 3331 3332 mii->priv = pdata; 3333 mii->name = "amd-xgbe-mii"; 3334 mii->read = xgbe_phy_mii_read; 3335 mii->write = xgbe_phy_mii_write; 3336 mii->parent = pdata->dev; 3337 mii->phy_mask = ~0; 3338 snprintf(mii->id, sizeof(mii->id), "%s", dev_name(pdata->dev)); 3339 ret = mdiobus_register(mii); 3340 if (ret) { 3341 dev_err(pdata->dev, "mdiobus_register failed\n"); 3342 return ret; 3343 } 3344 phy_data->mii = mii; 3345 3346 return 0; 3347 } 3348 3349 void xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if *phy_if) 3350 { 3351 struct xgbe_phy_impl_if *phy_impl = &phy_if->phy_impl; 3352 3353 phy_impl->init = xgbe_phy_init; 3354 phy_impl->exit = xgbe_phy_exit; 3355 3356 phy_impl->reset = xgbe_phy_reset; 3357 phy_impl->start = xgbe_phy_start; 3358 phy_impl->stop = xgbe_phy_stop; 3359 3360 phy_impl->link_status = xgbe_phy_link_status; 3361 3362 phy_impl->valid_speed = xgbe_phy_valid_speed; 3363 3364 phy_impl->use_mode = xgbe_phy_use_mode; 3365 phy_impl->set_mode = xgbe_phy_set_mode; 3366 phy_impl->get_mode = xgbe_phy_get_mode; 3367 phy_impl->switch_mode = xgbe_phy_switch_mode; 3368 phy_impl->cur_mode = xgbe_phy_cur_mode; 3369 3370 phy_impl->an_mode = xgbe_phy_an_mode; 3371 3372 phy_impl->an_config = xgbe_phy_an_config; 3373 3374 phy_impl->an_advertising = xgbe_phy_an_advertising; 3375 3376 phy_impl->an_outcome = xgbe_phy_an_outcome; 3377 3378 phy_impl->an_pre = xgbe_phy_an_pre; 3379 phy_impl->an_post = xgbe_phy_an_post; 3380 3381 phy_impl->kr_training_pre = xgbe_phy_kr_training_pre; 3382 phy_impl->kr_training_post = xgbe_phy_kr_training_post; 3383 3384 phy_impl->module_info = xgbe_phy_module_info; 3385 phy_impl->module_eeprom = xgbe_phy_module_eeprom; 3386 } 3387