1 /* 2 * AMD 10Gb Ethernet driver 3 * 4 * This file is available to you under your choice of the following two 5 * licenses: 6 * 7 * License 1: GPLv2 8 * 9 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc. 10 * 11 * This file is free software; you may copy, redistribute and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation, either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program. If not, see <http://www.gnu.org/licenses/>. 23 * 24 * This file incorporates work covered by the following copyright and 25 * permission notice: 26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 28 * Inc. unless otherwise expressly agreed to in writing between Synopsys 29 * and you. 30 * 31 * The Software IS NOT an item of Licensed Software or Licensed Product 32 * under any End User Software License Agreement or Agreement for Licensed 33 * Product with Synopsys or any supplement thereto. Permission is hereby 34 * granted, free of charge, to any person obtaining a copy of this software 35 * annotated with this license and the Software, to deal in the Software 36 * without restriction, including without limitation the rights to use, 37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 38 * of the Software, and to permit persons to whom the Software is furnished 39 * to do so, subject to the following conditions: 40 * 41 * The above copyright notice and this permission notice shall be included 42 * in all copies or substantial portions of the Software. 43 * 44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 54 * THE POSSIBILITY OF SUCH DAMAGE. 55 * 56 * 57 * License 2: Modified BSD 58 * 59 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc. 60 * All rights reserved. 61 * 62 * Redistribution and use in source and binary forms, with or without 63 * modification, are permitted provided that the following conditions are met: 64 * * Redistributions of source code must retain the above copyright 65 * notice, this list of conditions and the following disclaimer. 66 * * Redistributions in binary form must reproduce the above copyright 67 * notice, this list of conditions and the following disclaimer in the 68 * documentation and/or other materials provided with the distribution. 69 * * Neither the name of Advanced Micro Devices, Inc. nor the 70 * names of its contributors may be used to endorse or promote products 71 * derived from this software without specific prior written permission. 72 * 73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY 77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 83 * 84 * This file incorporates work covered by the following copyright and 85 * permission notice: 86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 88 * Inc. unless otherwise expressly agreed to in writing between Synopsys 89 * and you. 90 * 91 * The Software IS NOT an item of Licensed Software or Licensed Product 92 * under any End User Software License Agreement or Agreement for Licensed 93 * Product with Synopsys or any supplement thereto. Permission is hereby 94 * granted, free of charge, to any person obtaining a copy of this software 95 * annotated with this license and the Software, to deal in the Software 96 * without restriction, including without limitation the rights to use, 97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 98 * of the Software, and to permit persons to whom the Software is furnished 99 * to do so, subject to the following conditions: 100 * 101 * The above copyright notice and this permission notice shall be included 102 * in all copies or substantial portions of the Software. 103 * 104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 114 * THE POSSIBILITY OF SUCH DAMAGE. 115 */ 116 117 #include <linux/interrupt.h> 118 #include <linux/module.h> 119 #include <linux/kmod.h> 120 #include <linux/mdio.h> 121 #include <linux/phy.h> 122 #include <linux/of.h> 123 #include <linux/bitops.h> 124 #include <linux/jiffies.h> 125 126 #include "xgbe.h" 127 #include "xgbe-common.h" 128 129 static void xgbe_an37_clear_interrupts(struct xgbe_prv_data *pdata) 130 { 131 int reg; 132 133 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT); 134 reg &= ~XGBE_AN_CL37_INT_MASK; 135 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT, reg); 136 } 137 138 static void xgbe_an37_disable_interrupts(struct xgbe_prv_data *pdata) 139 { 140 int reg; 141 142 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL); 143 reg &= ~XGBE_AN_CL37_INT_MASK; 144 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg); 145 146 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL); 147 reg &= ~XGBE_PCS_CL37_BP; 148 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL, reg); 149 } 150 151 static void xgbe_an37_enable_interrupts(struct xgbe_prv_data *pdata) 152 { 153 int reg; 154 155 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL); 156 reg |= XGBE_PCS_CL37_BP; 157 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL, reg); 158 159 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL); 160 reg |= XGBE_AN_CL37_INT_MASK; 161 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg); 162 } 163 164 static void xgbe_an73_clear_interrupts(struct xgbe_prv_data *pdata) 165 { 166 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, 0); 167 } 168 169 static void xgbe_an73_disable_interrupts(struct xgbe_prv_data *pdata) 170 { 171 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, 0); 172 } 173 174 static void xgbe_an73_enable_interrupts(struct xgbe_prv_data *pdata) 175 { 176 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, XGBE_AN_CL73_INT_MASK); 177 } 178 179 static void xgbe_an_enable_interrupts(struct xgbe_prv_data *pdata) 180 { 181 switch (pdata->an_mode) { 182 case XGBE_AN_MODE_CL73: 183 case XGBE_AN_MODE_CL73_REDRV: 184 xgbe_an73_enable_interrupts(pdata); 185 break; 186 case XGBE_AN_MODE_CL37: 187 case XGBE_AN_MODE_CL37_SGMII: 188 xgbe_an37_enable_interrupts(pdata); 189 break; 190 default: 191 break; 192 } 193 } 194 195 static void xgbe_an_clear_interrupts_all(struct xgbe_prv_data *pdata) 196 { 197 xgbe_an73_clear_interrupts(pdata); 198 xgbe_an37_clear_interrupts(pdata); 199 } 200 201 static void xgbe_an73_enable_kr_training(struct xgbe_prv_data *pdata) 202 { 203 unsigned int reg; 204 205 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL); 206 207 reg |= XGBE_KR_TRAINING_ENABLE; 208 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg); 209 } 210 211 static void xgbe_an73_disable_kr_training(struct xgbe_prv_data *pdata) 212 { 213 unsigned int reg; 214 215 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL); 216 217 reg &= ~XGBE_KR_TRAINING_ENABLE; 218 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg); 219 } 220 221 static void xgbe_kr_mode(struct xgbe_prv_data *pdata) 222 { 223 /* Enable KR training */ 224 xgbe_an73_enable_kr_training(pdata); 225 226 /* Set MAC to 10G speed */ 227 pdata->hw_if.set_speed(pdata, SPEED_10000); 228 229 /* Call PHY implementation support to complete rate change */ 230 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_KR); 231 } 232 233 static void xgbe_kx_2500_mode(struct xgbe_prv_data *pdata) 234 { 235 /* Disable KR training */ 236 xgbe_an73_disable_kr_training(pdata); 237 238 /* Set MAC to 2.5G speed */ 239 pdata->hw_if.set_speed(pdata, SPEED_2500); 240 241 /* Call PHY implementation support to complete rate change */ 242 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_KX_2500); 243 } 244 245 static void xgbe_kx_1000_mode(struct xgbe_prv_data *pdata) 246 { 247 /* Disable KR training */ 248 xgbe_an73_disable_kr_training(pdata); 249 250 /* Set MAC to 1G speed */ 251 pdata->hw_if.set_speed(pdata, SPEED_1000); 252 253 /* Call PHY implementation support to complete rate change */ 254 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_KX_1000); 255 } 256 257 static void xgbe_sfi_mode(struct xgbe_prv_data *pdata) 258 { 259 /* If a KR re-driver is present, change to KR mode instead */ 260 if (pdata->kr_redrv) 261 return xgbe_kr_mode(pdata); 262 263 /* Disable KR training */ 264 xgbe_an73_disable_kr_training(pdata); 265 266 /* Set MAC to 10G speed */ 267 pdata->hw_if.set_speed(pdata, SPEED_10000); 268 269 /* Call PHY implementation support to complete rate change */ 270 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SFI); 271 } 272 273 static void xgbe_x_mode(struct xgbe_prv_data *pdata) 274 { 275 /* Disable KR training */ 276 xgbe_an73_disable_kr_training(pdata); 277 278 /* Set MAC to 1G speed */ 279 pdata->hw_if.set_speed(pdata, SPEED_1000); 280 281 /* Call PHY implementation support to complete rate change */ 282 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_X); 283 } 284 285 static void xgbe_sgmii_1000_mode(struct xgbe_prv_data *pdata) 286 { 287 /* Disable KR training */ 288 xgbe_an73_disable_kr_training(pdata); 289 290 /* Set MAC to 1G speed */ 291 pdata->hw_if.set_speed(pdata, SPEED_1000); 292 293 /* Call PHY implementation support to complete rate change */ 294 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SGMII_1000); 295 } 296 297 static void xgbe_sgmii_100_mode(struct xgbe_prv_data *pdata) 298 { 299 /* Disable KR training */ 300 xgbe_an73_disable_kr_training(pdata); 301 302 /* Set MAC to 1G speed */ 303 pdata->hw_if.set_speed(pdata, SPEED_1000); 304 305 /* Call PHY implementation support to complete rate change */ 306 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SGMII_100); 307 } 308 309 static enum xgbe_mode xgbe_cur_mode(struct xgbe_prv_data *pdata) 310 { 311 return pdata->phy_if.phy_impl.cur_mode(pdata); 312 } 313 314 static bool xgbe_in_kr_mode(struct xgbe_prv_data *pdata) 315 { 316 return (xgbe_cur_mode(pdata) == XGBE_MODE_KR); 317 } 318 319 static void xgbe_change_mode(struct xgbe_prv_data *pdata, 320 enum xgbe_mode mode) 321 { 322 switch (mode) { 323 case XGBE_MODE_KX_1000: 324 xgbe_kx_1000_mode(pdata); 325 break; 326 case XGBE_MODE_KX_2500: 327 xgbe_kx_2500_mode(pdata); 328 break; 329 case XGBE_MODE_KR: 330 xgbe_kr_mode(pdata); 331 break; 332 case XGBE_MODE_SGMII_100: 333 xgbe_sgmii_100_mode(pdata); 334 break; 335 case XGBE_MODE_SGMII_1000: 336 xgbe_sgmii_1000_mode(pdata); 337 break; 338 case XGBE_MODE_X: 339 xgbe_x_mode(pdata); 340 break; 341 case XGBE_MODE_SFI: 342 xgbe_sfi_mode(pdata); 343 break; 344 case XGBE_MODE_UNKNOWN: 345 break; 346 default: 347 netif_dbg(pdata, link, pdata->netdev, 348 "invalid operation mode requested (%u)\n", mode); 349 } 350 } 351 352 static void xgbe_switch_mode(struct xgbe_prv_data *pdata) 353 { 354 xgbe_change_mode(pdata, pdata->phy_if.phy_impl.switch_mode(pdata)); 355 } 356 357 static void xgbe_set_mode(struct xgbe_prv_data *pdata, 358 enum xgbe_mode mode) 359 { 360 if (mode == xgbe_cur_mode(pdata)) 361 return; 362 363 xgbe_change_mode(pdata, mode); 364 } 365 366 static bool xgbe_use_mode(struct xgbe_prv_data *pdata, 367 enum xgbe_mode mode) 368 { 369 return pdata->phy_if.phy_impl.use_mode(pdata, mode); 370 } 371 372 static void xgbe_an37_set(struct xgbe_prv_data *pdata, bool enable, 373 bool restart) 374 { 375 unsigned int reg; 376 377 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_CTRL1); 378 reg &= ~MDIO_VEND2_CTRL1_AN_ENABLE; 379 380 if (enable) 381 reg |= MDIO_VEND2_CTRL1_AN_ENABLE; 382 383 if (restart) 384 reg |= MDIO_VEND2_CTRL1_AN_RESTART; 385 386 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_CTRL1, reg); 387 } 388 389 static void xgbe_an37_restart(struct xgbe_prv_data *pdata) 390 { 391 xgbe_an37_enable_interrupts(pdata); 392 xgbe_an37_set(pdata, true, true); 393 394 netif_dbg(pdata, link, pdata->netdev, "CL37 AN enabled/restarted\n"); 395 } 396 397 static void xgbe_an37_disable(struct xgbe_prv_data *pdata) 398 { 399 xgbe_an37_set(pdata, false, false); 400 xgbe_an37_disable_interrupts(pdata); 401 402 netif_dbg(pdata, link, pdata->netdev, "CL37 AN disabled\n"); 403 } 404 405 static void xgbe_an73_set(struct xgbe_prv_data *pdata, bool enable, 406 bool restart) 407 { 408 unsigned int reg; 409 410 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1); 411 reg &= ~MDIO_AN_CTRL1_ENABLE; 412 413 if (enable) 414 reg |= MDIO_AN_CTRL1_ENABLE; 415 416 if (restart) 417 reg |= MDIO_AN_CTRL1_RESTART; 418 419 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_CTRL1, reg); 420 } 421 422 static void xgbe_an73_restart(struct xgbe_prv_data *pdata) 423 { 424 xgbe_an73_enable_interrupts(pdata); 425 xgbe_an73_set(pdata, true, true); 426 427 netif_dbg(pdata, link, pdata->netdev, "CL73 AN enabled/restarted\n"); 428 } 429 430 static void xgbe_an73_disable(struct xgbe_prv_data *pdata) 431 { 432 xgbe_an73_set(pdata, false, false); 433 xgbe_an73_disable_interrupts(pdata); 434 435 netif_dbg(pdata, link, pdata->netdev, "CL73 AN disabled\n"); 436 } 437 438 static void xgbe_an_restart(struct xgbe_prv_data *pdata) 439 { 440 switch (pdata->an_mode) { 441 case XGBE_AN_MODE_CL73: 442 case XGBE_AN_MODE_CL73_REDRV: 443 xgbe_an73_restart(pdata); 444 break; 445 case XGBE_AN_MODE_CL37: 446 case XGBE_AN_MODE_CL37_SGMII: 447 xgbe_an37_restart(pdata); 448 break; 449 default: 450 break; 451 } 452 } 453 454 static void xgbe_an_disable(struct xgbe_prv_data *pdata) 455 { 456 switch (pdata->an_mode) { 457 case XGBE_AN_MODE_CL73: 458 case XGBE_AN_MODE_CL73_REDRV: 459 xgbe_an73_disable(pdata); 460 break; 461 case XGBE_AN_MODE_CL37: 462 case XGBE_AN_MODE_CL37_SGMII: 463 xgbe_an37_disable(pdata); 464 break; 465 default: 466 break; 467 } 468 } 469 470 static void xgbe_an_disable_all(struct xgbe_prv_data *pdata) 471 { 472 xgbe_an73_disable(pdata); 473 xgbe_an37_disable(pdata); 474 } 475 476 static enum xgbe_an xgbe_an73_tx_training(struct xgbe_prv_data *pdata, 477 enum xgbe_rx *state) 478 { 479 unsigned int ad_reg, lp_reg, reg; 480 481 *state = XGBE_RX_COMPLETE; 482 483 /* If we're not in KR mode then we're done */ 484 if (!xgbe_in_kr_mode(pdata)) 485 return XGBE_AN_PAGE_RECEIVED; 486 487 /* Enable/Disable FEC */ 488 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); 489 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); 490 491 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL); 492 reg &= ~(MDIO_PMA_10GBR_FECABLE_ABLE | MDIO_PMA_10GBR_FECABLE_ERRABLE); 493 if ((ad_reg & 0xc000) && (lp_reg & 0xc000)) 494 reg |= pdata->fec_ability; 495 496 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL, reg); 497 498 /* Start KR training */ 499 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL); 500 if (reg & XGBE_KR_TRAINING_ENABLE) { 501 if (pdata->phy_if.phy_impl.kr_training_pre) 502 pdata->phy_if.phy_impl.kr_training_pre(pdata); 503 504 reg |= XGBE_KR_TRAINING_START; 505 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, 506 reg); 507 508 if (pdata->phy_if.phy_impl.kr_training_post) 509 pdata->phy_if.phy_impl.kr_training_post(pdata); 510 511 netif_dbg(pdata, link, pdata->netdev, 512 "KR training initiated\n"); 513 } 514 515 return XGBE_AN_PAGE_RECEIVED; 516 } 517 518 static enum xgbe_an xgbe_an73_tx_xnp(struct xgbe_prv_data *pdata, 519 enum xgbe_rx *state) 520 { 521 u16 msg; 522 523 *state = XGBE_RX_XNP; 524 525 msg = XGBE_XNP_MCF_NULL_MESSAGE; 526 msg |= XGBE_XNP_MP_FORMATTED; 527 528 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP + 2, 0); 529 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP + 1, 0); 530 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP, msg); 531 532 return XGBE_AN_PAGE_RECEIVED; 533 } 534 535 static enum xgbe_an xgbe_an73_rx_bpa(struct xgbe_prv_data *pdata, 536 enum xgbe_rx *state) 537 { 538 unsigned int link_support; 539 unsigned int reg, ad_reg, lp_reg; 540 541 /* Read Base Ability register 2 first */ 542 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); 543 544 /* Check for a supported mode, otherwise restart in a different one */ 545 link_support = xgbe_in_kr_mode(pdata) ? 0x80 : 0x20; 546 if (!(reg & link_support)) 547 return XGBE_AN_INCOMPAT_LINK; 548 549 /* Check Extended Next Page support */ 550 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE); 551 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA); 552 553 return ((ad_reg & XGBE_XNP_NP_EXCHANGE) || 554 (lp_reg & XGBE_XNP_NP_EXCHANGE)) 555 ? xgbe_an73_tx_xnp(pdata, state) 556 : xgbe_an73_tx_training(pdata, state); 557 } 558 559 static enum xgbe_an xgbe_an73_rx_xnp(struct xgbe_prv_data *pdata, 560 enum xgbe_rx *state) 561 { 562 unsigned int ad_reg, lp_reg; 563 564 /* Check Extended Next Page support */ 565 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_XNP); 566 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPX); 567 568 return ((ad_reg & XGBE_XNP_NP_EXCHANGE) || 569 (lp_reg & XGBE_XNP_NP_EXCHANGE)) 570 ? xgbe_an73_tx_xnp(pdata, state) 571 : xgbe_an73_tx_training(pdata, state); 572 } 573 574 static enum xgbe_an xgbe_an73_page_received(struct xgbe_prv_data *pdata) 575 { 576 enum xgbe_rx *state; 577 unsigned long an_timeout; 578 enum xgbe_an ret; 579 580 if (!pdata->an_start) { 581 pdata->an_start = jiffies; 582 } else { 583 an_timeout = pdata->an_start + 584 msecs_to_jiffies(XGBE_AN_MS_TIMEOUT); 585 if (time_after(jiffies, an_timeout)) { 586 /* Auto-negotiation timed out, reset state */ 587 pdata->kr_state = XGBE_RX_BPA; 588 pdata->kx_state = XGBE_RX_BPA; 589 590 pdata->an_start = jiffies; 591 592 netif_dbg(pdata, link, pdata->netdev, 593 "CL73 AN timed out, resetting state\n"); 594 } 595 } 596 597 state = xgbe_in_kr_mode(pdata) ? &pdata->kr_state 598 : &pdata->kx_state; 599 600 switch (*state) { 601 case XGBE_RX_BPA: 602 ret = xgbe_an73_rx_bpa(pdata, state); 603 break; 604 605 case XGBE_RX_XNP: 606 ret = xgbe_an73_rx_xnp(pdata, state); 607 break; 608 609 default: 610 ret = XGBE_AN_ERROR; 611 } 612 613 return ret; 614 } 615 616 static enum xgbe_an xgbe_an73_incompat_link(struct xgbe_prv_data *pdata) 617 { 618 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 619 620 /* Be sure we aren't looping trying to negotiate */ 621 if (xgbe_in_kr_mode(pdata)) { 622 pdata->kr_state = XGBE_RX_ERROR; 623 624 if (!XGBE_ADV(lks, 1000baseKX_Full) && 625 !XGBE_ADV(lks, 2500baseX_Full)) 626 return XGBE_AN_NO_LINK; 627 628 if (pdata->kx_state != XGBE_RX_BPA) 629 return XGBE_AN_NO_LINK; 630 } else { 631 pdata->kx_state = XGBE_RX_ERROR; 632 633 if (!XGBE_ADV(lks, 10000baseKR_Full)) 634 return XGBE_AN_NO_LINK; 635 636 if (pdata->kr_state != XGBE_RX_BPA) 637 return XGBE_AN_NO_LINK; 638 } 639 640 xgbe_an73_disable(pdata); 641 642 xgbe_switch_mode(pdata); 643 644 xgbe_an73_restart(pdata); 645 646 return XGBE_AN_INCOMPAT_LINK; 647 } 648 649 static void xgbe_an37_isr(struct xgbe_prv_data *pdata) 650 { 651 unsigned int reg; 652 653 /* Disable AN interrupts */ 654 xgbe_an37_disable_interrupts(pdata); 655 656 /* Save the interrupt(s) that fired */ 657 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT); 658 pdata->an_int = reg & XGBE_AN_CL37_INT_MASK; 659 pdata->an_status = reg & ~XGBE_AN_CL37_INT_MASK; 660 661 if (pdata->an_int) { 662 /* Clear the interrupt(s) that fired and process them */ 663 reg &= ~XGBE_AN_CL37_INT_MASK; 664 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT, reg); 665 666 queue_work(pdata->an_workqueue, &pdata->an_irq_work); 667 } else { 668 /* Enable AN interrupts */ 669 xgbe_an37_enable_interrupts(pdata); 670 671 /* Reissue interrupt if status is not clear */ 672 if (pdata->vdata->irq_reissue_support) 673 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 3); 674 } 675 } 676 677 static void xgbe_an73_isr(struct xgbe_prv_data *pdata) 678 { 679 /* Disable AN interrupts */ 680 xgbe_an73_disable_interrupts(pdata); 681 682 /* Save the interrupt(s) that fired */ 683 pdata->an_int = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_INT); 684 685 if (pdata->an_int) { 686 /* Clear the interrupt(s) that fired and process them */ 687 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, ~pdata->an_int); 688 689 queue_work(pdata->an_workqueue, &pdata->an_irq_work); 690 } else { 691 /* Enable AN interrupts */ 692 xgbe_an73_enable_interrupts(pdata); 693 694 /* Reissue interrupt if status is not clear */ 695 if (pdata->vdata->irq_reissue_support) 696 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 3); 697 } 698 } 699 700 static void xgbe_an_isr_task(unsigned long data) 701 { 702 struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data; 703 704 netif_dbg(pdata, intr, pdata->netdev, "AN interrupt received\n"); 705 706 switch (pdata->an_mode) { 707 case XGBE_AN_MODE_CL73: 708 case XGBE_AN_MODE_CL73_REDRV: 709 xgbe_an73_isr(pdata); 710 break; 711 case XGBE_AN_MODE_CL37: 712 case XGBE_AN_MODE_CL37_SGMII: 713 xgbe_an37_isr(pdata); 714 break; 715 default: 716 break; 717 } 718 } 719 720 static irqreturn_t xgbe_an_isr(int irq, void *data) 721 { 722 struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data; 723 724 if (pdata->isr_as_tasklet) 725 tasklet_schedule(&pdata->tasklet_an); 726 else 727 xgbe_an_isr_task((unsigned long)pdata); 728 729 return IRQ_HANDLED; 730 } 731 732 static irqreturn_t xgbe_an_combined_isr(struct xgbe_prv_data *pdata) 733 { 734 xgbe_an_isr_task((unsigned long)pdata); 735 736 return IRQ_HANDLED; 737 } 738 739 static void xgbe_an_irq_work(struct work_struct *work) 740 { 741 struct xgbe_prv_data *pdata = container_of(work, 742 struct xgbe_prv_data, 743 an_irq_work); 744 745 /* Avoid a race between enabling the IRQ and exiting the work by 746 * waiting for the work to finish and then queueing it 747 */ 748 flush_work(&pdata->an_work); 749 queue_work(pdata->an_workqueue, &pdata->an_work); 750 } 751 752 static const char *xgbe_state_as_string(enum xgbe_an state) 753 { 754 switch (state) { 755 case XGBE_AN_READY: 756 return "Ready"; 757 case XGBE_AN_PAGE_RECEIVED: 758 return "Page-Received"; 759 case XGBE_AN_INCOMPAT_LINK: 760 return "Incompatible-Link"; 761 case XGBE_AN_COMPLETE: 762 return "Complete"; 763 case XGBE_AN_NO_LINK: 764 return "No-Link"; 765 case XGBE_AN_ERROR: 766 return "Error"; 767 default: 768 return "Undefined"; 769 } 770 } 771 772 static void xgbe_an37_state_machine(struct xgbe_prv_data *pdata) 773 { 774 enum xgbe_an cur_state = pdata->an_state; 775 776 if (!pdata->an_int) 777 return; 778 779 if (pdata->an_int & XGBE_AN_CL37_INT_CMPLT) { 780 pdata->an_state = XGBE_AN_COMPLETE; 781 pdata->an_int &= ~XGBE_AN_CL37_INT_CMPLT; 782 783 /* If SGMII is enabled, check the link status */ 784 if ((pdata->an_mode == XGBE_AN_MODE_CL37_SGMII) && 785 !(pdata->an_status & XGBE_SGMII_AN_LINK_STATUS)) 786 pdata->an_state = XGBE_AN_NO_LINK; 787 } 788 789 netif_dbg(pdata, link, pdata->netdev, "CL37 AN %s\n", 790 xgbe_state_as_string(pdata->an_state)); 791 792 cur_state = pdata->an_state; 793 794 switch (pdata->an_state) { 795 case XGBE_AN_READY: 796 break; 797 798 case XGBE_AN_COMPLETE: 799 netif_dbg(pdata, link, pdata->netdev, 800 "Auto negotiation successful\n"); 801 break; 802 803 case XGBE_AN_NO_LINK: 804 break; 805 806 default: 807 pdata->an_state = XGBE_AN_ERROR; 808 } 809 810 if (pdata->an_state == XGBE_AN_ERROR) { 811 netdev_err(pdata->netdev, 812 "error during auto-negotiation, state=%u\n", 813 cur_state); 814 815 pdata->an_int = 0; 816 xgbe_an37_clear_interrupts(pdata); 817 } 818 819 if (pdata->an_state >= XGBE_AN_COMPLETE) { 820 pdata->an_result = pdata->an_state; 821 pdata->an_state = XGBE_AN_READY; 822 823 netif_dbg(pdata, link, pdata->netdev, "CL37 AN result: %s\n", 824 xgbe_state_as_string(pdata->an_result)); 825 } 826 827 xgbe_an37_enable_interrupts(pdata); 828 } 829 830 static void xgbe_an73_state_machine(struct xgbe_prv_data *pdata) 831 { 832 enum xgbe_an cur_state = pdata->an_state; 833 834 if (!pdata->an_int) 835 return; 836 837 next_int: 838 if (pdata->an_int & XGBE_AN_CL73_PG_RCV) { 839 pdata->an_state = XGBE_AN_PAGE_RECEIVED; 840 pdata->an_int &= ~XGBE_AN_CL73_PG_RCV; 841 } else if (pdata->an_int & XGBE_AN_CL73_INC_LINK) { 842 pdata->an_state = XGBE_AN_INCOMPAT_LINK; 843 pdata->an_int &= ~XGBE_AN_CL73_INC_LINK; 844 } else if (pdata->an_int & XGBE_AN_CL73_INT_CMPLT) { 845 pdata->an_state = XGBE_AN_COMPLETE; 846 pdata->an_int &= ~XGBE_AN_CL73_INT_CMPLT; 847 } else { 848 pdata->an_state = XGBE_AN_ERROR; 849 } 850 851 again: 852 netif_dbg(pdata, link, pdata->netdev, "CL73 AN %s\n", 853 xgbe_state_as_string(pdata->an_state)); 854 855 cur_state = pdata->an_state; 856 857 switch (pdata->an_state) { 858 case XGBE_AN_READY: 859 pdata->an_supported = 0; 860 break; 861 862 case XGBE_AN_PAGE_RECEIVED: 863 pdata->an_state = xgbe_an73_page_received(pdata); 864 pdata->an_supported++; 865 break; 866 867 case XGBE_AN_INCOMPAT_LINK: 868 pdata->an_supported = 0; 869 pdata->parallel_detect = 0; 870 pdata->an_state = xgbe_an73_incompat_link(pdata); 871 break; 872 873 case XGBE_AN_COMPLETE: 874 pdata->parallel_detect = pdata->an_supported ? 0 : 1; 875 netif_dbg(pdata, link, pdata->netdev, "%s successful\n", 876 pdata->an_supported ? "Auto negotiation" 877 : "Parallel detection"); 878 break; 879 880 case XGBE_AN_NO_LINK: 881 break; 882 883 default: 884 pdata->an_state = XGBE_AN_ERROR; 885 } 886 887 if (pdata->an_state == XGBE_AN_NO_LINK) { 888 pdata->an_int = 0; 889 xgbe_an73_clear_interrupts(pdata); 890 } else if (pdata->an_state == XGBE_AN_ERROR) { 891 netdev_err(pdata->netdev, 892 "error during auto-negotiation, state=%u\n", 893 cur_state); 894 895 pdata->an_int = 0; 896 xgbe_an73_clear_interrupts(pdata); 897 } 898 899 if (pdata->an_state >= XGBE_AN_COMPLETE) { 900 pdata->an_result = pdata->an_state; 901 pdata->an_state = XGBE_AN_READY; 902 pdata->kr_state = XGBE_RX_BPA; 903 pdata->kx_state = XGBE_RX_BPA; 904 pdata->an_start = 0; 905 906 netif_dbg(pdata, link, pdata->netdev, "CL73 AN result: %s\n", 907 xgbe_state_as_string(pdata->an_result)); 908 } 909 910 if (cur_state != pdata->an_state) 911 goto again; 912 913 if (pdata->an_int) 914 goto next_int; 915 916 xgbe_an73_enable_interrupts(pdata); 917 } 918 919 static void xgbe_an_state_machine(struct work_struct *work) 920 { 921 struct xgbe_prv_data *pdata = container_of(work, 922 struct xgbe_prv_data, 923 an_work); 924 925 mutex_lock(&pdata->an_mutex); 926 927 switch (pdata->an_mode) { 928 case XGBE_AN_MODE_CL73: 929 case XGBE_AN_MODE_CL73_REDRV: 930 xgbe_an73_state_machine(pdata); 931 break; 932 case XGBE_AN_MODE_CL37: 933 case XGBE_AN_MODE_CL37_SGMII: 934 xgbe_an37_state_machine(pdata); 935 break; 936 default: 937 break; 938 } 939 940 /* Reissue interrupt if status is not clear */ 941 if (pdata->vdata->irq_reissue_support) 942 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 3); 943 944 mutex_unlock(&pdata->an_mutex); 945 } 946 947 static void xgbe_an37_init(struct xgbe_prv_data *pdata) 948 { 949 struct ethtool_link_ksettings lks; 950 unsigned int reg; 951 952 pdata->phy_if.phy_impl.an_advertising(pdata, &lks); 953 954 /* Set up Advertisement register */ 955 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE); 956 if (XGBE_ADV(&lks, Pause)) 957 reg |= 0x100; 958 else 959 reg &= ~0x100; 960 961 if (XGBE_ADV(&lks, Asym_Pause)) 962 reg |= 0x80; 963 else 964 reg &= ~0x80; 965 966 /* Full duplex, but not half */ 967 reg |= XGBE_AN_CL37_FD_MASK; 968 reg &= ~XGBE_AN_CL37_HD_MASK; 969 970 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE, reg); 971 972 /* Set up the Control register */ 973 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL); 974 reg &= ~XGBE_AN_CL37_TX_CONFIG_MASK; 975 reg &= ~XGBE_AN_CL37_PCS_MODE_MASK; 976 977 switch (pdata->an_mode) { 978 case XGBE_AN_MODE_CL37: 979 reg |= XGBE_AN_CL37_PCS_MODE_BASEX; 980 break; 981 case XGBE_AN_MODE_CL37_SGMII: 982 reg |= XGBE_AN_CL37_PCS_MODE_SGMII; 983 break; 984 default: 985 break; 986 } 987 988 reg |= XGBE_AN_CL37_MII_CTRL_8BIT; 989 990 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg); 991 992 netif_dbg(pdata, link, pdata->netdev, "CL37 AN (%s) initialized\n", 993 (pdata->an_mode == XGBE_AN_MODE_CL37) ? "BaseX" : "SGMII"); 994 } 995 996 static void xgbe_an73_init(struct xgbe_prv_data *pdata) 997 { 998 struct ethtool_link_ksettings lks; 999 unsigned int reg; 1000 1001 pdata->phy_if.phy_impl.an_advertising(pdata, &lks); 1002 1003 /* Set up Advertisement register 3 first */ 1004 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); 1005 if (XGBE_ADV(&lks, 10000baseR_FEC)) 1006 reg |= 0xc000; 1007 else 1008 reg &= ~0xc000; 1009 1010 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2, reg); 1011 1012 /* Set up Advertisement register 2 next */ 1013 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); 1014 if (XGBE_ADV(&lks, 10000baseKR_Full)) 1015 reg |= 0x80; 1016 else 1017 reg &= ~0x80; 1018 1019 if (XGBE_ADV(&lks, 1000baseKX_Full) || 1020 XGBE_ADV(&lks, 2500baseX_Full)) 1021 reg |= 0x20; 1022 else 1023 reg &= ~0x20; 1024 1025 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1, reg); 1026 1027 /* Set up Advertisement register 1 last */ 1028 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE); 1029 if (XGBE_ADV(&lks, Pause)) 1030 reg |= 0x400; 1031 else 1032 reg &= ~0x400; 1033 1034 if (XGBE_ADV(&lks, Asym_Pause)) 1035 reg |= 0x800; 1036 else 1037 reg &= ~0x800; 1038 1039 /* We don't intend to perform XNP */ 1040 reg &= ~XGBE_XNP_NP_EXCHANGE; 1041 1042 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE, reg); 1043 1044 netif_dbg(pdata, link, pdata->netdev, "CL73 AN initialized\n"); 1045 } 1046 1047 static void xgbe_an_init(struct xgbe_prv_data *pdata) 1048 { 1049 /* Set up advertisement registers based on current settings */ 1050 pdata->an_mode = pdata->phy_if.phy_impl.an_mode(pdata); 1051 switch (pdata->an_mode) { 1052 case XGBE_AN_MODE_CL73: 1053 case XGBE_AN_MODE_CL73_REDRV: 1054 xgbe_an73_init(pdata); 1055 break; 1056 case XGBE_AN_MODE_CL37: 1057 case XGBE_AN_MODE_CL37_SGMII: 1058 xgbe_an37_init(pdata); 1059 break; 1060 default: 1061 break; 1062 } 1063 } 1064 1065 static const char *xgbe_phy_fc_string(struct xgbe_prv_data *pdata) 1066 { 1067 if (pdata->tx_pause && pdata->rx_pause) 1068 return "rx/tx"; 1069 else if (pdata->rx_pause) 1070 return "rx"; 1071 else if (pdata->tx_pause) 1072 return "tx"; 1073 else 1074 return "off"; 1075 } 1076 1077 static const char *xgbe_phy_speed_string(int speed) 1078 { 1079 switch (speed) { 1080 case SPEED_100: 1081 return "100Mbps"; 1082 case SPEED_1000: 1083 return "1Gbps"; 1084 case SPEED_2500: 1085 return "2.5Gbps"; 1086 case SPEED_10000: 1087 return "10Gbps"; 1088 case SPEED_UNKNOWN: 1089 return "Unknown"; 1090 default: 1091 return "Unsupported"; 1092 } 1093 } 1094 1095 static void xgbe_phy_print_status(struct xgbe_prv_data *pdata) 1096 { 1097 if (pdata->phy.link) 1098 netdev_info(pdata->netdev, 1099 "Link is Up - %s/%s - flow control %s\n", 1100 xgbe_phy_speed_string(pdata->phy.speed), 1101 pdata->phy.duplex == DUPLEX_FULL ? "Full" : "Half", 1102 xgbe_phy_fc_string(pdata)); 1103 else 1104 netdev_info(pdata->netdev, "Link is Down\n"); 1105 } 1106 1107 static void xgbe_phy_adjust_link(struct xgbe_prv_data *pdata) 1108 { 1109 int new_state = 0; 1110 1111 if (pdata->phy.link) { 1112 /* Flow control support */ 1113 pdata->pause_autoneg = pdata->phy.pause_autoneg; 1114 1115 if (pdata->tx_pause != pdata->phy.tx_pause) { 1116 new_state = 1; 1117 pdata->hw_if.config_tx_flow_control(pdata); 1118 pdata->tx_pause = pdata->phy.tx_pause; 1119 } 1120 1121 if (pdata->rx_pause != pdata->phy.rx_pause) { 1122 new_state = 1; 1123 pdata->hw_if.config_rx_flow_control(pdata); 1124 pdata->rx_pause = pdata->phy.rx_pause; 1125 } 1126 1127 /* Speed support */ 1128 if (pdata->phy_speed != pdata->phy.speed) { 1129 new_state = 1; 1130 pdata->phy_speed = pdata->phy.speed; 1131 } 1132 1133 if (pdata->phy_link != pdata->phy.link) { 1134 new_state = 1; 1135 pdata->phy_link = pdata->phy.link; 1136 } 1137 } else if (pdata->phy_link) { 1138 new_state = 1; 1139 pdata->phy_link = 0; 1140 pdata->phy_speed = SPEED_UNKNOWN; 1141 } 1142 1143 if (new_state && netif_msg_link(pdata)) 1144 xgbe_phy_print_status(pdata); 1145 } 1146 1147 static bool xgbe_phy_valid_speed(struct xgbe_prv_data *pdata, int speed) 1148 { 1149 return pdata->phy_if.phy_impl.valid_speed(pdata, speed); 1150 } 1151 1152 static int xgbe_phy_config_fixed(struct xgbe_prv_data *pdata) 1153 { 1154 enum xgbe_mode mode; 1155 1156 netif_dbg(pdata, link, pdata->netdev, "fixed PHY configuration\n"); 1157 1158 /* Disable auto-negotiation */ 1159 xgbe_an_disable(pdata); 1160 1161 /* Set specified mode for specified speed */ 1162 mode = pdata->phy_if.phy_impl.get_mode(pdata, pdata->phy.speed); 1163 switch (mode) { 1164 case XGBE_MODE_KX_1000: 1165 case XGBE_MODE_KX_2500: 1166 case XGBE_MODE_KR: 1167 case XGBE_MODE_SGMII_100: 1168 case XGBE_MODE_SGMII_1000: 1169 case XGBE_MODE_X: 1170 case XGBE_MODE_SFI: 1171 break; 1172 case XGBE_MODE_UNKNOWN: 1173 default: 1174 return -EINVAL; 1175 } 1176 1177 /* Validate duplex mode */ 1178 if (pdata->phy.duplex != DUPLEX_FULL) 1179 return -EINVAL; 1180 1181 xgbe_set_mode(pdata, mode); 1182 1183 return 0; 1184 } 1185 1186 static int __xgbe_phy_config_aneg(struct xgbe_prv_data *pdata) 1187 { 1188 int ret; 1189 1190 set_bit(XGBE_LINK_INIT, &pdata->dev_state); 1191 pdata->link_check = jiffies; 1192 1193 ret = pdata->phy_if.phy_impl.an_config(pdata); 1194 if (ret) 1195 return ret; 1196 1197 if (pdata->phy.autoneg != AUTONEG_ENABLE) { 1198 ret = xgbe_phy_config_fixed(pdata); 1199 if (ret || !pdata->kr_redrv) 1200 return ret; 1201 1202 netif_dbg(pdata, link, pdata->netdev, "AN redriver support\n"); 1203 } else { 1204 netif_dbg(pdata, link, pdata->netdev, "AN PHY configuration\n"); 1205 } 1206 1207 /* Disable auto-negotiation interrupt */ 1208 disable_irq(pdata->an_irq); 1209 1210 /* Start auto-negotiation in a supported mode */ 1211 if (xgbe_use_mode(pdata, XGBE_MODE_KR)) { 1212 xgbe_set_mode(pdata, XGBE_MODE_KR); 1213 } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_2500)) { 1214 xgbe_set_mode(pdata, XGBE_MODE_KX_2500); 1215 } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_1000)) { 1216 xgbe_set_mode(pdata, XGBE_MODE_KX_1000); 1217 } else if (xgbe_use_mode(pdata, XGBE_MODE_SFI)) { 1218 xgbe_set_mode(pdata, XGBE_MODE_SFI); 1219 } else if (xgbe_use_mode(pdata, XGBE_MODE_X)) { 1220 xgbe_set_mode(pdata, XGBE_MODE_X); 1221 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_1000)) { 1222 xgbe_set_mode(pdata, XGBE_MODE_SGMII_1000); 1223 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_100)) { 1224 xgbe_set_mode(pdata, XGBE_MODE_SGMII_100); 1225 } else { 1226 enable_irq(pdata->an_irq); 1227 return -EINVAL; 1228 } 1229 1230 /* Disable and stop any in progress auto-negotiation */ 1231 xgbe_an_disable_all(pdata); 1232 1233 /* Clear any auto-negotitation interrupts */ 1234 xgbe_an_clear_interrupts_all(pdata); 1235 1236 pdata->an_result = XGBE_AN_READY; 1237 pdata->an_state = XGBE_AN_READY; 1238 pdata->kr_state = XGBE_RX_BPA; 1239 pdata->kx_state = XGBE_RX_BPA; 1240 1241 /* Re-enable auto-negotiation interrupt */ 1242 enable_irq(pdata->an_irq); 1243 1244 xgbe_an_init(pdata); 1245 xgbe_an_restart(pdata); 1246 1247 return 0; 1248 } 1249 1250 static int xgbe_phy_config_aneg(struct xgbe_prv_data *pdata) 1251 { 1252 int ret; 1253 1254 mutex_lock(&pdata->an_mutex); 1255 1256 ret = __xgbe_phy_config_aneg(pdata); 1257 if (ret) 1258 set_bit(XGBE_LINK_ERR, &pdata->dev_state); 1259 else 1260 clear_bit(XGBE_LINK_ERR, &pdata->dev_state); 1261 1262 mutex_unlock(&pdata->an_mutex); 1263 1264 return ret; 1265 } 1266 1267 static bool xgbe_phy_aneg_done(struct xgbe_prv_data *pdata) 1268 { 1269 return (pdata->an_result == XGBE_AN_COMPLETE); 1270 } 1271 1272 static void xgbe_check_link_timeout(struct xgbe_prv_data *pdata) 1273 { 1274 unsigned long link_timeout; 1275 1276 link_timeout = pdata->link_check + (XGBE_LINK_TIMEOUT * HZ); 1277 if (time_after(jiffies, link_timeout)) { 1278 netif_dbg(pdata, link, pdata->netdev, "AN link timeout\n"); 1279 xgbe_phy_config_aneg(pdata); 1280 } 1281 } 1282 1283 static enum xgbe_mode xgbe_phy_status_aneg(struct xgbe_prv_data *pdata) 1284 { 1285 return pdata->phy_if.phy_impl.an_outcome(pdata); 1286 } 1287 1288 static void xgbe_phy_status_result(struct xgbe_prv_data *pdata) 1289 { 1290 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 1291 enum xgbe_mode mode; 1292 1293 XGBE_ZERO_LP_ADV(lks); 1294 1295 if ((pdata->phy.autoneg != AUTONEG_ENABLE) || pdata->parallel_detect) 1296 mode = xgbe_cur_mode(pdata); 1297 else 1298 mode = xgbe_phy_status_aneg(pdata); 1299 1300 switch (mode) { 1301 case XGBE_MODE_SGMII_100: 1302 pdata->phy.speed = SPEED_100; 1303 break; 1304 case XGBE_MODE_X: 1305 case XGBE_MODE_KX_1000: 1306 case XGBE_MODE_SGMII_1000: 1307 pdata->phy.speed = SPEED_1000; 1308 break; 1309 case XGBE_MODE_KX_2500: 1310 pdata->phy.speed = SPEED_2500; 1311 break; 1312 case XGBE_MODE_KR: 1313 case XGBE_MODE_SFI: 1314 pdata->phy.speed = SPEED_10000; 1315 break; 1316 case XGBE_MODE_UNKNOWN: 1317 default: 1318 pdata->phy.speed = SPEED_UNKNOWN; 1319 } 1320 1321 pdata->phy.duplex = DUPLEX_FULL; 1322 1323 xgbe_set_mode(pdata, mode); 1324 } 1325 1326 static void xgbe_phy_status(struct xgbe_prv_data *pdata) 1327 { 1328 unsigned int link_aneg; 1329 int an_restart; 1330 1331 if (test_bit(XGBE_LINK_ERR, &pdata->dev_state)) { 1332 netif_carrier_off(pdata->netdev); 1333 1334 pdata->phy.link = 0; 1335 goto adjust_link; 1336 } 1337 1338 link_aneg = (pdata->phy.autoneg == AUTONEG_ENABLE); 1339 1340 pdata->phy.link = pdata->phy_if.phy_impl.link_status(pdata, 1341 &an_restart); 1342 if (an_restart) { 1343 xgbe_phy_config_aneg(pdata); 1344 return; 1345 } 1346 1347 if (pdata->phy.link) { 1348 if (link_aneg && !xgbe_phy_aneg_done(pdata)) { 1349 xgbe_check_link_timeout(pdata); 1350 return; 1351 } 1352 1353 xgbe_phy_status_result(pdata); 1354 1355 if (test_bit(XGBE_LINK_INIT, &pdata->dev_state)) 1356 clear_bit(XGBE_LINK_INIT, &pdata->dev_state); 1357 1358 netif_carrier_on(pdata->netdev); 1359 } else { 1360 if (test_bit(XGBE_LINK_INIT, &pdata->dev_state)) { 1361 xgbe_check_link_timeout(pdata); 1362 1363 if (link_aneg) 1364 return; 1365 } 1366 1367 xgbe_phy_status_result(pdata); 1368 1369 netif_carrier_off(pdata->netdev); 1370 } 1371 1372 adjust_link: 1373 xgbe_phy_adjust_link(pdata); 1374 } 1375 1376 static void xgbe_phy_stop(struct xgbe_prv_data *pdata) 1377 { 1378 netif_dbg(pdata, link, pdata->netdev, "stopping PHY\n"); 1379 1380 if (!pdata->phy_started) 1381 return; 1382 1383 /* Indicate the PHY is down */ 1384 pdata->phy_started = 0; 1385 1386 /* Disable auto-negotiation */ 1387 xgbe_an_disable_all(pdata); 1388 1389 if (pdata->dev_irq != pdata->an_irq) 1390 devm_free_irq(pdata->dev, pdata->an_irq, pdata); 1391 1392 pdata->phy_if.phy_impl.stop(pdata); 1393 1394 pdata->phy.link = 0; 1395 netif_carrier_off(pdata->netdev); 1396 1397 xgbe_phy_adjust_link(pdata); 1398 } 1399 1400 static int xgbe_phy_start(struct xgbe_prv_data *pdata) 1401 { 1402 struct net_device *netdev = pdata->netdev; 1403 int ret; 1404 1405 netif_dbg(pdata, link, pdata->netdev, "starting PHY\n"); 1406 1407 ret = pdata->phy_if.phy_impl.start(pdata); 1408 if (ret) 1409 return ret; 1410 1411 /* If we have a separate AN irq, enable it */ 1412 if (pdata->dev_irq != pdata->an_irq) { 1413 tasklet_init(&pdata->tasklet_an, xgbe_an_isr_task, 1414 (unsigned long)pdata); 1415 1416 ret = devm_request_irq(pdata->dev, pdata->an_irq, 1417 xgbe_an_isr, 0, pdata->an_name, 1418 pdata); 1419 if (ret) { 1420 netdev_err(netdev, "phy irq request failed\n"); 1421 goto err_stop; 1422 } 1423 } 1424 1425 /* Set initial mode - call the mode setting routines 1426 * directly to insure we are properly configured 1427 */ 1428 if (xgbe_use_mode(pdata, XGBE_MODE_KR)) { 1429 xgbe_kr_mode(pdata); 1430 } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_2500)) { 1431 xgbe_kx_2500_mode(pdata); 1432 } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_1000)) { 1433 xgbe_kx_1000_mode(pdata); 1434 } else if (xgbe_use_mode(pdata, XGBE_MODE_SFI)) { 1435 xgbe_sfi_mode(pdata); 1436 } else if (xgbe_use_mode(pdata, XGBE_MODE_X)) { 1437 xgbe_x_mode(pdata); 1438 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_1000)) { 1439 xgbe_sgmii_1000_mode(pdata); 1440 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_100)) { 1441 xgbe_sgmii_100_mode(pdata); 1442 } else { 1443 ret = -EINVAL; 1444 goto err_irq; 1445 } 1446 1447 /* Indicate the PHY is up and running */ 1448 pdata->phy_started = 1; 1449 1450 xgbe_an_init(pdata); 1451 xgbe_an_enable_interrupts(pdata); 1452 1453 return xgbe_phy_config_aneg(pdata); 1454 1455 err_irq: 1456 if (pdata->dev_irq != pdata->an_irq) 1457 devm_free_irq(pdata->dev, pdata->an_irq, pdata); 1458 1459 err_stop: 1460 pdata->phy_if.phy_impl.stop(pdata); 1461 1462 return ret; 1463 } 1464 1465 static int xgbe_phy_reset(struct xgbe_prv_data *pdata) 1466 { 1467 int ret; 1468 1469 ret = pdata->phy_if.phy_impl.reset(pdata); 1470 if (ret) 1471 return ret; 1472 1473 /* Disable auto-negotiation for now */ 1474 xgbe_an_disable_all(pdata); 1475 1476 /* Clear auto-negotiation interrupts */ 1477 xgbe_an_clear_interrupts_all(pdata); 1478 1479 return 0; 1480 } 1481 1482 static void xgbe_dump_phy_registers(struct xgbe_prv_data *pdata) 1483 { 1484 struct device *dev = pdata->dev; 1485 1486 dev_dbg(dev, "\n************* PHY Reg dump **********************\n"); 1487 1488 dev_dbg(dev, "PCS Control Reg (%#06x) = %#06x\n", MDIO_CTRL1, 1489 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1)); 1490 dev_dbg(dev, "PCS Status Reg (%#06x) = %#06x\n", MDIO_STAT1, 1491 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1)); 1492 dev_dbg(dev, "Phy Id (PHYS ID 1 %#06x)= %#06x\n", MDIO_DEVID1, 1493 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID1)); 1494 dev_dbg(dev, "Phy Id (PHYS ID 2 %#06x)= %#06x\n", MDIO_DEVID2, 1495 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID2)); 1496 dev_dbg(dev, "Devices in Package (%#06x)= %#06x\n", MDIO_DEVS1, 1497 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS1)); 1498 dev_dbg(dev, "Devices in Package (%#06x)= %#06x\n", MDIO_DEVS2, 1499 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS2)); 1500 1501 dev_dbg(dev, "Auto-Neg Control Reg (%#06x) = %#06x\n", MDIO_CTRL1, 1502 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1)); 1503 dev_dbg(dev, "Auto-Neg Status Reg (%#06x) = %#06x\n", MDIO_STAT1, 1504 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_STAT1)); 1505 dev_dbg(dev, "Auto-Neg Ad Reg 1 (%#06x) = %#06x\n", 1506 MDIO_AN_ADVERTISE, 1507 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE)); 1508 dev_dbg(dev, "Auto-Neg Ad Reg 2 (%#06x) = %#06x\n", 1509 MDIO_AN_ADVERTISE + 1, 1510 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1)); 1511 dev_dbg(dev, "Auto-Neg Ad Reg 3 (%#06x) = %#06x\n", 1512 MDIO_AN_ADVERTISE + 2, 1513 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2)); 1514 dev_dbg(dev, "Auto-Neg Completion Reg (%#06x) = %#06x\n", 1515 MDIO_AN_COMP_STAT, 1516 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_COMP_STAT)); 1517 1518 dev_dbg(dev, "\n*************************************************\n"); 1519 } 1520 1521 static int xgbe_phy_best_advertised_speed(struct xgbe_prv_data *pdata) 1522 { 1523 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 1524 1525 if (XGBE_ADV(lks, 10000baseKR_Full)) 1526 return SPEED_10000; 1527 else if (XGBE_ADV(lks, 10000baseT_Full)) 1528 return SPEED_10000; 1529 else if (XGBE_ADV(lks, 2500baseX_Full)) 1530 return SPEED_2500; 1531 else if (XGBE_ADV(lks, 2500baseT_Full)) 1532 return SPEED_2500; 1533 else if (XGBE_ADV(lks, 1000baseKX_Full)) 1534 return SPEED_1000; 1535 else if (XGBE_ADV(lks, 1000baseT_Full)) 1536 return SPEED_1000; 1537 else if (XGBE_ADV(lks, 100baseT_Full)) 1538 return SPEED_100; 1539 1540 return SPEED_UNKNOWN; 1541 } 1542 1543 static void xgbe_phy_exit(struct xgbe_prv_data *pdata) 1544 { 1545 pdata->phy_if.phy_impl.exit(pdata); 1546 } 1547 1548 static int xgbe_phy_init(struct xgbe_prv_data *pdata) 1549 { 1550 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 1551 int ret; 1552 1553 mutex_init(&pdata->an_mutex); 1554 INIT_WORK(&pdata->an_irq_work, xgbe_an_irq_work); 1555 INIT_WORK(&pdata->an_work, xgbe_an_state_machine); 1556 pdata->mdio_mmd = MDIO_MMD_PCS; 1557 1558 /* Check for FEC support */ 1559 pdata->fec_ability = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, 1560 MDIO_PMA_10GBR_FECABLE); 1561 pdata->fec_ability &= (MDIO_PMA_10GBR_FECABLE_ABLE | 1562 MDIO_PMA_10GBR_FECABLE_ERRABLE); 1563 1564 /* Setup the phy (including supported features) */ 1565 ret = pdata->phy_if.phy_impl.init(pdata); 1566 if (ret) 1567 return ret; 1568 1569 /* Copy supported link modes to advertising link modes */ 1570 XGBE_LM_COPY(lks, advertising, lks, supported); 1571 1572 pdata->phy.address = 0; 1573 1574 if (XGBE_ADV(lks, Autoneg)) { 1575 pdata->phy.autoneg = AUTONEG_ENABLE; 1576 pdata->phy.speed = SPEED_UNKNOWN; 1577 pdata->phy.duplex = DUPLEX_UNKNOWN; 1578 } else { 1579 pdata->phy.autoneg = AUTONEG_DISABLE; 1580 pdata->phy.speed = xgbe_phy_best_advertised_speed(pdata); 1581 pdata->phy.duplex = DUPLEX_FULL; 1582 } 1583 1584 pdata->phy.link = 0; 1585 1586 pdata->phy.pause_autoneg = pdata->pause_autoneg; 1587 pdata->phy.tx_pause = pdata->tx_pause; 1588 pdata->phy.rx_pause = pdata->rx_pause; 1589 1590 /* Fix up Flow Control advertising */ 1591 XGBE_CLR_ADV(lks, Pause); 1592 XGBE_CLR_ADV(lks, Asym_Pause); 1593 1594 if (pdata->rx_pause) { 1595 XGBE_SET_ADV(lks, Pause); 1596 XGBE_SET_ADV(lks, Asym_Pause); 1597 } 1598 1599 if (pdata->tx_pause) { 1600 /* Equivalent to XOR of Asym_Pause */ 1601 if (XGBE_ADV(lks, Asym_Pause)) 1602 XGBE_CLR_ADV(lks, Asym_Pause); 1603 else 1604 XGBE_SET_ADV(lks, Asym_Pause); 1605 } 1606 1607 if (netif_msg_drv(pdata)) 1608 xgbe_dump_phy_registers(pdata); 1609 1610 return 0; 1611 } 1612 1613 void xgbe_init_function_ptrs_phy(struct xgbe_phy_if *phy_if) 1614 { 1615 phy_if->phy_init = xgbe_phy_init; 1616 phy_if->phy_exit = xgbe_phy_exit; 1617 1618 phy_if->phy_reset = xgbe_phy_reset; 1619 phy_if->phy_start = xgbe_phy_start; 1620 phy_if->phy_stop = xgbe_phy_stop; 1621 1622 phy_if->phy_status = xgbe_phy_status; 1623 phy_if->phy_config_aneg = xgbe_phy_config_aneg; 1624 1625 phy_if->phy_valid_speed = xgbe_phy_valid_speed; 1626 1627 phy_if->an_isr = xgbe_an_combined_isr; 1628 } 1629