1 /* 2 * AMD 10Gb Ethernet driver 3 * 4 * This file is available to you under your choice of the following two 5 * licenses: 6 * 7 * License 1: GPLv2 8 * 9 * Copyright (c) 2014 Advanced Micro Devices, Inc. 10 * 11 * This file is free software; you may copy, redistribute and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation, either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program. If not, see <http://www.gnu.org/licenses/>. 23 * 24 * This file incorporates work covered by the following copyright and 25 * permission notice: 26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 28 * Inc. unless otherwise expressly agreed to in writing between Synopsys 29 * and you. 30 * 31 * The Software IS NOT an item of Licensed Software or Licensed Product 32 * under any End User Software License Agreement or Agreement for Licensed 33 * Product with Synopsys or any supplement thereto. Permission is hereby 34 * granted, free of charge, to any person obtaining a copy of this software 35 * annotated with this license and the Software, to deal in the Software 36 * without restriction, including without limitation the rights to use, 37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 38 * of the Software, and to permit persons to whom the Software is furnished 39 * to do so, subject to the following conditions: 40 * 41 * The above copyright notice and this permission notice shall be included 42 * in all copies or substantial portions of the Software. 43 * 44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 54 * THE POSSIBILITY OF SUCH DAMAGE. 55 * 56 * 57 * License 2: Modified BSD 58 * 59 * Copyright (c) 2014 Advanced Micro Devices, Inc. 60 * All rights reserved. 61 * 62 * Redistribution and use in source and binary forms, with or without 63 * modification, are permitted provided that the following conditions are met: 64 * * Redistributions of source code must retain the above copyright 65 * notice, this list of conditions and the following disclaimer. 66 * * Redistributions in binary form must reproduce the above copyright 67 * notice, this list of conditions and the following disclaimer in the 68 * documentation and/or other materials provided with the distribution. 69 * * Neither the name of Advanced Micro Devices, Inc. nor the 70 * names of its contributors may be used to endorse or promote products 71 * derived from this software without specific prior written permission. 72 * 73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY 77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 83 * 84 * This file incorporates work covered by the following copyright and 85 * permission notice: 86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 88 * Inc. unless otherwise expressly agreed to in writing between Synopsys 89 * and you. 90 * 91 * The Software IS NOT an item of Licensed Software or Licensed Product 92 * under any End User Software License Agreement or Agreement for Licensed 93 * Product with Synopsys or any supplement thereto. Permission is hereby 94 * granted, free of charge, to any person obtaining a copy of this software 95 * annotated with this license and the Software, to deal in the Software 96 * without restriction, including without limitation the rights to use, 97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 98 * of the Software, and to permit persons to whom the Software is furnished 99 * to do so, subject to the following conditions: 100 * 101 * The above copyright notice and this permission notice shall be included 102 * in all copies or substantial portions of the Software. 103 * 104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 114 * THE POSSIBILITY OF SUCH DAMAGE. 115 */ 116 117 #include <linux/module.h> 118 #include <linux/kmod.h> 119 #include <linux/spinlock.h> 120 #include <linux/mdio.h> 121 #include <linux/phy.h> 122 #include <linux/of.h> 123 124 #include "xgbe.h" 125 #include "xgbe-common.h" 126 127 128 static int xgbe_mdio_read(struct mii_bus *mii, int prtad, int mmd_reg) 129 { 130 struct xgbe_prv_data *pdata = mii->priv; 131 struct xgbe_hw_if *hw_if = &pdata->hw_if; 132 int mmd_data; 133 134 DBGPR_MDIO("-->xgbe_mdio_read: prtad=%#x mmd_reg=%#x\n", 135 prtad, mmd_reg); 136 137 mmd_data = hw_if->read_mmd_regs(pdata, prtad, mmd_reg); 138 139 DBGPR_MDIO("<--xgbe_mdio_read: mmd_data=%#x\n", mmd_data); 140 141 return mmd_data; 142 } 143 144 static int xgbe_mdio_write(struct mii_bus *mii, int prtad, int mmd_reg, 145 u16 mmd_val) 146 { 147 struct xgbe_prv_data *pdata = mii->priv; 148 struct xgbe_hw_if *hw_if = &pdata->hw_if; 149 int mmd_data = mmd_val; 150 151 DBGPR_MDIO("-->xgbe_mdio_write: prtad=%#x mmd_reg=%#x mmd_data=%#x\n", 152 prtad, mmd_reg, mmd_data); 153 154 hw_if->write_mmd_regs(pdata, prtad, mmd_reg, mmd_data); 155 156 DBGPR_MDIO("<--xgbe_mdio_write\n"); 157 158 return 0; 159 } 160 161 static void xgbe_adjust_link(struct net_device *netdev) 162 { 163 struct xgbe_prv_data *pdata = netdev_priv(netdev); 164 struct xgbe_hw_if *hw_if = &pdata->hw_if; 165 struct phy_device *phydev = pdata->phydev; 166 unsigned long flags; 167 int new_state = 0; 168 169 if (phydev == NULL) 170 return; 171 172 DBGPR_MDIO("-->xgbe_adjust_link: address=%d, newlink=%d, curlink=%d\n", 173 phydev->addr, phydev->link, pdata->phy_link); 174 175 spin_lock_irqsave(&pdata->lock, flags); 176 177 if (phydev->link) { 178 /* Flow control support */ 179 if (pdata->pause_autoneg) { 180 if (phydev->pause || phydev->asym_pause) { 181 pdata->tx_pause = 1; 182 pdata->rx_pause = 1; 183 } else { 184 pdata->tx_pause = 0; 185 pdata->rx_pause = 0; 186 } 187 } 188 189 if (pdata->tx_pause != pdata->phy_tx_pause) { 190 hw_if->config_tx_flow_control(pdata); 191 pdata->phy_tx_pause = pdata->tx_pause; 192 } 193 194 if (pdata->rx_pause != pdata->phy_rx_pause) { 195 hw_if->config_rx_flow_control(pdata); 196 pdata->phy_rx_pause = pdata->rx_pause; 197 } 198 199 /* Speed support */ 200 if (phydev->speed != pdata->phy_speed) { 201 new_state = 1; 202 203 switch (phydev->speed) { 204 case SPEED_10000: 205 hw_if->set_xgmii_speed(pdata); 206 break; 207 208 case SPEED_2500: 209 hw_if->set_gmii_2500_speed(pdata); 210 break; 211 212 case SPEED_1000: 213 hw_if->set_gmii_speed(pdata); 214 break; 215 } 216 pdata->phy_speed = phydev->speed; 217 } 218 219 if (phydev->link != pdata->phy_link) { 220 new_state = 1; 221 pdata->phy_link = 1; 222 } 223 } else if (pdata->phy_link) { 224 new_state = 1; 225 pdata->phy_link = 0; 226 pdata->phy_speed = SPEED_UNKNOWN; 227 } 228 229 if (new_state) 230 phy_print_status(phydev); 231 232 spin_unlock_irqrestore(&pdata->lock, flags); 233 234 DBGPR_MDIO("<--xgbe_adjust_link\n"); 235 } 236 237 void xgbe_dump_phy_registers(struct xgbe_prv_data *pdata) 238 { 239 struct device *dev = pdata->dev; 240 struct phy_device *phydev = pdata->mii->phy_map[XGBE_PRTAD]; 241 int i; 242 243 dev_alert(dev, "\n************* PHY Reg dump **********************\n"); 244 245 dev_alert(dev, "PCS Control Reg (%#04x) = %#04x\n", MDIO_CTRL1, 246 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1)); 247 dev_alert(dev, "PCS Status Reg (%#04x) = %#04x\n", MDIO_STAT1, 248 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1)); 249 dev_alert(dev, "Phy Id (PHYS ID 1 %#04x)= %#04x\n", MDIO_DEVID1, 250 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID1)); 251 dev_alert(dev, "Phy Id (PHYS ID 2 %#04x)= %#04x\n", MDIO_DEVID2, 252 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID2)); 253 dev_alert(dev, "Devices in Package (%#04x)= %#04x\n", MDIO_DEVS1, 254 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS1)); 255 dev_alert(dev, "Devices in Package (%#04x)= %#04x\n", MDIO_DEVS2, 256 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS2)); 257 258 dev_alert(dev, "Auto-Neg Control Reg (%#04x) = %#04x\n", MDIO_CTRL1, 259 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1)); 260 dev_alert(dev, "Auto-Neg Status Reg (%#04x) = %#04x\n", MDIO_STAT1, 261 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_STAT1)); 262 dev_alert(dev, "Auto-Neg Ad Reg 1 (%#04x) = %#04x\n", 263 MDIO_AN_ADVERTISE, 264 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE)); 265 dev_alert(dev, "Auto-Neg Ad Reg 2 (%#04x) = %#04x\n", 266 MDIO_AN_ADVERTISE + 1, 267 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1)); 268 dev_alert(dev, "Auto-Neg Ad Reg 3 (%#04x) = %#04x\n", 269 MDIO_AN_ADVERTISE + 2, 270 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2)); 271 dev_alert(dev, "Auto-Neg Completion Reg (%#04x) = %#04x\n", 272 MDIO_AN_COMP_STAT, 273 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_COMP_STAT)); 274 275 dev_alert(dev, "MMD Device Mask = %#x\n", 276 phydev->c45_ids.devices_in_package); 277 for (i = 0; i < ARRAY_SIZE(phydev->c45_ids.device_ids); i++) 278 dev_alert(dev, " MMD %d: ID = %#08x\n", i, 279 phydev->c45_ids.device_ids[i]); 280 281 dev_alert(dev, "\n*************************************************\n"); 282 } 283 284 int xgbe_mdio_register(struct xgbe_prv_data *pdata) 285 { 286 struct net_device *netdev = pdata->netdev; 287 struct device_node *phy_node; 288 struct mii_bus *mii; 289 struct phy_device *phydev; 290 int ret = 0; 291 292 DBGPR("-->xgbe_mdio_register\n"); 293 294 /* Retrieve the phy-handle */ 295 phy_node = of_parse_phandle(pdata->dev->of_node, "phy-handle", 0); 296 if (!phy_node) { 297 dev_err(pdata->dev, "unable to parse phy-handle\n"); 298 return -EINVAL; 299 } 300 301 /* Register with the MDIO bus */ 302 mii = mdiobus_alloc(); 303 if (mii == NULL) { 304 dev_err(pdata->dev, "mdiobus_alloc failed\n"); 305 ret = -ENOMEM; 306 goto err_node_get; 307 } 308 309 /* Register on the MDIO bus (don't probe any PHYs) */ 310 mii->name = XGBE_PHY_NAME; 311 mii->read = xgbe_mdio_read; 312 mii->write = xgbe_mdio_write; 313 snprintf(mii->id, sizeof(mii->id), "%s", pdata->mii_bus_id); 314 mii->priv = pdata; 315 mii->phy_mask = ~0; 316 mii->parent = pdata->dev; 317 ret = mdiobus_register(mii); 318 if (ret) { 319 dev_err(pdata->dev, "mdiobus_register failed\n"); 320 goto err_mdiobus_alloc; 321 } 322 DBGPR(" mdiobus_register succeeded for %s\n", pdata->mii_bus_id); 323 324 /* Probe the PCS using Clause 45 */ 325 phydev = get_phy_device(mii, XGBE_PRTAD, true); 326 if (IS_ERR(phydev) || !phydev || 327 !phydev->c45_ids.device_ids[MDIO_MMD_PCS]) { 328 dev_err(pdata->dev, "get_phy_device failed\n"); 329 ret = phydev ? PTR_ERR(phydev) : -ENOLINK; 330 goto err_mdiobus_register; 331 } 332 request_module(MDIO_MODULE_PREFIX MDIO_ID_FMT, 333 MDIO_ID_ARGS(phydev->c45_ids.device_ids[MDIO_MMD_PCS])); 334 335 of_node_get(phy_node); 336 phydev->dev.of_node = phy_node; 337 ret = phy_device_register(phydev); 338 if (ret) { 339 dev_err(pdata->dev, "phy_device_register failed\n"); 340 of_node_put(phy_node); 341 goto err_phy_device; 342 } 343 344 /* Add a reference to the PHY driver so it can't be unloaded */ 345 pdata->phy_module = phydev->dev.driver ? 346 phydev->dev.driver->owner : NULL; 347 if (!try_module_get(pdata->phy_module)) { 348 dev_err(pdata->dev, "try_module_get failed\n"); 349 ret = -EIO; 350 goto err_phy_device; 351 } 352 353 pdata->mii = mii; 354 pdata->mdio_mmd = MDIO_MMD_PCS; 355 356 pdata->phy_link = -1; 357 pdata->phy_speed = SPEED_UNKNOWN; 358 pdata->phy_tx_pause = pdata->tx_pause; 359 pdata->phy_rx_pause = pdata->rx_pause; 360 361 ret = phy_connect_direct(netdev, phydev, &xgbe_adjust_link, 362 pdata->phy_mode); 363 if (ret) { 364 netdev_err(netdev, "phy_connect_direct failed\n"); 365 goto err_phy_device; 366 } 367 368 if (!phydev->drv || (phydev->drv->phy_id == 0)) { 369 netdev_err(netdev, "phy_id not valid\n"); 370 ret = -ENODEV; 371 goto err_phy_connect; 372 } 373 DBGPR(" phy_connect_direct succeeded for PHY %s, link=%d\n", 374 dev_name(&phydev->dev), phydev->link); 375 376 phydev->autoneg = pdata->default_autoneg; 377 if (phydev->autoneg == AUTONEG_DISABLE) { 378 /* Add settings needed to force speed */ 379 phydev->supported |= SUPPORTED_1000baseT_Full; 380 phydev->supported |= SUPPORTED_10000baseT_Full; 381 382 phydev->speed = pdata->default_speed; 383 phydev->duplex = DUPLEX_FULL; 384 385 phydev->advertising &= ~ADVERTISED_Autoneg; 386 } 387 388 pdata->phydev = phydev; 389 390 of_node_put(phy_node); 391 392 DBGPHY_REGS(pdata); 393 394 DBGPR("<--xgbe_mdio_register\n"); 395 396 return 0; 397 398 err_phy_connect: 399 phy_disconnect(phydev); 400 401 err_phy_device: 402 phy_device_free(phydev); 403 404 err_mdiobus_register: 405 mdiobus_unregister(mii); 406 407 err_mdiobus_alloc: 408 mdiobus_free(mii); 409 410 err_node_get: 411 of_node_put(phy_node); 412 413 return ret; 414 } 415 416 void xgbe_mdio_unregister(struct xgbe_prv_data *pdata) 417 { 418 DBGPR("-->xgbe_mdio_unregister\n"); 419 420 phy_disconnect(pdata->phydev); 421 pdata->phydev = NULL; 422 423 module_put(pdata->phy_module); 424 pdata->phy_module = NULL; 425 426 mdiobus_unregister(pdata->mii); 427 pdata->mii->priv = NULL; 428 429 mdiobus_free(pdata->mii); 430 pdata->mii = NULL; 431 432 DBGPR("<--xgbe_mdio_unregister\n"); 433 } 434