1 /* 2 * AMD 10Gb Ethernet driver 3 * 4 * This file is available to you under your choice of the following two 5 * licenses: 6 * 7 * License 1: GPLv2 8 * 9 * Copyright (c) 2016 Advanced Micro Devices, Inc. 10 * 11 * This file is free software; you may copy, redistribute and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation, either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program. If not, see <http://www.gnu.org/licenses/>. 23 * 24 * This file incorporates work covered by the following copyright and 25 * permission notice: 26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 28 * Inc. unless otherwise expressly agreed to in writing between Synopsys 29 * and you. 30 * 31 * The Software IS NOT an item of Licensed Software or Licensed Product 32 * under any End User Software License Agreement or Agreement for Licensed 33 * Product with Synopsys or any supplement thereto. Permission is hereby 34 * granted, free of charge, to any person obtaining a copy of this software 35 * annotated with this license and the Software, to deal in the Software 36 * without restriction, including without limitation the rights to use, 37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 38 * of the Software, and to permit persons to whom the Software is furnished 39 * to do so, subject to the following conditions: 40 * 41 * The above copyright notice and this permission notice shall be included 42 * in all copies or substantial portions of the Software. 43 * 44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 54 * THE POSSIBILITY OF SUCH DAMAGE. 55 * 56 * 57 * License 2: Modified BSD 58 * 59 * Copyright (c) 2016 Advanced Micro Devices, Inc. 60 * All rights reserved. 61 * 62 * Redistribution and use in source and binary forms, with or without 63 * modification, are permitted provided that the following conditions are met: 64 * * Redistributions of source code must retain the above copyright 65 * notice, this list of conditions and the following disclaimer. 66 * * Redistributions in binary form must reproduce the above copyright 67 * notice, this list of conditions and the following disclaimer in the 68 * documentation and/or other materials provided with the distribution. 69 * * Neither the name of Advanced Micro Devices, Inc. nor the 70 * names of its contributors may be used to endorse or promote products 71 * derived from this software without specific prior written permission. 72 * 73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY 77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 83 * 84 * This file incorporates work covered by the following copyright and 85 * permission notice: 86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 88 * Inc. unless otherwise expressly agreed to in writing between Synopsys 89 * and you. 90 * 91 * The Software IS NOT an item of Licensed Software or Licensed Product 92 * under any End User Software License Agreement or Agreement for Licensed 93 * Product with Synopsys or any supplement thereto. Permission is hereby 94 * granted, free of charge, to any person obtaining a copy of this software 95 * annotated with this license and the Software, to deal in the Software 96 * without restriction, including without limitation the rights to use, 97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 98 * of the Software, and to permit persons to whom the Software is furnished 99 * to do so, subject to the following conditions: 100 * 101 * The above copyright notice and this permission notice shall be included 102 * in all copies or substantial portions of the Software. 103 * 104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 114 * THE POSSIBILITY OF SUCH DAMAGE. 115 */ 116 117 #include <linux/module.h> 118 #include <linux/kmod.h> 119 #include <linux/delay.h> 120 #include <linux/completion.h> 121 #include <linux/mutex.h> 122 123 #include "xgbe.h" 124 #include "xgbe-common.h" 125 126 #define XGBE_ABORT_COUNT 500 127 #define XGBE_DISABLE_COUNT 1000 128 129 #define XGBE_STD_SPEED 1 130 131 #define XGBE_INTR_RX_FULL BIT(IC_RAW_INTR_STAT_RX_FULL_INDEX) 132 #define XGBE_INTR_TX_EMPTY BIT(IC_RAW_INTR_STAT_TX_EMPTY_INDEX) 133 #define XGBE_INTR_TX_ABRT BIT(IC_RAW_INTR_STAT_TX_ABRT_INDEX) 134 #define XGBE_INTR_STOP_DET BIT(IC_RAW_INTR_STAT_STOP_DET_INDEX) 135 #define XGBE_DEFAULT_INT_MASK (XGBE_INTR_RX_FULL | \ 136 XGBE_INTR_TX_EMPTY | \ 137 XGBE_INTR_TX_ABRT | \ 138 XGBE_INTR_STOP_DET) 139 140 #define XGBE_I2C_READ BIT(8) 141 #define XGBE_I2C_STOP BIT(9) 142 143 static int xgbe_i2c_abort(struct xgbe_prv_data *pdata) 144 { 145 unsigned int wait = XGBE_ABORT_COUNT; 146 147 /* Must be enabled to recognize the abort request */ 148 XI2C_IOWRITE_BITS(pdata, IC_ENABLE, EN, 1); 149 150 /* Issue the abort */ 151 XI2C_IOWRITE_BITS(pdata, IC_ENABLE, ABORT, 1); 152 153 while (wait--) { 154 if (!XI2C_IOREAD_BITS(pdata, IC_ENABLE, ABORT)) 155 return 0; 156 157 usleep_range(500, 600); 158 } 159 160 return -EBUSY; 161 } 162 163 static int xgbe_i2c_set_enable(struct xgbe_prv_data *pdata, bool enable) 164 { 165 unsigned int wait = XGBE_DISABLE_COUNT; 166 unsigned int mode = enable ? 1 : 0; 167 168 while (wait--) { 169 XI2C_IOWRITE_BITS(pdata, IC_ENABLE, EN, mode); 170 if (XI2C_IOREAD_BITS(pdata, IC_ENABLE_STATUS, EN) == mode) 171 return 0; 172 173 usleep_range(100, 110); 174 } 175 176 return -EBUSY; 177 } 178 179 static int xgbe_i2c_disable(struct xgbe_prv_data *pdata) 180 { 181 unsigned int ret; 182 183 ret = xgbe_i2c_set_enable(pdata, false); 184 if (ret) { 185 /* Disable failed, try an abort */ 186 ret = xgbe_i2c_abort(pdata); 187 if (ret) 188 return ret; 189 190 /* Abort succeeded, try to disable again */ 191 ret = xgbe_i2c_set_enable(pdata, false); 192 } 193 194 return ret; 195 } 196 197 static int xgbe_i2c_enable(struct xgbe_prv_data *pdata) 198 { 199 return xgbe_i2c_set_enable(pdata, true); 200 } 201 202 static void xgbe_i2c_clear_all_interrupts(struct xgbe_prv_data *pdata) 203 { 204 XI2C_IOREAD(pdata, IC_CLR_INTR); 205 } 206 207 static void xgbe_i2c_disable_interrupts(struct xgbe_prv_data *pdata) 208 { 209 XI2C_IOWRITE(pdata, IC_INTR_MASK, 0); 210 } 211 212 static void xgbe_i2c_enable_interrupts(struct xgbe_prv_data *pdata) 213 { 214 XI2C_IOWRITE(pdata, IC_INTR_MASK, XGBE_DEFAULT_INT_MASK); 215 } 216 217 static void xgbe_i2c_write(struct xgbe_prv_data *pdata) 218 { 219 struct xgbe_i2c_op_state *state = &pdata->i2c.op_state; 220 unsigned int tx_slots; 221 unsigned int cmd; 222 223 /* Configured to never receive Rx overflows, so fill up Tx fifo */ 224 tx_slots = pdata->i2c.tx_fifo_size - XI2C_IOREAD(pdata, IC_TXFLR); 225 while (tx_slots && state->tx_len) { 226 if (state->op->cmd == XGBE_I2C_CMD_READ) 227 cmd = XGBE_I2C_READ; 228 else 229 cmd = *state->tx_buf++; 230 231 if (state->tx_len == 1) 232 XI2C_SET_BITS(cmd, IC_DATA_CMD, STOP, 1); 233 234 XI2C_IOWRITE(pdata, IC_DATA_CMD, cmd); 235 236 tx_slots--; 237 state->tx_len--; 238 } 239 240 /* No more Tx operations, so ignore TX_EMPTY and return */ 241 if (!state->tx_len) 242 XI2C_IOWRITE_BITS(pdata, IC_INTR_MASK, TX_EMPTY, 0); 243 } 244 245 static void xgbe_i2c_read(struct xgbe_prv_data *pdata) 246 { 247 struct xgbe_i2c_op_state *state = &pdata->i2c.op_state; 248 unsigned int rx_slots; 249 250 /* Anything to be read? */ 251 if (state->op->cmd != XGBE_I2C_CMD_READ) 252 return; 253 254 rx_slots = XI2C_IOREAD(pdata, IC_RXFLR); 255 while (rx_slots && state->rx_len) { 256 *state->rx_buf++ = XI2C_IOREAD(pdata, IC_DATA_CMD); 257 state->rx_len--; 258 rx_slots--; 259 } 260 } 261 262 static void xgbe_i2c_clear_isr_interrupts(struct xgbe_prv_data *pdata, 263 unsigned int isr) 264 { 265 struct xgbe_i2c_op_state *state = &pdata->i2c.op_state; 266 267 if (isr & XGBE_INTR_TX_ABRT) { 268 state->tx_abort_source = XI2C_IOREAD(pdata, IC_TX_ABRT_SOURCE); 269 XI2C_IOREAD(pdata, IC_CLR_TX_ABRT); 270 } 271 272 if (isr & XGBE_INTR_STOP_DET) 273 XI2C_IOREAD(pdata, IC_CLR_STOP_DET); 274 } 275 276 static irqreturn_t xgbe_i2c_isr(int irq, void *data) 277 { 278 struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data; 279 struct xgbe_i2c_op_state *state = &pdata->i2c.op_state; 280 unsigned int isr; 281 282 isr = XI2C_IOREAD(pdata, IC_RAW_INTR_STAT); 283 netif_dbg(pdata, intr, pdata->netdev, 284 "I2C interrupt received: status=%#010x\n", isr); 285 286 xgbe_i2c_clear_isr_interrupts(pdata, isr); 287 288 if (isr & XGBE_INTR_TX_ABRT) { 289 netif_dbg(pdata, link, pdata->netdev, 290 "I2C TX_ABRT received (%#010x) for target %#04x\n", 291 state->tx_abort_source, state->op->target); 292 293 xgbe_i2c_disable_interrupts(pdata); 294 295 state->ret = -EIO; 296 goto out; 297 } 298 299 /* Check for data in the Rx fifo */ 300 xgbe_i2c_read(pdata); 301 302 /* Fill up the Tx fifo next */ 303 xgbe_i2c_write(pdata); 304 305 out: 306 /* Complete on an error or STOP condition */ 307 if (state->ret || XI2C_GET_BITS(isr, IC_RAW_INTR_STAT, STOP_DET)) 308 complete(&pdata->i2c_complete); 309 310 return IRQ_HANDLED; 311 } 312 313 static void xgbe_i2c_set_mode(struct xgbe_prv_data *pdata) 314 { 315 unsigned int reg; 316 317 reg = XI2C_IOREAD(pdata, IC_CON); 318 XI2C_SET_BITS(reg, IC_CON, MASTER_MODE, 1); 319 XI2C_SET_BITS(reg, IC_CON, SLAVE_DISABLE, 1); 320 XI2C_SET_BITS(reg, IC_CON, RESTART_EN, 1); 321 XI2C_SET_BITS(reg, IC_CON, SPEED, XGBE_STD_SPEED); 322 XI2C_SET_BITS(reg, IC_CON, RX_FIFO_FULL_HOLD, 1); 323 XI2C_IOWRITE(pdata, IC_CON, reg); 324 } 325 326 static void xgbe_i2c_get_features(struct xgbe_prv_data *pdata) 327 { 328 struct xgbe_i2c *i2c = &pdata->i2c; 329 unsigned int reg; 330 331 reg = XI2C_IOREAD(pdata, IC_COMP_PARAM_1); 332 i2c->max_speed_mode = XI2C_GET_BITS(reg, IC_COMP_PARAM_1, 333 MAX_SPEED_MODE); 334 i2c->rx_fifo_size = XI2C_GET_BITS(reg, IC_COMP_PARAM_1, 335 RX_BUFFER_DEPTH); 336 i2c->tx_fifo_size = XI2C_GET_BITS(reg, IC_COMP_PARAM_1, 337 TX_BUFFER_DEPTH); 338 339 if (netif_msg_probe(pdata)) 340 dev_dbg(pdata->dev, "I2C features: %s=%u, %s=%u, %s=%u\n", 341 "MAX_SPEED_MODE", i2c->max_speed_mode, 342 "RX_BUFFER_DEPTH", i2c->rx_fifo_size, 343 "TX_BUFFER_DEPTH", i2c->tx_fifo_size); 344 } 345 346 static void xgbe_i2c_set_target(struct xgbe_prv_data *pdata, unsigned int addr) 347 { 348 XI2C_IOWRITE(pdata, IC_TAR, addr); 349 } 350 351 static irqreturn_t xgbe_i2c_combined_isr(int irq, struct xgbe_prv_data *pdata) 352 { 353 if (!XI2C_IOREAD(pdata, IC_RAW_INTR_STAT)) 354 return IRQ_HANDLED; 355 356 return xgbe_i2c_isr(irq, pdata); 357 } 358 359 static int xgbe_i2c_xfer(struct xgbe_prv_data *pdata, struct xgbe_i2c_op *op) 360 { 361 struct xgbe_i2c_op_state *state = &pdata->i2c.op_state; 362 int ret; 363 364 mutex_lock(&pdata->i2c_mutex); 365 366 reinit_completion(&pdata->i2c_complete); 367 368 ret = xgbe_i2c_disable(pdata); 369 if (ret) { 370 netdev_err(pdata->netdev, "failed to disable i2c master\n"); 371 goto unlock; 372 } 373 374 xgbe_i2c_set_target(pdata, op->target); 375 376 memset(state, 0, sizeof(*state)); 377 state->op = op; 378 state->tx_len = op->len; 379 state->tx_buf = op->buf; 380 state->rx_len = op->len; 381 state->rx_buf = op->buf; 382 383 xgbe_i2c_clear_all_interrupts(pdata); 384 ret = xgbe_i2c_enable(pdata); 385 if (ret) { 386 netdev_err(pdata->netdev, "failed to enable i2c master\n"); 387 goto unlock; 388 } 389 390 /* Enabling the interrupts will cause the TX FIFO empty interrupt to 391 * fire and begin to process the command via the ISR. 392 */ 393 xgbe_i2c_enable_interrupts(pdata); 394 395 if (!wait_for_completion_timeout(&pdata->i2c_complete, HZ)) { 396 netdev_err(pdata->netdev, "i2c operation timed out\n"); 397 ret = -ETIMEDOUT; 398 goto disable; 399 } 400 401 ret = state->ret; 402 if (ret) { 403 if (state->tx_abort_source & IC_TX_ABRT_7B_ADDR_NOACK) 404 ret = -ENOTCONN; 405 else if (state->tx_abort_source & IC_TX_ABRT_ARB_LOST) 406 ret = -EAGAIN; 407 } 408 409 disable: 410 xgbe_i2c_disable_interrupts(pdata); 411 xgbe_i2c_disable(pdata); 412 413 unlock: 414 mutex_unlock(&pdata->i2c_mutex); 415 416 return ret; 417 } 418 419 static void xgbe_i2c_stop(struct xgbe_prv_data *pdata) 420 { 421 if (!pdata->i2c.started) 422 return; 423 424 netif_dbg(pdata, link, pdata->netdev, "stopping I2C\n"); 425 426 pdata->i2c.started = 0; 427 428 xgbe_i2c_disable_interrupts(pdata); 429 xgbe_i2c_disable(pdata); 430 xgbe_i2c_clear_all_interrupts(pdata); 431 432 if (pdata->dev_irq != pdata->i2c_irq) 433 devm_free_irq(pdata->dev, pdata->i2c_irq, pdata); 434 } 435 436 static int xgbe_i2c_start(struct xgbe_prv_data *pdata) 437 { 438 int ret; 439 440 if (pdata->i2c.started) 441 return 0; 442 443 netif_dbg(pdata, link, pdata->netdev, "starting I2C\n"); 444 445 /* If we have a separate I2C irq, enable it */ 446 if (pdata->dev_irq != pdata->i2c_irq) { 447 ret = devm_request_irq(pdata->dev, pdata->i2c_irq, 448 xgbe_i2c_isr, 0, pdata->i2c_name, 449 pdata); 450 if (ret) { 451 netdev_err(pdata->netdev, "i2c irq request failed\n"); 452 return ret; 453 } 454 } 455 456 pdata->i2c.started = 1; 457 458 return 0; 459 } 460 461 static int xgbe_i2c_init(struct xgbe_prv_data *pdata) 462 { 463 int ret; 464 465 xgbe_i2c_disable_interrupts(pdata); 466 467 ret = xgbe_i2c_disable(pdata); 468 if (ret) { 469 dev_err(pdata->dev, "failed to disable i2c master\n"); 470 return ret; 471 } 472 473 xgbe_i2c_get_features(pdata); 474 475 xgbe_i2c_set_mode(pdata); 476 477 xgbe_i2c_clear_all_interrupts(pdata); 478 479 return 0; 480 } 481 482 void xgbe_init_function_ptrs_i2c(struct xgbe_i2c_if *i2c_if) 483 { 484 i2c_if->i2c_init = xgbe_i2c_init; 485 486 i2c_if->i2c_start = xgbe_i2c_start; 487 i2c_if->i2c_stop = xgbe_i2c_stop; 488 489 i2c_if->i2c_xfer = xgbe_i2c_xfer; 490 491 i2c_if->i2c_isr = xgbe_i2c_combined_isr; 492 } 493