1 /* 2 * AMD 10Gb Ethernet driver 3 * 4 * This file is available to you under your choice of the following two 5 * licenses: 6 * 7 * License 1: GPLv2 8 * 9 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc. 10 * 11 * This file is free software; you may copy, redistribute and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation, either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program. If not, see <http://www.gnu.org/licenses/>. 23 * 24 * This file incorporates work covered by the following copyright and 25 * permission notice: 26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 28 * Inc. unless otherwise expressly agreed to in writing between Synopsys 29 * and you. 30 * 31 * The Software IS NOT an item of Licensed Software or Licensed Product 32 * under any End User Software License Agreement or Agreement for Licensed 33 * Product with Synopsys or any supplement thereto. Permission is hereby 34 * granted, free of charge, to any person obtaining a copy of this software 35 * annotated with this license and the Software, to deal in the Software 36 * without restriction, including without limitation the rights to use, 37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 38 * of the Software, and to permit persons to whom the Software is furnished 39 * to do so, subject to the following conditions: 40 * 41 * The above copyright notice and this permission notice shall be included 42 * in all copies or substantial portions of the Software. 43 * 44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 54 * THE POSSIBILITY OF SUCH DAMAGE. 55 * 56 * 57 * License 2: Modified BSD 58 * 59 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc. 60 * All rights reserved. 61 * 62 * Redistribution and use in source and binary forms, with or without 63 * modification, are permitted provided that the following conditions are met: 64 * * Redistributions of source code must retain the above copyright 65 * notice, this list of conditions and the following disclaimer. 66 * * Redistributions in binary form must reproduce the above copyright 67 * notice, this list of conditions and the following disclaimer in the 68 * documentation and/or other materials provided with the distribution. 69 * * Neither the name of Advanced Micro Devices, Inc. nor the 70 * names of its contributors may be used to endorse or promote products 71 * derived from this software without specific prior written permission. 72 * 73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY 77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 83 * 84 * This file incorporates work covered by the following copyright and 85 * permission notice: 86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 88 * Inc. unless otherwise expressly agreed to in writing between Synopsys 89 * and you. 90 * 91 * The Software IS NOT an item of Licensed Software or Licensed Product 92 * under any End User Software License Agreement or Agreement for Licensed 93 * Product with Synopsys or any supplement thereto. Permission is hereby 94 * granted, free of charge, to any person obtaining a copy of this software 95 * annotated with this license and the Software, to deal in the Software 96 * without restriction, including without limitation the rights to use, 97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 98 * of the Software, and to permit persons to whom the Software is furnished 99 * to do so, subject to the following conditions: 100 * 101 * The above copyright notice and this permission notice shall be included 102 * in all copies or substantial portions of the Software. 103 * 104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 114 * THE POSSIBILITY OF SUCH DAMAGE. 115 */ 116 117 #include <linux/module.h> 118 #include <linux/spinlock.h> 119 #include <linux/tcp.h> 120 #include <linux/if_vlan.h> 121 #include <net/busy_poll.h> 122 #include <linux/clk.h> 123 #include <linux/if_ether.h> 124 #include <linux/net_tstamp.h> 125 #include <linux/phy.h> 126 127 #include "xgbe.h" 128 #include "xgbe-common.h" 129 130 static unsigned int ecc_sec_info_threshold = 10; 131 static unsigned int ecc_sec_warn_threshold = 10000; 132 static unsigned int ecc_sec_period = 600; 133 static unsigned int ecc_ded_threshold = 2; 134 static unsigned int ecc_ded_period = 600; 135 136 #ifdef CONFIG_AMD_XGBE_HAVE_ECC 137 /* Only expose the ECC parameters if supported */ 138 module_param(ecc_sec_info_threshold, uint, S_IWUSR | S_IRUGO); 139 MODULE_PARM_DESC(ecc_sec_info_threshold, 140 " ECC corrected error informational threshold setting"); 141 142 module_param(ecc_sec_warn_threshold, uint, S_IWUSR | S_IRUGO); 143 MODULE_PARM_DESC(ecc_sec_warn_threshold, 144 " ECC corrected error warning threshold setting"); 145 146 module_param(ecc_sec_period, uint, S_IWUSR | S_IRUGO); 147 MODULE_PARM_DESC(ecc_sec_period, " ECC corrected error period (in seconds)"); 148 149 module_param(ecc_ded_threshold, uint, S_IWUSR | S_IRUGO); 150 MODULE_PARM_DESC(ecc_ded_threshold, " ECC detected error threshold setting"); 151 152 module_param(ecc_ded_period, uint, S_IWUSR | S_IRUGO); 153 MODULE_PARM_DESC(ecc_ded_period, " ECC detected error period (in seconds)"); 154 #endif 155 156 static int xgbe_one_poll(struct napi_struct *, int); 157 static int xgbe_all_poll(struct napi_struct *, int); 158 static void xgbe_stop(struct xgbe_prv_data *); 159 160 static int xgbe_alloc_channels(struct xgbe_prv_data *pdata) 161 { 162 struct xgbe_channel *channel_mem, *channel; 163 struct xgbe_ring *tx_ring, *rx_ring; 164 unsigned int count, i; 165 int ret = -ENOMEM; 166 167 count = max_t(unsigned int, pdata->tx_ring_count, pdata->rx_ring_count); 168 169 channel_mem = kcalloc(count, sizeof(struct xgbe_channel), GFP_KERNEL); 170 if (!channel_mem) 171 goto err_channel; 172 173 tx_ring = kcalloc(pdata->tx_ring_count, sizeof(struct xgbe_ring), 174 GFP_KERNEL); 175 if (!tx_ring) 176 goto err_tx_ring; 177 178 rx_ring = kcalloc(pdata->rx_ring_count, sizeof(struct xgbe_ring), 179 GFP_KERNEL); 180 if (!rx_ring) 181 goto err_rx_ring; 182 183 for (i = 0, channel = channel_mem; i < count; i++, channel++) { 184 snprintf(channel->name, sizeof(channel->name), "channel-%u", i); 185 channel->pdata = pdata; 186 channel->queue_index = i; 187 channel->dma_regs = pdata->xgmac_regs + DMA_CH_BASE + 188 (DMA_CH_INC * i); 189 190 if (pdata->per_channel_irq) 191 channel->dma_irq = pdata->channel_irq[i]; 192 193 if (i < pdata->tx_ring_count) { 194 spin_lock_init(&tx_ring->lock); 195 channel->tx_ring = tx_ring++; 196 } 197 198 if (i < pdata->rx_ring_count) { 199 spin_lock_init(&rx_ring->lock); 200 channel->rx_ring = rx_ring++; 201 } 202 203 netif_dbg(pdata, drv, pdata->netdev, 204 "%s: dma_regs=%p, dma_irq=%d, tx=%p, rx=%p\n", 205 channel->name, channel->dma_regs, channel->dma_irq, 206 channel->tx_ring, channel->rx_ring); 207 } 208 209 pdata->channel = channel_mem; 210 pdata->channel_count = count; 211 212 return 0; 213 214 err_rx_ring: 215 kfree(tx_ring); 216 217 err_tx_ring: 218 kfree(channel_mem); 219 220 err_channel: 221 return ret; 222 } 223 224 static void xgbe_free_channels(struct xgbe_prv_data *pdata) 225 { 226 if (!pdata->channel) 227 return; 228 229 kfree(pdata->channel->rx_ring); 230 kfree(pdata->channel->tx_ring); 231 kfree(pdata->channel); 232 233 pdata->channel = NULL; 234 pdata->channel_count = 0; 235 } 236 237 static inline unsigned int xgbe_tx_avail_desc(struct xgbe_ring *ring) 238 { 239 return (ring->rdesc_count - (ring->cur - ring->dirty)); 240 } 241 242 static inline unsigned int xgbe_rx_dirty_desc(struct xgbe_ring *ring) 243 { 244 return (ring->cur - ring->dirty); 245 } 246 247 static int xgbe_maybe_stop_tx_queue(struct xgbe_channel *channel, 248 struct xgbe_ring *ring, unsigned int count) 249 { 250 struct xgbe_prv_data *pdata = channel->pdata; 251 252 if (count > xgbe_tx_avail_desc(ring)) { 253 netif_info(pdata, drv, pdata->netdev, 254 "Tx queue stopped, not enough descriptors available\n"); 255 netif_stop_subqueue(pdata->netdev, channel->queue_index); 256 ring->tx.queue_stopped = 1; 257 258 /* If we haven't notified the hardware because of xmit_more 259 * support, tell it now 260 */ 261 if (ring->tx.xmit_more) 262 pdata->hw_if.tx_start_xmit(channel, ring); 263 264 return NETDEV_TX_BUSY; 265 } 266 267 return 0; 268 } 269 270 static int xgbe_calc_rx_buf_size(struct net_device *netdev, unsigned int mtu) 271 { 272 unsigned int rx_buf_size; 273 274 rx_buf_size = mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 275 rx_buf_size = clamp_val(rx_buf_size, XGBE_RX_MIN_BUF_SIZE, PAGE_SIZE); 276 277 rx_buf_size = (rx_buf_size + XGBE_RX_BUF_ALIGN - 1) & 278 ~(XGBE_RX_BUF_ALIGN - 1); 279 280 return rx_buf_size; 281 } 282 283 static void xgbe_enable_rx_tx_int(struct xgbe_prv_data *pdata, 284 struct xgbe_channel *channel) 285 { 286 struct xgbe_hw_if *hw_if = &pdata->hw_if; 287 enum xgbe_int int_id; 288 289 if (channel->tx_ring && channel->rx_ring) 290 int_id = XGMAC_INT_DMA_CH_SR_TI_RI; 291 else if (channel->tx_ring) 292 int_id = XGMAC_INT_DMA_CH_SR_TI; 293 else if (channel->rx_ring) 294 int_id = XGMAC_INT_DMA_CH_SR_RI; 295 else 296 return; 297 298 hw_if->enable_int(channel, int_id); 299 } 300 301 static void xgbe_enable_rx_tx_ints(struct xgbe_prv_data *pdata) 302 { 303 struct xgbe_channel *channel; 304 unsigned int i; 305 306 channel = pdata->channel; 307 for (i = 0; i < pdata->channel_count; i++, channel++) 308 xgbe_enable_rx_tx_int(pdata, channel); 309 } 310 311 static void xgbe_disable_rx_tx_int(struct xgbe_prv_data *pdata, 312 struct xgbe_channel *channel) 313 { 314 struct xgbe_hw_if *hw_if = &pdata->hw_if; 315 enum xgbe_int int_id; 316 317 if (channel->tx_ring && channel->rx_ring) 318 int_id = XGMAC_INT_DMA_CH_SR_TI_RI; 319 else if (channel->tx_ring) 320 int_id = XGMAC_INT_DMA_CH_SR_TI; 321 else if (channel->rx_ring) 322 int_id = XGMAC_INT_DMA_CH_SR_RI; 323 else 324 return; 325 326 hw_if->disable_int(channel, int_id); 327 } 328 329 static void xgbe_disable_rx_tx_ints(struct xgbe_prv_data *pdata) 330 { 331 struct xgbe_channel *channel; 332 unsigned int i; 333 334 channel = pdata->channel; 335 for (i = 0; i < pdata->channel_count; i++, channel++) 336 xgbe_disable_rx_tx_int(pdata, channel); 337 } 338 339 static bool xgbe_ecc_sec(struct xgbe_prv_data *pdata, unsigned long *period, 340 unsigned int *count, const char *area) 341 { 342 if (time_before(jiffies, *period)) { 343 (*count)++; 344 } else { 345 *period = jiffies + (ecc_sec_period * HZ); 346 *count = 1; 347 } 348 349 if (*count > ecc_sec_info_threshold) 350 dev_warn_once(pdata->dev, 351 "%s ECC corrected errors exceed informational threshold\n", 352 area); 353 354 if (*count > ecc_sec_warn_threshold) { 355 dev_warn_once(pdata->dev, 356 "%s ECC corrected errors exceed warning threshold\n", 357 area); 358 return true; 359 } 360 361 return false; 362 } 363 364 static bool xgbe_ecc_ded(struct xgbe_prv_data *pdata, unsigned long *period, 365 unsigned int *count, const char *area) 366 { 367 if (time_before(jiffies, *period)) { 368 (*count)++; 369 } else { 370 *period = jiffies + (ecc_ded_period * HZ); 371 *count = 1; 372 } 373 374 if (*count > ecc_ded_threshold) { 375 netdev_alert(pdata->netdev, 376 "%s ECC detected errors exceed threshold\n", 377 area); 378 return true; 379 } 380 381 return false; 382 } 383 384 static irqreturn_t xgbe_ecc_isr(int irq, void *data) 385 { 386 struct xgbe_prv_data *pdata = data; 387 unsigned int ecc_isr; 388 bool stop = false; 389 390 /* Mask status with only the interrupts we care about */ 391 ecc_isr = XP_IOREAD(pdata, XP_ECC_ISR); 392 ecc_isr &= XP_IOREAD(pdata, XP_ECC_IER); 393 netif_dbg(pdata, intr, pdata->netdev, "ECC_ISR=%#010x\n", ecc_isr); 394 395 if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, TX_DED)) { 396 stop |= xgbe_ecc_ded(pdata, &pdata->tx_ded_period, 397 &pdata->tx_ded_count, "TX fifo"); 398 } 399 400 if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, RX_DED)) { 401 stop |= xgbe_ecc_ded(pdata, &pdata->rx_ded_period, 402 &pdata->rx_ded_count, "RX fifo"); 403 } 404 405 if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, DESC_DED)) { 406 stop |= xgbe_ecc_ded(pdata, &pdata->desc_ded_period, 407 &pdata->desc_ded_count, 408 "descriptor cache"); 409 } 410 411 if (stop) { 412 pdata->hw_if.disable_ecc_ded(pdata); 413 schedule_work(&pdata->stopdev_work); 414 goto out; 415 } 416 417 if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, TX_SEC)) { 418 if (xgbe_ecc_sec(pdata, &pdata->tx_sec_period, 419 &pdata->tx_sec_count, "TX fifo")) 420 pdata->hw_if.disable_ecc_sec(pdata, XGBE_ECC_SEC_TX); 421 } 422 423 if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, RX_SEC)) 424 if (xgbe_ecc_sec(pdata, &pdata->rx_sec_period, 425 &pdata->rx_sec_count, "RX fifo")) 426 pdata->hw_if.disable_ecc_sec(pdata, XGBE_ECC_SEC_RX); 427 428 if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, DESC_SEC)) 429 if (xgbe_ecc_sec(pdata, &pdata->desc_sec_period, 430 &pdata->desc_sec_count, "descriptor cache")) 431 pdata->hw_if.disable_ecc_sec(pdata, XGBE_ECC_SEC_DESC); 432 433 out: 434 /* Clear all ECC interrupts */ 435 XP_IOWRITE(pdata, XP_ECC_ISR, ecc_isr); 436 437 return IRQ_HANDLED; 438 } 439 440 static irqreturn_t xgbe_isr(int irq, void *data) 441 { 442 struct xgbe_prv_data *pdata = data; 443 struct xgbe_hw_if *hw_if = &pdata->hw_if; 444 struct xgbe_channel *channel; 445 unsigned int dma_isr, dma_ch_isr; 446 unsigned int mac_isr, mac_tssr, mac_mdioisr; 447 unsigned int i; 448 449 /* The DMA interrupt status register also reports MAC and MTL 450 * interrupts. So for polling mode, we just need to check for 451 * this register to be non-zero 452 */ 453 dma_isr = XGMAC_IOREAD(pdata, DMA_ISR); 454 if (!dma_isr) 455 goto isr_done; 456 457 netif_dbg(pdata, intr, pdata->netdev, "DMA_ISR=%#010x\n", dma_isr); 458 459 for (i = 0; i < pdata->channel_count; i++) { 460 if (!(dma_isr & (1 << i))) 461 continue; 462 463 channel = pdata->channel + i; 464 465 dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR); 466 netif_dbg(pdata, intr, pdata->netdev, "DMA_CH%u_ISR=%#010x\n", 467 i, dma_ch_isr); 468 469 /* The TI or RI interrupt bits may still be set even if using 470 * per channel DMA interrupts. Check to be sure those are not 471 * enabled before using the private data napi structure. 472 */ 473 if (!pdata->per_channel_irq && 474 (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, TI) || 475 XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RI))) { 476 if (napi_schedule_prep(&pdata->napi)) { 477 /* Disable Tx and Rx interrupts */ 478 xgbe_disable_rx_tx_ints(pdata); 479 480 /* Turn on polling */ 481 __napi_schedule_irqoff(&pdata->napi); 482 } 483 } else { 484 /* Don't clear Rx/Tx status if doing per channel DMA 485 * interrupts, these will be cleared by the ISR for 486 * per channel DMA interrupts. 487 */ 488 XGMAC_SET_BITS(dma_ch_isr, DMA_CH_SR, TI, 0); 489 XGMAC_SET_BITS(dma_ch_isr, DMA_CH_SR, RI, 0); 490 } 491 492 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RBU)) 493 pdata->ext_stats.rx_buffer_unavailable++; 494 495 /* Restart the device on a Fatal Bus Error */ 496 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, FBE)) 497 schedule_work(&pdata->restart_work); 498 499 /* Clear interrupt signals */ 500 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr); 501 } 502 503 if (XGMAC_GET_BITS(dma_isr, DMA_ISR, MACIS)) { 504 mac_isr = XGMAC_IOREAD(pdata, MAC_ISR); 505 506 netif_dbg(pdata, intr, pdata->netdev, "MAC_ISR=%#010x\n", 507 mac_isr); 508 509 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCTXIS)) 510 hw_if->tx_mmc_int(pdata); 511 512 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCRXIS)) 513 hw_if->rx_mmc_int(pdata); 514 515 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, TSIS)) { 516 mac_tssr = XGMAC_IOREAD(pdata, MAC_TSSR); 517 518 netif_dbg(pdata, intr, pdata->netdev, 519 "MAC_TSSR=%#010x\n", mac_tssr); 520 521 if (XGMAC_GET_BITS(mac_tssr, MAC_TSSR, TXTSC)) { 522 /* Read Tx Timestamp to clear interrupt */ 523 pdata->tx_tstamp = 524 hw_if->get_tx_tstamp(pdata); 525 queue_work(pdata->dev_workqueue, 526 &pdata->tx_tstamp_work); 527 } 528 } 529 530 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, SMI)) { 531 mac_mdioisr = XGMAC_IOREAD(pdata, MAC_MDIOISR); 532 533 netif_dbg(pdata, intr, pdata->netdev, 534 "MAC_MDIOISR=%#010x\n", mac_mdioisr); 535 536 if (XGMAC_GET_BITS(mac_mdioisr, MAC_MDIOISR, 537 SNGLCOMPINT)) 538 complete(&pdata->mdio_complete); 539 } 540 } 541 542 /* If there is not a separate AN irq, handle it here */ 543 if (pdata->dev_irq == pdata->an_irq) 544 pdata->phy_if.an_isr(irq, pdata); 545 546 /* If there is not a separate ECC irq, handle it here */ 547 if (pdata->vdata->ecc_support && (pdata->dev_irq == pdata->ecc_irq)) 548 xgbe_ecc_isr(irq, pdata); 549 550 /* If there is not a separate I2C irq, handle it here */ 551 if (pdata->vdata->i2c_support && (pdata->dev_irq == pdata->i2c_irq)) 552 pdata->i2c_if.i2c_isr(irq, pdata); 553 554 isr_done: 555 return IRQ_HANDLED; 556 } 557 558 static irqreturn_t xgbe_dma_isr(int irq, void *data) 559 { 560 struct xgbe_channel *channel = data; 561 struct xgbe_prv_data *pdata = channel->pdata; 562 unsigned int dma_status; 563 564 /* Per channel DMA interrupts are enabled, so we use the per 565 * channel napi structure and not the private data napi structure 566 */ 567 if (napi_schedule_prep(&channel->napi)) { 568 /* Disable Tx and Rx interrupts */ 569 if (pdata->channel_irq_mode) 570 xgbe_disable_rx_tx_int(pdata, channel); 571 else 572 disable_irq_nosync(channel->dma_irq); 573 574 /* Turn on polling */ 575 __napi_schedule_irqoff(&channel->napi); 576 } 577 578 /* Clear Tx/Rx signals */ 579 dma_status = 0; 580 XGMAC_SET_BITS(dma_status, DMA_CH_SR, TI, 1); 581 XGMAC_SET_BITS(dma_status, DMA_CH_SR, RI, 1); 582 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_status); 583 584 return IRQ_HANDLED; 585 } 586 587 static void xgbe_tx_timer(unsigned long data) 588 { 589 struct xgbe_channel *channel = (struct xgbe_channel *)data; 590 struct xgbe_prv_data *pdata = channel->pdata; 591 struct napi_struct *napi; 592 593 DBGPR("-->xgbe_tx_timer\n"); 594 595 napi = (pdata->per_channel_irq) ? &channel->napi : &pdata->napi; 596 597 if (napi_schedule_prep(napi)) { 598 /* Disable Tx and Rx interrupts */ 599 if (pdata->per_channel_irq) 600 if (pdata->channel_irq_mode) 601 xgbe_disable_rx_tx_int(pdata, channel); 602 else 603 disable_irq_nosync(channel->dma_irq); 604 else 605 xgbe_disable_rx_tx_ints(pdata); 606 607 /* Turn on polling */ 608 __napi_schedule(napi); 609 } 610 611 channel->tx_timer_active = 0; 612 613 DBGPR("<--xgbe_tx_timer\n"); 614 } 615 616 static void xgbe_service(struct work_struct *work) 617 { 618 struct xgbe_prv_data *pdata = container_of(work, 619 struct xgbe_prv_data, 620 service_work); 621 622 pdata->phy_if.phy_status(pdata); 623 } 624 625 static void xgbe_service_timer(unsigned long data) 626 { 627 struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data; 628 629 queue_work(pdata->dev_workqueue, &pdata->service_work); 630 631 mod_timer(&pdata->service_timer, jiffies + HZ); 632 } 633 634 static void xgbe_init_timers(struct xgbe_prv_data *pdata) 635 { 636 struct xgbe_channel *channel; 637 unsigned int i; 638 639 setup_timer(&pdata->service_timer, xgbe_service_timer, 640 (unsigned long)pdata); 641 642 channel = pdata->channel; 643 for (i = 0; i < pdata->channel_count; i++, channel++) { 644 if (!channel->tx_ring) 645 break; 646 647 setup_timer(&channel->tx_timer, xgbe_tx_timer, 648 (unsigned long)channel); 649 } 650 } 651 652 static void xgbe_start_timers(struct xgbe_prv_data *pdata) 653 { 654 mod_timer(&pdata->service_timer, jiffies + HZ); 655 } 656 657 static void xgbe_stop_timers(struct xgbe_prv_data *pdata) 658 { 659 struct xgbe_channel *channel; 660 unsigned int i; 661 662 del_timer_sync(&pdata->service_timer); 663 664 channel = pdata->channel; 665 for (i = 0; i < pdata->channel_count; i++, channel++) { 666 if (!channel->tx_ring) 667 break; 668 669 del_timer_sync(&channel->tx_timer); 670 } 671 } 672 673 void xgbe_get_all_hw_features(struct xgbe_prv_data *pdata) 674 { 675 unsigned int mac_hfr0, mac_hfr1, mac_hfr2; 676 struct xgbe_hw_features *hw_feat = &pdata->hw_feat; 677 678 DBGPR("-->xgbe_get_all_hw_features\n"); 679 680 mac_hfr0 = XGMAC_IOREAD(pdata, MAC_HWF0R); 681 mac_hfr1 = XGMAC_IOREAD(pdata, MAC_HWF1R); 682 mac_hfr2 = XGMAC_IOREAD(pdata, MAC_HWF2R); 683 684 memset(hw_feat, 0, sizeof(*hw_feat)); 685 686 hw_feat->version = XGMAC_IOREAD(pdata, MAC_VR); 687 688 /* Hardware feature register 0 */ 689 hw_feat->gmii = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, GMIISEL); 690 hw_feat->vlhash = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VLHASH); 691 hw_feat->sma = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SMASEL); 692 hw_feat->rwk = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RWKSEL); 693 hw_feat->mgk = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MGKSEL); 694 hw_feat->mmc = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MMCSEL); 695 hw_feat->aoe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, ARPOFFSEL); 696 hw_feat->ts = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSEL); 697 hw_feat->eee = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, EEESEL); 698 hw_feat->tx_coe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TXCOESEL); 699 hw_feat->rx_coe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RXCOESEL); 700 hw_feat->addn_mac = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, 701 ADDMACADRSEL); 702 hw_feat->ts_src = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSTSSEL); 703 hw_feat->sa_vlan_ins = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SAVLANINS); 704 705 /* Hardware feature register 1 */ 706 hw_feat->rx_fifo_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, 707 RXFIFOSIZE); 708 hw_feat->tx_fifo_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, 709 TXFIFOSIZE); 710 hw_feat->adv_ts_hi = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADVTHWORD); 711 hw_feat->dma_width = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADDR64); 712 hw_feat->dcb = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DCBEN); 713 hw_feat->sph = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, SPHEN); 714 hw_feat->tso = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, TSOEN); 715 hw_feat->dma_debug = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DBGMEMA); 716 hw_feat->rss = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, RSSEN); 717 hw_feat->tc_cnt = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, NUMTC); 718 hw_feat->hash_table_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, 719 HASHTBLSZ); 720 hw_feat->l3l4_filter_num = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, 721 L3L4FNUM); 722 723 /* Hardware feature register 2 */ 724 hw_feat->rx_q_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXQCNT); 725 hw_feat->tx_q_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXQCNT); 726 hw_feat->rx_ch_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXCHCNT); 727 hw_feat->tx_ch_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXCHCNT); 728 hw_feat->pps_out_num = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, PPSOUTNUM); 729 hw_feat->aux_snap_num = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, AUXSNAPNUM); 730 731 /* Translate the Hash Table size into actual number */ 732 switch (hw_feat->hash_table_size) { 733 case 0: 734 break; 735 case 1: 736 hw_feat->hash_table_size = 64; 737 break; 738 case 2: 739 hw_feat->hash_table_size = 128; 740 break; 741 case 3: 742 hw_feat->hash_table_size = 256; 743 break; 744 } 745 746 /* Translate the address width setting into actual number */ 747 switch (hw_feat->dma_width) { 748 case 0: 749 hw_feat->dma_width = 32; 750 break; 751 case 1: 752 hw_feat->dma_width = 40; 753 break; 754 case 2: 755 hw_feat->dma_width = 48; 756 break; 757 default: 758 hw_feat->dma_width = 32; 759 } 760 761 /* The Queue, Channel and TC counts are zero based so increment them 762 * to get the actual number 763 */ 764 hw_feat->rx_q_cnt++; 765 hw_feat->tx_q_cnt++; 766 hw_feat->rx_ch_cnt++; 767 hw_feat->tx_ch_cnt++; 768 hw_feat->tc_cnt++; 769 770 /* Translate the fifo sizes into actual numbers */ 771 hw_feat->rx_fifo_size = 1 << (hw_feat->rx_fifo_size + 7); 772 hw_feat->tx_fifo_size = 1 << (hw_feat->tx_fifo_size + 7); 773 774 DBGPR("<--xgbe_get_all_hw_features\n"); 775 } 776 777 static void xgbe_napi_enable(struct xgbe_prv_data *pdata, unsigned int add) 778 { 779 struct xgbe_channel *channel; 780 unsigned int i; 781 782 if (pdata->per_channel_irq) { 783 channel = pdata->channel; 784 for (i = 0; i < pdata->channel_count; i++, channel++) { 785 if (add) 786 netif_napi_add(pdata->netdev, &channel->napi, 787 xgbe_one_poll, NAPI_POLL_WEIGHT); 788 789 napi_enable(&channel->napi); 790 } 791 } else { 792 if (add) 793 netif_napi_add(pdata->netdev, &pdata->napi, 794 xgbe_all_poll, NAPI_POLL_WEIGHT); 795 796 napi_enable(&pdata->napi); 797 } 798 } 799 800 static void xgbe_napi_disable(struct xgbe_prv_data *pdata, unsigned int del) 801 { 802 struct xgbe_channel *channel; 803 unsigned int i; 804 805 if (pdata->per_channel_irq) { 806 channel = pdata->channel; 807 for (i = 0; i < pdata->channel_count; i++, channel++) { 808 napi_disable(&channel->napi); 809 810 if (del) 811 netif_napi_del(&channel->napi); 812 } 813 } else { 814 napi_disable(&pdata->napi); 815 816 if (del) 817 netif_napi_del(&pdata->napi); 818 } 819 } 820 821 static int xgbe_request_irqs(struct xgbe_prv_data *pdata) 822 { 823 struct xgbe_channel *channel; 824 struct net_device *netdev = pdata->netdev; 825 unsigned int i; 826 int ret; 827 828 ret = devm_request_irq(pdata->dev, pdata->dev_irq, xgbe_isr, 0, 829 netdev->name, pdata); 830 if (ret) { 831 netdev_alert(netdev, "error requesting irq %d\n", 832 pdata->dev_irq); 833 return ret; 834 } 835 836 if (pdata->vdata->ecc_support && (pdata->dev_irq != pdata->ecc_irq)) { 837 ret = devm_request_irq(pdata->dev, pdata->ecc_irq, xgbe_ecc_isr, 838 0, pdata->ecc_name, pdata); 839 if (ret) { 840 netdev_alert(netdev, "error requesting ecc irq %d\n", 841 pdata->ecc_irq); 842 goto err_dev_irq; 843 } 844 } 845 846 if (!pdata->per_channel_irq) 847 return 0; 848 849 channel = pdata->channel; 850 for (i = 0; i < pdata->channel_count; i++, channel++) { 851 snprintf(channel->dma_irq_name, 852 sizeof(channel->dma_irq_name) - 1, 853 "%s-TxRx-%u", netdev_name(netdev), 854 channel->queue_index); 855 856 ret = devm_request_irq(pdata->dev, channel->dma_irq, 857 xgbe_dma_isr, 0, 858 channel->dma_irq_name, channel); 859 if (ret) { 860 netdev_alert(netdev, "error requesting irq %d\n", 861 channel->dma_irq); 862 goto err_dma_irq; 863 } 864 } 865 866 return 0; 867 868 err_dma_irq: 869 /* Using an unsigned int, 'i' will go to UINT_MAX and exit */ 870 for (i--, channel--; i < pdata->channel_count; i--, channel--) 871 devm_free_irq(pdata->dev, channel->dma_irq, channel); 872 873 if (pdata->vdata->ecc_support && (pdata->dev_irq != pdata->ecc_irq)) 874 devm_free_irq(pdata->dev, pdata->ecc_irq, pdata); 875 876 err_dev_irq: 877 devm_free_irq(pdata->dev, pdata->dev_irq, pdata); 878 879 return ret; 880 } 881 882 static void xgbe_free_irqs(struct xgbe_prv_data *pdata) 883 { 884 struct xgbe_channel *channel; 885 unsigned int i; 886 887 devm_free_irq(pdata->dev, pdata->dev_irq, pdata); 888 889 if (pdata->vdata->ecc_support && (pdata->dev_irq != pdata->ecc_irq)) 890 devm_free_irq(pdata->dev, pdata->ecc_irq, pdata); 891 892 if (!pdata->per_channel_irq) 893 return; 894 895 channel = pdata->channel; 896 for (i = 0; i < pdata->channel_count; i++, channel++) 897 devm_free_irq(pdata->dev, channel->dma_irq, channel); 898 } 899 900 void xgbe_init_tx_coalesce(struct xgbe_prv_data *pdata) 901 { 902 struct xgbe_hw_if *hw_if = &pdata->hw_if; 903 904 DBGPR("-->xgbe_init_tx_coalesce\n"); 905 906 pdata->tx_usecs = XGMAC_INIT_DMA_TX_USECS; 907 pdata->tx_frames = XGMAC_INIT_DMA_TX_FRAMES; 908 909 hw_if->config_tx_coalesce(pdata); 910 911 DBGPR("<--xgbe_init_tx_coalesce\n"); 912 } 913 914 void xgbe_init_rx_coalesce(struct xgbe_prv_data *pdata) 915 { 916 struct xgbe_hw_if *hw_if = &pdata->hw_if; 917 918 DBGPR("-->xgbe_init_rx_coalesce\n"); 919 920 pdata->rx_riwt = hw_if->usec_to_riwt(pdata, XGMAC_INIT_DMA_RX_USECS); 921 pdata->rx_usecs = XGMAC_INIT_DMA_RX_USECS; 922 pdata->rx_frames = XGMAC_INIT_DMA_RX_FRAMES; 923 924 hw_if->config_rx_coalesce(pdata); 925 926 DBGPR("<--xgbe_init_rx_coalesce\n"); 927 } 928 929 static void xgbe_free_tx_data(struct xgbe_prv_data *pdata) 930 { 931 struct xgbe_desc_if *desc_if = &pdata->desc_if; 932 struct xgbe_channel *channel; 933 struct xgbe_ring *ring; 934 struct xgbe_ring_data *rdata; 935 unsigned int i, j; 936 937 DBGPR("-->xgbe_free_tx_data\n"); 938 939 channel = pdata->channel; 940 for (i = 0; i < pdata->channel_count; i++, channel++) { 941 ring = channel->tx_ring; 942 if (!ring) 943 break; 944 945 for (j = 0; j < ring->rdesc_count; j++) { 946 rdata = XGBE_GET_DESC_DATA(ring, j); 947 desc_if->unmap_rdata(pdata, rdata); 948 } 949 } 950 951 DBGPR("<--xgbe_free_tx_data\n"); 952 } 953 954 static void xgbe_free_rx_data(struct xgbe_prv_data *pdata) 955 { 956 struct xgbe_desc_if *desc_if = &pdata->desc_if; 957 struct xgbe_channel *channel; 958 struct xgbe_ring *ring; 959 struct xgbe_ring_data *rdata; 960 unsigned int i, j; 961 962 DBGPR("-->xgbe_free_rx_data\n"); 963 964 channel = pdata->channel; 965 for (i = 0; i < pdata->channel_count; i++, channel++) { 966 ring = channel->rx_ring; 967 if (!ring) 968 break; 969 970 for (j = 0; j < ring->rdesc_count; j++) { 971 rdata = XGBE_GET_DESC_DATA(ring, j); 972 desc_if->unmap_rdata(pdata, rdata); 973 } 974 } 975 976 DBGPR("<--xgbe_free_rx_data\n"); 977 } 978 979 static int xgbe_phy_reset(struct xgbe_prv_data *pdata) 980 { 981 pdata->phy_link = -1; 982 pdata->phy_speed = SPEED_UNKNOWN; 983 984 return pdata->phy_if.phy_reset(pdata); 985 } 986 987 int xgbe_powerdown(struct net_device *netdev, unsigned int caller) 988 { 989 struct xgbe_prv_data *pdata = netdev_priv(netdev); 990 struct xgbe_hw_if *hw_if = &pdata->hw_if; 991 unsigned long flags; 992 993 DBGPR("-->xgbe_powerdown\n"); 994 995 if (!netif_running(netdev) || 996 (caller == XGMAC_IOCTL_CONTEXT && pdata->power_down)) { 997 netdev_alert(netdev, "Device is already powered down\n"); 998 DBGPR("<--xgbe_powerdown\n"); 999 return -EINVAL; 1000 } 1001 1002 spin_lock_irqsave(&pdata->lock, flags); 1003 1004 if (caller == XGMAC_DRIVER_CONTEXT) 1005 netif_device_detach(netdev); 1006 1007 netif_tx_stop_all_queues(netdev); 1008 1009 xgbe_stop_timers(pdata); 1010 flush_workqueue(pdata->dev_workqueue); 1011 1012 hw_if->powerdown_tx(pdata); 1013 hw_if->powerdown_rx(pdata); 1014 1015 xgbe_napi_disable(pdata, 0); 1016 1017 pdata->power_down = 1; 1018 1019 spin_unlock_irqrestore(&pdata->lock, flags); 1020 1021 DBGPR("<--xgbe_powerdown\n"); 1022 1023 return 0; 1024 } 1025 1026 int xgbe_powerup(struct net_device *netdev, unsigned int caller) 1027 { 1028 struct xgbe_prv_data *pdata = netdev_priv(netdev); 1029 struct xgbe_hw_if *hw_if = &pdata->hw_if; 1030 unsigned long flags; 1031 1032 DBGPR("-->xgbe_powerup\n"); 1033 1034 if (!netif_running(netdev) || 1035 (caller == XGMAC_IOCTL_CONTEXT && !pdata->power_down)) { 1036 netdev_alert(netdev, "Device is already powered up\n"); 1037 DBGPR("<--xgbe_powerup\n"); 1038 return -EINVAL; 1039 } 1040 1041 spin_lock_irqsave(&pdata->lock, flags); 1042 1043 pdata->power_down = 0; 1044 1045 xgbe_napi_enable(pdata, 0); 1046 1047 hw_if->powerup_tx(pdata); 1048 hw_if->powerup_rx(pdata); 1049 1050 if (caller == XGMAC_DRIVER_CONTEXT) 1051 netif_device_attach(netdev); 1052 1053 netif_tx_start_all_queues(netdev); 1054 1055 xgbe_start_timers(pdata); 1056 1057 spin_unlock_irqrestore(&pdata->lock, flags); 1058 1059 DBGPR("<--xgbe_powerup\n"); 1060 1061 return 0; 1062 } 1063 1064 static int xgbe_start(struct xgbe_prv_data *pdata) 1065 { 1066 struct xgbe_hw_if *hw_if = &pdata->hw_if; 1067 struct xgbe_phy_if *phy_if = &pdata->phy_if; 1068 struct net_device *netdev = pdata->netdev; 1069 int ret; 1070 1071 DBGPR("-->xgbe_start\n"); 1072 1073 hw_if->init(pdata); 1074 1075 xgbe_napi_enable(pdata, 1); 1076 1077 ret = xgbe_request_irqs(pdata); 1078 if (ret) 1079 goto err_napi; 1080 1081 ret = phy_if->phy_start(pdata); 1082 if (ret) 1083 goto err_irqs; 1084 1085 hw_if->enable_tx(pdata); 1086 hw_if->enable_rx(pdata); 1087 1088 netif_tx_start_all_queues(netdev); 1089 1090 xgbe_start_timers(pdata); 1091 queue_work(pdata->dev_workqueue, &pdata->service_work); 1092 1093 clear_bit(XGBE_STOPPED, &pdata->dev_state); 1094 1095 DBGPR("<--xgbe_start\n"); 1096 1097 return 0; 1098 1099 err_irqs: 1100 xgbe_free_irqs(pdata); 1101 1102 err_napi: 1103 xgbe_napi_disable(pdata, 1); 1104 1105 hw_if->exit(pdata); 1106 1107 return ret; 1108 } 1109 1110 static void xgbe_stop(struct xgbe_prv_data *pdata) 1111 { 1112 struct xgbe_hw_if *hw_if = &pdata->hw_if; 1113 struct xgbe_phy_if *phy_if = &pdata->phy_if; 1114 struct xgbe_channel *channel; 1115 struct net_device *netdev = pdata->netdev; 1116 struct netdev_queue *txq; 1117 unsigned int i; 1118 1119 DBGPR("-->xgbe_stop\n"); 1120 1121 if (test_bit(XGBE_STOPPED, &pdata->dev_state)) 1122 return; 1123 1124 netif_tx_stop_all_queues(netdev); 1125 1126 xgbe_stop_timers(pdata); 1127 flush_workqueue(pdata->dev_workqueue); 1128 1129 hw_if->disable_tx(pdata); 1130 hw_if->disable_rx(pdata); 1131 1132 xgbe_free_irqs(pdata); 1133 1134 xgbe_napi_disable(pdata, 1); 1135 1136 phy_if->phy_stop(pdata); 1137 1138 hw_if->exit(pdata); 1139 1140 channel = pdata->channel; 1141 for (i = 0; i < pdata->channel_count; i++, channel++) { 1142 if (!channel->tx_ring) 1143 continue; 1144 1145 txq = netdev_get_tx_queue(netdev, channel->queue_index); 1146 netdev_tx_reset_queue(txq); 1147 } 1148 1149 set_bit(XGBE_STOPPED, &pdata->dev_state); 1150 1151 DBGPR("<--xgbe_stop\n"); 1152 } 1153 1154 static void xgbe_stopdev(struct work_struct *work) 1155 { 1156 struct xgbe_prv_data *pdata = container_of(work, 1157 struct xgbe_prv_data, 1158 stopdev_work); 1159 1160 rtnl_lock(); 1161 1162 xgbe_stop(pdata); 1163 1164 xgbe_free_tx_data(pdata); 1165 xgbe_free_rx_data(pdata); 1166 1167 rtnl_unlock(); 1168 1169 netdev_alert(pdata->netdev, "device stopped\n"); 1170 } 1171 1172 static void xgbe_restart_dev(struct xgbe_prv_data *pdata) 1173 { 1174 DBGPR("-->xgbe_restart_dev\n"); 1175 1176 /* If not running, "restart" will happen on open */ 1177 if (!netif_running(pdata->netdev)) 1178 return; 1179 1180 xgbe_stop(pdata); 1181 1182 xgbe_free_tx_data(pdata); 1183 xgbe_free_rx_data(pdata); 1184 1185 xgbe_start(pdata); 1186 1187 DBGPR("<--xgbe_restart_dev\n"); 1188 } 1189 1190 static void xgbe_restart(struct work_struct *work) 1191 { 1192 struct xgbe_prv_data *pdata = container_of(work, 1193 struct xgbe_prv_data, 1194 restart_work); 1195 1196 rtnl_lock(); 1197 1198 xgbe_restart_dev(pdata); 1199 1200 rtnl_unlock(); 1201 } 1202 1203 static void xgbe_tx_tstamp(struct work_struct *work) 1204 { 1205 struct xgbe_prv_data *pdata = container_of(work, 1206 struct xgbe_prv_data, 1207 tx_tstamp_work); 1208 struct skb_shared_hwtstamps hwtstamps; 1209 u64 nsec; 1210 unsigned long flags; 1211 1212 if (pdata->tx_tstamp) { 1213 nsec = timecounter_cyc2time(&pdata->tstamp_tc, 1214 pdata->tx_tstamp); 1215 1216 memset(&hwtstamps, 0, sizeof(hwtstamps)); 1217 hwtstamps.hwtstamp = ns_to_ktime(nsec); 1218 skb_tstamp_tx(pdata->tx_tstamp_skb, &hwtstamps); 1219 } 1220 1221 dev_kfree_skb_any(pdata->tx_tstamp_skb); 1222 1223 spin_lock_irqsave(&pdata->tstamp_lock, flags); 1224 pdata->tx_tstamp_skb = NULL; 1225 spin_unlock_irqrestore(&pdata->tstamp_lock, flags); 1226 } 1227 1228 static int xgbe_get_hwtstamp_settings(struct xgbe_prv_data *pdata, 1229 struct ifreq *ifreq) 1230 { 1231 if (copy_to_user(ifreq->ifr_data, &pdata->tstamp_config, 1232 sizeof(pdata->tstamp_config))) 1233 return -EFAULT; 1234 1235 return 0; 1236 } 1237 1238 static int xgbe_set_hwtstamp_settings(struct xgbe_prv_data *pdata, 1239 struct ifreq *ifreq) 1240 { 1241 struct hwtstamp_config config; 1242 unsigned int mac_tscr; 1243 1244 if (copy_from_user(&config, ifreq->ifr_data, sizeof(config))) 1245 return -EFAULT; 1246 1247 if (config.flags) 1248 return -EINVAL; 1249 1250 mac_tscr = 0; 1251 1252 switch (config.tx_type) { 1253 case HWTSTAMP_TX_OFF: 1254 break; 1255 1256 case HWTSTAMP_TX_ON: 1257 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 1258 break; 1259 1260 default: 1261 return -ERANGE; 1262 } 1263 1264 switch (config.rx_filter) { 1265 case HWTSTAMP_FILTER_NONE: 1266 break; 1267 1268 case HWTSTAMP_FILTER_ALL: 1269 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 1); 1270 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 1271 break; 1272 1273 /* PTP v2, UDP, any kind of event packet */ 1274 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1275 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); 1276 /* PTP v1, UDP, any kind of event packet */ 1277 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1278 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1); 1279 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1); 1280 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1); 1281 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 1282 break; 1283 1284 /* PTP v2, UDP, Sync packet */ 1285 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1286 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); 1287 /* PTP v1, UDP, Sync packet */ 1288 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1289 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1); 1290 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1); 1291 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1); 1292 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 1293 break; 1294 1295 /* PTP v2, UDP, Delay_req packet */ 1296 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1297 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); 1298 /* PTP v1, UDP, Delay_req packet */ 1299 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1300 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1); 1301 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1); 1302 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1); 1303 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1); 1304 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 1305 break; 1306 1307 /* 802.AS1, Ethernet, any kind of event packet */ 1308 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1309 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1); 1310 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1); 1311 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 1312 break; 1313 1314 /* 802.AS1, Ethernet, Sync packet */ 1315 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1316 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1); 1317 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1); 1318 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 1319 break; 1320 1321 /* 802.AS1, Ethernet, Delay_req packet */ 1322 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1323 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1); 1324 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1); 1325 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1); 1326 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 1327 break; 1328 1329 /* PTP v2/802.AS1, any layer, any kind of event packet */ 1330 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1331 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); 1332 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1); 1333 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1); 1334 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1); 1335 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1); 1336 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 1337 break; 1338 1339 /* PTP v2/802.AS1, any layer, Sync packet */ 1340 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1341 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); 1342 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1); 1343 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1); 1344 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1); 1345 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1); 1346 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 1347 break; 1348 1349 /* PTP v2/802.AS1, any layer, Delay_req packet */ 1350 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1351 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); 1352 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1); 1353 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1); 1354 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1); 1355 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1); 1356 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1); 1357 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 1358 break; 1359 1360 default: 1361 return -ERANGE; 1362 } 1363 1364 pdata->hw_if.config_tstamp(pdata, mac_tscr); 1365 1366 memcpy(&pdata->tstamp_config, &config, sizeof(config)); 1367 1368 return 0; 1369 } 1370 1371 static void xgbe_prep_tx_tstamp(struct xgbe_prv_data *pdata, 1372 struct sk_buff *skb, 1373 struct xgbe_packet_data *packet) 1374 { 1375 unsigned long flags; 1376 1377 if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP)) { 1378 spin_lock_irqsave(&pdata->tstamp_lock, flags); 1379 if (pdata->tx_tstamp_skb) { 1380 /* Another timestamp in progress, ignore this one */ 1381 XGMAC_SET_BITS(packet->attributes, 1382 TX_PACKET_ATTRIBUTES, PTP, 0); 1383 } else { 1384 pdata->tx_tstamp_skb = skb_get(skb); 1385 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1386 } 1387 spin_unlock_irqrestore(&pdata->tstamp_lock, flags); 1388 } 1389 1390 if (!XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP)) 1391 skb_tx_timestamp(skb); 1392 } 1393 1394 static void xgbe_prep_vlan(struct sk_buff *skb, struct xgbe_packet_data *packet) 1395 { 1396 if (skb_vlan_tag_present(skb)) 1397 packet->vlan_ctag = skb_vlan_tag_get(skb); 1398 } 1399 1400 static int xgbe_prep_tso(struct sk_buff *skb, struct xgbe_packet_data *packet) 1401 { 1402 int ret; 1403 1404 if (!XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, 1405 TSO_ENABLE)) 1406 return 0; 1407 1408 ret = skb_cow_head(skb, 0); 1409 if (ret) 1410 return ret; 1411 1412 packet->header_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 1413 packet->tcp_header_len = tcp_hdrlen(skb); 1414 packet->tcp_payload_len = skb->len - packet->header_len; 1415 packet->mss = skb_shinfo(skb)->gso_size; 1416 DBGPR(" packet->header_len=%u\n", packet->header_len); 1417 DBGPR(" packet->tcp_header_len=%u, packet->tcp_payload_len=%u\n", 1418 packet->tcp_header_len, packet->tcp_payload_len); 1419 DBGPR(" packet->mss=%u\n", packet->mss); 1420 1421 /* Update the number of packets that will ultimately be transmitted 1422 * along with the extra bytes for each extra packet 1423 */ 1424 packet->tx_packets = skb_shinfo(skb)->gso_segs; 1425 packet->tx_bytes += (packet->tx_packets - 1) * packet->header_len; 1426 1427 return 0; 1428 } 1429 1430 static int xgbe_is_tso(struct sk_buff *skb) 1431 { 1432 if (skb->ip_summed != CHECKSUM_PARTIAL) 1433 return 0; 1434 1435 if (!skb_is_gso(skb)) 1436 return 0; 1437 1438 DBGPR(" TSO packet to be processed\n"); 1439 1440 return 1; 1441 } 1442 1443 static void xgbe_packet_info(struct xgbe_prv_data *pdata, 1444 struct xgbe_ring *ring, struct sk_buff *skb, 1445 struct xgbe_packet_data *packet) 1446 { 1447 struct skb_frag_struct *frag; 1448 unsigned int context_desc; 1449 unsigned int len; 1450 unsigned int i; 1451 1452 packet->skb = skb; 1453 1454 context_desc = 0; 1455 packet->rdesc_count = 0; 1456 1457 packet->tx_packets = 1; 1458 packet->tx_bytes = skb->len; 1459 1460 if (xgbe_is_tso(skb)) { 1461 /* TSO requires an extra descriptor if mss is different */ 1462 if (skb_shinfo(skb)->gso_size != ring->tx.cur_mss) { 1463 context_desc = 1; 1464 packet->rdesc_count++; 1465 } 1466 1467 /* TSO requires an extra descriptor for TSO header */ 1468 packet->rdesc_count++; 1469 1470 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, 1471 TSO_ENABLE, 1); 1472 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, 1473 CSUM_ENABLE, 1); 1474 } else if (skb->ip_summed == CHECKSUM_PARTIAL) 1475 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, 1476 CSUM_ENABLE, 1); 1477 1478 if (skb_vlan_tag_present(skb)) { 1479 /* VLAN requires an extra descriptor if tag is different */ 1480 if (skb_vlan_tag_get(skb) != ring->tx.cur_vlan_ctag) 1481 /* We can share with the TSO context descriptor */ 1482 if (!context_desc) { 1483 context_desc = 1; 1484 packet->rdesc_count++; 1485 } 1486 1487 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, 1488 VLAN_CTAG, 1); 1489 } 1490 1491 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 1492 (pdata->tstamp_config.tx_type == HWTSTAMP_TX_ON)) 1493 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, 1494 PTP, 1); 1495 1496 for (len = skb_headlen(skb); len;) { 1497 packet->rdesc_count++; 1498 len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE); 1499 } 1500 1501 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1502 frag = &skb_shinfo(skb)->frags[i]; 1503 for (len = skb_frag_size(frag); len; ) { 1504 packet->rdesc_count++; 1505 len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE); 1506 } 1507 } 1508 } 1509 1510 static int xgbe_open(struct net_device *netdev) 1511 { 1512 struct xgbe_prv_data *pdata = netdev_priv(netdev); 1513 struct xgbe_desc_if *desc_if = &pdata->desc_if; 1514 int ret; 1515 1516 DBGPR("-->xgbe_open\n"); 1517 1518 /* Reset the phy settings */ 1519 ret = xgbe_phy_reset(pdata); 1520 if (ret) 1521 return ret; 1522 1523 /* Enable the clocks */ 1524 ret = clk_prepare_enable(pdata->sysclk); 1525 if (ret) { 1526 netdev_alert(netdev, "dma clk_prepare_enable failed\n"); 1527 return ret; 1528 } 1529 1530 ret = clk_prepare_enable(pdata->ptpclk); 1531 if (ret) { 1532 netdev_alert(netdev, "ptp clk_prepare_enable failed\n"); 1533 goto err_sysclk; 1534 } 1535 1536 /* Calculate the Rx buffer size before allocating rings */ 1537 ret = xgbe_calc_rx_buf_size(netdev, netdev->mtu); 1538 if (ret < 0) 1539 goto err_ptpclk; 1540 pdata->rx_buf_size = ret; 1541 1542 /* Allocate the channel and ring structures */ 1543 ret = xgbe_alloc_channels(pdata); 1544 if (ret) 1545 goto err_ptpclk; 1546 1547 /* Allocate the ring descriptors and buffers */ 1548 ret = desc_if->alloc_ring_resources(pdata); 1549 if (ret) 1550 goto err_channels; 1551 1552 INIT_WORK(&pdata->service_work, xgbe_service); 1553 INIT_WORK(&pdata->restart_work, xgbe_restart); 1554 INIT_WORK(&pdata->stopdev_work, xgbe_stopdev); 1555 INIT_WORK(&pdata->tx_tstamp_work, xgbe_tx_tstamp); 1556 xgbe_init_timers(pdata); 1557 1558 ret = xgbe_start(pdata); 1559 if (ret) 1560 goto err_rings; 1561 1562 clear_bit(XGBE_DOWN, &pdata->dev_state); 1563 1564 DBGPR("<--xgbe_open\n"); 1565 1566 return 0; 1567 1568 err_rings: 1569 desc_if->free_ring_resources(pdata); 1570 1571 err_channels: 1572 xgbe_free_channels(pdata); 1573 1574 err_ptpclk: 1575 clk_disable_unprepare(pdata->ptpclk); 1576 1577 err_sysclk: 1578 clk_disable_unprepare(pdata->sysclk); 1579 1580 return ret; 1581 } 1582 1583 static int xgbe_close(struct net_device *netdev) 1584 { 1585 struct xgbe_prv_data *pdata = netdev_priv(netdev); 1586 struct xgbe_desc_if *desc_if = &pdata->desc_if; 1587 1588 DBGPR("-->xgbe_close\n"); 1589 1590 /* Stop the device */ 1591 xgbe_stop(pdata); 1592 1593 /* Free the ring descriptors and buffers */ 1594 desc_if->free_ring_resources(pdata); 1595 1596 /* Free the channel and ring structures */ 1597 xgbe_free_channels(pdata); 1598 1599 /* Disable the clocks */ 1600 clk_disable_unprepare(pdata->ptpclk); 1601 clk_disable_unprepare(pdata->sysclk); 1602 1603 set_bit(XGBE_DOWN, &pdata->dev_state); 1604 1605 DBGPR("<--xgbe_close\n"); 1606 1607 return 0; 1608 } 1609 1610 static int xgbe_xmit(struct sk_buff *skb, struct net_device *netdev) 1611 { 1612 struct xgbe_prv_data *pdata = netdev_priv(netdev); 1613 struct xgbe_hw_if *hw_if = &pdata->hw_if; 1614 struct xgbe_desc_if *desc_if = &pdata->desc_if; 1615 struct xgbe_channel *channel; 1616 struct xgbe_ring *ring; 1617 struct xgbe_packet_data *packet; 1618 struct netdev_queue *txq; 1619 int ret; 1620 1621 DBGPR("-->xgbe_xmit: skb->len = %d\n", skb->len); 1622 1623 channel = pdata->channel + skb->queue_mapping; 1624 txq = netdev_get_tx_queue(netdev, channel->queue_index); 1625 ring = channel->tx_ring; 1626 packet = &ring->packet_data; 1627 1628 ret = NETDEV_TX_OK; 1629 1630 if (skb->len == 0) { 1631 netif_err(pdata, tx_err, netdev, 1632 "empty skb received from stack\n"); 1633 dev_kfree_skb_any(skb); 1634 goto tx_netdev_return; 1635 } 1636 1637 /* Calculate preliminary packet info */ 1638 memset(packet, 0, sizeof(*packet)); 1639 xgbe_packet_info(pdata, ring, skb, packet); 1640 1641 /* Check that there are enough descriptors available */ 1642 ret = xgbe_maybe_stop_tx_queue(channel, ring, packet->rdesc_count); 1643 if (ret) 1644 goto tx_netdev_return; 1645 1646 ret = xgbe_prep_tso(skb, packet); 1647 if (ret) { 1648 netif_err(pdata, tx_err, netdev, 1649 "error processing TSO packet\n"); 1650 dev_kfree_skb_any(skb); 1651 goto tx_netdev_return; 1652 } 1653 xgbe_prep_vlan(skb, packet); 1654 1655 if (!desc_if->map_tx_skb(channel, skb)) { 1656 dev_kfree_skb_any(skb); 1657 goto tx_netdev_return; 1658 } 1659 1660 xgbe_prep_tx_tstamp(pdata, skb, packet); 1661 1662 /* Report on the actual number of bytes (to be) sent */ 1663 netdev_tx_sent_queue(txq, packet->tx_bytes); 1664 1665 /* Configure required descriptor fields for transmission */ 1666 hw_if->dev_xmit(channel); 1667 1668 if (netif_msg_pktdata(pdata)) 1669 xgbe_print_pkt(netdev, skb, true); 1670 1671 /* Stop the queue in advance if there may not be enough descriptors */ 1672 xgbe_maybe_stop_tx_queue(channel, ring, XGBE_TX_MAX_DESCS); 1673 1674 ret = NETDEV_TX_OK; 1675 1676 tx_netdev_return: 1677 return ret; 1678 } 1679 1680 static void xgbe_set_rx_mode(struct net_device *netdev) 1681 { 1682 struct xgbe_prv_data *pdata = netdev_priv(netdev); 1683 struct xgbe_hw_if *hw_if = &pdata->hw_if; 1684 1685 DBGPR("-->xgbe_set_rx_mode\n"); 1686 1687 hw_if->config_rx_mode(pdata); 1688 1689 DBGPR("<--xgbe_set_rx_mode\n"); 1690 } 1691 1692 static int xgbe_set_mac_address(struct net_device *netdev, void *addr) 1693 { 1694 struct xgbe_prv_data *pdata = netdev_priv(netdev); 1695 struct xgbe_hw_if *hw_if = &pdata->hw_if; 1696 struct sockaddr *saddr = addr; 1697 1698 DBGPR("-->xgbe_set_mac_address\n"); 1699 1700 if (!is_valid_ether_addr(saddr->sa_data)) 1701 return -EADDRNOTAVAIL; 1702 1703 memcpy(netdev->dev_addr, saddr->sa_data, netdev->addr_len); 1704 1705 hw_if->set_mac_address(pdata, netdev->dev_addr); 1706 1707 DBGPR("<--xgbe_set_mac_address\n"); 1708 1709 return 0; 1710 } 1711 1712 static int xgbe_ioctl(struct net_device *netdev, struct ifreq *ifreq, int cmd) 1713 { 1714 struct xgbe_prv_data *pdata = netdev_priv(netdev); 1715 int ret; 1716 1717 switch (cmd) { 1718 case SIOCGHWTSTAMP: 1719 ret = xgbe_get_hwtstamp_settings(pdata, ifreq); 1720 break; 1721 1722 case SIOCSHWTSTAMP: 1723 ret = xgbe_set_hwtstamp_settings(pdata, ifreq); 1724 break; 1725 1726 default: 1727 ret = -EOPNOTSUPP; 1728 } 1729 1730 return ret; 1731 } 1732 1733 static int xgbe_change_mtu(struct net_device *netdev, int mtu) 1734 { 1735 struct xgbe_prv_data *pdata = netdev_priv(netdev); 1736 int ret; 1737 1738 DBGPR("-->xgbe_change_mtu\n"); 1739 1740 ret = xgbe_calc_rx_buf_size(netdev, mtu); 1741 if (ret < 0) 1742 return ret; 1743 1744 pdata->rx_buf_size = ret; 1745 netdev->mtu = mtu; 1746 1747 xgbe_restart_dev(pdata); 1748 1749 DBGPR("<--xgbe_change_mtu\n"); 1750 1751 return 0; 1752 } 1753 1754 static void xgbe_tx_timeout(struct net_device *netdev) 1755 { 1756 struct xgbe_prv_data *pdata = netdev_priv(netdev); 1757 1758 netdev_warn(netdev, "tx timeout, device restarting\n"); 1759 schedule_work(&pdata->restart_work); 1760 } 1761 1762 static struct rtnl_link_stats64 *xgbe_get_stats64(struct net_device *netdev, 1763 struct rtnl_link_stats64 *s) 1764 { 1765 struct xgbe_prv_data *pdata = netdev_priv(netdev); 1766 struct xgbe_mmc_stats *pstats = &pdata->mmc_stats; 1767 1768 DBGPR("-->%s\n", __func__); 1769 1770 pdata->hw_if.read_mmc_stats(pdata); 1771 1772 s->rx_packets = pstats->rxframecount_gb; 1773 s->rx_bytes = pstats->rxoctetcount_gb; 1774 s->rx_errors = pstats->rxframecount_gb - 1775 pstats->rxbroadcastframes_g - 1776 pstats->rxmulticastframes_g - 1777 pstats->rxunicastframes_g; 1778 s->multicast = pstats->rxmulticastframes_g; 1779 s->rx_length_errors = pstats->rxlengtherror; 1780 s->rx_crc_errors = pstats->rxcrcerror; 1781 s->rx_fifo_errors = pstats->rxfifooverflow; 1782 1783 s->tx_packets = pstats->txframecount_gb; 1784 s->tx_bytes = pstats->txoctetcount_gb; 1785 s->tx_errors = pstats->txframecount_gb - pstats->txframecount_g; 1786 s->tx_dropped = netdev->stats.tx_dropped; 1787 1788 DBGPR("<--%s\n", __func__); 1789 1790 return s; 1791 } 1792 1793 static int xgbe_vlan_rx_add_vid(struct net_device *netdev, __be16 proto, 1794 u16 vid) 1795 { 1796 struct xgbe_prv_data *pdata = netdev_priv(netdev); 1797 struct xgbe_hw_if *hw_if = &pdata->hw_if; 1798 1799 DBGPR("-->%s\n", __func__); 1800 1801 set_bit(vid, pdata->active_vlans); 1802 hw_if->update_vlan_hash_table(pdata); 1803 1804 DBGPR("<--%s\n", __func__); 1805 1806 return 0; 1807 } 1808 1809 static int xgbe_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, 1810 u16 vid) 1811 { 1812 struct xgbe_prv_data *pdata = netdev_priv(netdev); 1813 struct xgbe_hw_if *hw_if = &pdata->hw_if; 1814 1815 DBGPR("-->%s\n", __func__); 1816 1817 clear_bit(vid, pdata->active_vlans); 1818 hw_if->update_vlan_hash_table(pdata); 1819 1820 DBGPR("<--%s\n", __func__); 1821 1822 return 0; 1823 } 1824 1825 #ifdef CONFIG_NET_POLL_CONTROLLER 1826 static void xgbe_poll_controller(struct net_device *netdev) 1827 { 1828 struct xgbe_prv_data *pdata = netdev_priv(netdev); 1829 struct xgbe_channel *channel; 1830 unsigned int i; 1831 1832 DBGPR("-->xgbe_poll_controller\n"); 1833 1834 if (pdata->per_channel_irq) { 1835 channel = pdata->channel; 1836 for (i = 0; i < pdata->channel_count; i++, channel++) 1837 xgbe_dma_isr(channel->dma_irq, channel); 1838 } else { 1839 disable_irq(pdata->dev_irq); 1840 xgbe_isr(pdata->dev_irq, pdata); 1841 enable_irq(pdata->dev_irq); 1842 } 1843 1844 DBGPR("<--xgbe_poll_controller\n"); 1845 } 1846 #endif /* End CONFIG_NET_POLL_CONTROLLER */ 1847 1848 static int xgbe_setup_tc(struct net_device *netdev, u32 handle, __be16 proto, 1849 struct tc_to_netdev *tc_to_netdev) 1850 { 1851 struct xgbe_prv_data *pdata = netdev_priv(netdev); 1852 u8 tc; 1853 1854 if (tc_to_netdev->type != TC_SETUP_MQPRIO) 1855 return -EINVAL; 1856 1857 tc = tc_to_netdev->tc; 1858 1859 if (tc > pdata->hw_feat.tc_cnt) 1860 return -EINVAL; 1861 1862 pdata->num_tcs = tc; 1863 pdata->hw_if.config_tc(pdata); 1864 1865 return 0; 1866 } 1867 1868 static int xgbe_set_features(struct net_device *netdev, 1869 netdev_features_t features) 1870 { 1871 struct xgbe_prv_data *pdata = netdev_priv(netdev); 1872 struct xgbe_hw_if *hw_if = &pdata->hw_if; 1873 netdev_features_t rxhash, rxcsum, rxvlan, rxvlan_filter; 1874 int ret = 0; 1875 1876 rxhash = pdata->netdev_features & NETIF_F_RXHASH; 1877 rxcsum = pdata->netdev_features & NETIF_F_RXCSUM; 1878 rxvlan = pdata->netdev_features & NETIF_F_HW_VLAN_CTAG_RX; 1879 rxvlan_filter = pdata->netdev_features & NETIF_F_HW_VLAN_CTAG_FILTER; 1880 1881 if ((features & NETIF_F_RXHASH) && !rxhash) 1882 ret = hw_if->enable_rss(pdata); 1883 else if (!(features & NETIF_F_RXHASH) && rxhash) 1884 ret = hw_if->disable_rss(pdata); 1885 if (ret) 1886 return ret; 1887 1888 if ((features & NETIF_F_RXCSUM) && !rxcsum) 1889 hw_if->enable_rx_csum(pdata); 1890 else if (!(features & NETIF_F_RXCSUM) && rxcsum) 1891 hw_if->disable_rx_csum(pdata); 1892 1893 if ((features & NETIF_F_HW_VLAN_CTAG_RX) && !rxvlan) 1894 hw_if->enable_rx_vlan_stripping(pdata); 1895 else if (!(features & NETIF_F_HW_VLAN_CTAG_RX) && rxvlan) 1896 hw_if->disable_rx_vlan_stripping(pdata); 1897 1898 if ((features & NETIF_F_HW_VLAN_CTAG_FILTER) && !rxvlan_filter) 1899 hw_if->enable_rx_vlan_filtering(pdata); 1900 else if (!(features & NETIF_F_HW_VLAN_CTAG_FILTER) && rxvlan_filter) 1901 hw_if->disable_rx_vlan_filtering(pdata); 1902 1903 pdata->netdev_features = features; 1904 1905 DBGPR("<--xgbe_set_features\n"); 1906 1907 return 0; 1908 } 1909 1910 static const struct net_device_ops xgbe_netdev_ops = { 1911 .ndo_open = xgbe_open, 1912 .ndo_stop = xgbe_close, 1913 .ndo_start_xmit = xgbe_xmit, 1914 .ndo_set_rx_mode = xgbe_set_rx_mode, 1915 .ndo_set_mac_address = xgbe_set_mac_address, 1916 .ndo_validate_addr = eth_validate_addr, 1917 .ndo_do_ioctl = xgbe_ioctl, 1918 .ndo_change_mtu = xgbe_change_mtu, 1919 .ndo_tx_timeout = xgbe_tx_timeout, 1920 .ndo_get_stats64 = xgbe_get_stats64, 1921 .ndo_vlan_rx_add_vid = xgbe_vlan_rx_add_vid, 1922 .ndo_vlan_rx_kill_vid = xgbe_vlan_rx_kill_vid, 1923 #ifdef CONFIG_NET_POLL_CONTROLLER 1924 .ndo_poll_controller = xgbe_poll_controller, 1925 #endif 1926 .ndo_setup_tc = xgbe_setup_tc, 1927 .ndo_set_features = xgbe_set_features, 1928 }; 1929 1930 const struct net_device_ops *xgbe_get_netdev_ops(void) 1931 { 1932 return &xgbe_netdev_ops; 1933 } 1934 1935 static void xgbe_rx_refresh(struct xgbe_channel *channel) 1936 { 1937 struct xgbe_prv_data *pdata = channel->pdata; 1938 struct xgbe_hw_if *hw_if = &pdata->hw_if; 1939 struct xgbe_desc_if *desc_if = &pdata->desc_if; 1940 struct xgbe_ring *ring = channel->rx_ring; 1941 struct xgbe_ring_data *rdata; 1942 1943 while (ring->dirty != ring->cur) { 1944 rdata = XGBE_GET_DESC_DATA(ring, ring->dirty); 1945 1946 /* Reset rdata values */ 1947 desc_if->unmap_rdata(pdata, rdata); 1948 1949 if (desc_if->map_rx_buffer(pdata, ring, rdata)) 1950 break; 1951 1952 hw_if->rx_desc_reset(pdata, rdata, ring->dirty); 1953 1954 ring->dirty++; 1955 } 1956 1957 /* Make sure everything is written before the register write */ 1958 wmb(); 1959 1960 /* Update the Rx Tail Pointer Register with address of 1961 * the last cleaned entry */ 1962 rdata = XGBE_GET_DESC_DATA(ring, ring->dirty - 1); 1963 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO, 1964 lower_32_bits(rdata->rdesc_dma)); 1965 } 1966 1967 static struct sk_buff *xgbe_create_skb(struct xgbe_prv_data *pdata, 1968 struct napi_struct *napi, 1969 struct xgbe_ring_data *rdata, 1970 unsigned int len) 1971 { 1972 struct sk_buff *skb; 1973 u8 *packet; 1974 unsigned int copy_len; 1975 1976 skb = napi_alloc_skb(napi, rdata->rx.hdr.dma_len); 1977 if (!skb) 1978 return NULL; 1979 1980 /* Start with the header buffer which may contain just the header 1981 * or the header plus data 1982 */ 1983 dma_sync_single_range_for_cpu(pdata->dev, rdata->rx.hdr.dma_base, 1984 rdata->rx.hdr.dma_off, 1985 rdata->rx.hdr.dma_len, DMA_FROM_DEVICE); 1986 1987 packet = page_address(rdata->rx.hdr.pa.pages) + 1988 rdata->rx.hdr.pa.pages_offset; 1989 copy_len = (rdata->rx.hdr_len) ? rdata->rx.hdr_len : len; 1990 copy_len = min(rdata->rx.hdr.dma_len, copy_len); 1991 skb_copy_to_linear_data(skb, packet, copy_len); 1992 skb_put(skb, copy_len); 1993 1994 len -= copy_len; 1995 if (len) { 1996 /* Add the remaining data as a frag */ 1997 dma_sync_single_range_for_cpu(pdata->dev, 1998 rdata->rx.buf.dma_base, 1999 rdata->rx.buf.dma_off, 2000 rdata->rx.buf.dma_len, 2001 DMA_FROM_DEVICE); 2002 2003 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 2004 rdata->rx.buf.pa.pages, 2005 rdata->rx.buf.pa.pages_offset, 2006 len, rdata->rx.buf.dma_len); 2007 rdata->rx.buf.pa.pages = NULL; 2008 } 2009 2010 return skb; 2011 } 2012 2013 static int xgbe_tx_poll(struct xgbe_channel *channel) 2014 { 2015 struct xgbe_prv_data *pdata = channel->pdata; 2016 struct xgbe_hw_if *hw_if = &pdata->hw_if; 2017 struct xgbe_desc_if *desc_if = &pdata->desc_if; 2018 struct xgbe_ring *ring = channel->tx_ring; 2019 struct xgbe_ring_data *rdata; 2020 struct xgbe_ring_desc *rdesc; 2021 struct net_device *netdev = pdata->netdev; 2022 struct netdev_queue *txq; 2023 int processed = 0; 2024 unsigned int tx_packets = 0, tx_bytes = 0; 2025 unsigned int cur; 2026 2027 DBGPR("-->xgbe_tx_poll\n"); 2028 2029 /* Nothing to do if there isn't a Tx ring for this channel */ 2030 if (!ring) 2031 return 0; 2032 2033 cur = ring->cur; 2034 2035 /* Be sure we get ring->cur before accessing descriptor data */ 2036 smp_rmb(); 2037 2038 txq = netdev_get_tx_queue(netdev, channel->queue_index); 2039 2040 while ((processed < XGBE_TX_DESC_MAX_PROC) && 2041 (ring->dirty != cur)) { 2042 rdata = XGBE_GET_DESC_DATA(ring, ring->dirty); 2043 rdesc = rdata->rdesc; 2044 2045 if (!hw_if->tx_complete(rdesc)) 2046 break; 2047 2048 /* Make sure descriptor fields are read after reading the OWN 2049 * bit */ 2050 dma_rmb(); 2051 2052 if (netif_msg_tx_done(pdata)) 2053 xgbe_dump_tx_desc(pdata, ring, ring->dirty, 1, 0); 2054 2055 if (hw_if->is_last_desc(rdesc)) { 2056 tx_packets += rdata->tx.packets; 2057 tx_bytes += rdata->tx.bytes; 2058 } 2059 2060 /* Free the SKB and reset the descriptor for re-use */ 2061 desc_if->unmap_rdata(pdata, rdata); 2062 hw_if->tx_desc_reset(rdata); 2063 2064 processed++; 2065 ring->dirty++; 2066 } 2067 2068 if (!processed) 2069 return 0; 2070 2071 netdev_tx_completed_queue(txq, tx_packets, tx_bytes); 2072 2073 if ((ring->tx.queue_stopped == 1) && 2074 (xgbe_tx_avail_desc(ring) > XGBE_TX_DESC_MIN_FREE)) { 2075 ring->tx.queue_stopped = 0; 2076 netif_tx_wake_queue(txq); 2077 } 2078 2079 DBGPR("<--xgbe_tx_poll: processed=%d\n", processed); 2080 2081 return processed; 2082 } 2083 2084 static int xgbe_rx_poll(struct xgbe_channel *channel, int budget) 2085 { 2086 struct xgbe_prv_data *pdata = channel->pdata; 2087 struct xgbe_hw_if *hw_if = &pdata->hw_if; 2088 struct xgbe_ring *ring = channel->rx_ring; 2089 struct xgbe_ring_data *rdata; 2090 struct xgbe_packet_data *packet; 2091 struct net_device *netdev = pdata->netdev; 2092 struct napi_struct *napi; 2093 struct sk_buff *skb; 2094 struct skb_shared_hwtstamps *hwtstamps; 2095 unsigned int incomplete, error, context_next, context; 2096 unsigned int len, rdesc_len, max_len; 2097 unsigned int received = 0; 2098 int packet_count = 0; 2099 2100 DBGPR("-->xgbe_rx_poll: budget=%d\n", budget); 2101 2102 /* Nothing to do if there isn't a Rx ring for this channel */ 2103 if (!ring) 2104 return 0; 2105 2106 incomplete = 0; 2107 context_next = 0; 2108 2109 napi = (pdata->per_channel_irq) ? &channel->napi : &pdata->napi; 2110 2111 rdata = XGBE_GET_DESC_DATA(ring, ring->cur); 2112 packet = &ring->packet_data; 2113 while (packet_count < budget) { 2114 DBGPR(" cur = %d\n", ring->cur); 2115 2116 /* First time in loop see if we need to restore state */ 2117 if (!received && rdata->state_saved) { 2118 skb = rdata->state.skb; 2119 error = rdata->state.error; 2120 len = rdata->state.len; 2121 } else { 2122 memset(packet, 0, sizeof(*packet)); 2123 skb = NULL; 2124 error = 0; 2125 len = 0; 2126 } 2127 2128 read_again: 2129 rdata = XGBE_GET_DESC_DATA(ring, ring->cur); 2130 2131 if (xgbe_rx_dirty_desc(ring) > (XGBE_RX_DESC_CNT >> 3)) 2132 xgbe_rx_refresh(channel); 2133 2134 if (hw_if->dev_read(channel)) 2135 break; 2136 2137 received++; 2138 ring->cur++; 2139 2140 incomplete = XGMAC_GET_BITS(packet->attributes, 2141 RX_PACKET_ATTRIBUTES, 2142 INCOMPLETE); 2143 context_next = XGMAC_GET_BITS(packet->attributes, 2144 RX_PACKET_ATTRIBUTES, 2145 CONTEXT_NEXT); 2146 context = XGMAC_GET_BITS(packet->attributes, 2147 RX_PACKET_ATTRIBUTES, 2148 CONTEXT); 2149 2150 /* Earlier error, just drain the remaining data */ 2151 if ((incomplete || context_next) && error) 2152 goto read_again; 2153 2154 if (error || packet->errors) { 2155 if (packet->errors) 2156 netif_err(pdata, rx_err, netdev, 2157 "error in received packet\n"); 2158 dev_kfree_skb(skb); 2159 goto next_packet; 2160 } 2161 2162 if (!context) { 2163 /* Length is cumulative, get this descriptor's length */ 2164 rdesc_len = rdata->rx.len - len; 2165 len += rdesc_len; 2166 2167 if (rdesc_len && !skb) { 2168 skb = xgbe_create_skb(pdata, napi, rdata, 2169 rdesc_len); 2170 if (!skb) 2171 error = 1; 2172 } else if (rdesc_len) { 2173 dma_sync_single_range_for_cpu(pdata->dev, 2174 rdata->rx.buf.dma_base, 2175 rdata->rx.buf.dma_off, 2176 rdata->rx.buf.dma_len, 2177 DMA_FROM_DEVICE); 2178 2179 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 2180 rdata->rx.buf.pa.pages, 2181 rdata->rx.buf.pa.pages_offset, 2182 rdesc_len, 2183 rdata->rx.buf.dma_len); 2184 rdata->rx.buf.pa.pages = NULL; 2185 } 2186 } 2187 2188 if (incomplete || context_next) 2189 goto read_again; 2190 2191 if (!skb) 2192 goto next_packet; 2193 2194 /* Be sure we don't exceed the configured MTU */ 2195 max_len = netdev->mtu + ETH_HLEN; 2196 if (!(netdev->features & NETIF_F_HW_VLAN_CTAG_RX) && 2197 (skb->protocol == htons(ETH_P_8021Q))) 2198 max_len += VLAN_HLEN; 2199 2200 if (skb->len > max_len) { 2201 netif_err(pdata, rx_err, netdev, 2202 "packet length exceeds configured MTU\n"); 2203 dev_kfree_skb(skb); 2204 goto next_packet; 2205 } 2206 2207 if (netif_msg_pktdata(pdata)) 2208 xgbe_print_pkt(netdev, skb, false); 2209 2210 skb_checksum_none_assert(skb); 2211 if (XGMAC_GET_BITS(packet->attributes, 2212 RX_PACKET_ATTRIBUTES, CSUM_DONE)) 2213 skb->ip_summed = CHECKSUM_UNNECESSARY; 2214 2215 if (XGMAC_GET_BITS(packet->attributes, 2216 RX_PACKET_ATTRIBUTES, VLAN_CTAG)) 2217 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 2218 packet->vlan_ctag); 2219 2220 if (XGMAC_GET_BITS(packet->attributes, 2221 RX_PACKET_ATTRIBUTES, RX_TSTAMP)) { 2222 u64 nsec; 2223 2224 nsec = timecounter_cyc2time(&pdata->tstamp_tc, 2225 packet->rx_tstamp); 2226 hwtstamps = skb_hwtstamps(skb); 2227 hwtstamps->hwtstamp = ns_to_ktime(nsec); 2228 } 2229 2230 if (XGMAC_GET_BITS(packet->attributes, 2231 RX_PACKET_ATTRIBUTES, RSS_HASH)) 2232 skb_set_hash(skb, packet->rss_hash, 2233 packet->rss_hash_type); 2234 2235 skb->dev = netdev; 2236 skb->protocol = eth_type_trans(skb, netdev); 2237 skb_record_rx_queue(skb, channel->queue_index); 2238 2239 napi_gro_receive(napi, skb); 2240 2241 next_packet: 2242 packet_count++; 2243 } 2244 2245 /* Check if we need to save state before leaving */ 2246 if (received && (incomplete || context_next)) { 2247 rdata = XGBE_GET_DESC_DATA(ring, ring->cur); 2248 rdata->state_saved = 1; 2249 rdata->state.skb = skb; 2250 rdata->state.len = len; 2251 rdata->state.error = error; 2252 } 2253 2254 DBGPR("<--xgbe_rx_poll: packet_count = %d\n", packet_count); 2255 2256 return packet_count; 2257 } 2258 2259 static int xgbe_one_poll(struct napi_struct *napi, int budget) 2260 { 2261 struct xgbe_channel *channel = container_of(napi, struct xgbe_channel, 2262 napi); 2263 struct xgbe_prv_data *pdata = channel->pdata; 2264 int processed = 0; 2265 2266 DBGPR("-->xgbe_one_poll: budget=%d\n", budget); 2267 2268 /* Cleanup Tx ring first */ 2269 xgbe_tx_poll(channel); 2270 2271 /* Process Rx ring next */ 2272 processed = xgbe_rx_poll(channel, budget); 2273 2274 /* If we processed everything, we are done */ 2275 if (processed < budget) { 2276 /* Turn off polling */ 2277 napi_complete_done(napi, processed); 2278 2279 /* Enable Tx and Rx interrupts */ 2280 if (pdata->channel_irq_mode) 2281 xgbe_enable_rx_tx_int(pdata, channel); 2282 else 2283 enable_irq(channel->dma_irq); 2284 } 2285 2286 DBGPR("<--xgbe_one_poll: received = %d\n", processed); 2287 2288 return processed; 2289 } 2290 2291 static int xgbe_all_poll(struct napi_struct *napi, int budget) 2292 { 2293 struct xgbe_prv_data *pdata = container_of(napi, struct xgbe_prv_data, 2294 napi); 2295 struct xgbe_channel *channel; 2296 int ring_budget; 2297 int processed, last_processed; 2298 unsigned int i; 2299 2300 DBGPR("-->xgbe_all_poll: budget=%d\n", budget); 2301 2302 processed = 0; 2303 ring_budget = budget / pdata->rx_ring_count; 2304 do { 2305 last_processed = processed; 2306 2307 channel = pdata->channel; 2308 for (i = 0; i < pdata->channel_count; i++, channel++) { 2309 /* Cleanup Tx ring first */ 2310 xgbe_tx_poll(channel); 2311 2312 /* Process Rx ring next */ 2313 if (ring_budget > (budget - processed)) 2314 ring_budget = budget - processed; 2315 processed += xgbe_rx_poll(channel, ring_budget); 2316 } 2317 } while ((processed < budget) && (processed != last_processed)); 2318 2319 /* If we processed everything, we are done */ 2320 if (processed < budget) { 2321 /* Turn off polling */ 2322 napi_complete_done(napi, processed); 2323 2324 /* Enable Tx and Rx interrupts */ 2325 xgbe_enable_rx_tx_ints(pdata); 2326 } 2327 2328 DBGPR("<--xgbe_all_poll: received = %d\n", processed); 2329 2330 return processed; 2331 } 2332 2333 void xgbe_dump_tx_desc(struct xgbe_prv_data *pdata, struct xgbe_ring *ring, 2334 unsigned int idx, unsigned int count, unsigned int flag) 2335 { 2336 struct xgbe_ring_data *rdata; 2337 struct xgbe_ring_desc *rdesc; 2338 2339 while (count--) { 2340 rdata = XGBE_GET_DESC_DATA(ring, idx); 2341 rdesc = rdata->rdesc; 2342 netdev_dbg(pdata->netdev, 2343 "TX_NORMAL_DESC[%d %s] = %08x:%08x:%08x:%08x\n", idx, 2344 (flag == 1) ? "QUEUED FOR TX" : "TX BY DEVICE", 2345 le32_to_cpu(rdesc->desc0), 2346 le32_to_cpu(rdesc->desc1), 2347 le32_to_cpu(rdesc->desc2), 2348 le32_to_cpu(rdesc->desc3)); 2349 idx++; 2350 } 2351 } 2352 2353 void xgbe_dump_rx_desc(struct xgbe_prv_data *pdata, struct xgbe_ring *ring, 2354 unsigned int idx) 2355 { 2356 struct xgbe_ring_data *rdata; 2357 struct xgbe_ring_desc *rdesc; 2358 2359 rdata = XGBE_GET_DESC_DATA(ring, idx); 2360 rdesc = rdata->rdesc; 2361 netdev_dbg(pdata->netdev, 2362 "RX_NORMAL_DESC[%d RX BY DEVICE] = %08x:%08x:%08x:%08x\n", 2363 idx, le32_to_cpu(rdesc->desc0), le32_to_cpu(rdesc->desc1), 2364 le32_to_cpu(rdesc->desc2), le32_to_cpu(rdesc->desc3)); 2365 } 2366 2367 void xgbe_print_pkt(struct net_device *netdev, struct sk_buff *skb, bool tx_rx) 2368 { 2369 struct ethhdr *eth = (struct ethhdr *)skb->data; 2370 unsigned char *buf = skb->data; 2371 unsigned char buffer[128]; 2372 unsigned int i, j; 2373 2374 netdev_dbg(netdev, "\n************** SKB dump ****************\n"); 2375 2376 netdev_dbg(netdev, "%s packet of %d bytes\n", 2377 (tx_rx ? "TX" : "RX"), skb->len); 2378 2379 netdev_dbg(netdev, "Dst MAC addr: %pM\n", eth->h_dest); 2380 netdev_dbg(netdev, "Src MAC addr: %pM\n", eth->h_source); 2381 netdev_dbg(netdev, "Protocol: %#06hx\n", ntohs(eth->h_proto)); 2382 2383 for (i = 0, j = 0; i < skb->len;) { 2384 j += snprintf(buffer + j, sizeof(buffer) - j, "%02hhx", 2385 buf[i++]); 2386 2387 if ((i % 32) == 0) { 2388 netdev_dbg(netdev, " %#06x: %s\n", i - 32, buffer); 2389 j = 0; 2390 } else if ((i % 16) == 0) { 2391 buffer[j++] = ' '; 2392 buffer[j++] = ' '; 2393 } else if ((i % 4) == 0) { 2394 buffer[j++] = ' '; 2395 } 2396 } 2397 if (i % 32) 2398 netdev_dbg(netdev, " %#06x: %s\n", i - (i % 32), buffer); 2399 2400 netdev_dbg(netdev, "\n************** SKB dump ****************\n"); 2401 } 2402