1 /*
2  * AMD 10Gb Ethernet driver
3  *
4  * This file is available to you under your choice of the following two
5  * licenses:
6  *
7  * License 1: GPLv2
8  *
9  * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
10  *
11  * This file is free software; you may copy, redistribute and/or modify
12  * it under the terms of the GNU General Public License as published by
13  * the Free Software Foundation, either version 2 of the License, or (at
14  * your option) any later version.
15  *
16  * This file is distributed in the hope that it will be useful, but
17  * WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19  * General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
23  *
24  * This file incorporates work covered by the following copyright and
25  * permission notice:
26  *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
27  *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28  *     Inc. unless otherwise expressly agreed to in writing between Synopsys
29  *     and you.
30  *
31  *     The Software IS NOT an item of Licensed Software or Licensed Product
32  *     under any End User Software License Agreement or Agreement for Licensed
33  *     Product with Synopsys or any supplement thereto.  Permission is hereby
34  *     granted, free of charge, to any person obtaining a copy of this software
35  *     annotated with this license and the Software, to deal in the Software
36  *     without restriction, including without limitation the rights to use,
37  *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38  *     of the Software, and to permit persons to whom the Software is furnished
39  *     to do so, subject to the following conditions:
40  *
41  *     The above copyright notice and this permission notice shall be included
42  *     in all copies or substantial portions of the Software.
43  *
44  *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45  *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46  *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47  *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48  *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49  *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50  *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51  *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52  *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53  *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54  *     THE POSSIBILITY OF SUCH DAMAGE.
55  *
56  *
57  * License 2: Modified BSD
58  *
59  * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
60  * All rights reserved.
61  *
62  * Redistribution and use in source and binary forms, with or without
63  * modification, are permitted provided that the following conditions are met:
64  *     * Redistributions of source code must retain the above copyright
65  *       notice, this list of conditions and the following disclaimer.
66  *     * Redistributions in binary form must reproduce the above copyright
67  *       notice, this list of conditions and the following disclaimer in the
68  *       documentation and/or other materials provided with the distribution.
69  *     * Neither the name of Advanced Micro Devices, Inc. nor the
70  *       names of its contributors may be used to endorse or promote products
71  *       derived from this software without specific prior written permission.
72  *
73  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76  * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
83  *
84  * This file incorporates work covered by the following copyright and
85  * permission notice:
86  *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
87  *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88  *     Inc. unless otherwise expressly agreed to in writing between Synopsys
89  *     and you.
90  *
91  *     The Software IS NOT an item of Licensed Software or Licensed Product
92  *     under any End User Software License Agreement or Agreement for Licensed
93  *     Product with Synopsys or any supplement thereto.  Permission is hereby
94  *     granted, free of charge, to any person obtaining a copy of this software
95  *     annotated with this license and the Software, to deal in the Software
96  *     without restriction, including without limitation the rights to use,
97  *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98  *     of the Software, and to permit persons to whom the Software is furnished
99  *     to do so, subject to the following conditions:
100  *
101  *     The above copyright notice and this permission notice shall be included
102  *     in all copies or substantial portions of the Software.
103  *
104  *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105  *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106  *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107  *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108  *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109  *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110  *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111  *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112  *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113  *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114  *     THE POSSIBILITY OF SUCH DAMAGE.
115  */
116 
117 #include <linux/module.h>
118 #include <linux/spinlock.h>
119 #include <linux/tcp.h>
120 #include <linux/if_vlan.h>
121 #include <linux/interrupt.h>
122 #include <linux/clk.h>
123 #include <linux/if_ether.h>
124 #include <linux/net_tstamp.h>
125 #include <linux/phy.h>
126 #include <net/vxlan.h>
127 
128 #include "xgbe.h"
129 #include "xgbe-common.h"
130 
131 static unsigned int ecc_sec_info_threshold = 10;
132 static unsigned int ecc_sec_warn_threshold = 10000;
133 static unsigned int ecc_sec_period = 600;
134 static unsigned int ecc_ded_threshold = 2;
135 static unsigned int ecc_ded_period = 600;
136 
137 #ifdef CONFIG_AMD_XGBE_HAVE_ECC
138 /* Only expose the ECC parameters if supported */
139 module_param(ecc_sec_info_threshold, uint, 0644);
140 MODULE_PARM_DESC(ecc_sec_info_threshold,
141 		 " ECC corrected error informational threshold setting");
142 
143 module_param(ecc_sec_warn_threshold, uint, 0644);
144 MODULE_PARM_DESC(ecc_sec_warn_threshold,
145 		 " ECC corrected error warning threshold setting");
146 
147 module_param(ecc_sec_period, uint, 0644);
148 MODULE_PARM_DESC(ecc_sec_period, " ECC corrected error period (in seconds)");
149 
150 module_param(ecc_ded_threshold, uint, 0644);
151 MODULE_PARM_DESC(ecc_ded_threshold, " ECC detected error threshold setting");
152 
153 module_param(ecc_ded_period, uint, 0644);
154 MODULE_PARM_DESC(ecc_ded_period, " ECC detected error period (in seconds)");
155 #endif
156 
157 static int xgbe_one_poll(struct napi_struct *, int);
158 static int xgbe_all_poll(struct napi_struct *, int);
159 static void xgbe_stop(struct xgbe_prv_data *);
160 
161 static void *xgbe_alloc_node(size_t size, int node)
162 {
163 	void *mem;
164 
165 	mem = kzalloc_node(size, GFP_KERNEL, node);
166 	if (!mem)
167 		mem = kzalloc(size, GFP_KERNEL);
168 
169 	return mem;
170 }
171 
172 static void xgbe_free_channels(struct xgbe_prv_data *pdata)
173 {
174 	unsigned int i;
175 
176 	for (i = 0; i < ARRAY_SIZE(pdata->channel); i++) {
177 		if (!pdata->channel[i])
178 			continue;
179 
180 		kfree(pdata->channel[i]->rx_ring);
181 		kfree(pdata->channel[i]->tx_ring);
182 		kfree(pdata->channel[i]);
183 
184 		pdata->channel[i] = NULL;
185 	}
186 
187 	pdata->channel_count = 0;
188 }
189 
190 static int xgbe_alloc_channels(struct xgbe_prv_data *pdata)
191 {
192 	struct xgbe_channel *channel;
193 	struct xgbe_ring *ring;
194 	unsigned int count, i;
195 	unsigned int cpu;
196 	int node;
197 
198 	count = max_t(unsigned int, pdata->tx_ring_count, pdata->rx_ring_count);
199 	for (i = 0; i < count; i++) {
200 		/* Attempt to use a CPU on the node the device is on */
201 		cpu = cpumask_local_spread(i, dev_to_node(pdata->dev));
202 
203 		/* Set the allocation node based on the returned CPU */
204 		node = cpu_to_node(cpu);
205 
206 		channel = xgbe_alloc_node(sizeof(*channel), node);
207 		if (!channel)
208 			goto err_mem;
209 		pdata->channel[i] = channel;
210 
211 		snprintf(channel->name, sizeof(channel->name), "channel-%u", i);
212 		channel->pdata = pdata;
213 		channel->queue_index = i;
214 		channel->dma_regs = pdata->xgmac_regs + DMA_CH_BASE +
215 				    (DMA_CH_INC * i);
216 		channel->node = node;
217 		cpumask_set_cpu(cpu, &channel->affinity_mask);
218 
219 		if (pdata->per_channel_irq)
220 			channel->dma_irq = pdata->channel_irq[i];
221 
222 		if (i < pdata->tx_ring_count) {
223 			ring = xgbe_alloc_node(sizeof(*ring), node);
224 			if (!ring)
225 				goto err_mem;
226 
227 			spin_lock_init(&ring->lock);
228 			ring->node = node;
229 
230 			channel->tx_ring = ring;
231 		}
232 
233 		if (i < pdata->rx_ring_count) {
234 			ring = xgbe_alloc_node(sizeof(*ring), node);
235 			if (!ring)
236 				goto err_mem;
237 
238 			spin_lock_init(&ring->lock);
239 			ring->node = node;
240 
241 			channel->rx_ring = ring;
242 		}
243 
244 		netif_dbg(pdata, drv, pdata->netdev,
245 			  "%s: cpu=%u, node=%d\n", channel->name, cpu, node);
246 
247 		netif_dbg(pdata, drv, pdata->netdev,
248 			  "%s: dma_regs=%p, dma_irq=%d, tx=%p, rx=%p\n",
249 			  channel->name, channel->dma_regs, channel->dma_irq,
250 			  channel->tx_ring, channel->rx_ring);
251 	}
252 
253 	pdata->channel_count = count;
254 
255 	return 0;
256 
257 err_mem:
258 	xgbe_free_channels(pdata);
259 
260 	return -ENOMEM;
261 }
262 
263 static inline unsigned int xgbe_tx_avail_desc(struct xgbe_ring *ring)
264 {
265 	return (ring->rdesc_count - (ring->cur - ring->dirty));
266 }
267 
268 static inline unsigned int xgbe_rx_dirty_desc(struct xgbe_ring *ring)
269 {
270 	return (ring->cur - ring->dirty);
271 }
272 
273 static int xgbe_maybe_stop_tx_queue(struct xgbe_channel *channel,
274 				    struct xgbe_ring *ring, unsigned int count)
275 {
276 	struct xgbe_prv_data *pdata = channel->pdata;
277 
278 	if (count > xgbe_tx_avail_desc(ring)) {
279 		netif_info(pdata, drv, pdata->netdev,
280 			   "Tx queue stopped, not enough descriptors available\n");
281 		netif_stop_subqueue(pdata->netdev, channel->queue_index);
282 		ring->tx.queue_stopped = 1;
283 
284 		/* If we haven't notified the hardware because of xmit_more
285 		 * support, tell it now
286 		 */
287 		if (ring->tx.xmit_more)
288 			pdata->hw_if.tx_start_xmit(channel, ring);
289 
290 		return NETDEV_TX_BUSY;
291 	}
292 
293 	return 0;
294 }
295 
296 static int xgbe_calc_rx_buf_size(struct net_device *netdev, unsigned int mtu)
297 {
298 	unsigned int rx_buf_size;
299 
300 	rx_buf_size = mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
301 	rx_buf_size = clamp_val(rx_buf_size, XGBE_RX_MIN_BUF_SIZE, PAGE_SIZE);
302 
303 	rx_buf_size = (rx_buf_size + XGBE_RX_BUF_ALIGN - 1) &
304 		      ~(XGBE_RX_BUF_ALIGN - 1);
305 
306 	return rx_buf_size;
307 }
308 
309 static void xgbe_enable_rx_tx_int(struct xgbe_prv_data *pdata,
310 				  struct xgbe_channel *channel)
311 {
312 	struct xgbe_hw_if *hw_if = &pdata->hw_if;
313 	enum xgbe_int int_id;
314 
315 	if (channel->tx_ring && channel->rx_ring)
316 		int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
317 	else if (channel->tx_ring)
318 		int_id = XGMAC_INT_DMA_CH_SR_TI;
319 	else if (channel->rx_ring)
320 		int_id = XGMAC_INT_DMA_CH_SR_RI;
321 	else
322 		return;
323 
324 	hw_if->enable_int(channel, int_id);
325 }
326 
327 static void xgbe_enable_rx_tx_ints(struct xgbe_prv_data *pdata)
328 {
329 	unsigned int i;
330 
331 	for (i = 0; i < pdata->channel_count; i++)
332 		xgbe_enable_rx_tx_int(pdata, pdata->channel[i]);
333 }
334 
335 static void xgbe_disable_rx_tx_int(struct xgbe_prv_data *pdata,
336 				   struct xgbe_channel *channel)
337 {
338 	struct xgbe_hw_if *hw_if = &pdata->hw_if;
339 	enum xgbe_int int_id;
340 
341 	if (channel->tx_ring && channel->rx_ring)
342 		int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
343 	else if (channel->tx_ring)
344 		int_id = XGMAC_INT_DMA_CH_SR_TI;
345 	else if (channel->rx_ring)
346 		int_id = XGMAC_INT_DMA_CH_SR_RI;
347 	else
348 		return;
349 
350 	hw_if->disable_int(channel, int_id);
351 }
352 
353 static void xgbe_disable_rx_tx_ints(struct xgbe_prv_data *pdata)
354 {
355 	unsigned int i;
356 
357 	for (i = 0; i < pdata->channel_count; i++)
358 		xgbe_disable_rx_tx_int(pdata, pdata->channel[i]);
359 }
360 
361 static bool xgbe_ecc_sec(struct xgbe_prv_data *pdata, unsigned long *period,
362 			 unsigned int *count, const char *area)
363 {
364 	if (time_before(jiffies, *period)) {
365 		(*count)++;
366 	} else {
367 		*period = jiffies + (ecc_sec_period * HZ);
368 		*count = 1;
369 	}
370 
371 	if (*count > ecc_sec_info_threshold)
372 		dev_warn_once(pdata->dev,
373 			      "%s ECC corrected errors exceed informational threshold\n",
374 			      area);
375 
376 	if (*count > ecc_sec_warn_threshold) {
377 		dev_warn_once(pdata->dev,
378 			      "%s ECC corrected errors exceed warning threshold\n",
379 			      area);
380 		return true;
381 	}
382 
383 	return false;
384 }
385 
386 static bool xgbe_ecc_ded(struct xgbe_prv_data *pdata, unsigned long *period,
387 			 unsigned int *count, const char *area)
388 {
389 	if (time_before(jiffies, *period)) {
390 		(*count)++;
391 	} else {
392 		*period = jiffies + (ecc_ded_period * HZ);
393 		*count = 1;
394 	}
395 
396 	if (*count > ecc_ded_threshold) {
397 		netdev_alert(pdata->netdev,
398 			     "%s ECC detected errors exceed threshold\n",
399 			     area);
400 		return true;
401 	}
402 
403 	return false;
404 }
405 
406 static void xgbe_ecc_isr_task(struct tasklet_struct *t)
407 {
408 	struct xgbe_prv_data *pdata = from_tasklet(pdata, t, tasklet_ecc);
409 	unsigned int ecc_isr;
410 	bool stop = false;
411 
412 	/* Mask status with only the interrupts we care about */
413 	ecc_isr = XP_IOREAD(pdata, XP_ECC_ISR);
414 	ecc_isr &= XP_IOREAD(pdata, XP_ECC_IER);
415 	netif_dbg(pdata, intr, pdata->netdev, "ECC_ISR=%#010x\n", ecc_isr);
416 
417 	if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, TX_DED)) {
418 		stop |= xgbe_ecc_ded(pdata, &pdata->tx_ded_period,
419 				     &pdata->tx_ded_count, "TX fifo");
420 	}
421 
422 	if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, RX_DED)) {
423 		stop |= xgbe_ecc_ded(pdata, &pdata->rx_ded_period,
424 				     &pdata->rx_ded_count, "RX fifo");
425 	}
426 
427 	if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, DESC_DED)) {
428 		stop |= xgbe_ecc_ded(pdata, &pdata->desc_ded_period,
429 				     &pdata->desc_ded_count,
430 				     "descriptor cache");
431 	}
432 
433 	if (stop) {
434 		pdata->hw_if.disable_ecc_ded(pdata);
435 		schedule_work(&pdata->stopdev_work);
436 		goto out;
437 	}
438 
439 	if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, TX_SEC)) {
440 		if (xgbe_ecc_sec(pdata, &pdata->tx_sec_period,
441 				 &pdata->tx_sec_count, "TX fifo"))
442 			pdata->hw_if.disable_ecc_sec(pdata, XGBE_ECC_SEC_TX);
443 	}
444 
445 	if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, RX_SEC))
446 		if (xgbe_ecc_sec(pdata, &pdata->rx_sec_period,
447 				 &pdata->rx_sec_count, "RX fifo"))
448 			pdata->hw_if.disable_ecc_sec(pdata, XGBE_ECC_SEC_RX);
449 
450 	if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, DESC_SEC))
451 		if (xgbe_ecc_sec(pdata, &pdata->desc_sec_period,
452 				 &pdata->desc_sec_count, "descriptor cache"))
453 			pdata->hw_if.disable_ecc_sec(pdata, XGBE_ECC_SEC_DESC);
454 
455 out:
456 	/* Clear all ECC interrupts */
457 	XP_IOWRITE(pdata, XP_ECC_ISR, ecc_isr);
458 
459 	/* Reissue interrupt if status is not clear */
460 	if (pdata->vdata->irq_reissue_support)
461 		XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 1);
462 }
463 
464 static irqreturn_t xgbe_ecc_isr(int irq, void *data)
465 {
466 	struct xgbe_prv_data *pdata = data;
467 
468 	if (pdata->isr_as_tasklet)
469 		tasklet_schedule(&pdata->tasklet_ecc);
470 	else
471 		xgbe_ecc_isr_task(&pdata->tasklet_ecc);
472 
473 	return IRQ_HANDLED;
474 }
475 
476 static void xgbe_isr_task(struct tasklet_struct *t)
477 {
478 	struct xgbe_prv_data *pdata = from_tasklet(pdata, t, tasklet_dev);
479 	struct xgbe_hw_if *hw_if = &pdata->hw_if;
480 	struct xgbe_channel *channel;
481 	unsigned int dma_isr, dma_ch_isr;
482 	unsigned int mac_isr, mac_tssr, mac_mdioisr;
483 	unsigned int i;
484 
485 	/* The DMA interrupt status register also reports MAC and MTL
486 	 * interrupts. So for polling mode, we just need to check for
487 	 * this register to be non-zero
488 	 */
489 	dma_isr = XGMAC_IOREAD(pdata, DMA_ISR);
490 	if (!dma_isr)
491 		goto isr_done;
492 
493 	netif_dbg(pdata, intr, pdata->netdev, "DMA_ISR=%#010x\n", dma_isr);
494 
495 	for (i = 0; i < pdata->channel_count; i++) {
496 		if (!(dma_isr & (1 << i)))
497 			continue;
498 
499 		channel = pdata->channel[i];
500 
501 		dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR);
502 		netif_dbg(pdata, intr, pdata->netdev, "DMA_CH%u_ISR=%#010x\n",
503 			  i, dma_ch_isr);
504 
505 		/* The TI or RI interrupt bits may still be set even if using
506 		 * per channel DMA interrupts. Check to be sure those are not
507 		 * enabled before using the private data napi structure.
508 		 */
509 		if (!pdata->per_channel_irq &&
510 		    (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, TI) ||
511 		     XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RI))) {
512 			if (napi_schedule_prep(&pdata->napi)) {
513 				/* Disable Tx and Rx interrupts */
514 				xgbe_disable_rx_tx_ints(pdata);
515 
516 				/* Turn on polling */
517 				__napi_schedule(&pdata->napi);
518 			}
519 		} else {
520 			/* Don't clear Rx/Tx status if doing per channel DMA
521 			 * interrupts, these will be cleared by the ISR for
522 			 * per channel DMA interrupts.
523 			 */
524 			XGMAC_SET_BITS(dma_ch_isr, DMA_CH_SR, TI, 0);
525 			XGMAC_SET_BITS(dma_ch_isr, DMA_CH_SR, RI, 0);
526 		}
527 
528 		if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RBU))
529 			pdata->ext_stats.rx_buffer_unavailable++;
530 
531 		/* Restart the device on a Fatal Bus Error */
532 		if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, FBE))
533 			schedule_work(&pdata->restart_work);
534 
535 		/* Clear interrupt signals */
536 		XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr);
537 	}
538 
539 	if (XGMAC_GET_BITS(dma_isr, DMA_ISR, MACIS)) {
540 		mac_isr = XGMAC_IOREAD(pdata, MAC_ISR);
541 
542 		netif_dbg(pdata, intr, pdata->netdev, "MAC_ISR=%#010x\n",
543 			  mac_isr);
544 
545 		if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCTXIS))
546 			hw_if->tx_mmc_int(pdata);
547 
548 		if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCRXIS))
549 			hw_if->rx_mmc_int(pdata);
550 
551 		if (XGMAC_GET_BITS(mac_isr, MAC_ISR, TSIS)) {
552 			mac_tssr = XGMAC_IOREAD(pdata, MAC_TSSR);
553 
554 			netif_dbg(pdata, intr, pdata->netdev,
555 				  "MAC_TSSR=%#010x\n", mac_tssr);
556 
557 			if (XGMAC_GET_BITS(mac_tssr, MAC_TSSR, TXTSC)) {
558 				/* Read Tx Timestamp to clear interrupt */
559 				pdata->tx_tstamp =
560 					hw_if->get_tx_tstamp(pdata);
561 				queue_work(pdata->dev_workqueue,
562 					   &pdata->tx_tstamp_work);
563 			}
564 		}
565 
566 		if (XGMAC_GET_BITS(mac_isr, MAC_ISR, SMI)) {
567 			mac_mdioisr = XGMAC_IOREAD(pdata, MAC_MDIOISR);
568 
569 			netif_dbg(pdata, intr, pdata->netdev,
570 				  "MAC_MDIOISR=%#010x\n", mac_mdioisr);
571 
572 			if (XGMAC_GET_BITS(mac_mdioisr, MAC_MDIOISR,
573 					   SNGLCOMPINT))
574 				complete(&pdata->mdio_complete);
575 		}
576 	}
577 
578 isr_done:
579 	/* If there is not a separate AN irq, handle it here */
580 	if (pdata->dev_irq == pdata->an_irq)
581 		pdata->phy_if.an_isr(pdata);
582 
583 	/* If there is not a separate ECC irq, handle it here */
584 	if (pdata->vdata->ecc_support && (pdata->dev_irq == pdata->ecc_irq))
585 		xgbe_ecc_isr_task(&pdata->tasklet_ecc);
586 
587 	/* If there is not a separate I2C irq, handle it here */
588 	if (pdata->vdata->i2c_support && (pdata->dev_irq == pdata->i2c_irq))
589 		pdata->i2c_if.i2c_isr(pdata);
590 
591 	/* Reissue interrupt if status is not clear */
592 	if (pdata->vdata->irq_reissue_support) {
593 		unsigned int reissue_mask;
594 
595 		reissue_mask = 1 << 0;
596 		if (!pdata->per_channel_irq)
597 			reissue_mask |= 0xffff << 4;
598 
599 		XP_IOWRITE(pdata, XP_INT_REISSUE_EN, reissue_mask);
600 	}
601 }
602 
603 static irqreturn_t xgbe_isr(int irq, void *data)
604 {
605 	struct xgbe_prv_data *pdata = data;
606 
607 	if (pdata->isr_as_tasklet)
608 		tasklet_schedule(&pdata->tasklet_dev);
609 	else
610 		xgbe_isr_task(&pdata->tasklet_dev);
611 
612 	return IRQ_HANDLED;
613 }
614 
615 static irqreturn_t xgbe_dma_isr(int irq, void *data)
616 {
617 	struct xgbe_channel *channel = data;
618 	struct xgbe_prv_data *pdata = channel->pdata;
619 	unsigned int dma_status;
620 
621 	/* Per channel DMA interrupts are enabled, so we use the per
622 	 * channel napi structure and not the private data napi structure
623 	 */
624 	if (napi_schedule_prep(&channel->napi)) {
625 		/* Disable Tx and Rx interrupts */
626 		if (pdata->channel_irq_mode)
627 			xgbe_disable_rx_tx_int(pdata, channel);
628 		else
629 			disable_irq_nosync(channel->dma_irq);
630 
631 		/* Turn on polling */
632 		__napi_schedule_irqoff(&channel->napi);
633 	}
634 
635 	/* Clear Tx/Rx signals */
636 	dma_status = 0;
637 	XGMAC_SET_BITS(dma_status, DMA_CH_SR, TI, 1);
638 	XGMAC_SET_BITS(dma_status, DMA_CH_SR, RI, 1);
639 	XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_status);
640 
641 	return IRQ_HANDLED;
642 }
643 
644 static void xgbe_tx_timer(struct timer_list *t)
645 {
646 	struct xgbe_channel *channel = from_timer(channel, t, tx_timer);
647 	struct xgbe_prv_data *pdata = channel->pdata;
648 	struct napi_struct *napi;
649 
650 	DBGPR("-->xgbe_tx_timer\n");
651 
652 	napi = (pdata->per_channel_irq) ? &channel->napi : &pdata->napi;
653 
654 	if (napi_schedule_prep(napi)) {
655 		/* Disable Tx and Rx interrupts */
656 		if (pdata->per_channel_irq)
657 			if (pdata->channel_irq_mode)
658 				xgbe_disable_rx_tx_int(pdata, channel);
659 			else
660 				disable_irq_nosync(channel->dma_irq);
661 		else
662 			xgbe_disable_rx_tx_ints(pdata);
663 
664 		/* Turn on polling */
665 		__napi_schedule(napi);
666 	}
667 
668 	channel->tx_timer_active = 0;
669 
670 	DBGPR("<--xgbe_tx_timer\n");
671 }
672 
673 static void xgbe_service(struct work_struct *work)
674 {
675 	struct xgbe_prv_data *pdata = container_of(work,
676 						   struct xgbe_prv_data,
677 						   service_work);
678 
679 	pdata->phy_if.phy_status(pdata);
680 }
681 
682 static void xgbe_service_timer(struct timer_list *t)
683 {
684 	struct xgbe_prv_data *pdata = from_timer(pdata, t, service_timer);
685 
686 	queue_work(pdata->dev_workqueue, &pdata->service_work);
687 
688 	mod_timer(&pdata->service_timer, jiffies + HZ);
689 }
690 
691 static void xgbe_init_timers(struct xgbe_prv_data *pdata)
692 {
693 	struct xgbe_channel *channel;
694 	unsigned int i;
695 
696 	timer_setup(&pdata->service_timer, xgbe_service_timer, 0);
697 
698 	for (i = 0; i < pdata->channel_count; i++) {
699 		channel = pdata->channel[i];
700 		if (!channel->tx_ring)
701 			break;
702 
703 		timer_setup(&channel->tx_timer, xgbe_tx_timer, 0);
704 	}
705 }
706 
707 static void xgbe_start_timers(struct xgbe_prv_data *pdata)
708 {
709 	mod_timer(&pdata->service_timer, jiffies + HZ);
710 }
711 
712 static void xgbe_stop_timers(struct xgbe_prv_data *pdata)
713 {
714 	struct xgbe_channel *channel;
715 	unsigned int i;
716 
717 	del_timer_sync(&pdata->service_timer);
718 
719 	for (i = 0; i < pdata->channel_count; i++) {
720 		channel = pdata->channel[i];
721 		if (!channel->tx_ring)
722 			break;
723 
724 		del_timer_sync(&channel->tx_timer);
725 	}
726 }
727 
728 void xgbe_get_all_hw_features(struct xgbe_prv_data *pdata)
729 {
730 	unsigned int mac_hfr0, mac_hfr1, mac_hfr2;
731 	struct xgbe_hw_features *hw_feat = &pdata->hw_feat;
732 
733 	mac_hfr0 = XGMAC_IOREAD(pdata, MAC_HWF0R);
734 	mac_hfr1 = XGMAC_IOREAD(pdata, MAC_HWF1R);
735 	mac_hfr2 = XGMAC_IOREAD(pdata, MAC_HWF2R);
736 
737 	memset(hw_feat, 0, sizeof(*hw_feat));
738 
739 	hw_feat->version = XGMAC_IOREAD(pdata, MAC_VR);
740 
741 	/* Hardware feature register 0 */
742 	hw_feat->gmii        = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, GMIISEL);
743 	hw_feat->vlhash      = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VLHASH);
744 	hw_feat->sma         = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SMASEL);
745 	hw_feat->rwk         = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RWKSEL);
746 	hw_feat->mgk         = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MGKSEL);
747 	hw_feat->mmc         = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MMCSEL);
748 	hw_feat->aoe         = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, ARPOFFSEL);
749 	hw_feat->ts          = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSEL);
750 	hw_feat->eee         = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, EEESEL);
751 	hw_feat->tx_coe      = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TXCOESEL);
752 	hw_feat->rx_coe      = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RXCOESEL);
753 	hw_feat->addn_mac    = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R,
754 					      ADDMACADRSEL);
755 	hw_feat->ts_src      = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSTSSEL);
756 	hw_feat->sa_vlan_ins = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SAVLANINS);
757 	hw_feat->vxn         = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VXN);
758 
759 	/* Hardware feature register 1 */
760 	hw_feat->rx_fifo_size  = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
761 						RXFIFOSIZE);
762 	hw_feat->tx_fifo_size  = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
763 						TXFIFOSIZE);
764 	hw_feat->adv_ts_hi     = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADVTHWORD);
765 	hw_feat->dma_width     = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADDR64);
766 	hw_feat->dcb           = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DCBEN);
767 	hw_feat->sph           = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, SPHEN);
768 	hw_feat->tso           = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, TSOEN);
769 	hw_feat->dma_debug     = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DBGMEMA);
770 	hw_feat->rss           = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, RSSEN);
771 	hw_feat->tc_cnt	       = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, NUMTC);
772 	hw_feat->hash_table_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
773 						  HASHTBLSZ);
774 	hw_feat->l3l4_filter_num = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
775 						  L3L4FNUM);
776 
777 	/* Hardware feature register 2 */
778 	hw_feat->rx_q_cnt     = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXQCNT);
779 	hw_feat->tx_q_cnt     = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXQCNT);
780 	hw_feat->rx_ch_cnt    = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXCHCNT);
781 	hw_feat->tx_ch_cnt    = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXCHCNT);
782 	hw_feat->pps_out_num  = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, PPSOUTNUM);
783 	hw_feat->aux_snap_num = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, AUXSNAPNUM);
784 
785 	/* Translate the Hash Table size into actual number */
786 	switch (hw_feat->hash_table_size) {
787 	case 0:
788 		break;
789 	case 1:
790 		hw_feat->hash_table_size = 64;
791 		break;
792 	case 2:
793 		hw_feat->hash_table_size = 128;
794 		break;
795 	case 3:
796 		hw_feat->hash_table_size = 256;
797 		break;
798 	}
799 
800 	/* Translate the address width setting into actual number */
801 	switch (hw_feat->dma_width) {
802 	case 0:
803 		hw_feat->dma_width = 32;
804 		break;
805 	case 1:
806 		hw_feat->dma_width = 40;
807 		break;
808 	case 2:
809 		hw_feat->dma_width = 48;
810 		break;
811 	default:
812 		hw_feat->dma_width = 32;
813 	}
814 
815 	/* The Queue, Channel and TC counts are zero based so increment them
816 	 * to get the actual number
817 	 */
818 	hw_feat->rx_q_cnt++;
819 	hw_feat->tx_q_cnt++;
820 	hw_feat->rx_ch_cnt++;
821 	hw_feat->tx_ch_cnt++;
822 	hw_feat->tc_cnt++;
823 
824 	/* Translate the fifo sizes into actual numbers */
825 	hw_feat->rx_fifo_size = 1 << (hw_feat->rx_fifo_size + 7);
826 	hw_feat->tx_fifo_size = 1 << (hw_feat->tx_fifo_size + 7);
827 
828 	if (netif_msg_probe(pdata)) {
829 		dev_dbg(pdata->dev, "Hardware features:\n");
830 
831 		/* Hardware feature register 0 */
832 		dev_dbg(pdata->dev, "  1GbE support              : %s\n",
833 			hw_feat->gmii ? "yes" : "no");
834 		dev_dbg(pdata->dev, "  VLAN hash filter          : %s\n",
835 			hw_feat->vlhash ? "yes" : "no");
836 		dev_dbg(pdata->dev, "  MDIO interface            : %s\n",
837 			hw_feat->sma ? "yes" : "no");
838 		dev_dbg(pdata->dev, "  Wake-up packet support    : %s\n",
839 			hw_feat->rwk ? "yes" : "no");
840 		dev_dbg(pdata->dev, "  Magic packet support      : %s\n",
841 			hw_feat->mgk ? "yes" : "no");
842 		dev_dbg(pdata->dev, "  Management counters       : %s\n",
843 			hw_feat->mmc ? "yes" : "no");
844 		dev_dbg(pdata->dev, "  ARP offload               : %s\n",
845 			hw_feat->aoe ? "yes" : "no");
846 		dev_dbg(pdata->dev, "  IEEE 1588-2008 Timestamp  : %s\n",
847 			hw_feat->ts ? "yes" : "no");
848 		dev_dbg(pdata->dev, "  Energy Efficient Ethernet : %s\n",
849 			hw_feat->eee ? "yes" : "no");
850 		dev_dbg(pdata->dev, "  TX checksum offload       : %s\n",
851 			hw_feat->tx_coe ? "yes" : "no");
852 		dev_dbg(pdata->dev, "  RX checksum offload       : %s\n",
853 			hw_feat->rx_coe ? "yes" : "no");
854 		dev_dbg(pdata->dev, "  Additional MAC addresses  : %u\n",
855 			hw_feat->addn_mac);
856 		dev_dbg(pdata->dev, "  Timestamp source          : %s\n",
857 			(hw_feat->ts_src == 1) ? "internal" :
858 			(hw_feat->ts_src == 2) ? "external" :
859 			(hw_feat->ts_src == 3) ? "internal/external" : "n/a");
860 		dev_dbg(pdata->dev, "  SA/VLAN insertion         : %s\n",
861 			hw_feat->sa_vlan_ins ? "yes" : "no");
862 		dev_dbg(pdata->dev, "  VXLAN/NVGRE support       : %s\n",
863 			hw_feat->vxn ? "yes" : "no");
864 
865 		/* Hardware feature register 1 */
866 		dev_dbg(pdata->dev, "  RX fifo size              : %u\n",
867 			hw_feat->rx_fifo_size);
868 		dev_dbg(pdata->dev, "  TX fifo size              : %u\n",
869 			hw_feat->tx_fifo_size);
870 		dev_dbg(pdata->dev, "  IEEE 1588 high word       : %s\n",
871 			hw_feat->adv_ts_hi ? "yes" : "no");
872 		dev_dbg(pdata->dev, "  DMA width                 : %u\n",
873 			hw_feat->dma_width);
874 		dev_dbg(pdata->dev, "  Data Center Bridging      : %s\n",
875 			hw_feat->dcb ? "yes" : "no");
876 		dev_dbg(pdata->dev, "  Split header              : %s\n",
877 			hw_feat->sph ? "yes" : "no");
878 		dev_dbg(pdata->dev, "  TCP Segmentation Offload  : %s\n",
879 			hw_feat->tso ? "yes" : "no");
880 		dev_dbg(pdata->dev, "  Debug memory interface    : %s\n",
881 			hw_feat->dma_debug ? "yes" : "no");
882 		dev_dbg(pdata->dev, "  Receive Side Scaling      : %s\n",
883 			hw_feat->rss ? "yes" : "no");
884 		dev_dbg(pdata->dev, "  Traffic Class count       : %u\n",
885 			hw_feat->tc_cnt);
886 		dev_dbg(pdata->dev, "  Hash table size           : %u\n",
887 			hw_feat->hash_table_size);
888 		dev_dbg(pdata->dev, "  L3/L4 Filters             : %u\n",
889 			hw_feat->l3l4_filter_num);
890 
891 		/* Hardware feature register 2 */
892 		dev_dbg(pdata->dev, "  RX queue count            : %u\n",
893 			hw_feat->rx_q_cnt);
894 		dev_dbg(pdata->dev, "  TX queue count            : %u\n",
895 			hw_feat->tx_q_cnt);
896 		dev_dbg(pdata->dev, "  RX DMA channel count      : %u\n",
897 			hw_feat->rx_ch_cnt);
898 		dev_dbg(pdata->dev, "  TX DMA channel count      : %u\n",
899 			hw_feat->rx_ch_cnt);
900 		dev_dbg(pdata->dev, "  PPS outputs               : %u\n",
901 			hw_feat->pps_out_num);
902 		dev_dbg(pdata->dev, "  Auxiliary snapshot inputs : %u\n",
903 			hw_feat->aux_snap_num);
904 	}
905 }
906 
907 static int xgbe_vxlan_set_port(struct net_device *netdev, unsigned int table,
908 			       unsigned int entry, struct udp_tunnel_info *ti)
909 {
910 	struct xgbe_prv_data *pdata = netdev_priv(netdev);
911 
912 	pdata->vxlan_port = be16_to_cpu(ti->port);
913 	pdata->hw_if.enable_vxlan(pdata);
914 
915 	return 0;
916 }
917 
918 static int xgbe_vxlan_unset_port(struct net_device *netdev, unsigned int table,
919 				 unsigned int entry, struct udp_tunnel_info *ti)
920 {
921 	struct xgbe_prv_data *pdata = netdev_priv(netdev);
922 
923 	pdata->hw_if.disable_vxlan(pdata);
924 	pdata->vxlan_port = 0;
925 
926 	return 0;
927 }
928 
929 static const struct udp_tunnel_nic_info xgbe_udp_tunnels = {
930 	.set_port	= xgbe_vxlan_set_port,
931 	.unset_port	= xgbe_vxlan_unset_port,
932 	.flags		= UDP_TUNNEL_NIC_INFO_OPEN_ONLY,
933 	.tables		= {
934 		{ .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN, },
935 	},
936 };
937 
938 const struct udp_tunnel_nic_info *xgbe_get_udp_tunnel_info(void)
939 {
940 	return &xgbe_udp_tunnels;
941 }
942 
943 static void xgbe_napi_enable(struct xgbe_prv_data *pdata, unsigned int add)
944 {
945 	struct xgbe_channel *channel;
946 	unsigned int i;
947 
948 	if (pdata->per_channel_irq) {
949 		for (i = 0; i < pdata->channel_count; i++) {
950 			channel = pdata->channel[i];
951 			if (add)
952 				netif_napi_add(pdata->netdev, &channel->napi,
953 					       xgbe_one_poll, NAPI_POLL_WEIGHT);
954 
955 			napi_enable(&channel->napi);
956 		}
957 	} else {
958 		if (add)
959 			netif_napi_add(pdata->netdev, &pdata->napi,
960 				       xgbe_all_poll, NAPI_POLL_WEIGHT);
961 
962 		napi_enable(&pdata->napi);
963 	}
964 }
965 
966 static void xgbe_napi_disable(struct xgbe_prv_data *pdata, unsigned int del)
967 {
968 	struct xgbe_channel *channel;
969 	unsigned int i;
970 
971 	if (pdata->per_channel_irq) {
972 		for (i = 0; i < pdata->channel_count; i++) {
973 			channel = pdata->channel[i];
974 			napi_disable(&channel->napi);
975 
976 			if (del)
977 				netif_napi_del(&channel->napi);
978 		}
979 	} else {
980 		napi_disable(&pdata->napi);
981 
982 		if (del)
983 			netif_napi_del(&pdata->napi);
984 	}
985 }
986 
987 static int xgbe_request_irqs(struct xgbe_prv_data *pdata)
988 {
989 	struct xgbe_channel *channel;
990 	struct net_device *netdev = pdata->netdev;
991 	unsigned int i;
992 	int ret;
993 
994 	tasklet_setup(&pdata->tasklet_dev, xgbe_isr_task);
995 	tasklet_setup(&pdata->tasklet_ecc, xgbe_ecc_isr_task);
996 
997 	ret = devm_request_irq(pdata->dev, pdata->dev_irq, xgbe_isr, 0,
998 			       netdev_name(netdev), pdata);
999 	if (ret) {
1000 		netdev_alert(netdev, "error requesting irq %d\n",
1001 			     pdata->dev_irq);
1002 		return ret;
1003 	}
1004 
1005 	if (pdata->vdata->ecc_support && (pdata->dev_irq != pdata->ecc_irq)) {
1006 		ret = devm_request_irq(pdata->dev, pdata->ecc_irq, xgbe_ecc_isr,
1007 				       0, pdata->ecc_name, pdata);
1008 		if (ret) {
1009 			netdev_alert(netdev, "error requesting ecc irq %d\n",
1010 				     pdata->ecc_irq);
1011 			goto err_dev_irq;
1012 		}
1013 	}
1014 
1015 	if (!pdata->per_channel_irq)
1016 		return 0;
1017 
1018 	for (i = 0; i < pdata->channel_count; i++) {
1019 		channel = pdata->channel[i];
1020 		snprintf(channel->dma_irq_name,
1021 			 sizeof(channel->dma_irq_name) - 1,
1022 			 "%s-TxRx-%u", netdev_name(netdev),
1023 			 channel->queue_index);
1024 
1025 		ret = devm_request_irq(pdata->dev, channel->dma_irq,
1026 				       xgbe_dma_isr, 0,
1027 				       channel->dma_irq_name, channel);
1028 		if (ret) {
1029 			netdev_alert(netdev, "error requesting irq %d\n",
1030 				     channel->dma_irq);
1031 			goto err_dma_irq;
1032 		}
1033 
1034 		irq_set_affinity_hint(channel->dma_irq,
1035 				      &channel->affinity_mask);
1036 	}
1037 
1038 	return 0;
1039 
1040 err_dma_irq:
1041 	/* Using an unsigned int, 'i' will go to UINT_MAX and exit */
1042 	for (i--; i < pdata->channel_count; i--) {
1043 		channel = pdata->channel[i];
1044 
1045 		irq_set_affinity_hint(channel->dma_irq, NULL);
1046 		devm_free_irq(pdata->dev, channel->dma_irq, channel);
1047 	}
1048 
1049 	if (pdata->vdata->ecc_support && (pdata->dev_irq != pdata->ecc_irq))
1050 		devm_free_irq(pdata->dev, pdata->ecc_irq, pdata);
1051 
1052 err_dev_irq:
1053 	devm_free_irq(pdata->dev, pdata->dev_irq, pdata);
1054 
1055 	return ret;
1056 }
1057 
1058 static void xgbe_free_irqs(struct xgbe_prv_data *pdata)
1059 {
1060 	struct xgbe_channel *channel;
1061 	unsigned int i;
1062 
1063 	devm_free_irq(pdata->dev, pdata->dev_irq, pdata);
1064 
1065 	if (pdata->vdata->ecc_support && (pdata->dev_irq != pdata->ecc_irq))
1066 		devm_free_irq(pdata->dev, pdata->ecc_irq, pdata);
1067 
1068 	if (!pdata->per_channel_irq)
1069 		return;
1070 
1071 	for (i = 0; i < pdata->channel_count; i++) {
1072 		channel = pdata->channel[i];
1073 
1074 		irq_set_affinity_hint(channel->dma_irq, NULL);
1075 		devm_free_irq(pdata->dev, channel->dma_irq, channel);
1076 	}
1077 }
1078 
1079 void xgbe_init_tx_coalesce(struct xgbe_prv_data *pdata)
1080 {
1081 	struct xgbe_hw_if *hw_if = &pdata->hw_if;
1082 
1083 	DBGPR("-->xgbe_init_tx_coalesce\n");
1084 
1085 	pdata->tx_usecs = XGMAC_INIT_DMA_TX_USECS;
1086 	pdata->tx_frames = XGMAC_INIT_DMA_TX_FRAMES;
1087 
1088 	hw_if->config_tx_coalesce(pdata);
1089 
1090 	DBGPR("<--xgbe_init_tx_coalesce\n");
1091 }
1092 
1093 void xgbe_init_rx_coalesce(struct xgbe_prv_data *pdata)
1094 {
1095 	struct xgbe_hw_if *hw_if = &pdata->hw_if;
1096 
1097 	DBGPR("-->xgbe_init_rx_coalesce\n");
1098 
1099 	pdata->rx_riwt = hw_if->usec_to_riwt(pdata, XGMAC_INIT_DMA_RX_USECS);
1100 	pdata->rx_usecs = XGMAC_INIT_DMA_RX_USECS;
1101 	pdata->rx_frames = XGMAC_INIT_DMA_RX_FRAMES;
1102 
1103 	hw_if->config_rx_coalesce(pdata);
1104 
1105 	DBGPR("<--xgbe_init_rx_coalesce\n");
1106 }
1107 
1108 static void xgbe_free_tx_data(struct xgbe_prv_data *pdata)
1109 {
1110 	struct xgbe_desc_if *desc_if = &pdata->desc_if;
1111 	struct xgbe_ring *ring;
1112 	struct xgbe_ring_data *rdata;
1113 	unsigned int i, j;
1114 
1115 	DBGPR("-->xgbe_free_tx_data\n");
1116 
1117 	for (i = 0; i < pdata->channel_count; i++) {
1118 		ring = pdata->channel[i]->tx_ring;
1119 		if (!ring)
1120 			break;
1121 
1122 		for (j = 0; j < ring->rdesc_count; j++) {
1123 			rdata = XGBE_GET_DESC_DATA(ring, j);
1124 			desc_if->unmap_rdata(pdata, rdata);
1125 		}
1126 	}
1127 
1128 	DBGPR("<--xgbe_free_tx_data\n");
1129 }
1130 
1131 static void xgbe_free_rx_data(struct xgbe_prv_data *pdata)
1132 {
1133 	struct xgbe_desc_if *desc_if = &pdata->desc_if;
1134 	struct xgbe_ring *ring;
1135 	struct xgbe_ring_data *rdata;
1136 	unsigned int i, j;
1137 
1138 	DBGPR("-->xgbe_free_rx_data\n");
1139 
1140 	for (i = 0; i < pdata->channel_count; i++) {
1141 		ring = pdata->channel[i]->rx_ring;
1142 		if (!ring)
1143 			break;
1144 
1145 		for (j = 0; j < ring->rdesc_count; j++) {
1146 			rdata = XGBE_GET_DESC_DATA(ring, j);
1147 			desc_if->unmap_rdata(pdata, rdata);
1148 		}
1149 	}
1150 
1151 	DBGPR("<--xgbe_free_rx_data\n");
1152 }
1153 
1154 static int xgbe_phy_reset(struct xgbe_prv_data *pdata)
1155 {
1156 	pdata->phy_link = -1;
1157 	pdata->phy_speed = SPEED_UNKNOWN;
1158 
1159 	return pdata->phy_if.phy_reset(pdata);
1160 }
1161 
1162 int xgbe_powerdown(struct net_device *netdev, unsigned int caller)
1163 {
1164 	struct xgbe_prv_data *pdata = netdev_priv(netdev);
1165 	struct xgbe_hw_if *hw_if = &pdata->hw_if;
1166 	unsigned long flags;
1167 
1168 	DBGPR("-->xgbe_powerdown\n");
1169 
1170 	if (!netif_running(netdev) ||
1171 	    (caller == XGMAC_IOCTL_CONTEXT && pdata->power_down)) {
1172 		netdev_alert(netdev, "Device is already powered down\n");
1173 		DBGPR("<--xgbe_powerdown\n");
1174 		return -EINVAL;
1175 	}
1176 
1177 	spin_lock_irqsave(&pdata->lock, flags);
1178 
1179 	if (caller == XGMAC_DRIVER_CONTEXT)
1180 		netif_device_detach(netdev);
1181 
1182 	netif_tx_stop_all_queues(netdev);
1183 
1184 	xgbe_stop_timers(pdata);
1185 	flush_workqueue(pdata->dev_workqueue);
1186 
1187 	hw_if->powerdown_tx(pdata);
1188 	hw_if->powerdown_rx(pdata);
1189 
1190 	xgbe_napi_disable(pdata, 0);
1191 
1192 	pdata->power_down = 1;
1193 
1194 	spin_unlock_irqrestore(&pdata->lock, flags);
1195 
1196 	DBGPR("<--xgbe_powerdown\n");
1197 
1198 	return 0;
1199 }
1200 
1201 int xgbe_powerup(struct net_device *netdev, unsigned int caller)
1202 {
1203 	struct xgbe_prv_data *pdata = netdev_priv(netdev);
1204 	struct xgbe_hw_if *hw_if = &pdata->hw_if;
1205 	unsigned long flags;
1206 
1207 	DBGPR("-->xgbe_powerup\n");
1208 
1209 	if (!netif_running(netdev) ||
1210 	    (caller == XGMAC_IOCTL_CONTEXT && !pdata->power_down)) {
1211 		netdev_alert(netdev, "Device is already powered up\n");
1212 		DBGPR("<--xgbe_powerup\n");
1213 		return -EINVAL;
1214 	}
1215 
1216 	spin_lock_irqsave(&pdata->lock, flags);
1217 
1218 	pdata->power_down = 0;
1219 
1220 	xgbe_napi_enable(pdata, 0);
1221 
1222 	hw_if->powerup_tx(pdata);
1223 	hw_if->powerup_rx(pdata);
1224 
1225 	if (caller == XGMAC_DRIVER_CONTEXT)
1226 		netif_device_attach(netdev);
1227 
1228 	netif_tx_start_all_queues(netdev);
1229 
1230 	xgbe_start_timers(pdata);
1231 
1232 	spin_unlock_irqrestore(&pdata->lock, flags);
1233 
1234 	DBGPR("<--xgbe_powerup\n");
1235 
1236 	return 0;
1237 }
1238 
1239 static void xgbe_free_memory(struct xgbe_prv_data *pdata)
1240 {
1241 	struct xgbe_desc_if *desc_if = &pdata->desc_if;
1242 
1243 	/* Free the ring descriptors and buffers */
1244 	desc_if->free_ring_resources(pdata);
1245 
1246 	/* Free the channel and ring structures */
1247 	xgbe_free_channels(pdata);
1248 }
1249 
1250 static int xgbe_alloc_memory(struct xgbe_prv_data *pdata)
1251 {
1252 	struct xgbe_desc_if *desc_if = &pdata->desc_if;
1253 	struct net_device *netdev = pdata->netdev;
1254 	int ret;
1255 
1256 	if (pdata->new_tx_ring_count) {
1257 		pdata->tx_ring_count = pdata->new_tx_ring_count;
1258 		pdata->tx_q_count = pdata->tx_ring_count;
1259 		pdata->new_tx_ring_count = 0;
1260 	}
1261 
1262 	if (pdata->new_rx_ring_count) {
1263 		pdata->rx_ring_count = pdata->new_rx_ring_count;
1264 		pdata->new_rx_ring_count = 0;
1265 	}
1266 
1267 	/* Calculate the Rx buffer size before allocating rings */
1268 	pdata->rx_buf_size = xgbe_calc_rx_buf_size(netdev, netdev->mtu);
1269 
1270 	/* Allocate the channel and ring structures */
1271 	ret = xgbe_alloc_channels(pdata);
1272 	if (ret)
1273 		return ret;
1274 
1275 	/* Allocate the ring descriptors and buffers */
1276 	ret = desc_if->alloc_ring_resources(pdata);
1277 	if (ret)
1278 		goto err_channels;
1279 
1280 	/* Initialize the service and Tx timers */
1281 	xgbe_init_timers(pdata);
1282 
1283 	return 0;
1284 
1285 err_channels:
1286 	xgbe_free_memory(pdata);
1287 
1288 	return ret;
1289 }
1290 
1291 static int xgbe_start(struct xgbe_prv_data *pdata)
1292 {
1293 	struct xgbe_hw_if *hw_if = &pdata->hw_if;
1294 	struct xgbe_phy_if *phy_if = &pdata->phy_if;
1295 	struct net_device *netdev = pdata->netdev;
1296 	unsigned int i;
1297 	int ret;
1298 
1299 	/* Set the number of queues */
1300 	ret = netif_set_real_num_tx_queues(netdev, pdata->tx_ring_count);
1301 	if (ret) {
1302 		netdev_err(netdev, "error setting real tx queue count\n");
1303 		return ret;
1304 	}
1305 
1306 	ret = netif_set_real_num_rx_queues(netdev, pdata->rx_ring_count);
1307 	if (ret) {
1308 		netdev_err(netdev, "error setting real rx queue count\n");
1309 		return ret;
1310 	}
1311 
1312 	/* Set RSS lookup table data for programming */
1313 	for (i = 0; i < XGBE_RSS_MAX_TABLE_SIZE; i++)
1314 		XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH,
1315 			       i % pdata->rx_ring_count);
1316 
1317 	ret = hw_if->init(pdata);
1318 	if (ret)
1319 		return ret;
1320 
1321 	xgbe_napi_enable(pdata, 1);
1322 
1323 	ret = xgbe_request_irqs(pdata);
1324 	if (ret)
1325 		goto err_napi;
1326 
1327 	ret = phy_if->phy_start(pdata);
1328 	if (ret)
1329 		goto err_irqs;
1330 
1331 	hw_if->enable_tx(pdata);
1332 	hw_if->enable_rx(pdata);
1333 
1334 	udp_tunnel_nic_reset_ntf(netdev);
1335 
1336 	netif_tx_start_all_queues(netdev);
1337 
1338 	xgbe_start_timers(pdata);
1339 	queue_work(pdata->dev_workqueue, &pdata->service_work);
1340 
1341 	clear_bit(XGBE_STOPPED, &pdata->dev_state);
1342 
1343 	return 0;
1344 
1345 err_irqs:
1346 	xgbe_free_irqs(pdata);
1347 
1348 err_napi:
1349 	xgbe_napi_disable(pdata, 1);
1350 
1351 	hw_if->exit(pdata);
1352 
1353 	return ret;
1354 }
1355 
1356 static void xgbe_stop(struct xgbe_prv_data *pdata)
1357 {
1358 	struct xgbe_hw_if *hw_if = &pdata->hw_if;
1359 	struct xgbe_phy_if *phy_if = &pdata->phy_if;
1360 	struct xgbe_channel *channel;
1361 	struct net_device *netdev = pdata->netdev;
1362 	struct netdev_queue *txq;
1363 	unsigned int i;
1364 
1365 	DBGPR("-->xgbe_stop\n");
1366 
1367 	if (test_bit(XGBE_STOPPED, &pdata->dev_state))
1368 		return;
1369 
1370 	netif_tx_stop_all_queues(netdev);
1371 
1372 	xgbe_stop_timers(pdata);
1373 	flush_workqueue(pdata->dev_workqueue);
1374 
1375 	xgbe_vxlan_unset_port(netdev, 0, 0, NULL);
1376 
1377 	hw_if->disable_tx(pdata);
1378 	hw_if->disable_rx(pdata);
1379 
1380 	phy_if->phy_stop(pdata);
1381 
1382 	xgbe_free_irqs(pdata);
1383 
1384 	xgbe_napi_disable(pdata, 1);
1385 
1386 	hw_if->exit(pdata);
1387 
1388 	for (i = 0; i < pdata->channel_count; i++) {
1389 		channel = pdata->channel[i];
1390 		if (!channel->tx_ring)
1391 			continue;
1392 
1393 		txq = netdev_get_tx_queue(netdev, channel->queue_index);
1394 		netdev_tx_reset_queue(txq);
1395 	}
1396 
1397 	set_bit(XGBE_STOPPED, &pdata->dev_state);
1398 
1399 	DBGPR("<--xgbe_stop\n");
1400 }
1401 
1402 static void xgbe_stopdev(struct work_struct *work)
1403 {
1404 	struct xgbe_prv_data *pdata = container_of(work,
1405 						   struct xgbe_prv_data,
1406 						   stopdev_work);
1407 
1408 	rtnl_lock();
1409 
1410 	xgbe_stop(pdata);
1411 
1412 	xgbe_free_tx_data(pdata);
1413 	xgbe_free_rx_data(pdata);
1414 
1415 	rtnl_unlock();
1416 
1417 	netdev_alert(pdata->netdev, "device stopped\n");
1418 }
1419 
1420 void xgbe_full_restart_dev(struct xgbe_prv_data *pdata)
1421 {
1422 	/* If not running, "restart" will happen on open */
1423 	if (!netif_running(pdata->netdev))
1424 		return;
1425 
1426 	xgbe_stop(pdata);
1427 
1428 	xgbe_free_memory(pdata);
1429 	xgbe_alloc_memory(pdata);
1430 
1431 	xgbe_start(pdata);
1432 }
1433 
1434 void xgbe_restart_dev(struct xgbe_prv_data *pdata)
1435 {
1436 	/* If not running, "restart" will happen on open */
1437 	if (!netif_running(pdata->netdev))
1438 		return;
1439 
1440 	xgbe_stop(pdata);
1441 
1442 	xgbe_free_tx_data(pdata);
1443 	xgbe_free_rx_data(pdata);
1444 
1445 	xgbe_start(pdata);
1446 }
1447 
1448 static void xgbe_restart(struct work_struct *work)
1449 {
1450 	struct xgbe_prv_data *pdata = container_of(work,
1451 						   struct xgbe_prv_data,
1452 						   restart_work);
1453 
1454 	rtnl_lock();
1455 
1456 	xgbe_restart_dev(pdata);
1457 
1458 	rtnl_unlock();
1459 }
1460 
1461 static void xgbe_tx_tstamp(struct work_struct *work)
1462 {
1463 	struct xgbe_prv_data *pdata = container_of(work,
1464 						   struct xgbe_prv_data,
1465 						   tx_tstamp_work);
1466 	struct skb_shared_hwtstamps hwtstamps;
1467 	u64 nsec;
1468 	unsigned long flags;
1469 
1470 	spin_lock_irqsave(&pdata->tstamp_lock, flags);
1471 	if (!pdata->tx_tstamp_skb)
1472 		goto unlock;
1473 
1474 	if (pdata->tx_tstamp) {
1475 		nsec = timecounter_cyc2time(&pdata->tstamp_tc,
1476 					    pdata->tx_tstamp);
1477 
1478 		memset(&hwtstamps, 0, sizeof(hwtstamps));
1479 		hwtstamps.hwtstamp = ns_to_ktime(nsec);
1480 		skb_tstamp_tx(pdata->tx_tstamp_skb, &hwtstamps);
1481 	}
1482 
1483 	dev_kfree_skb_any(pdata->tx_tstamp_skb);
1484 
1485 	pdata->tx_tstamp_skb = NULL;
1486 
1487 unlock:
1488 	spin_unlock_irqrestore(&pdata->tstamp_lock, flags);
1489 }
1490 
1491 static int xgbe_get_hwtstamp_settings(struct xgbe_prv_data *pdata,
1492 				      struct ifreq *ifreq)
1493 {
1494 	if (copy_to_user(ifreq->ifr_data, &pdata->tstamp_config,
1495 			 sizeof(pdata->tstamp_config)))
1496 		return -EFAULT;
1497 
1498 	return 0;
1499 }
1500 
1501 static int xgbe_set_hwtstamp_settings(struct xgbe_prv_data *pdata,
1502 				      struct ifreq *ifreq)
1503 {
1504 	struct hwtstamp_config config;
1505 	unsigned int mac_tscr;
1506 
1507 	if (copy_from_user(&config, ifreq->ifr_data, sizeof(config)))
1508 		return -EFAULT;
1509 
1510 	if (config.flags)
1511 		return -EINVAL;
1512 
1513 	mac_tscr = 0;
1514 
1515 	switch (config.tx_type) {
1516 	case HWTSTAMP_TX_OFF:
1517 		break;
1518 
1519 	case HWTSTAMP_TX_ON:
1520 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1521 		break;
1522 
1523 	default:
1524 		return -ERANGE;
1525 	}
1526 
1527 	switch (config.rx_filter) {
1528 	case HWTSTAMP_FILTER_NONE:
1529 		break;
1530 
1531 	case HWTSTAMP_FILTER_NTP_ALL:
1532 	case HWTSTAMP_FILTER_ALL:
1533 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 1);
1534 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1535 		break;
1536 
1537 	/* PTP v2, UDP, any kind of event packet */
1538 	case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1539 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1540 		fallthrough;	/* to PTP v1, UDP, any kind of event packet */
1541 	case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1542 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1543 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1544 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
1545 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1546 		break;
1547 
1548 	/* PTP v2, UDP, Sync packet */
1549 	case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1550 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1551 		fallthrough;	/* to PTP v1, UDP, Sync packet */
1552 	case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1553 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1554 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1555 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1556 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1557 		break;
1558 
1559 	/* PTP v2, UDP, Delay_req packet */
1560 	case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1561 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1562 		fallthrough;	/* to PTP v1, UDP, Delay_req packet */
1563 	case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1564 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1565 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1566 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1567 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
1568 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1569 		break;
1570 
1571 	/* 802.AS1, Ethernet, any kind of event packet */
1572 	case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1573 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
1574 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
1575 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1576 		break;
1577 
1578 	/* 802.AS1, Ethernet, Sync packet */
1579 	case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1580 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
1581 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1582 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1583 		break;
1584 
1585 	/* 802.AS1, Ethernet, Delay_req packet */
1586 	case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1587 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
1588 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
1589 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1590 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1591 		break;
1592 
1593 	/* PTP v2/802.AS1, any layer, any kind of event packet */
1594 	case HWTSTAMP_FILTER_PTP_V2_EVENT:
1595 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1596 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
1597 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1598 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1599 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
1600 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1601 		break;
1602 
1603 	/* PTP v2/802.AS1, any layer, Sync packet */
1604 	case HWTSTAMP_FILTER_PTP_V2_SYNC:
1605 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1606 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
1607 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1608 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1609 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1610 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1611 		break;
1612 
1613 	/* PTP v2/802.AS1, any layer, Delay_req packet */
1614 	case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1615 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1616 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
1617 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1618 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1619 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
1620 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1621 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1622 		break;
1623 
1624 	default:
1625 		return -ERANGE;
1626 	}
1627 
1628 	pdata->hw_if.config_tstamp(pdata, mac_tscr);
1629 
1630 	memcpy(&pdata->tstamp_config, &config, sizeof(config));
1631 
1632 	return 0;
1633 }
1634 
1635 static void xgbe_prep_tx_tstamp(struct xgbe_prv_data *pdata,
1636 				struct sk_buff *skb,
1637 				struct xgbe_packet_data *packet)
1638 {
1639 	unsigned long flags;
1640 
1641 	if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP)) {
1642 		spin_lock_irqsave(&pdata->tstamp_lock, flags);
1643 		if (pdata->tx_tstamp_skb) {
1644 			/* Another timestamp in progress, ignore this one */
1645 			XGMAC_SET_BITS(packet->attributes,
1646 				       TX_PACKET_ATTRIBUTES, PTP, 0);
1647 		} else {
1648 			pdata->tx_tstamp_skb = skb_get(skb);
1649 			skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1650 		}
1651 		spin_unlock_irqrestore(&pdata->tstamp_lock, flags);
1652 	}
1653 
1654 	skb_tx_timestamp(skb);
1655 }
1656 
1657 static void xgbe_prep_vlan(struct sk_buff *skb, struct xgbe_packet_data *packet)
1658 {
1659 	if (skb_vlan_tag_present(skb))
1660 		packet->vlan_ctag = skb_vlan_tag_get(skb);
1661 }
1662 
1663 static int xgbe_prep_tso(struct sk_buff *skb, struct xgbe_packet_data *packet)
1664 {
1665 	int ret;
1666 
1667 	if (!XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1668 			    TSO_ENABLE))
1669 		return 0;
1670 
1671 	ret = skb_cow_head(skb, 0);
1672 	if (ret)
1673 		return ret;
1674 
1675 	if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, VXLAN)) {
1676 		packet->header_len = skb_inner_transport_offset(skb) +
1677 				     inner_tcp_hdrlen(skb);
1678 		packet->tcp_header_len = inner_tcp_hdrlen(skb);
1679 	} else {
1680 		packet->header_len = skb_transport_offset(skb) +
1681 				     tcp_hdrlen(skb);
1682 		packet->tcp_header_len = tcp_hdrlen(skb);
1683 	}
1684 	packet->tcp_payload_len = skb->len - packet->header_len;
1685 	packet->mss = skb_shinfo(skb)->gso_size;
1686 
1687 	DBGPR("  packet->header_len=%u\n", packet->header_len);
1688 	DBGPR("  packet->tcp_header_len=%u, packet->tcp_payload_len=%u\n",
1689 	      packet->tcp_header_len, packet->tcp_payload_len);
1690 	DBGPR("  packet->mss=%u\n", packet->mss);
1691 
1692 	/* Update the number of packets that will ultimately be transmitted
1693 	 * along with the extra bytes for each extra packet
1694 	 */
1695 	packet->tx_packets = skb_shinfo(skb)->gso_segs;
1696 	packet->tx_bytes += (packet->tx_packets - 1) * packet->header_len;
1697 
1698 	return 0;
1699 }
1700 
1701 static bool xgbe_is_vxlan(struct sk_buff *skb)
1702 {
1703 	if (!skb->encapsulation)
1704 		return false;
1705 
1706 	if (skb->ip_summed != CHECKSUM_PARTIAL)
1707 		return false;
1708 
1709 	switch (skb->protocol) {
1710 	case htons(ETH_P_IP):
1711 		if (ip_hdr(skb)->protocol != IPPROTO_UDP)
1712 			return false;
1713 		break;
1714 
1715 	case htons(ETH_P_IPV6):
1716 		if (ipv6_hdr(skb)->nexthdr != IPPROTO_UDP)
1717 			return false;
1718 		break;
1719 
1720 	default:
1721 		return false;
1722 	}
1723 
1724 	if (skb->inner_protocol_type != ENCAP_TYPE_ETHER ||
1725 	    skb->inner_protocol != htons(ETH_P_TEB) ||
1726 	    (skb_inner_mac_header(skb) - skb_transport_header(skb) !=
1727 	     sizeof(struct udphdr) + sizeof(struct vxlanhdr)))
1728 		return false;
1729 
1730 	return true;
1731 }
1732 
1733 static int xgbe_is_tso(struct sk_buff *skb)
1734 {
1735 	if (skb->ip_summed != CHECKSUM_PARTIAL)
1736 		return 0;
1737 
1738 	if (!skb_is_gso(skb))
1739 		return 0;
1740 
1741 	DBGPR("  TSO packet to be processed\n");
1742 
1743 	return 1;
1744 }
1745 
1746 static void xgbe_packet_info(struct xgbe_prv_data *pdata,
1747 			     struct xgbe_ring *ring, struct sk_buff *skb,
1748 			     struct xgbe_packet_data *packet)
1749 {
1750 	skb_frag_t *frag;
1751 	unsigned int context_desc;
1752 	unsigned int len;
1753 	unsigned int i;
1754 
1755 	packet->skb = skb;
1756 
1757 	context_desc = 0;
1758 	packet->rdesc_count = 0;
1759 
1760 	packet->tx_packets = 1;
1761 	packet->tx_bytes = skb->len;
1762 
1763 	if (xgbe_is_tso(skb)) {
1764 		/* TSO requires an extra descriptor if mss is different */
1765 		if (skb_shinfo(skb)->gso_size != ring->tx.cur_mss) {
1766 			context_desc = 1;
1767 			packet->rdesc_count++;
1768 		}
1769 
1770 		/* TSO requires an extra descriptor for TSO header */
1771 		packet->rdesc_count++;
1772 
1773 		XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1774 			       TSO_ENABLE, 1);
1775 		XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1776 			       CSUM_ENABLE, 1);
1777 	} else if (skb->ip_summed == CHECKSUM_PARTIAL)
1778 		XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1779 			       CSUM_ENABLE, 1);
1780 
1781 	if (xgbe_is_vxlan(skb))
1782 		XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1783 			       VXLAN, 1);
1784 
1785 	if (skb_vlan_tag_present(skb)) {
1786 		/* VLAN requires an extra descriptor if tag is different */
1787 		if (skb_vlan_tag_get(skb) != ring->tx.cur_vlan_ctag)
1788 			/* We can share with the TSO context descriptor */
1789 			if (!context_desc) {
1790 				context_desc = 1;
1791 				packet->rdesc_count++;
1792 			}
1793 
1794 		XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1795 			       VLAN_CTAG, 1);
1796 	}
1797 
1798 	if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
1799 	    (pdata->tstamp_config.tx_type == HWTSTAMP_TX_ON))
1800 		XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1801 			       PTP, 1);
1802 
1803 	for (len = skb_headlen(skb); len;) {
1804 		packet->rdesc_count++;
1805 		len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE);
1806 	}
1807 
1808 	for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1809 		frag = &skb_shinfo(skb)->frags[i];
1810 		for (len = skb_frag_size(frag); len; ) {
1811 			packet->rdesc_count++;
1812 			len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE);
1813 		}
1814 	}
1815 }
1816 
1817 static int xgbe_open(struct net_device *netdev)
1818 {
1819 	struct xgbe_prv_data *pdata = netdev_priv(netdev);
1820 	int ret;
1821 
1822 	/* Create the various names based on netdev name */
1823 	snprintf(pdata->an_name, sizeof(pdata->an_name) - 1, "%s-pcs",
1824 		 netdev_name(netdev));
1825 
1826 	snprintf(pdata->ecc_name, sizeof(pdata->ecc_name) - 1, "%s-ecc",
1827 		 netdev_name(netdev));
1828 
1829 	snprintf(pdata->i2c_name, sizeof(pdata->i2c_name) - 1, "%s-i2c",
1830 		 netdev_name(netdev));
1831 
1832 	/* Create workqueues */
1833 	pdata->dev_workqueue =
1834 		create_singlethread_workqueue(netdev_name(netdev));
1835 	if (!pdata->dev_workqueue) {
1836 		netdev_err(netdev, "device workqueue creation failed\n");
1837 		return -ENOMEM;
1838 	}
1839 
1840 	pdata->an_workqueue =
1841 		create_singlethread_workqueue(pdata->an_name);
1842 	if (!pdata->an_workqueue) {
1843 		netdev_err(netdev, "phy workqueue creation failed\n");
1844 		ret = -ENOMEM;
1845 		goto err_dev_wq;
1846 	}
1847 
1848 	/* Reset the phy settings */
1849 	ret = xgbe_phy_reset(pdata);
1850 	if (ret)
1851 		goto err_an_wq;
1852 
1853 	/* Enable the clocks */
1854 	ret = clk_prepare_enable(pdata->sysclk);
1855 	if (ret) {
1856 		netdev_alert(netdev, "dma clk_prepare_enable failed\n");
1857 		goto err_an_wq;
1858 	}
1859 
1860 	ret = clk_prepare_enable(pdata->ptpclk);
1861 	if (ret) {
1862 		netdev_alert(netdev, "ptp clk_prepare_enable failed\n");
1863 		goto err_sysclk;
1864 	}
1865 
1866 	INIT_WORK(&pdata->service_work, xgbe_service);
1867 	INIT_WORK(&pdata->restart_work, xgbe_restart);
1868 	INIT_WORK(&pdata->stopdev_work, xgbe_stopdev);
1869 	INIT_WORK(&pdata->tx_tstamp_work, xgbe_tx_tstamp);
1870 
1871 	ret = xgbe_alloc_memory(pdata);
1872 	if (ret)
1873 		goto err_ptpclk;
1874 
1875 	ret = xgbe_start(pdata);
1876 	if (ret)
1877 		goto err_mem;
1878 
1879 	clear_bit(XGBE_DOWN, &pdata->dev_state);
1880 
1881 	return 0;
1882 
1883 err_mem:
1884 	xgbe_free_memory(pdata);
1885 
1886 err_ptpclk:
1887 	clk_disable_unprepare(pdata->ptpclk);
1888 
1889 err_sysclk:
1890 	clk_disable_unprepare(pdata->sysclk);
1891 
1892 err_an_wq:
1893 	destroy_workqueue(pdata->an_workqueue);
1894 
1895 err_dev_wq:
1896 	destroy_workqueue(pdata->dev_workqueue);
1897 
1898 	return ret;
1899 }
1900 
1901 static int xgbe_close(struct net_device *netdev)
1902 {
1903 	struct xgbe_prv_data *pdata = netdev_priv(netdev);
1904 
1905 	/* Stop the device */
1906 	xgbe_stop(pdata);
1907 
1908 	xgbe_free_memory(pdata);
1909 
1910 	/* Disable the clocks */
1911 	clk_disable_unprepare(pdata->ptpclk);
1912 	clk_disable_unprepare(pdata->sysclk);
1913 
1914 	flush_workqueue(pdata->an_workqueue);
1915 	destroy_workqueue(pdata->an_workqueue);
1916 
1917 	flush_workqueue(pdata->dev_workqueue);
1918 	destroy_workqueue(pdata->dev_workqueue);
1919 
1920 	set_bit(XGBE_DOWN, &pdata->dev_state);
1921 
1922 	return 0;
1923 }
1924 
1925 static netdev_tx_t xgbe_xmit(struct sk_buff *skb, struct net_device *netdev)
1926 {
1927 	struct xgbe_prv_data *pdata = netdev_priv(netdev);
1928 	struct xgbe_hw_if *hw_if = &pdata->hw_if;
1929 	struct xgbe_desc_if *desc_if = &pdata->desc_if;
1930 	struct xgbe_channel *channel;
1931 	struct xgbe_ring *ring;
1932 	struct xgbe_packet_data *packet;
1933 	struct netdev_queue *txq;
1934 	netdev_tx_t ret;
1935 
1936 	DBGPR("-->xgbe_xmit: skb->len = %d\n", skb->len);
1937 
1938 	channel = pdata->channel[skb->queue_mapping];
1939 	txq = netdev_get_tx_queue(netdev, channel->queue_index);
1940 	ring = channel->tx_ring;
1941 	packet = &ring->packet_data;
1942 
1943 	ret = NETDEV_TX_OK;
1944 
1945 	if (skb->len == 0) {
1946 		netif_err(pdata, tx_err, netdev,
1947 			  "empty skb received from stack\n");
1948 		dev_kfree_skb_any(skb);
1949 		goto tx_netdev_return;
1950 	}
1951 
1952 	/* Calculate preliminary packet info */
1953 	memset(packet, 0, sizeof(*packet));
1954 	xgbe_packet_info(pdata, ring, skb, packet);
1955 
1956 	/* Check that there are enough descriptors available */
1957 	ret = xgbe_maybe_stop_tx_queue(channel, ring, packet->rdesc_count);
1958 	if (ret)
1959 		goto tx_netdev_return;
1960 
1961 	ret = xgbe_prep_tso(skb, packet);
1962 	if (ret) {
1963 		netif_err(pdata, tx_err, netdev,
1964 			  "error processing TSO packet\n");
1965 		dev_kfree_skb_any(skb);
1966 		goto tx_netdev_return;
1967 	}
1968 	xgbe_prep_vlan(skb, packet);
1969 
1970 	if (!desc_if->map_tx_skb(channel, skb)) {
1971 		dev_kfree_skb_any(skb);
1972 		goto tx_netdev_return;
1973 	}
1974 
1975 	xgbe_prep_tx_tstamp(pdata, skb, packet);
1976 
1977 	/* Report on the actual number of bytes (to be) sent */
1978 	netdev_tx_sent_queue(txq, packet->tx_bytes);
1979 
1980 	/* Configure required descriptor fields for transmission */
1981 	hw_if->dev_xmit(channel);
1982 
1983 	if (netif_msg_pktdata(pdata))
1984 		xgbe_print_pkt(netdev, skb, true);
1985 
1986 	/* Stop the queue in advance if there may not be enough descriptors */
1987 	xgbe_maybe_stop_tx_queue(channel, ring, XGBE_TX_MAX_DESCS);
1988 
1989 	ret = NETDEV_TX_OK;
1990 
1991 tx_netdev_return:
1992 	return ret;
1993 }
1994 
1995 static void xgbe_set_rx_mode(struct net_device *netdev)
1996 {
1997 	struct xgbe_prv_data *pdata = netdev_priv(netdev);
1998 	struct xgbe_hw_if *hw_if = &pdata->hw_if;
1999 
2000 	DBGPR("-->xgbe_set_rx_mode\n");
2001 
2002 	hw_if->config_rx_mode(pdata);
2003 
2004 	DBGPR("<--xgbe_set_rx_mode\n");
2005 }
2006 
2007 static int xgbe_set_mac_address(struct net_device *netdev, void *addr)
2008 {
2009 	struct xgbe_prv_data *pdata = netdev_priv(netdev);
2010 	struct xgbe_hw_if *hw_if = &pdata->hw_if;
2011 	struct sockaddr *saddr = addr;
2012 
2013 	DBGPR("-->xgbe_set_mac_address\n");
2014 
2015 	if (!is_valid_ether_addr(saddr->sa_data))
2016 		return -EADDRNOTAVAIL;
2017 
2018 	memcpy(netdev->dev_addr, saddr->sa_data, netdev->addr_len);
2019 
2020 	hw_if->set_mac_address(pdata, netdev->dev_addr);
2021 
2022 	DBGPR("<--xgbe_set_mac_address\n");
2023 
2024 	return 0;
2025 }
2026 
2027 static int xgbe_ioctl(struct net_device *netdev, struct ifreq *ifreq, int cmd)
2028 {
2029 	struct xgbe_prv_data *pdata = netdev_priv(netdev);
2030 	int ret;
2031 
2032 	switch (cmd) {
2033 	case SIOCGHWTSTAMP:
2034 		ret = xgbe_get_hwtstamp_settings(pdata, ifreq);
2035 		break;
2036 
2037 	case SIOCSHWTSTAMP:
2038 		ret = xgbe_set_hwtstamp_settings(pdata, ifreq);
2039 		break;
2040 
2041 	default:
2042 		ret = -EOPNOTSUPP;
2043 	}
2044 
2045 	return ret;
2046 }
2047 
2048 static int xgbe_change_mtu(struct net_device *netdev, int mtu)
2049 {
2050 	struct xgbe_prv_data *pdata = netdev_priv(netdev);
2051 	int ret;
2052 
2053 	DBGPR("-->xgbe_change_mtu\n");
2054 
2055 	ret = xgbe_calc_rx_buf_size(netdev, mtu);
2056 	if (ret < 0)
2057 		return ret;
2058 
2059 	pdata->rx_buf_size = ret;
2060 	netdev->mtu = mtu;
2061 
2062 	xgbe_restart_dev(pdata);
2063 
2064 	DBGPR("<--xgbe_change_mtu\n");
2065 
2066 	return 0;
2067 }
2068 
2069 static void xgbe_tx_timeout(struct net_device *netdev, unsigned int txqueue)
2070 {
2071 	struct xgbe_prv_data *pdata = netdev_priv(netdev);
2072 
2073 	netdev_warn(netdev, "tx timeout, device restarting\n");
2074 	schedule_work(&pdata->restart_work);
2075 }
2076 
2077 static void xgbe_get_stats64(struct net_device *netdev,
2078 			     struct rtnl_link_stats64 *s)
2079 {
2080 	struct xgbe_prv_data *pdata = netdev_priv(netdev);
2081 	struct xgbe_mmc_stats *pstats = &pdata->mmc_stats;
2082 
2083 	DBGPR("-->%s\n", __func__);
2084 
2085 	pdata->hw_if.read_mmc_stats(pdata);
2086 
2087 	s->rx_packets = pstats->rxframecount_gb;
2088 	s->rx_bytes = pstats->rxoctetcount_gb;
2089 	s->rx_errors = pstats->rxframecount_gb -
2090 		       pstats->rxbroadcastframes_g -
2091 		       pstats->rxmulticastframes_g -
2092 		       pstats->rxunicastframes_g;
2093 	s->multicast = pstats->rxmulticastframes_g;
2094 	s->rx_length_errors = pstats->rxlengtherror;
2095 	s->rx_crc_errors = pstats->rxcrcerror;
2096 	s->rx_fifo_errors = pstats->rxfifooverflow;
2097 
2098 	s->tx_packets = pstats->txframecount_gb;
2099 	s->tx_bytes = pstats->txoctetcount_gb;
2100 	s->tx_errors = pstats->txframecount_gb - pstats->txframecount_g;
2101 	s->tx_dropped = netdev->stats.tx_dropped;
2102 
2103 	DBGPR("<--%s\n", __func__);
2104 }
2105 
2106 static int xgbe_vlan_rx_add_vid(struct net_device *netdev, __be16 proto,
2107 				u16 vid)
2108 {
2109 	struct xgbe_prv_data *pdata = netdev_priv(netdev);
2110 	struct xgbe_hw_if *hw_if = &pdata->hw_if;
2111 
2112 	DBGPR("-->%s\n", __func__);
2113 
2114 	set_bit(vid, pdata->active_vlans);
2115 	hw_if->update_vlan_hash_table(pdata);
2116 
2117 	DBGPR("<--%s\n", __func__);
2118 
2119 	return 0;
2120 }
2121 
2122 static int xgbe_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto,
2123 				 u16 vid)
2124 {
2125 	struct xgbe_prv_data *pdata = netdev_priv(netdev);
2126 	struct xgbe_hw_if *hw_if = &pdata->hw_if;
2127 
2128 	DBGPR("-->%s\n", __func__);
2129 
2130 	clear_bit(vid, pdata->active_vlans);
2131 	hw_if->update_vlan_hash_table(pdata);
2132 
2133 	DBGPR("<--%s\n", __func__);
2134 
2135 	return 0;
2136 }
2137 
2138 #ifdef CONFIG_NET_POLL_CONTROLLER
2139 static void xgbe_poll_controller(struct net_device *netdev)
2140 {
2141 	struct xgbe_prv_data *pdata = netdev_priv(netdev);
2142 	struct xgbe_channel *channel;
2143 	unsigned int i;
2144 
2145 	DBGPR("-->xgbe_poll_controller\n");
2146 
2147 	if (pdata->per_channel_irq) {
2148 		for (i = 0; i < pdata->channel_count; i++) {
2149 			channel = pdata->channel[i];
2150 			xgbe_dma_isr(channel->dma_irq, channel);
2151 		}
2152 	} else {
2153 		disable_irq(pdata->dev_irq);
2154 		xgbe_isr(pdata->dev_irq, pdata);
2155 		enable_irq(pdata->dev_irq);
2156 	}
2157 
2158 	DBGPR("<--xgbe_poll_controller\n");
2159 }
2160 #endif /* End CONFIG_NET_POLL_CONTROLLER */
2161 
2162 static int xgbe_setup_tc(struct net_device *netdev, enum tc_setup_type type,
2163 			 void *type_data)
2164 {
2165 	struct xgbe_prv_data *pdata = netdev_priv(netdev);
2166 	struct tc_mqprio_qopt *mqprio = type_data;
2167 	u8 tc;
2168 
2169 	if (type != TC_SETUP_QDISC_MQPRIO)
2170 		return -EOPNOTSUPP;
2171 
2172 	mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
2173 	tc = mqprio->num_tc;
2174 
2175 	if (tc > pdata->hw_feat.tc_cnt)
2176 		return -EINVAL;
2177 
2178 	pdata->num_tcs = tc;
2179 	pdata->hw_if.config_tc(pdata);
2180 
2181 	return 0;
2182 }
2183 
2184 static netdev_features_t xgbe_fix_features(struct net_device *netdev,
2185 					   netdev_features_t features)
2186 {
2187 	struct xgbe_prv_data *pdata = netdev_priv(netdev);
2188 	netdev_features_t vxlan_base;
2189 
2190 	vxlan_base = NETIF_F_GSO_UDP_TUNNEL | NETIF_F_RX_UDP_TUNNEL_PORT;
2191 
2192 	if (!pdata->hw_feat.vxn)
2193 		return features;
2194 
2195 	/* VXLAN CSUM requires VXLAN base */
2196 	if ((features & NETIF_F_GSO_UDP_TUNNEL_CSUM) &&
2197 	    !(features & NETIF_F_GSO_UDP_TUNNEL)) {
2198 		netdev_notice(netdev,
2199 			      "forcing tx udp tunnel support\n");
2200 		features |= NETIF_F_GSO_UDP_TUNNEL;
2201 	}
2202 
2203 	/* Can't do one without doing the other */
2204 	if ((features & vxlan_base) != vxlan_base) {
2205 		netdev_notice(netdev,
2206 			      "forcing both tx and rx udp tunnel support\n");
2207 		features |= vxlan_base;
2208 	}
2209 
2210 	if (features & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)) {
2211 		if (!(features & NETIF_F_GSO_UDP_TUNNEL_CSUM)) {
2212 			netdev_notice(netdev,
2213 				      "forcing tx udp tunnel checksumming on\n");
2214 			features |= NETIF_F_GSO_UDP_TUNNEL_CSUM;
2215 		}
2216 	} else {
2217 		if (features & NETIF_F_GSO_UDP_TUNNEL_CSUM) {
2218 			netdev_notice(netdev,
2219 				      "forcing tx udp tunnel checksumming off\n");
2220 			features &= ~NETIF_F_GSO_UDP_TUNNEL_CSUM;
2221 		}
2222 	}
2223 
2224 	return features;
2225 }
2226 
2227 static int xgbe_set_features(struct net_device *netdev,
2228 			     netdev_features_t features)
2229 {
2230 	struct xgbe_prv_data *pdata = netdev_priv(netdev);
2231 	struct xgbe_hw_if *hw_if = &pdata->hw_if;
2232 	netdev_features_t rxhash, rxcsum, rxvlan, rxvlan_filter;
2233 	int ret = 0;
2234 
2235 	rxhash = pdata->netdev_features & NETIF_F_RXHASH;
2236 	rxcsum = pdata->netdev_features & NETIF_F_RXCSUM;
2237 	rxvlan = pdata->netdev_features & NETIF_F_HW_VLAN_CTAG_RX;
2238 	rxvlan_filter = pdata->netdev_features & NETIF_F_HW_VLAN_CTAG_FILTER;
2239 
2240 	if ((features & NETIF_F_RXHASH) && !rxhash)
2241 		ret = hw_if->enable_rss(pdata);
2242 	else if (!(features & NETIF_F_RXHASH) && rxhash)
2243 		ret = hw_if->disable_rss(pdata);
2244 	if (ret)
2245 		return ret;
2246 
2247 	if ((features & NETIF_F_RXCSUM) && !rxcsum)
2248 		hw_if->enable_rx_csum(pdata);
2249 	else if (!(features & NETIF_F_RXCSUM) && rxcsum)
2250 		hw_if->disable_rx_csum(pdata);
2251 
2252 	if ((features & NETIF_F_HW_VLAN_CTAG_RX) && !rxvlan)
2253 		hw_if->enable_rx_vlan_stripping(pdata);
2254 	else if (!(features & NETIF_F_HW_VLAN_CTAG_RX) && rxvlan)
2255 		hw_if->disable_rx_vlan_stripping(pdata);
2256 
2257 	if ((features & NETIF_F_HW_VLAN_CTAG_FILTER) && !rxvlan_filter)
2258 		hw_if->enable_rx_vlan_filtering(pdata);
2259 	else if (!(features & NETIF_F_HW_VLAN_CTAG_FILTER) && rxvlan_filter)
2260 		hw_if->disable_rx_vlan_filtering(pdata);
2261 
2262 	pdata->netdev_features = features;
2263 
2264 	DBGPR("<--xgbe_set_features\n");
2265 
2266 	return 0;
2267 }
2268 
2269 static netdev_features_t xgbe_features_check(struct sk_buff *skb,
2270 					     struct net_device *netdev,
2271 					     netdev_features_t features)
2272 {
2273 	features = vlan_features_check(skb, features);
2274 	features = vxlan_features_check(skb, features);
2275 
2276 	return features;
2277 }
2278 
2279 static const struct net_device_ops xgbe_netdev_ops = {
2280 	.ndo_open		= xgbe_open,
2281 	.ndo_stop		= xgbe_close,
2282 	.ndo_start_xmit		= xgbe_xmit,
2283 	.ndo_set_rx_mode	= xgbe_set_rx_mode,
2284 	.ndo_set_mac_address	= xgbe_set_mac_address,
2285 	.ndo_validate_addr	= eth_validate_addr,
2286 	.ndo_do_ioctl		= xgbe_ioctl,
2287 	.ndo_change_mtu		= xgbe_change_mtu,
2288 	.ndo_tx_timeout		= xgbe_tx_timeout,
2289 	.ndo_get_stats64	= xgbe_get_stats64,
2290 	.ndo_vlan_rx_add_vid	= xgbe_vlan_rx_add_vid,
2291 	.ndo_vlan_rx_kill_vid	= xgbe_vlan_rx_kill_vid,
2292 #ifdef CONFIG_NET_POLL_CONTROLLER
2293 	.ndo_poll_controller	= xgbe_poll_controller,
2294 #endif
2295 	.ndo_setup_tc		= xgbe_setup_tc,
2296 	.ndo_fix_features	= xgbe_fix_features,
2297 	.ndo_set_features	= xgbe_set_features,
2298 	.ndo_udp_tunnel_add	= udp_tunnel_nic_add_port,
2299 	.ndo_udp_tunnel_del	= udp_tunnel_nic_del_port,
2300 	.ndo_features_check	= xgbe_features_check,
2301 };
2302 
2303 const struct net_device_ops *xgbe_get_netdev_ops(void)
2304 {
2305 	return &xgbe_netdev_ops;
2306 }
2307 
2308 static void xgbe_rx_refresh(struct xgbe_channel *channel)
2309 {
2310 	struct xgbe_prv_data *pdata = channel->pdata;
2311 	struct xgbe_hw_if *hw_if = &pdata->hw_if;
2312 	struct xgbe_desc_if *desc_if = &pdata->desc_if;
2313 	struct xgbe_ring *ring = channel->rx_ring;
2314 	struct xgbe_ring_data *rdata;
2315 
2316 	while (ring->dirty != ring->cur) {
2317 		rdata = XGBE_GET_DESC_DATA(ring, ring->dirty);
2318 
2319 		/* Reset rdata values */
2320 		desc_if->unmap_rdata(pdata, rdata);
2321 
2322 		if (desc_if->map_rx_buffer(pdata, ring, rdata))
2323 			break;
2324 
2325 		hw_if->rx_desc_reset(pdata, rdata, ring->dirty);
2326 
2327 		ring->dirty++;
2328 	}
2329 
2330 	/* Make sure everything is written before the register write */
2331 	wmb();
2332 
2333 	/* Update the Rx Tail Pointer Register with address of
2334 	 * the last cleaned entry */
2335 	rdata = XGBE_GET_DESC_DATA(ring, ring->dirty - 1);
2336 	XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO,
2337 			  lower_32_bits(rdata->rdesc_dma));
2338 }
2339 
2340 static struct sk_buff *xgbe_create_skb(struct xgbe_prv_data *pdata,
2341 				       struct napi_struct *napi,
2342 				       struct xgbe_ring_data *rdata,
2343 				       unsigned int len)
2344 {
2345 	struct sk_buff *skb;
2346 	u8 *packet;
2347 
2348 	skb = napi_alloc_skb(napi, rdata->rx.hdr.dma_len);
2349 	if (!skb)
2350 		return NULL;
2351 
2352 	/* Pull in the header buffer which may contain just the header
2353 	 * or the header plus data
2354 	 */
2355 	dma_sync_single_range_for_cpu(pdata->dev, rdata->rx.hdr.dma_base,
2356 				      rdata->rx.hdr.dma_off,
2357 				      rdata->rx.hdr.dma_len, DMA_FROM_DEVICE);
2358 
2359 	packet = page_address(rdata->rx.hdr.pa.pages) +
2360 		 rdata->rx.hdr.pa.pages_offset;
2361 	skb_copy_to_linear_data(skb, packet, len);
2362 	skb_put(skb, len);
2363 
2364 	return skb;
2365 }
2366 
2367 static unsigned int xgbe_rx_buf1_len(struct xgbe_ring_data *rdata,
2368 				     struct xgbe_packet_data *packet)
2369 {
2370 	/* Always zero if not the first descriptor */
2371 	if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, FIRST))
2372 		return 0;
2373 
2374 	/* First descriptor with split header, return header length */
2375 	if (rdata->rx.hdr_len)
2376 		return rdata->rx.hdr_len;
2377 
2378 	/* First descriptor but not the last descriptor and no split header,
2379 	 * so the full buffer was used
2380 	 */
2381 	if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, LAST))
2382 		return rdata->rx.hdr.dma_len;
2383 
2384 	/* First descriptor and last descriptor and no split header, so
2385 	 * calculate how much of the buffer was used
2386 	 */
2387 	return min_t(unsigned int, rdata->rx.hdr.dma_len, rdata->rx.len);
2388 }
2389 
2390 static unsigned int xgbe_rx_buf2_len(struct xgbe_ring_data *rdata,
2391 				     struct xgbe_packet_data *packet,
2392 				     unsigned int len)
2393 {
2394 	/* Always the full buffer if not the last descriptor */
2395 	if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, LAST))
2396 		return rdata->rx.buf.dma_len;
2397 
2398 	/* Last descriptor so calculate how much of the buffer was used
2399 	 * for the last bit of data
2400 	 */
2401 	return rdata->rx.len - len;
2402 }
2403 
2404 static int xgbe_tx_poll(struct xgbe_channel *channel)
2405 {
2406 	struct xgbe_prv_data *pdata = channel->pdata;
2407 	struct xgbe_hw_if *hw_if = &pdata->hw_if;
2408 	struct xgbe_desc_if *desc_if = &pdata->desc_if;
2409 	struct xgbe_ring *ring = channel->tx_ring;
2410 	struct xgbe_ring_data *rdata;
2411 	struct xgbe_ring_desc *rdesc;
2412 	struct net_device *netdev = pdata->netdev;
2413 	struct netdev_queue *txq;
2414 	int processed = 0;
2415 	unsigned int tx_packets = 0, tx_bytes = 0;
2416 	unsigned int cur;
2417 
2418 	DBGPR("-->xgbe_tx_poll\n");
2419 
2420 	/* Nothing to do if there isn't a Tx ring for this channel */
2421 	if (!ring)
2422 		return 0;
2423 
2424 	cur = ring->cur;
2425 
2426 	/* Be sure we get ring->cur before accessing descriptor data */
2427 	smp_rmb();
2428 
2429 	txq = netdev_get_tx_queue(netdev, channel->queue_index);
2430 
2431 	while ((processed < XGBE_TX_DESC_MAX_PROC) &&
2432 	       (ring->dirty != cur)) {
2433 		rdata = XGBE_GET_DESC_DATA(ring, ring->dirty);
2434 		rdesc = rdata->rdesc;
2435 
2436 		if (!hw_if->tx_complete(rdesc))
2437 			break;
2438 
2439 		/* Make sure descriptor fields are read after reading the OWN
2440 		 * bit */
2441 		dma_rmb();
2442 
2443 		if (netif_msg_tx_done(pdata))
2444 			xgbe_dump_tx_desc(pdata, ring, ring->dirty, 1, 0);
2445 
2446 		if (hw_if->is_last_desc(rdesc)) {
2447 			tx_packets += rdata->tx.packets;
2448 			tx_bytes += rdata->tx.bytes;
2449 		}
2450 
2451 		/* Free the SKB and reset the descriptor for re-use */
2452 		desc_if->unmap_rdata(pdata, rdata);
2453 		hw_if->tx_desc_reset(rdata);
2454 
2455 		processed++;
2456 		ring->dirty++;
2457 	}
2458 
2459 	if (!processed)
2460 		return 0;
2461 
2462 	netdev_tx_completed_queue(txq, tx_packets, tx_bytes);
2463 
2464 	if ((ring->tx.queue_stopped == 1) &&
2465 	    (xgbe_tx_avail_desc(ring) > XGBE_TX_DESC_MIN_FREE)) {
2466 		ring->tx.queue_stopped = 0;
2467 		netif_tx_wake_queue(txq);
2468 	}
2469 
2470 	DBGPR("<--xgbe_tx_poll: processed=%d\n", processed);
2471 
2472 	return processed;
2473 }
2474 
2475 static int xgbe_rx_poll(struct xgbe_channel *channel, int budget)
2476 {
2477 	struct xgbe_prv_data *pdata = channel->pdata;
2478 	struct xgbe_hw_if *hw_if = &pdata->hw_if;
2479 	struct xgbe_ring *ring = channel->rx_ring;
2480 	struct xgbe_ring_data *rdata;
2481 	struct xgbe_packet_data *packet;
2482 	struct net_device *netdev = pdata->netdev;
2483 	struct napi_struct *napi;
2484 	struct sk_buff *skb;
2485 	struct skb_shared_hwtstamps *hwtstamps;
2486 	unsigned int last, error, context_next, context;
2487 	unsigned int len, buf1_len, buf2_len, max_len;
2488 	unsigned int received = 0;
2489 	int packet_count = 0;
2490 
2491 	DBGPR("-->xgbe_rx_poll: budget=%d\n", budget);
2492 
2493 	/* Nothing to do if there isn't a Rx ring for this channel */
2494 	if (!ring)
2495 		return 0;
2496 
2497 	last = 0;
2498 	context_next = 0;
2499 
2500 	napi = (pdata->per_channel_irq) ? &channel->napi : &pdata->napi;
2501 
2502 	rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
2503 	packet = &ring->packet_data;
2504 	while (packet_count < budget) {
2505 		DBGPR("  cur = %d\n", ring->cur);
2506 
2507 		/* First time in loop see if we need to restore state */
2508 		if (!received && rdata->state_saved) {
2509 			skb = rdata->state.skb;
2510 			error = rdata->state.error;
2511 			len = rdata->state.len;
2512 		} else {
2513 			memset(packet, 0, sizeof(*packet));
2514 			skb = NULL;
2515 			error = 0;
2516 			len = 0;
2517 		}
2518 
2519 read_again:
2520 		rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
2521 
2522 		if (xgbe_rx_dirty_desc(ring) > (XGBE_RX_DESC_CNT >> 3))
2523 			xgbe_rx_refresh(channel);
2524 
2525 		if (hw_if->dev_read(channel))
2526 			break;
2527 
2528 		received++;
2529 		ring->cur++;
2530 
2531 		last = XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
2532 				      LAST);
2533 		context_next = XGMAC_GET_BITS(packet->attributes,
2534 					      RX_PACKET_ATTRIBUTES,
2535 					      CONTEXT_NEXT);
2536 		context = XGMAC_GET_BITS(packet->attributes,
2537 					 RX_PACKET_ATTRIBUTES,
2538 					 CONTEXT);
2539 
2540 		/* Earlier error, just drain the remaining data */
2541 		if ((!last || context_next) && error)
2542 			goto read_again;
2543 
2544 		if (error || packet->errors) {
2545 			if (packet->errors)
2546 				netif_err(pdata, rx_err, netdev,
2547 					  "error in received packet\n");
2548 			dev_kfree_skb(skb);
2549 			goto next_packet;
2550 		}
2551 
2552 		if (!context) {
2553 			/* Get the data length in the descriptor buffers */
2554 			buf1_len = xgbe_rx_buf1_len(rdata, packet);
2555 			len += buf1_len;
2556 			buf2_len = xgbe_rx_buf2_len(rdata, packet, len);
2557 			len += buf2_len;
2558 
2559 			if (!skb) {
2560 				skb = xgbe_create_skb(pdata, napi, rdata,
2561 						      buf1_len);
2562 				if (!skb) {
2563 					error = 1;
2564 					goto skip_data;
2565 				}
2566 			}
2567 
2568 			if (buf2_len) {
2569 				dma_sync_single_range_for_cpu(pdata->dev,
2570 							rdata->rx.buf.dma_base,
2571 							rdata->rx.buf.dma_off,
2572 							rdata->rx.buf.dma_len,
2573 							DMA_FROM_DEVICE);
2574 
2575 				skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
2576 						rdata->rx.buf.pa.pages,
2577 						rdata->rx.buf.pa.pages_offset,
2578 						buf2_len,
2579 						rdata->rx.buf.dma_len);
2580 				rdata->rx.buf.pa.pages = NULL;
2581 			}
2582 		}
2583 
2584 skip_data:
2585 		if (!last || context_next)
2586 			goto read_again;
2587 
2588 		if (!skb)
2589 			goto next_packet;
2590 
2591 		/* Be sure we don't exceed the configured MTU */
2592 		max_len = netdev->mtu + ETH_HLEN;
2593 		if (!(netdev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
2594 		    (skb->protocol == htons(ETH_P_8021Q)))
2595 			max_len += VLAN_HLEN;
2596 
2597 		if (skb->len > max_len) {
2598 			netif_err(pdata, rx_err, netdev,
2599 				  "packet length exceeds configured MTU\n");
2600 			dev_kfree_skb(skb);
2601 			goto next_packet;
2602 		}
2603 
2604 		if (netif_msg_pktdata(pdata))
2605 			xgbe_print_pkt(netdev, skb, false);
2606 
2607 		skb_checksum_none_assert(skb);
2608 		if (XGMAC_GET_BITS(packet->attributes,
2609 				   RX_PACKET_ATTRIBUTES, CSUM_DONE))
2610 			skb->ip_summed = CHECKSUM_UNNECESSARY;
2611 
2612 		if (XGMAC_GET_BITS(packet->attributes,
2613 				   RX_PACKET_ATTRIBUTES, TNP)) {
2614 			skb->encapsulation = 1;
2615 
2616 			if (XGMAC_GET_BITS(packet->attributes,
2617 					   RX_PACKET_ATTRIBUTES, TNPCSUM_DONE))
2618 				skb->csum_level = 1;
2619 		}
2620 
2621 		if (XGMAC_GET_BITS(packet->attributes,
2622 				   RX_PACKET_ATTRIBUTES, VLAN_CTAG))
2623 			__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
2624 					       packet->vlan_ctag);
2625 
2626 		if (XGMAC_GET_BITS(packet->attributes,
2627 				   RX_PACKET_ATTRIBUTES, RX_TSTAMP)) {
2628 			u64 nsec;
2629 
2630 			nsec = timecounter_cyc2time(&pdata->tstamp_tc,
2631 						    packet->rx_tstamp);
2632 			hwtstamps = skb_hwtstamps(skb);
2633 			hwtstamps->hwtstamp = ns_to_ktime(nsec);
2634 		}
2635 
2636 		if (XGMAC_GET_BITS(packet->attributes,
2637 				   RX_PACKET_ATTRIBUTES, RSS_HASH))
2638 			skb_set_hash(skb, packet->rss_hash,
2639 				     packet->rss_hash_type);
2640 
2641 		skb->dev = netdev;
2642 		skb->protocol = eth_type_trans(skb, netdev);
2643 		skb_record_rx_queue(skb, channel->queue_index);
2644 
2645 		napi_gro_receive(napi, skb);
2646 
2647 next_packet:
2648 		packet_count++;
2649 	}
2650 
2651 	/* Check if we need to save state before leaving */
2652 	if (received && (!last || context_next)) {
2653 		rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
2654 		rdata->state_saved = 1;
2655 		rdata->state.skb = skb;
2656 		rdata->state.len = len;
2657 		rdata->state.error = error;
2658 	}
2659 
2660 	DBGPR("<--xgbe_rx_poll: packet_count = %d\n", packet_count);
2661 
2662 	return packet_count;
2663 }
2664 
2665 static int xgbe_one_poll(struct napi_struct *napi, int budget)
2666 {
2667 	struct xgbe_channel *channel = container_of(napi, struct xgbe_channel,
2668 						    napi);
2669 	struct xgbe_prv_data *pdata = channel->pdata;
2670 	int processed = 0;
2671 
2672 	DBGPR("-->xgbe_one_poll: budget=%d\n", budget);
2673 
2674 	/* Cleanup Tx ring first */
2675 	xgbe_tx_poll(channel);
2676 
2677 	/* Process Rx ring next */
2678 	processed = xgbe_rx_poll(channel, budget);
2679 
2680 	/* If we processed everything, we are done */
2681 	if ((processed < budget) && napi_complete_done(napi, processed)) {
2682 		/* Enable Tx and Rx interrupts */
2683 		if (pdata->channel_irq_mode)
2684 			xgbe_enable_rx_tx_int(pdata, channel);
2685 		else
2686 			enable_irq(channel->dma_irq);
2687 	}
2688 
2689 	DBGPR("<--xgbe_one_poll: received = %d\n", processed);
2690 
2691 	return processed;
2692 }
2693 
2694 static int xgbe_all_poll(struct napi_struct *napi, int budget)
2695 {
2696 	struct xgbe_prv_data *pdata = container_of(napi, struct xgbe_prv_data,
2697 						   napi);
2698 	struct xgbe_channel *channel;
2699 	int ring_budget;
2700 	int processed, last_processed;
2701 	unsigned int i;
2702 
2703 	DBGPR("-->xgbe_all_poll: budget=%d\n", budget);
2704 
2705 	processed = 0;
2706 	ring_budget = budget / pdata->rx_ring_count;
2707 	do {
2708 		last_processed = processed;
2709 
2710 		for (i = 0; i < pdata->channel_count; i++) {
2711 			channel = pdata->channel[i];
2712 
2713 			/* Cleanup Tx ring first */
2714 			xgbe_tx_poll(channel);
2715 
2716 			/* Process Rx ring next */
2717 			if (ring_budget > (budget - processed))
2718 				ring_budget = budget - processed;
2719 			processed += xgbe_rx_poll(channel, ring_budget);
2720 		}
2721 	} while ((processed < budget) && (processed != last_processed));
2722 
2723 	/* If we processed everything, we are done */
2724 	if ((processed < budget) && napi_complete_done(napi, processed)) {
2725 		/* Enable Tx and Rx interrupts */
2726 		xgbe_enable_rx_tx_ints(pdata);
2727 	}
2728 
2729 	DBGPR("<--xgbe_all_poll: received = %d\n", processed);
2730 
2731 	return processed;
2732 }
2733 
2734 void xgbe_dump_tx_desc(struct xgbe_prv_data *pdata, struct xgbe_ring *ring,
2735 		       unsigned int idx, unsigned int count, unsigned int flag)
2736 {
2737 	struct xgbe_ring_data *rdata;
2738 	struct xgbe_ring_desc *rdesc;
2739 
2740 	while (count--) {
2741 		rdata = XGBE_GET_DESC_DATA(ring, idx);
2742 		rdesc = rdata->rdesc;
2743 		netdev_dbg(pdata->netdev,
2744 			   "TX_NORMAL_DESC[%d %s] = %08x:%08x:%08x:%08x\n", idx,
2745 			   (flag == 1) ? "QUEUED FOR TX" : "TX BY DEVICE",
2746 			   le32_to_cpu(rdesc->desc0),
2747 			   le32_to_cpu(rdesc->desc1),
2748 			   le32_to_cpu(rdesc->desc2),
2749 			   le32_to_cpu(rdesc->desc3));
2750 		idx++;
2751 	}
2752 }
2753 
2754 void xgbe_dump_rx_desc(struct xgbe_prv_data *pdata, struct xgbe_ring *ring,
2755 		       unsigned int idx)
2756 {
2757 	struct xgbe_ring_data *rdata;
2758 	struct xgbe_ring_desc *rdesc;
2759 
2760 	rdata = XGBE_GET_DESC_DATA(ring, idx);
2761 	rdesc = rdata->rdesc;
2762 	netdev_dbg(pdata->netdev,
2763 		   "RX_NORMAL_DESC[%d RX BY DEVICE] = %08x:%08x:%08x:%08x\n",
2764 		   idx, le32_to_cpu(rdesc->desc0), le32_to_cpu(rdesc->desc1),
2765 		   le32_to_cpu(rdesc->desc2), le32_to_cpu(rdesc->desc3));
2766 }
2767 
2768 void xgbe_print_pkt(struct net_device *netdev, struct sk_buff *skb, bool tx_rx)
2769 {
2770 	struct ethhdr *eth = (struct ethhdr *)skb->data;
2771 	unsigned char buffer[128];
2772 	unsigned int i;
2773 
2774 	netdev_dbg(netdev, "\n************** SKB dump ****************\n");
2775 
2776 	netdev_dbg(netdev, "%s packet of %d bytes\n",
2777 		   (tx_rx ? "TX" : "RX"), skb->len);
2778 
2779 	netdev_dbg(netdev, "Dst MAC addr: %pM\n", eth->h_dest);
2780 	netdev_dbg(netdev, "Src MAC addr: %pM\n", eth->h_source);
2781 	netdev_dbg(netdev, "Protocol: %#06hx\n", ntohs(eth->h_proto));
2782 
2783 	for (i = 0; i < skb->len; i += 32) {
2784 		unsigned int len = min(skb->len - i, 32U);
2785 
2786 		hex_dump_to_buffer(&skb->data[i], len, 32, 1,
2787 				   buffer, sizeof(buffer), false);
2788 		netdev_dbg(netdev, "  %#06x: %s\n", i, buffer);
2789 	}
2790 
2791 	netdev_dbg(netdev, "\n************** SKB dump ****************\n");
2792 }
2793