1 /*
2  * AMD 10Gb Ethernet driver
3  *
4  * This file is available to you under your choice of the following two
5  * licenses:
6  *
7  * License 1: GPLv2
8  *
9  * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
10  *
11  * This file is free software; you may copy, redistribute and/or modify
12  * it under the terms of the GNU General Public License as published by
13  * the Free Software Foundation, either version 2 of the License, or (at
14  * your option) any later version.
15  *
16  * This file is distributed in the hope that it will be useful, but
17  * WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19  * General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
23  *
24  * This file incorporates work covered by the following copyright and
25  * permission notice:
26  *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
27  *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28  *     Inc. unless otherwise expressly agreed to in writing between Synopsys
29  *     and you.
30  *
31  *     The Software IS NOT an item of Licensed Software or Licensed Product
32  *     under any End User Software License Agreement or Agreement for Licensed
33  *     Product with Synopsys or any supplement thereto.  Permission is hereby
34  *     granted, free of charge, to any person obtaining a copy of this software
35  *     annotated with this license and the Software, to deal in the Software
36  *     without restriction, including without limitation the rights to use,
37  *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38  *     of the Software, and to permit persons to whom the Software is furnished
39  *     to do so, subject to the following conditions:
40  *
41  *     The above copyright notice and this permission notice shall be included
42  *     in all copies or substantial portions of the Software.
43  *
44  *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45  *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46  *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47  *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48  *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49  *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50  *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51  *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52  *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53  *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54  *     THE POSSIBILITY OF SUCH DAMAGE.
55  *
56  *
57  * License 2: Modified BSD
58  *
59  * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
60  * All rights reserved.
61  *
62  * Redistribution and use in source and binary forms, with or without
63  * modification, are permitted provided that the following conditions are met:
64  *     * Redistributions of source code must retain the above copyright
65  *       notice, this list of conditions and the following disclaimer.
66  *     * Redistributions in binary form must reproduce the above copyright
67  *       notice, this list of conditions and the following disclaimer in the
68  *       documentation and/or other materials provided with the distribution.
69  *     * Neither the name of Advanced Micro Devices, Inc. nor the
70  *       names of its contributors may be used to endorse or promote products
71  *       derived from this software without specific prior written permission.
72  *
73  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76  * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
83  *
84  * This file incorporates work covered by the following copyright and
85  * permission notice:
86  *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
87  *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88  *     Inc. unless otherwise expressly agreed to in writing between Synopsys
89  *     and you.
90  *
91  *     The Software IS NOT an item of Licensed Software or Licensed Product
92  *     under any End User Software License Agreement or Agreement for Licensed
93  *     Product with Synopsys or any supplement thereto.  Permission is hereby
94  *     granted, free of charge, to any person obtaining a copy of this software
95  *     annotated with this license and the Software, to deal in the Software
96  *     without restriction, including without limitation the rights to use,
97  *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98  *     of the Software, and to permit persons to whom the Software is furnished
99  *     to do so, subject to the following conditions:
100  *
101  *     The above copyright notice and this permission notice shall be included
102  *     in all copies or substantial portions of the Software.
103  *
104  *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105  *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106  *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107  *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108  *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109  *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110  *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111  *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112  *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113  *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114  *     THE POSSIBILITY OF SUCH DAMAGE.
115  */
116 
117 #include <linux/module.h>
118 #include <linux/spinlock.h>
119 #include <linux/tcp.h>
120 #include <linux/if_vlan.h>
121 #include <linux/interrupt.h>
122 #include <linux/clk.h>
123 #include <linux/if_ether.h>
124 #include <linux/net_tstamp.h>
125 #include <linux/phy.h>
126 #include <net/vxlan.h>
127 
128 #include "xgbe.h"
129 #include "xgbe-common.h"
130 
131 static unsigned int ecc_sec_info_threshold = 10;
132 static unsigned int ecc_sec_warn_threshold = 10000;
133 static unsigned int ecc_sec_period = 600;
134 static unsigned int ecc_ded_threshold = 2;
135 static unsigned int ecc_ded_period = 600;
136 
137 #ifdef CONFIG_AMD_XGBE_HAVE_ECC
138 /* Only expose the ECC parameters if supported */
139 module_param(ecc_sec_info_threshold, uint, 0644);
140 MODULE_PARM_DESC(ecc_sec_info_threshold,
141 		 " ECC corrected error informational threshold setting");
142 
143 module_param(ecc_sec_warn_threshold, uint, 0644);
144 MODULE_PARM_DESC(ecc_sec_warn_threshold,
145 		 " ECC corrected error warning threshold setting");
146 
147 module_param(ecc_sec_period, uint, 0644);
148 MODULE_PARM_DESC(ecc_sec_period, " ECC corrected error period (in seconds)");
149 
150 module_param(ecc_ded_threshold, uint, 0644);
151 MODULE_PARM_DESC(ecc_ded_threshold, " ECC detected error threshold setting");
152 
153 module_param(ecc_ded_period, uint, 0644);
154 MODULE_PARM_DESC(ecc_ded_period, " ECC detected error period (in seconds)");
155 #endif
156 
157 static int xgbe_one_poll(struct napi_struct *, int);
158 static int xgbe_all_poll(struct napi_struct *, int);
159 static void xgbe_stop(struct xgbe_prv_data *);
160 
161 static void *xgbe_alloc_node(size_t size, int node)
162 {
163 	void *mem;
164 
165 	mem = kzalloc_node(size, GFP_KERNEL, node);
166 	if (!mem)
167 		mem = kzalloc(size, GFP_KERNEL);
168 
169 	return mem;
170 }
171 
172 static void xgbe_free_channels(struct xgbe_prv_data *pdata)
173 {
174 	unsigned int i;
175 
176 	for (i = 0; i < ARRAY_SIZE(pdata->channel); i++) {
177 		if (!pdata->channel[i])
178 			continue;
179 
180 		kfree(pdata->channel[i]->rx_ring);
181 		kfree(pdata->channel[i]->tx_ring);
182 		kfree(pdata->channel[i]);
183 
184 		pdata->channel[i] = NULL;
185 	}
186 
187 	pdata->channel_count = 0;
188 }
189 
190 static int xgbe_alloc_channels(struct xgbe_prv_data *pdata)
191 {
192 	struct xgbe_channel *channel;
193 	struct xgbe_ring *ring;
194 	unsigned int count, i;
195 	unsigned int cpu;
196 	int node;
197 
198 	count = max_t(unsigned int, pdata->tx_ring_count, pdata->rx_ring_count);
199 	for (i = 0; i < count; i++) {
200 		/* Attempt to use a CPU on the node the device is on */
201 		cpu = cpumask_local_spread(i, dev_to_node(pdata->dev));
202 
203 		/* Set the allocation node based on the returned CPU */
204 		node = cpu_to_node(cpu);
205 
206 		channel = xgbe_alloc_node(sizeof(*channel), node);
207 		if (!channel)
208 			goto err_mem;
209 		pdata->channel[i] = channel;
210 
211 		snprintf(channel->name, sizeof(channel->name), "channel-%u", i);
212 		channel->pdata = pdata;
213 		channel->queue_index = i;
214 		channel->dma_regs = pdata->xgmac_regs + DMA_CH_BASE +
215 				    (DMA_CH_INC * i);
216 		channel->node = node;
217 		cpumask_set_cpu(cpu, &channel->affinity_mask);
218 
219 		if (pdata->per_channel_irq)
220 			channel->dma_irq = pdata->channel_irq[i];
221 
222 		if (i < pdata->tx_ring_count) {
223 			ring = xgbe_alloc_node(sizeof(*ring), node);
224 			if (!ring)
225 				goto err_mem;
226 
227 			spin_lock_init(&ring->lock);
228 			ring->node = node;
229 
230 			channel->tx_ring = ring;
231 		}
232 
233 		if (i < pdata->rx_ring_count) {
234 			ring = xgbe_alloc_node(sizeof(*ring), node);
235 			if (!ring)
236 				goto err_mem;
237 
238 			spin_lock_init(&ring->lock);
239 			ring->node = node;
240 
241 			channel->rx_ring = ring;
242 		}
243 
244 		netif_dbg(pdata, drv, pdata->netdev,
245 			  "%s: cpu=%u, node=%d\n", channel->name, cpu, node);
246 
247 		netif_dbg(pdata, drv, pdata->netdev,
248 			  "%s: dma_regs=%p, dma_irq=%d, tx=%p, rx=%p\n",
249 			  channel->name, channel->dma_regs, channel->dma_irq,
250 			  channel->tx_ring, channel->rx_ring);
251 	}
252 
253 	pdata->channel_count = count;
254 
255 	return 0;
256 
257 err_mem:
258 	xgbe_free_channels(pdata);
259 
260 	return -ENOMEM;
261 }
262 
263 static inline unsigned int xgbe_tx_avail_desc(struct xgbe_ring *ring)
264 {
265 	return (ring->rdesc_count - (ring->cur - ring->dirty));
266 }
267 
268 static inline unsigned int xgbe_rx_dirty_desc(struct xgbe_ring *ring)
269 {
270 	return (ring->cur - ring->dirty);
271 }
272 
273 static int xgbe_maybe_stop_tx_queue(struct xgbe_channel *channel,
274 				    struct xgbe_ring *ring, unsigned int count)
275 {
276 	struct xgbe_prv_data *pdata = channel->pdata;
277 
278 	if (count > xgbe_tx_avail_desc(ring)) {
279 		netif_info(pdata, drv, pdata->netdev,
280 			   "Tx queue stopped, not enough descriptors available\n");
281 		netif_stop_subqueue(pdata->netdev, channel->queue_index);
282 		ring->tx.queue_stopped = 1;
283 
284 		/* If we haven't notified the hardware because of xmit_more
285 		 * support, tell it now
286 		 */
287 		if (ring->tx.xmit_more)
288 			pdata->hw_if.tx_start_xmit(channel, ring);
289 
290 		return NETDEV_TX_BUSY;
291 	}
292 
293 	return 0;
294 }
295 
296 static int xgbe_calc_rx_buf_size(struct net_device *netdev, unsigned int mtu)
297 {
298 	unsigned int rx_buf_size;
299 
300 	rx_buf_size = mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
301 	rx_buf_size = clamp_val(rx_buf_size, XGBE_RX_MIN_BUF_SIZE, PAGE_SIZE);
302 
303 	rx_buf_size = (rx_buf_size + XGBE_RX_BUF_ALIGN - 1) &
304 		      ~(XGBE_RX_BUF_ALIGN - 1);
305 
306 	return rx_buf_size;
307 }
308 
309 static void xgbe_enable_rx_tx_int(struct xgbe_prv_data *pdata,
310 				  struct xgbe_channel *channel)
311 {
312 	struct xgbe_hw_if *hw_if = &pdata->hw_if;
313 	enum xgbe_int int_id;
314 
315 	if (channel->tx_ring && channel->rx_ring)
316 		int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
317 	else if (channel->tx_ring)
318 		int_id = XGMAC_INT_DMA_CH_SR_TI;
319 	else if (channel->rx_ring)
320 		int_id = XGMAC_INT_DMA_CH_SR_RI;
321 	else
322 		return;
323 
324 	hw_if->enable_int(channel, int_id);
325 }
326 
327 static void xgbe_enable_rx_tx_ints(struct xgbe_prv_data *pdata)
328 {
329 	unsigned int i;
330 
331 	for (i = 0; i < pdata->channel_count; i++)
332 		xgbe_enable_rx_tx_int(pdata, pdata->channel[i]);
333 }
334 
335 static void xgbe_disable_rx_tx_int(struct xgbe_prv_data *pdata,
336 				   struct xgbe_channel *channel)
337 {
338 	struct xgbe_hw_if *hw_if = &pdata->hw_if;
339 	enum xgbe_int int_id;
340 
341 	if (channel->tx_ring && channel->rx_ring)
342 		int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
343 	else if (channel->tx_ring)
344 		int_id = XGMAC_INT_DMA_CH_SR_TI;
345 	else if (channel->rx_ring)
346 		int_id = XGMAC_INT_DMA_CH_SR_RI;
347 	else
348 		return;
349 
350 	hw_if->disable_int(channel, int_id);
351 }
352 
353 static void xgbe_disable_rx_tx_ints(struct xgbe_prv_data *pdata)
354 {
355 	unsigned int i;
356 
357 	for (i = 0; i < pdata->channel_count; i++)
358 		xgbe_disable_rx_tx_int(pdata, pdata->channel[i]);
359 }
360 
361 static bool xgbe_ecc_sec(struct xgbe_prv_data *pdata, unsigned long *period,
362 			 unsigned int *count, const char *area)
363 {
364 	if (time_before(jiffies, *period)) {
365 		(*count)++;
366 	} else {
367 		*period = jiffies + (ecc_sec_period * HZ);
368 		*count = 1;
369 	}
370 
371 	if (*count > ecc_sec_info_threshold)
372 		dev_warn_once(pdata->dev,
373 			      "%s ECC corrected errors exceed informational threshold\n",
374 			      area);
375 
376 	if (*count > ecc_sec_warn_threshold) {
377 		dev_warn_once(pdata->dev,
378 			      "%s ECC corrected errors exceed warning threshold\n",
379 			      area);
380 		return true;
381 	}
382 
383 	return false;
384 }
385 
386 static bool xgbe_ecc_ded(struct xgbe_prv_data *pdata, unsigned long *period,
387 			 unsigned int *count, const char *area)
388 {
389 	if (time_before(jiffies, *period)) {
390 		(*count)++;
391 	} else {
392 		*period = jiffies + (ecc_ded_period * HZ);
393 		*count = 1;
394 	}
395 
396 	if (*count > ecc_ded_threshold) {
397 		netdev_alert(pdata->netdev,
398 			     "%s ECC detected errors exceed threshold\n",
399 			     area);
400 		return true;
401 	}
402 
403 	return false;
404 }
405 
406 static void xgbe_ecc_isr_task(struct tasklet_struct *t)
407 {
408 	struct xgbe_prv_data *pdata = from_tasklet(pdata, t, tasklet_ecc);
409 	unsigned int ecc_isr;
410 	bool stop = false;
411 
412 	/* Mask status with only the interrupts we care about */
413 	ecc_isr = XP_IOREAD(pdata, XP_ECC_ISR);
414 	ecc_isr &= XP_IOREAD(pdata, XP_ECC_IER);
415 	netif_dbg(pdata, intr, pdata->netdev, "ECC_ISR=%#010x\n", ecc_isr);
416 
417 	if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, TX_DED)) {
418 		stop |= xgbe_ecc_ded(pdata, &pdata->tx_ded_period,
419 				     &pdata->tx_ded_count, "TX fifo");
420 	}
421 
422 	if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, RX_DED)) {
423 		stop |= xgbe_ecc_ded(pdata, &pdata->rx_ded_period,
424 				     &pdata->rx_ded_count, "RX fifo");
425 	}
426 
427 	if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, DESC_DED)) {
428 		stop |= xgbe_ecc_ded(pdata, &pdata->desc_ded_period,
429 				     &pdata->desc_ded_count,
430 				     "descriptor cache");
431 	}
432 
433 	if (stop) {
434 		pdata->hw_if.disable_ecc_ded(pdata);
435 		schedule_work(&pdata->stopdev_work);
436 		goto out;
437 	}
438 
439 	if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, TX_SEC)) {
440 		if (xgbe_ecc_sec(pdata, &pdata->tx_sec_period,
441 				 &pdata->tx_sec_count, "TX fifo"))
442 			pdata->hw_if.disable_ecc_sec(pdata, XGBE_ECC_SEC_TX);
443 	}
444 
445 	if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, RX_SEC))
446 		if (xgbe_ecc_sec(pdata, &pdata->rx_sec_period,
447 				 &pdata->rx_sec_count, "RX fifo"))
448 			pdata->hw_if.disable_ecc_sec(pdata, XGBE_ECC_SEC_RX);
449 
450 	if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, DESC_SEC))
451 		if (xgbe_ecc_sec(pdata, &pdata->desc_sec_period,
452 				 &pdata->desc_sec_count, "descriptor cache"))
453 			pdata->hw_if.disable_ecc_sec(pdata, XGBE_ECC_SEC_DESC);
454 
455 out:
456 	/* Clear all ECC interrupts */
457 	XP_IOWRITE(pdata, XP_ECC_ISR, ecc_isr);
458 
459 	/* Reissue interrupt if status is not clear */
460 	if (pdata->vdata->irq_reissue_support)
461 		XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 1);
462 }
463 
464 static irqreturn_t xgbe_ecc_isr(int irq, void *data)
465 {
466 	struct xgbe_prv_data *pdata = data;
467 
468 	if (pdata->isr_as_tasklet)
469 		tasklet_schedule(&pdata->tasklet_ecc);
470 	else
471 		xgbe_ecc_isr_task(&pdata->tasklet_ecc);
472 
473 	return IRQ_HANDLED;
474 }
475 
476 static void xgbe_isr_task(struct tasklet_struct *t)
477 {
478 	struct xgbe_prv_data *pdata = from_tasklet(pdata, t, tasklet_dev);
479 	struct xgbe_hw_if *hw_if = &pdata->hw_if;
480 	struct xgbe_channel *channel;
481 	unsigned int dma_isr, dma_ch_isr;
482 	unsigned int mac_isr, mac_tssr, mac_mdioisr;
483 	unsigned int i;
484 
485 	/* The DMA interrupt status register also reports MAC and MTL
486 	 * interrupts. So for polling mode, we just need to check for
487 	 * this register to be non-zero
488 	 */
489 	dma_isr = XGMAC_IOREAD(pdata, DMA_ISR);
490 	if (!dma_isr)
491 		goto isr_done;
492 
493 	netif_dbg(pdata, intr, pdata->netdev, "DMA_ISR=%#010x\n", dma_isr);
494 
495 	for (i = 0; i < pdata->channel_count; i++) {
496 		if (!(dma_isr & (1 << i)))
497 			continue;
498 
499 		channel = pdata->channel[i];
500 
501 		dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR);
502 		netif_dbg(pdata, intr, pdata->netdev, "DMA_CH%u_ISR=%#010x\n",
503 			  i, dma_ch_isr);
504 
505 		/* The TI or RI interrupt bits may still be set even if using
506 		 * per channel DMA interrupts. Check to be sure those are not
507 		 * enabled before using the private data napi structure.
508 		 */
509 		if (!pdata->per_channel_irq &&
510 		    (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, TI) ||
511 		     XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RI))) {
512 			if (napi_schedule_prep(&pdata->napi)) {
513 				/* Disable Tx and Rx interrupts */
514 				xgbe_disable_rx_tx_ints(pdata);
515 
516 				/* Turn on polling */
517 				__napi_schedule(&pdata->napi);
518 			}
519 		} else {
520 			/* Don't clear Rx/Tx status if doing per channel DMA
521 			 * interrupts, these will be cleared by the ISR for
522 			 * per channel DMA interrupts.
523 			 */
524 			XGMAC_SET_BITS(dma_ch_isr, DMA_CH_SR, TI, 0);
525 			XGMAC_SET_BITS(dma_ch_isr, DMA_CH_SR, RI, 0);
526 		}
527 
528 		if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RBU))
529 			pdata->ext_stats.rx_buffer_unavailable++;
530 
531 		/* Restart the device on a Fatal Bus Error */
532 		if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, FBE))
533 			schedule_work(&pdata->restart_work);
534 
535 		/* Clear interrupt signals */
536 		XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr);
537 	}
538 
539 	if (XGMAC_GET_BITS(dma_isr, DMA_ISR, MACIS)) {
540 		mac_isr = XGMAC_IOREAD(pdata, MAC_ISR);
541 
542 		netif_dbg(pdata, intr, pdata->netdev, "MAC_ISR=%#010x\n",
543 			  mac_isr);
544 
545 		if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCTXIS))
546 			hw_if->tx_mmc_int(pdata);
547 
548 		if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCRXIS))
549 			hw_if->rx_mmc_int(pdata);
550 
551 		if (XGMAC_GET_BITS(mac_isr, MAC_ISR, TSIS)) {
552 			mac_tssr = XGMAC_IOREAD(pdata, MAC_TSSR);
553 
554 			netif_dbg(pdata, intr, pdata->netdev,
555 				  "MAC_TSSR=%#010x\n", mac_tssr);
556 
557 			if (XGMAC_GET_BITS(mac_tssr, MAC_TSSR, TXTSC)) {
558 				/* Read Tx Timestamp to clear interrupt */
559 				pdata->tx_tstamp =
560 					hw_if->get_tx_tstamp(pdata);
561 				queue_work(pdata->dev_workqueue,
562 					   &pdata->tx_tstamp_work);
563 			}
564 		}
565 
566 		if (XGMAC_GET_BITS(mac_isr, MAC_ISR, SMI)) {
567 			mac_mdioisr = XGMAC_IOREAD(pdata, MAC_MDIOISR);
568 
569 			netif_dbg(pdata, intr, pdata->netdev,
570 				  "MAC_MDIOISR=%#010x\n", mac_mdioisr);
571 
572 			if (XGMAC_GET_BITS(mac_mdioisr, MAC_MDIOISR,
573 					   SNGLCOMPINT))
574 				complete(&pdata->mdio_complete);
575 		}
576 	}
577 
578 isr_done:
579 	/* If there is not a separate AN irq, handle it here */
580 	if (pdata->dev_irq == pdata->an_irq)
581 		pdata->phy_if.an_isr(pdata);
582 
583 	/* If there is not a separate ECC irq, handle it here */
584 	if (pdata->vdata->ecc_support && (pdata->dev_irq == pdata->ecc_irq))
585 		xgbe_ecc_isr_task(&pdata->tasklet_ecc);
586 
587 	/* If there is not a separate I2C irq, handle it here */
588 	if (pdata->vdata->i2c_support && (pdata->dev_irq == pdata->i2c_irq))
589 		pdata->i2c_if.i2c_isr(pdata);
590 
591 	/* Reissue interrupt if status is not clear */
592 	if (pdata->vdata->irq_reissue_support) {
593 		unsigned int reissue_mask;
594 
595 		reissue_mask = 1 << 0;
596 		if (!pdata->per_channel_irq)
597 			reissue_mask |= 0xffff << 4;
598 
599 		XP_IOWRITE(pdata, XP_INT_REISSUE_EN, reissue_mask);
600 	}
601 }
602 
603 static irqreturn_t xgbe_isr(int irq, void *data)
604 {
605 	struct xgbe_prv_data *pdata = data;
606 
607 	if (pdata->isr_as_tasklet)
608 		tasklet_schedule(&pdata->tasklet_dev);
609 	else
610 		xgbe_isr_task(&pdata->tasklet_dev);
611 
612 	return IRQ_HANDLED;
613 }
614 
615 static irqreturn_t xgbe_dma_isr(int irq, void *data)
616 {
617 	struct xgbe_channel *channel = data;
618 	struct xgbe_prv_data *pdata = channel->pdata;
619 	unsigned int dma_status;
620 
621 	/* Per channel DMA interrupts are enabled, so we use the per
622 	 * channel napi structure and not the private data napi structure
623 	 */
624 	if (napi_schedule_prep(&channel->napi)) {
625 		/* Disable Tx and Rx interrupts */
626 		if (pdata->channel_irq_mode)
627 			xgbe_disable_rx_tx_int(pdata, channel);
628 		else
629 			disable_irq_nosync(channel->dma_irq);
630 
631 		/* Turn on polling */
632 		__napi_schedule_irqoff(&channel->napi);
633 	}
634 
635 	/* Clear Tx/Rx signals */
636 	dma_status = 0;
637 	XGMAC_SET_BITS(dma_status, DMA_CH_SR, TI, 1);
638 	XGMAC_SET_BITS(dma_status, DMA_CH_SR, RI, 1);
639 	XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_status);
640 
641 	return IRQ_HANDLED;
642 }
643 
644 static void xgbe_tx_timer(struct timer_list *t)
645 {
646 	struct xgbe_channel *channel = from_timer(channel, t, tx_timer);
647 	struct xgbe_prv_data *pdata = channel->pdata;
648 	struct napi_struct *napi;
649 
650 	DBGPR("-->xgbe_tx_timer\n");
651 
652 	napi = (pdata->per_channel_irq) ? &channel->napi : &pdata->napi;
653 
654 	if (napi_schedule_prep(napi)) {
655 		/* Disable Tx and Rx interrupts */
656 		if (pdata->per_channel_irq)
657 			if (pdata->channel_irq_mode)
658 				xgbe_disable_rx_tx_int(pdata, channel);
659 			else
660 				disable_irq_nosync(channel->dma_irq);
661 		else
662 			xgbe_disable_rx_tx_ints(pdata);
663 
664 		/* Turn on polling */
665 		__napi_schedule(napi);
666 	}
667 
668 	channel->tx_timer_active = 0;
669 
670 	DBGPR("<--xgbe_tx_timer\n");
671 }
672 
673 static void xgbe_service(struct work_struct *work)
674 {
675 	struct xgbe_prv_data *pdata = container_of(work,
676 						   struct xgbe_prv_data,
677 						   service_work);
678 
679 	pdata->phy_if.phy_status(pdata);
680 }
681 
682 static void xgbe_service_timer(struct timer_list *t)
683 {
684 	struct xgbe_prv_data *pdata = from_timer(pdata, t, service_timer);
685 	struct xgbe_channel *channel;
686 	unsigned int i;
687 
688 	queue_work(pdata->dev_workqueue, &pdata->service_work);
689 
690 	mod_timer(&pdata->service_timer, jiffies + HZ);
691 
692 	if (!pdata->tx_usecs)
693 		return;
694 
695 	for (i = 0; i < pdata->channel_count; i++) {
696 		channel = pdata->channel[i];
697 		if (!channel->tx_ring || channel->tx_timer_active)
698 			break;
699 		channel->tx_timer_active = 1;
700 		mod_timer(&channel->tx_timer,
701 			  jiffies + usecs_to_jiffies(pdata->tx_usecs));
702 	}
703 }
704 
705 static void xgbe_init_timers(struct xgbe_prv_data *pdata)
706 {
707 	struct xgbe_channel *channel;
708 	unsigned int i;
709 
710 	timer_setup(&pdata->service_timer, xgbe_service_timer, 0);
711 
712 	for (i = 0; i < pdata->channel_count; i++) {
713 		channel = pdata->channel[i];
714 		if (!channel->tx_ring)
715 			break;
716 
717 		timer_setup(&channel->tx_timer, xgbe_tx_timer, 0);
718 	}
719 }
720 
721 static void xgbe_start_timers(struct xgbe_prv_data *pdata)
722 {
723 	mod_timer(&pdata->service_timer, jiffies + HZ);
724 }
725 
726 static void xgbe_stop_timers(struct xgbe_prv_data *pdata)
727 {
728 	struct xgbe_channel *channel;
729 	unsigned int i;
730 
731 	del_timer_sync(&pdata->service_timer);
732 
733 	for (i = 0; i < pdata->channel_count; i++) {
734 		channel = pdata->channel[i];
735 		if (!channel->tx_ring)
736 			break;
737 
738 		/* Deactivate the Tx timer */
739 		del_timer_sync(&channel->tx_timer);
740 		channel->tx_timer_active = 0;
741 	}
742 }
743 
744 void xgbe_get_all_hw_features(struct xgbe_prv_data *pdata)
745 {
746 	unsigned int mac_hfr0, mac_hfr1, mac_hfr2;
747 	struct xgbe_hw_features *hw_feat = &pdata->hw_feat;
748 
749 	mac_hfr0 = XGMAC_IOREAD(pdata, MAC_HWF0R);
750 	mac_hfr1 = XGMAC_IOREAD(pdata, MAC_HWF1R);
751 	mac_hfr2 = XGMAC_IOREAD(pdata, MAC_HWF2R);
752 
753 	memset(hw_feat, 0, sizeof(*hw_feat));
754 
755 	hw_feat->version = XGMAC_IOREAD(pdata, MAC_VR);
756 
757 	/* Hardware feature register 0 */
758 	hw_feat->gmii        = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, GMIISEL);
759 	hw_feat->vlhash      = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VLHASH);
760 	hw_feat->sma         = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SMASEL);
761 	hw_feat->rwk         = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RWKSEL);
762 	hw_feat->mgk         = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MGKSEL);
763 	hw_feat->mmc         = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MMCSEL);
764 	hw_feat->aoe         = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, ARPOFFSEL);
765 	hw_feat->ts          = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSEL);
766 	hw_feat->eee         = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, EEESEL);
767 	hw_feat->tx_coe      = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TXCOESEL);
768 	hw_feat->rx_coe      = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RXCOESEL);
769 	hw_feat->addn_mac    = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R,
770 					      ADDMACADRSEL);
771 	hw_feat->ts_src      = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSTSSEL);
772 	hw_feat->sa_vlan_ins = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SAVLANINS);
773 	hw_feat->vxn         = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VXN);
774 
775 	/* Hardware feature register 1 */
776 	hw_feat->rx_fifo_size  = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
777 						RXFIFOSIZE);
778 	hw_feat->tx_fifo_size  = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
779 						TXFIFOSIZE);
780 	hw_feat->adv_ts_hi     = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADVTHWORD);
781 	hw_feat->dma_width     = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADDR64);
782 	hw_feat->dcb           = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DCBEN);
783 	hw_feat->sph           = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, SPHEN);
784 	hw_feat->tso           = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, TSOEN);
785 	hw_feat->dma_debug     = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DBGMEMA);
786 	hw_feat->rss           = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, RSSEN);
787 	hw_feat->tc_cnt	       = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, NUMTC);
788 	hw_feat->hash_table_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
789 						  HASHTBLSZ);
790 	hw_feat->l3l4_filter_num = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
791 						  L3L4FNUM);
792 
793 	/* Hardware feature register 2 */
794 	hw_feat->rx_q_cnt     = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXQCNT);
795 	hw_feat->tx_q_cnt     = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXQCNT);
796 	hw_feat->rx_ch_cnt    = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXCHCNT);
797 	hw_feat->tx_ch_cnt    = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXCHCNT);
798 	hw_feat->pps_out_num  = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, PPSOUTNUM);
799 	hw_feat->aux_snap_num = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, AUXSNAPNUM);
800 
801 	/* Translate the Hash Table size into actual number */
802 	switch (hw_feat->hash_table_size) {
803 	case 0:
804 		break;
805 	case 1:
806 		hw_feat->hash_table_size = 64;
807 		break;
808 	case 2:
809 		hw_feat->hash_table_size = 128;
810 		break;
811 	case 3:
812 		hw_feat->hash_table_size = 256;
813 		break;
814 	}
815 
816 	/* Translate the address width setting into actual number */
817 	switch (hw_feat->dma_width) {
818 	case 0:
819 		hw_feat->dma_width = 32;
820 		break;
821 	case 1:
822 		hw_feat->dma_width = 40;
823 		break;
824 	case 2:
825 		hw_feat->dma_width = 48;
826 		break;
827 	default:
828 		hw_feat->dma_width = 32;
829 	}
830 
831 	/* The Queue, Channel and TC counts are zero based so increment them
832 	 * to get the actual number
833 	 */
834 	hw_feat->rx_q_cnt++;
835 	hw_feat->tx_q_cnt++;
836 	hw_feat->rx_ch_cnt++;
837 	hw_feat->tx_ch_cnt++;
838 	hw_feat->tc_cnt++;
839 
840 	/* Translate the fifo sizes into actual numbers */
841 	hw_feat->rx_fifo_size = 1 << (hw_feat->rx_fifo_size + 7);
842 	hw_feat->tx_fifo_size = 1 << (hw_feat->tx_fifo_size + 7);
843 
844 	if (netif_msg_probe(pdata)) {
845 		dev_dbg(pdata->dev, "Hardware features:\n");
846 
847 		/* Hardware feature register 0 */
848 		dev_dbg(pdata->dev, "  1GbE support              : %s\n",
849 			hw_feat->gmii ? "yes" : "no");
850 		dev_dbg(pdata->dev, "  VLAN hash filter          : %s\n",
851 			hw_feat->vlhash ? "yes" : "no");
852 		dev_dbg(pdata->dev, "  MDIO interface            : %s\n",
853 			hw_feat->sma ? "yes" : "no");
854 		dev_dbg(pdata->dev, "  Wake-up packet support    : %s\n",
855 			hw_feat->rwk ? "yes" : "no");
856 		dev_dbg(pdata->dev, "  Magic packet support      : %s\n",
857 			hw_feat->mgk ? "yes" : "no");
858 		dev_dbg(pdata->dev, "  Management counters       : %s\n",
859 			hw_feat->mmc ? "yes" : "no");
860 		dev_dbg(pdata->dev, "  ARP offload               : %s\n",
861 			hw_feat->aoe ? "yes" : "no");
862 		dev_dbg(pdata->dev, "  IEEE 1588-2008 Timestamp  : %s\n",
863 			hw_feat->ts ? "yes" : "no");
864 		dev_dbg(pdata->dev, "  Energy Efficient Ethernet : %s\n",
865 			hw_feat->eee ? "yes" : "no");
866 		dev_dbg(pdata->dev, "  TX checksum offload       : %s\n",
867 			hw_feat->tx_coe ? "yes" : "no");
868 		dev_dbg(pdata->dev, "  RX checksum offload       : %s\n",
869 			hw_feat->rx_coe ? "yes" : "no");
870 		dev_dbg(pdata->dev, "  Additional MAC addresses  : %u\n",
871 			hw_feat->addn_mac);
872 		dev_dbg(pdata->dev, "  Timestamp source          : %s\n",
873 			(hw_feat->ts_src == 1) ? "internal" :
874 			(hw_feat->ts_src == 2) ? "external" :
875 			(hw_feat->ts_src == 3) ? "internal/external" : "n/a");
876 		dev_dbg(pdata->dev, "  SA/VLAN insertion         : %s\n",
877 			hw_feat->sa_vlan_ins ? "yes" : "no");
878 		dev_dbg(pdata->dev, "  VXLAN/NVGRE support       : %s\n",
879 			hw_feat->vxn ? "yes" : "no");
880 
881 		/* Hardware feature register 1 */
882 		dev_dbg(pdata->dev, "  RX fifo size              : %u\n",
883 			hw_feat->rx_fifo_size);
884 		dev_dbg(pdata->dev, "  TX fifo size              : %u\n",
885 			hw_feat->tx_fifo_size);
886 		dev_dbg(pdata->dev, "  IEEE 1588 high word       : %s\n",
887 			hw_feat->adv_ts_hi ? "yes" : "no");
888 		dev_dbg(pdata->dev, "  DMA width                 : %u\n",
889 			hw_feat->dma_width);
890 		dev_dbg(pdata->dev, "  Data Center Bridging      : %s\n",
891 			hw_feat->dcb ? "yes" : "no");
892 		dev_dbg(pdata->dev, "  Split header              : %s\n",
893 			hw_feat->sph ? "yes" : "no");
894 		dev_dbg(pdata->dev, "  TCP Segmentation Offload  : %s\n",
895 			hw_feat->tso ? "yes" : "no");
896 		dev_dbg(pdata->dev, "  Debug memory interface    : %s\n",
897 			hw_feat->dma_debug ? "yes" : "no");
898 		dev_dbg(pdata->dev, "  Receive Side Scaling      : %s\n",
899 			hw_feat->rss ? "yes" : "no");
900 		dev_dbg(pdata->dev, "  Traffic Class count       : %u\n",
901 			hw_feat->tc_cnt);
902 		dev_dbg(pdata->dev, "  Hash table size           : %u\n",
903 			hw_feat->hash_table_size);
904 		dev_dbg(pdata->dev, "  L3/L4 Filters             : %u\n",
905 			hw_feat->l3l4_filter_num);
906 
907 		/* Hardware feature register 2 */
908 		dev_dbg(pdata->dev, "  RX queue count            : %u\n",
909 			hw_feat->rx_q_cnt);
910 		dev_dbg(pdata->dev, "  TX queue count            : %u\n",
911 			hw_feat->tx_q_cnt);
912 		dev_dbg(pdata->dev, "  RX DMA channel count      : %u\n",
913 			hw_feat->rx_ch_cnt);
914 		dev_dbg(pdata->dev, "  TX DMA channel count      : %u\n",
915 			hw_feat->rx_ch_cnt);
916 		dev_dbg(pdata->dev, "  PPS outputs               : %u\n",
917 			hw_feat->pps_out_num);
918 		dev_dbg(pdata->dev, "  Auxiliary snapshot inputs : %u\n",
919 			hw_feat->aux_snap_num);
920 	}
921 }
922 
923 static int xgbe_vxlan_set_port(struct net_device *netdev, unsigned int table,
924 			       unsigned int entry, struct udp_tunnel_info *ti)
925 {
926 	struct xgbe_prv_data *pdata = netdev_priv(netdev);
927 
928 	pdata->vxlan_port = be16_to_cpu(ti->port);
929 	pdata->hw_if.enable_vxlan(pdata);
930 
931 	return 0;
932 }
933 
934 static int xgbe_vxlan_unset_port(struct net_device *netdev, unsigned int table,
935 				 unsigned int entry, struct udp_tunnel_info *ti)
936 {
937 	struct xgbe_prv_data *pdata = netdev_priv(netdev);
938 
939 	pdata->hw_if.disable_vxlan(pdata);
940 	pdata->vxlan_port = 0;
941 
942 	return 0;
943 }
944 
945 static const struct udp_tunnel_nic_info xgbe_udp_tunnels = {
946 	.set_port	= xgbe_vxlan_set_port,
947 	.unset_port	= xgbe_vxlan_unset_port,
948 	.flags		= UDP_TUNNEL_NIC_INFO_OPEN_ONLY,
949 	.tables		= {
950 		{ .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN, },
951 	},
952 };
953 
954 const struct udp_tunnel_nic_info *xgbe_get_udp_tunnel_info(void)
955 {
956 	return &xgbe_udp_tunnels;
957 }
958 
959 static void xgbe_napi_enable(struct xgbe_prv_data *pdata, unsigned int add)
960 {
961 	struct xgbe_channel *channel;
962 	unsigned int i;
963 
964 	if (pdata->per_channel_irq) {
965 		for (i = 0; i < pdata->channel_count; i++) {
966 			channel = pdata->channel[i];
967 			if (add)
968 				netif_napi_add(pdata->netdev, &channel->napi,
969 					       xgbe_one_poll);
970 
971 			napi_enable(&channel->napi);
972 		}
973 	} else {
974 		if (add)
975 			netif_napi_add(pdata->netdev, &pdata->napi,
976 				       xgbe_all_poll);
977 
978 		napi_enable(&pdata->napi);
979 	}
980 }
981 
982 static void xgbe_napi_disable(struct xgbe_prv_data *pdata, unsigned int del)
983 {
984 	struct xgbe_channel *channel;
985 	unsigned int i;
986 
987 	if (pdata->per_channel_irq) {
988 		for (i = 0; i < pdata->channel_count; i++) {
989 			channel = pdata->channel[i];
990 			napi_disable(&channel->napi);
991 
992 			if (del)
993 				netif_napi_del(&channel->napi);
994 		}
995 	} else {
996 		napi_disable(&pdata->napi);
997 
998 		if (del)
999 			netif_napi_del(&pdata->napi);
1000 	}
1001 }
1002 
1003 static int xgbe_request_irqs(struct xgbe_prv_data *pdata)
1004 {
1005 	struct xgbe_channel *channel;
1006 	struct net_device *netdev = pdata->netdev;
1007 	unsigned int i;
1008 	int ret;
1009 
1010 	tasklet_setup(&pdata->tasklet_dev, xgbe_isr_task);
1011 	tasklet_setup(&pdata->tasklet_ecc, xgbe_ecc_isr_task);
1012 
1013 	ret = devm_request_irq(pdata->dev, pdata->dev_irq, xgbe_isr, 0,
1014 			       netdev_name(netdev), pdata);
1015 	if (ret) {
1016 		netdev_alert(netdev, "error requesting irq %d\n",
1017 			     pdata->dev_irq);
1018 		return ret;
1019 	}
1020 
1021 	if (pdata->vdata->ecc_support && (pdata->dev_irq != pdata->ecc_irq)) {
1022 		ret = devm_request_irq(pdata->dev, pdata->ecc_irq, xgbe_ecc_isr,
1023 				       0, pdata->ecc_name, pdata);
1024 		if (ret) {
1025 			netdev_alert(netdev, "error requesting ecc irq %d\n",
1026 				     pdata->ecc_irq);
1027 			goto err_dev_irq;
1028 		}
1029 	}
1030 
1031 	if (!pdata->per_channel_irq)
1032 		return 0;
1033 
1034 	for (i = 0; i < pdata->channel_count; i++) {
1035 		channel = pdata->channel[i];
1036 		snprintf(channel->dma_irq_name,
1037 			 sizeof(channel->dma_irq_name) - 1,
1038 			 "%s-TxRx-%u", netdev_name(netdev),
1039 			 channel->queue_index);
1040 
1041 		ret = devm_request_irq(pdata->dev, channel->dma_irq,
1042 				       xgbe_dma_isr, 0,
1043 				       channel->dma_irq_name, channel);
1044 		if (ret) {
1045 			netdev_alert(netdev, "error requesting irq %d\n",
1046 				     channel->dma_irq);
1047 			goto err_dma_irq;
1048 		}
1049 
1050 		irq_set_affinity_hint(channel->dma_irq,
1051 				      &channel->affinity_mask);
1052 	}
1053 
1054 	return 0;
1055 
1056 err_dma_irq:
1057 	/* Using an unsigned int, 'i' will go to UINT_MAX and exit */
1058 	for (i--; i < pdata->channel_count; i--) {
1059 		channel = pdata->channel[i];
1060 
1061 		irq_set_affinity_hint(channel->dma_irq, NULL);
1062 		devm_free_irq(pdata->dev, channel->dma_irq, channel);
1063 	}
1064 
1065 	if (pdata->vdata->ecc_support && (pdata->dev_irq != pdata->ecc_irq))
1066 		devm_free_irq(pdata->dev, pdata->ecc_irq, pdata);
1067 
1068 err_dev_irq:
1069 	devm_free_irq(pdata->dev, pdata->dev_irq, pdata);
1070 
1071 	return ret;
1072 }
1073 
1074 static void xgbe_free_irqs(struct xgbe_prv_data *pdata)
1075 {
1076 	struct xgbe_channel *channel;
1077 	unsigned int i;
1078 
1079 	devm_free_irq(pdata->dev, pdata->dev_irq, pdata);
1080 
1081 	tasklet_kill(&pdata->tasklet_dev);
1082 	tasklet_kill(&pdata->tasklet_ecc);
1083 
1084 	if (pdata->vdata->ecc_support && (pdata->dev_irq != pdata->ecc_irq))
1085 		devm_free_irq(pdata->dev, pdata->ecc_irq, pdata);
1086 
1087 	if (!pdata->per_channel_irq)
1088 		return;
1089 
1090 	for (i = 0; i < pdata->channel_count; i++) {
1091 		channel = pdata->channel[i];
1092 
1093 		irq_set_affinity_hint(channel->dma_irq, NULL);
1094 		devm_free_irq(pdata->dev, channel->dma_irq, channel);
1095 	}
1096 }
1097 
1098 void xgbe_init_tx_coalesce(struct xgbe_prv_data *pdata)
1099 {
1100 	struct xgbe_hw_if *hw_if = &pdata->hw_if;
1101 
1102 	DBGPR("-->xgbe_init_tx_coalesce\n");
1103 
1104 	pdata->tx_usecs = XGMAC_INIT_DMA_TX_USECS;
1105 	pdata->tx_frames = XGMAC_INIT_DMA_TX_FRAMES;
1106 
1107 	hw_if->config_tx_coalesce(pdata);
1108 
1109 	DBGPR("<--xgbe_init_tx_coalesce\n");
1110 }
1111 
1112 void xgbe_init_rx_coalesce(struct xgbe_prv_data *pdata)
1113 {
1114 	struct xgbe_hw_if *hw_if = &pdata->hw_if;
1115 
1116 	DBGPR("-->xgbe_init_rx_coalesce\n");
1117 
1118 	pdata->rx_riwt = hw_if->usec_to_riwt(pdata, XGMAC_INIT_DMA_RX_USECS);
1119 	pdata->rx_usecs = XGMAC_INIT_DMA_RX_USECS;
1120 	pdata->rx_frames = XGMAC_INIT_DMA_RX_FRAMES;
1121 
1122 	hw_if->config_rx_coalesce(pdata);
1123 
1124 	DBGPR("<--xgbe_init_rx_coalesce\n");
1125 }
1126 
1127 static void xgbe_free_tx_data(struct xgbe_prv_data *pdata)
1128 {
1129 	struct xgbe_desc_if *desc_if = &pdata->desc_if;
1130 	struct xgbe_ring *ring;
1131 	struct xgbe_ring_data *rdata;
1132 	unsigned int i, j;
1133 
1134 	DBGPR("-->xgbe_free_tx_data\n");
1135 
1136 	for (i = 0; i < pdata->channel_count; i++) {
1137 		ring = pdata->channel[i]->tx_ring;
1138 		if (!ring)
1139 			break;
1140 
1141 		for (j = 0; j < ring->rdesc_count; j++) {
1142 			rdata = XGBE_GET_DESC_DATA(ring, j);
1143 			desc_if->unmap_rdata(pdata, rdata);
1144 		}
1145 	}
1146 
1147 	DBGPR("<--xgbe_free_tx_data\n");
1148 }
1149 
1150 static void xgbe_free_rx_data(struct xgbe_prv_data *pdata)
1151 {
1152 	struct xgbe_desc_if *desc_if = &pdata->desc_if;
1153 	struct xgbe_ring *ring;
1154 	struct xgbe_ring_data *rdata;
1155 	unsigned int i, j;
1156 
1157 	DBGPR("-->xgbe_free_rx_data\n");
1158 
1159 	for (i = 0; i < pdata->channel_count; i++) {
1160 		ring = pdata->channel[i]->rx_ring;
1161 		if (!ring)
1162 			break;
1163 
1164 		for (j = 0; j < ring->rdesc_count; j++) {
1165 			rdata = XGBE_GET_DESC_DATA(ring, j);
1166 			desc_if->unmap_rdata(pdata, rdata);
1167 		}
1168 	}
1169 
1170 	DBGPR("<--xgbe_free_rx_data\n");
1171 }
1172 
1173 static int xgbe_phy_reset(struct xgbe_prv_data *pdata)
1174 {
1175 	pdata->phy_link = -1;
1176 	pdata->phy_speed = SPEED_UNKNOWN;
1177 
1178 	return pdata->phy_if.phy_reset(pdata);
1179 }
1180 
1181 int xgbe_powerdown(struct net_device *netdev, unsigned int caller)
1182 {
1183 	struct xgbe_prv_data *pdata = netdev_priv(netdev);
1184 	struct xgbe_hw_if *hw_if = &pdata->hw_if;
1185 	unsigned long flags;
1186 
1187 	DBGPR("-->xgbe_powerdown\n");
1188 
1189 	if (!netif_running(netdev) ||
1190 	    (caller == XGMAC_IOCTL_CONTEXT && pdata->power_down)) {
1191 		netdev_alert(netdev, "Device is already powered down\n");
1192 		DBGPR("<--xgbe_powerdown\n");
1193 		return -EINVAL;
1194 	}
1195 
1196 	spin_lock_irqsave(&pdata->lock, flags);
1197 
1198 	if (caller == XGMAC_DRIVER_CONTEXT)
1199 		netif_device_detach(netdev);
1200 
1201 	netif_tx_stop_all_queues(netdev);
1202 
1203 	xgbe_stop_timers(pdata);
1204 	flush_workqueue(pdata->dev_workqueue);
1205 
1206 	hw_if->powerdown_tx(pdata);
1207 	hw_if->powerdown_rx(pdata);
1208 
1209 	xgbe_napi_disable(pdata, 0);
1210 
1211 	pdata->power_down = 1;
1212 
1213 	spin_unlock_irqrestore(&pdata->lock, flags);
1214 
1215 	DBGPR("<--xgbe_powerdown\n");
1216 
1217 	return 0;
1218 }
1219 
1220 int xgbe_powerup(struct net_device *netdev, unsigned int caller)
1221 {
1222 	struct xgbe_prv_data *pdata = netdev_priv(netdev);
1223 	struct xgbe_hw_if *hw_if = &pdata->hw_if;
1224 	unsigned long flags;
1225 
1226 	DBGPR("-->xgbe_powerup\n");
1227 
1228 	if (!netif_running(netdev) ||
1229 	    (caller == XGMAC_IOCTL_CONTEXT && !pdata->power_down)) {
1230 		netdev_alert(netdev, "Device is already powered up\n");
1231 		DBGPR("<--xgbe_powerup\n");
1232 		return -EINVAL;
1233 	}
1234 
1235 	spin_lock_irqsave(&pdata->lock, flags);
1236 
1237 	pdata->power_down = 0;
1238 
1239 	xgbe_napi_enable(pdata, 0);
1240 
1241 	hw_if->powerup_tx(pdata);
1242 	hw_if->powerup_rx(pdata);
1243 
1244 	if (caller == XGMAC_DRIVER_CONTEXT)
1245 		netif_device_attach(netdev);
1246 
1247 	netif_tx_start_all_queues(netdev);
1248 
1249 	xgbe_start_timers(pdata);
1250 
1251 	spin_unlock_irqrestore(&pdata->lock, flags);
1252 
1253 	DBGPR("<--xgbe_powerup\n");
1254 
1255 	return 0;
1256 }
1257 
1258 static void xgbe_free_memory(struct xgbe_prv_data *pdata)
1259 {
1260 	struct xgbe_desc_if *desc_if = &pdata->desc_if;
1261 
1262 	/* Free the ring descriptors and buffers */
1263 	desc_if->free_ring_resources(pdata);
1264 
1265 	/* Free the channel and ring structures */
1266 	xgbe_free_channels(pdata);
1267 }
1268 
1269 static int xgbe_alloc_memory(struct xgbe_prv_data *pdata)
1270 {
1271 	struct xgbe_desc_if *desc_if = &pdata->desc_if;
1272 	struct net_device *netdev = pdata->netdev;
1273 	int ret;
1274 
1275 	if (pdata->new_tx_ring_count) {
1276 		pdata->tx_ring_count = pdata->new_tx_ring_count;
1277 		pdata->tx_q_count = pdata->tx_ring_count;
1278 		pdata->new_tx_ring_count = 0;
1279 	}
1280 
1281 	if (pdata->new_rx_ring_count) {
1282 		pdata->rx_ring_count = pdata->new_rx_ring_count;
1283 		pdata->new_rx_ring_count = 0;
1284 	}
1285 
1286 	/* Calculate the Rx buffer size before allocating rings */
1287 	pdata->rx_buf_size = xgbe_calc_rx_buf_size(netdev, netdev->mtu);
1288 
1289 	/* Allocate the channel and ring structures */
1290 	ret = xgbe_alloc_channels(pdata);
1291 	if (ret)
1292 		return ret;
1293 
1294 	/* Allocate the ring descriptors and buffers */
1295 	ret = desc_if->alloc_ring_resources(pdata);
1296 	if (ret)
1297 		goto err_channels;
1298 
1299 	/* Initialize the service and Tx timers */
1300 	xgbe_init_timers(pdata);
1301 
1302 	return 0;
1303 
1304 err_channels:
1305 	xgbe_free_memory(pdata);
1306 
1307 	return ret;
1308 }
1309 
1310 static int xgbe_start(struct xgbe_prv_data *pdata)
1311 {
1312 	struct xgbe_hw_if *hw_if = &pdata->hw_if;
1313 	struct xgbe_phy_if *phy_if = &pdata->phy_if;
1314 	struct net_device *netdev = pdata->netdev;
1315 	unsigned int i;
1316 	int ret;
1317 
1318 	/* Set the number of queues */
1319 	ret = netif_set_real_num_tx_queues(netdev, pdata->tx_ring_count);
1320 	if (ret) {
1321 		netdev_err(netdev, "error setting real tx queue count\n");
1322 		return ret;
1323 	}
1324 
1325 	ret = netif_set_real_num_rx_queues(netdev, pdata->rx_ring_count);
1326 	if (ret) {
1327 		netdev_err(netdev, "error setting real rx queue count\n");
1328 		return ret;
1329 	}
1330 
1331 	/* Set RSS lookup table data for programming */
1332 	for (i = 0; i < XGBE_RSS_MAX_TABLE_SIZE; i++)
1333 		XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH,
1334 			       i % pdata->rx_ring_count);
1335 
1336 	ret = hw_if->init(pdata);
1337 	if (ret)
1338 		return ret;
1339 
1340 	xgbe_napi_enable(pdata, 1);
1341 
1342 	ret = xgbe_request_irqs(pdata);
1343 	if (ret)
1344 		goto err_napi;
1345 
1346 	ret = phy_if->phy_start(pdata);
1347 	if (ret)
1348 		goto err_irqs;
1349 
1350 	hw_if->enable_tx(pdata);
1351 	hw_if->enable_rx(pdata);
1352 
1353 	udp_tunnel_nic_reset_ntf(netdev);
1354 
1355 	netif_tx_start_all_queues(netdev);
1356 
1357 	xgbe_start_timers(pdata);
1358 	queue_work(pdata->dev_workqueue, &pdata->service_work);
1359 
1360 	clear_bit(XGBE_STOPPED, &pdata->dev_state);
1361 
1362 	return 0;
1363 
1364 err_irqs:
1365 	xgbe_free_irqs(pdata);
1366 
1367 err_napi:
1368 	xgbe_napi_disable(pdata, 1);
1369 
1370 	hw_if->exit(pdata);
1371 
1372 	return ret;
1373 }
1374 
1375 static void xgbe_stop(struct xgbe_prv_data *pdata)
1376 {
1377 	struct xgbe_hw_if *hw_if = &pdata->hw_if;
1378 	struct xgbe_phy_if *phy_if = &pdata->phy_if;
1379 	struct xgbe_channel *channel;
1380 	struct net_device *netdev = pdata->netdev;
1381 	struct netdev_queue *txq;
1382 	unsigned int i;
1383 
1384 	DBGPR("-->xgbe_stop\n");
1385 
1386 	if (test_bit(XGBE_STOPPED, &pdata->dev_state))
1387 		return;
1388 
1389 	netif_tx_stop_all_queues(netdev);
1390 	netif_carrier_off(pdata->netdev);
1391 
1392 	xgbe_stop_timers(pdata);
1393 	flush_workqueue(pdata->dev_workqueue);
1394 
1395 	xgbe_vxlan_unset_port(netdev, 0, 0, NULL);
1396 
1397 	hw_if->disable_tx(pdata);
1398 	hw_if->disable_rx(pdata);
1399 
1400 	phy_if->phy_stop(pdata);
1401 
1402 	xgbe_free_irqs(pdata);
1403 
1404 	xgbe_napi_disable(pdata, 1);
1405 
1406 	hw_if->exit(pdata);
1407 
1408 	for (i = 0; i < pdata->channel_count; i++) {
1409 		channel = pdata->channel[i];
1410 		if (!channel->tx_ring)
1411 			continue;
1412 
1413 		txq = netdev_get_tx_queue(netdev, channel->queue_index);
1414 		netdev_tx_reset_queue(txq);
1415 	}
1416 
1417 	set_bit(XGBE_STOPPED, &pdata->dev_state);
1418 
1419 	DBGPR("<--xgbe_stop\n");
1420 }
1421 
1422 static void xgbe_stopdev(struct work_struct *work)
1423 {
1424 	struct xgbe_prv_data *pdata = container_of(work,
1425 						   struct xgbe_prv_data,
1426 						   stopdev_work);
1427 
1428 	rtnl_lock();
1429 
1430 	xgbe_stop(pdata);
1431 
1432 	xgbe_free_tx_data(pdata);
1433 	xgbe_free_rx_data(pdata);
1434 
1435 	rtnl_unlock();
1436 
1437 	netdev_alert(pdata->netdev, "device stopped\n");
1438 }
1439 
1440 void xgbe_full_restart_dev(struct xgbe_prv_data *pdata)
1441 {
1442 	/* If not running, "restart" will happen on open */
1443 	if (!netif_running(pdata->netdev))
1444 		return;
1445 
1446 	xgbe_stop(pdata);
1447 
1448 	xgbe_free_memory(pdata);
1449 	xgbe_alloc_memory(pdata);
1450 
1451 	xgbe_start(pdata);
1452 }
1453 
1454 void xgbe_restart_dev(struct xgbe_prv_data *pdata)
1455 {
1456 	/* If not running, "restart" will happen on open */
1457 	if (!netif_running(pdata->netdev))
1458 		return;
1459 
1460 	xgbe_stop(pdata);
1461 
1462 	xgbe_free_tx_data(pdata);
1463 	xgbe_free_rx_data(pdata);
1464 
1465 	xgbe_start(pdata);
1466 }
1467 
1468 static void xgbe_restart(struct work_struct *work)
1469 {
1470 	struct xgbe_prv_data *pdata = container_of(work,
1471 						   struct xgbe_prv_data,
1472 						   restart_work);
1473 
1474 	rtnl_lock();
1475 
1476 	xgbe_restart_dev(pdata);
1477 
1478 	rtnl_unlock();
1479 }
1480 
1481 static void xgbe_tx_tstamp(struct work_struct *work)
1482 {
1483 	struct xgbe_prv_data *pdata = container_of(work,
1484 						   struct xgbe_prv_data,
1485 						   tx_tstamp_work);
1486 	struct skb_shared_hwtstamps hwtstamps;
1487 	u64 nsec;
1488 	unsigned long flags;
1489 
1490 	spin_lock_irqsave(&pdata->tstamp_lock, flags);
1491 	if (!pdata->tx_tstamp_skb)
1492 		goto unlock;
1493 
1494 	if (pdata->tx_tstamp) {
1495 		nsec = timecounter_cyc2time(&pdata->tstamp_tc,
1496 					    pdata->tx_tstamp);
1497 
1498 		memset(&hwtstamps, 0, sizeof(hwtstamps));
1499 		hwtstamps.hwtstamp = ns_to_ktime(nsec);
1500 		skb_tstamp_tx(pdata->tx_tstamp_skb, &hwtstamps);
1501 	}
1502 
1503 	dev_kfree_skb_any(pdata->tx_tstamp_skb);
1504 
1505 	pdata->tx_tstamp_skb = NULL;
1506 
1507 unlock:
1508 	spin_unlock_irqrestore(&pdata->tstamp_lock, flags);
1509 }
1510 
1511 static int xgbe_get_hwtstamp_settings(struct xgbe_prv_data *pdata,
1512 				      struct ifreq *ifreq)
1513 {
1514 	if (copy_to_user(ifreq->ifr_data, &pdata->tstamp_config,
1515 			 sizeof(pdata->tstamp_config)))
1516 		return -EFAULT;
1517 
1518 	return 0;
1519 }
1520 
1521 static int xgbe_set_hwtstamp_settings(struct xgbe_prv_data *pdata,
1522 				      struct ifreq *ifreq)
1523 {
1524 	struct hwtstamp_config config;
1525 	unsigned int mac_tscr;
1526 
1527 	if (copy_from_user(&config, ifreq->ifr_data, sizeof(config)))
1528 		return -EFAULT;
1529 
1530 	mac_tscr = 0;
1531 
1532 	switch (config.tx_type) {
1533 	case HWTSTAMP_TX_OFF:
1534 		break;
1535 
1536 	case HWTSTAMP_TX_ON:
1537 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1538 		break;
1539 
1540 	default:
1541 		return -ERANGE;
1542 	}
1543 
1544 	switch (config.rx_filter) {
1545 	case HWTSTAMP_FILTER_NONE:
1546 		break;
1547 
1548 	case HWTSTAMP_FILTER_NTP_ALL:
1549 	case HWTSTAMP_FILTER_ALL:
1550 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 1);
1551 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1552 		break;
1553 
1554 	/* PTP v2, UDP, any kind of event packet */
1555 	case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1556 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1557 		fallthrough;	/* to PTP v1, UDP, any kind of event packet */
1558 	case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1559 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1560 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1561 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
1562 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1563 		break;
1564 
1565 	/* PTP v2, UDP, Sync packet */
1566 	case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1567 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1568 		fallthrough;	/* to PTP v1, UDP, Sync packet */
1569 	case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1570 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1571 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1572 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1573 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1574 		break;
1575 
1576 	/* PTP v2, UDP, Delay_req packet */
1577 	case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1578 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1579 		fallthrough;	/* to PTP v1, UDP, Delay_req packet */
1580 	case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1581 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1582 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1583 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1584 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
1585 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1586 		break;
1587 
1588 	/* 802.AS1, Ethernet, any kind of event packet */
1589 	case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1590 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
1591 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
1592 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1593 		break;
1594 
1595 	/* 802.AS1, Ethernet, Sync packet */
1596 	case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1597 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
1598 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1599 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1600 		break;
1601 
1602 	/* 802.AS1, Ethernet, Delay_req packet */
1603 	case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1604 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
1605 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
1606 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1607 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1608 		break;
1609 
1610 	/* PTP v2/802.AS1, any layer, any kind of event packet */
1611 	case HWTSTAMP_FILTER_PTP_V2_EVENT:
1612 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1613 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
1614 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1615 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1616 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
1617 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1618 		break;
1619 
1620 	/* PTP v2/802.AS1, any layer, Sync packet */
1621 	case HWTSTAMP_FILTER_PTP_V2_SYNC:
1622 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1623 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
1624 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1625 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1626 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1627 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1628 		break;
1629 
1630 	/* PTP v2/802.AS1, any layer, Delay_req packet */
1631 	case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1632 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1633 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
1634 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1635 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1636 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
1637 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1638 		XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1639 		break;
1640 
1641 	default:
1642 		return -ERANGE;
1643 	}
1644 
1645 	pdata->hw_if.config_tstamp(pdata, mac_tscr);
1646 
1647 	memcpy(&pdata->tstamp_config, &config, sizeof(config));
1648 
1649 	return 0;
1650 }
1651 
1652 static void xgbe_prep_tx_tstamp(struct xgbe_prv_data *pdata,
1653 				struct sk_buff *skb,
1654 				struct xgbe_packet_data *packet)
1655 {
1656 	unsigned long flags;
1657 
1658 	if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP)) {
1659 		spin_lock_irqsave(&pdata->tstamp_lock, flags);
1660 		if (pdata->tx_tstamp_skb) {
1661 			/* Another timestamp in progress, ignore this one */
1662 			XGMAC_SET_BITS(packet->attributes,
1663 				       TX_PACKET_ATTRIBUTES, PTP, 0);
1664 		} else {
1665 			pdata->tx_tstamp_skb = skb_get(skb);
1666 			skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1667 		}
1668 		spin_unlock_irqrestore(&pdata->tstamp_lock, flags);
1669 	}
1670 
1671 	skb_tx_timestamp(skb);
1672 }
1673 
1674 static void xgbe_prep_vlan(struct sk_buff *skb, struct xgbe_packet_data *packet)
1675 {
1676 	if (skb_vlan_tag_present(skb))
1677 		packet->vlan_ctag = skb_vlan_tag_get(skb);
1678 }
1679 
1680 static int xgbe_prep_tso(struct sk_buff *skb, struct xgbe_packet_data *packet)
1681 {
1682 	int ret;
1683 
1684 	if (!XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1685 			    TSO_ENABLE))
1686 		return 0;
1687 
1688 	ret = skb_cow_head(skb, 0);
1689 	if (ret)
1690 		return ret;
1691 
1692 	if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, VXLAN)) {
1693 		packet->header_len = skb_inner_tcp_all_headers(skb);
1694 		packet->tcp_header_len = inner_tcp_hdrlen(skb);
1695 	} else {
1696 		packet->header_len = skb_tcp_all_headers(skb);
1697 		packet->tcp_header_len = tcp_hdrlen(skb);
1698 	}
1699 	packet->tcp_payload_len = skb->len - packet->header_len;
1700 	packet->mss = skb_shinfo(skb)->gso_size;
1701 
1702 	DBGPR("  packet->header_len=%u\n", packet->header_len);
1703 	DBGPR("  packet->tcp_header_len=%u, packet->tcp_payload_len=%u\n",
1704 	      packet->tcp_header_len, packet->tcp_payload_len);
1705 	DBGPR("  packet->mss=%u\n", packet->mss);
1706 
1707 	/* Update the number of packets that will ultimately be transmitted
1708 	 * along with the extra bytes for each extra packet
1709 	 */
1710 	packet->tx_packets = skb_shinfo(skb)->gso_segs;
1711 	packet->tx_bytes += (packet->tx_packets - 1) * packet->header_len;
1712 
1713 	return 0;
1714 }
1715 
1716 static bool xgbe_is_vxlan(struct sk_buff *skb)
1717 {
1718 	if (!skb->encapsulation)
1719 		return false;
1720 
1721 	if (skb->ip_summed != CHECKSUM_PARTIAL)
1722 		return false;
1723 
1724 	switch (skb->protocol) {
1725 	case htons(ETH_P_IP):
1726 		if (ip_hdr(skb)->protocol != IPPROTO_UDP)
1727 			return false;
1728 		break;
1729 
1730 	case htons(ETH_P_IPV6):
1731 		if (ipv6_hdr(skb)->nexthdr != IPPROTO_UDP)
1732 			return false;
1733 		break;
1734 
1735 	default:
1736 		return false;
1737 	}
1738 
1739 	if (skb->inner_protocol_type != ENCAP_TYPE_ETHER ||
1740 	    skb->inner_protocol != htons(ETH_P_TEB) ||
1741 	    (skb_inner_mac_header(skb) - skb_transport_header(skb) !=
1742 	     sizeof(struct udphdr) + sizeof(struct vxlanhdr)))
1743 		return false;
1744 
1745 	return true;
1746 }
1747 
1748 static int xgbe_is_tso(struct sk_buff *skb)
1749 {
1750 	if (skb->ip_summed != CHECKSUM_PARTIAL)
1751 		return 0;
1752 
1753 	if (!skb_is_gso(skb))
1754 		return 0;
1755 
1756 	DBGPR("  TSO packet to be processed\n");
1757 
1758 	return 1;
1759 }
1760 
1761 static void xgbe_packet_info(struct xgbe_prv_data *pdata,
1762 			     struct xgbe_ring *ring, struct sk_buff *skb,
1763 			     struct xgbe_packet_data *packet)
1764 {
1765 	skb_frag_t *frag;
1766 	unsigned int context_desc;
1767 	unsigned int len;
1768 	unsigned int i;
1769 
1770 	packet->skb = skb;
1771 
1772 	context_desc = 0;
1773 	packet->rdesc_count = 0;
1774 
1775 	packet->tx_packets = 1;
1776 	packet->tx_bytes = skb->len;
1777 
1778 	if (xgbe_is_tso(skb)) {
1779 		/* TSO requires an extra descriptor if mss is different */
1780 		if (skb_shinfo(skb)->gso_size != ring->tx.cur_mss) {
1781 			context_desc = 1;
1782 			packet->rdesc_count++;
1783 		}
1784 
1785 		/* TSO requires an extra descriptor for TSO header */
1786 		packet->rdesc_count++;
1787 
1788 		XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1789 			       TSO_ENABLE, 1);
1790 		XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1791 			       CSUM_ENABLE, 1);
1792 	} else if (skb->ip_summed == CHECKSUM_PARTIAL)
1793 		XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1794 			       CSUM_ENABLE, 1);
1795 
1796 	if (xgbe_is_vxlan(skb))
1797 		XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1798 			       VXLAN, 1);
1799 
1800 	if (skb_vlan_tag_present(skb)) {
1801 		/* VLAN requires an extra descriptor if tag is different */
1802 		if (skb_vlan_tag_get(skb) != ring->tx.cur_vlan_ctag)
1803 			/* We can share with the TSO context descriptor */
1804 			if (!context_desc) {
1805 				context_desc = 1;
1806 				packet->rdesc_count++;
1807 			}
1808 
1809 		XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1810 			       VLAN_CTAG, 1);
1811 	}
1812 
1813 	if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
1814 	    (pdata->tstamp_config.tx_type == HWTSTAMP_TX_ON))
1815 		XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1816 			       PTP, 1);
1817 
1818 	for (len = skb_headlen(skb); len;) {
1819 		packet->rdesc_count++;
1820 		len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE);
1821 	}
1822 
1823 	for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1824 		frag = &skb_shinfo(skb)->frags[i];
1825 		for (len = skb_frag_size(frag); len; ) {
1826 			packet->rdesc_count++;
1827 			len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE);
1828 		}
1829 	}
1830 }
1831 
1832 static int xgbe_open(struct net_device *netdev)
1833 {
1834 	struct xgbe_prv_data *pdata = netdev_priv(netdev);
1835 	int ret;
1836 
1837 	/* Create the various names based on netdev name */
1838 	snprintf(pdata->an_name, sizeof(pdata->an_name) - 1, "%s-pcs",
1839 		 netdev_name(netdev));
1840 
1841 	snprintf(pdata->ecc_name, sizeof(pdata->ecc_name) - 1, "%s-ecc",
1842 		 netdev_name(netdev));
1843 
1844 	snprintf(pdata->i2c_name, sizeof(pdata->i2c_name) - 1, "%s-i2c",
1845 		 netdev_name(netdev));
1846 
1847 	/* Create workqueues */
1848 	pdata->dev_workqueue =
1849 		create_singlethread_workqueue(netdev_name(netdev));
1850 	if (!pdata->dev_workqueue) {
1851 		netdev_err(netdev, "device workqueue creation failed\n");
1852 		return -ENOMEM;
1853 	}
1854 
1855 	pdata->an_workqueue =
1856 		create_singlethread_workqueue(pdata->an_name);
1857 	if (!pdata->an_workqueue) {
1858 		netdev_err(netdev, "phy workqueue creation failed\n");
1859 		ret = -ENOMEM;
1860 		goto err_dev_wq;
1861 	}
1862 
1863 	/* Reset the phy settings */
1864 	ret = xgbe_phy_reset(pdata);
1865 	if (ret)
1866 		goto err_an_wq;
1867 
1868 	/* Enable the clocks */
1869 	ret = clk_prepare_enable(pdata->sysclk);
1870 	if (ret) {
1871 		netdev_alert(netdev, "dma clk_prepare_enable failed\n");
1872 		goto err_an_wq;
1873 	}
1874 
1875 	ret = clk_prepare_enable(pdata->ptpclk);
1876 	if (ret) {
1877 		netdev_alert(netdev, "ptp clk_prepare_enable failed\n");
1878 		goto err_sysclk;
1879 	}
1880 
1881 	INIT_WORK(&pdata->service_work, xgbe_service);
1882 	INIT_WORK(&pdata->restart_work, xgbe_restart);
1883 	INIT_WORK(&pdata->stopdev_work, xgbe_stopdev);
1884 	INIT_WORK(&pdata->tx_tstamp_work, xgbe_tx_tstamp);
1885 
1886 	ret = xgbe_alloc_memory(pdata);
1887 	if (ret)
1888 		goto err_ptpclk;
1889 
1890 	ret = xgbe_start(pdata);
1891 	if (ret)
1892 		goto err_mem;
1893 
1894 	clear_bit(XGBE_DOWN, &pdata->dev_state);
1895 
1896 	return 0;
1897 
1898 err_mem:
1899 	xgbe_free_memory(pdata);
1900 
1901 err_ptpclk:
1902 	clk_disable_unprepare(pdata->ptpclk);
1903 
1904 err_sysclk:
1905 	clk_disable_unprepare(pdata->sysclk);
1906 
1907 err_an_wq:
1908 	destroy_workqueue(pdata->an_workqueue);
1909 
1910 err_dev_wq:
1911 	destroy_workqueue(pdata->dev_workqueue);
1912 
1913 	return ret;
1914 }
1915 
1916 static int xgbe_close(struct net_device *netdev)
1917 {
1918 	struct xgbe_prv_data *pdata = netdev_priv(netdev);
1919 
1920 	/* Stop the device */
1921 	xgbe_stop(pdata);
1922 
1923 	xgbe_free_memory(pdata);
1924 
1925 	/* Disable the clocks */
1926 	clk_disable_unprepare(pdata->ptpclk);
1927 	clk_disable_unprepare(pdata->sysclk);
1928 
1929 	destroy_workqueue(pdata->an_workqueue);
1930 
1931 	destroy_workqueue(pdata->dev_workqueue);
1932 
1933 	set_bit(XGBE_DOWN, &pdata->dev_state);
1934 
1935 	return 0;
1936 }
1937 
1938 static netdev_tx_t xgbe_xmit(struct sk_buff *skb, struct net_device *netdev)
1939 {
1940 	struct xgbe_prv_data *pdata = netdev_priv(netdev);
1941 	struct xgbe_hw_if *hw_if = &pdata->hw_if;
1942 	struct xgbe_desc_if *desc_if = &pdata->desc_if;
1943 	struct xgbe_channel *channel;
1944 	struct xgbe_ring *ring;
1945 	struct xgbe_packet_data *packet;
1946 	struct netdev_queue *txq;
1947 	netdev_tx_t ret;
1948 
1949 	DBGPR("-->xgbe_xmit: skb->len = %d\n", skb->len);
1950 
1951 	channel = pdata->channel[skb->queue_mapping];
1952 	txq = netdev_get_tx_queue(netdev, channel->queue_index);
1953 	ring = channel->tx_ring;
1954 	packet = &ring->packet_data;
1955 
1956 	ret = NETDEV_TX_OK;
1957 
1958 	if (skb->len == 0) {
1959 		netif_err(pdata, tx_err, netdev,
1960 			  "empty skb received from stack\n");
1961 		dev_kfree_skb_any(skb);
1962 		goto tx_netdev_return;
1963 	}
1964 
1965 	/* Calculate preliminary packet info */
1966 	memset(packet, 0, sizeof(*packet));
1967 	xgbe_packet_info(pdata, ring, skb, packet);
1968 
1969 	/* Check that there are enough descriptors available */
1970 	ret = xgbe_maybe_stop_tx_queue(channel, ring, packet->rdesc_count);
1971 	if (ret)
1972 		goto tx_netdev_return;
1973 
1974 	ret = xgbe_prep_tso(skb, packet);
1975 	if (ret) {
1976 		netif_err(pdata, tx_err, netdev,
1977 			  "error processing TSO packet\n");
1978 		dev_kfree_skb_any(skb);
1979 		goto tx_netdev_return;
1980 	}
1981 	xgbe_prep_vlan(skb, packet);
1982 
1983 	if (!desc_if->map_tx_skb(channel, skb)) {
1984 		dev_kfree_skb_any(skb);
1985 		goto tx_netdev_return;
1986 	}
1987 
1988 	xgbe_prep_tx_tstamp(pdata, skb, packet);
1989 
1990 	/* Report on the actual number of bytes (to be) sent */
1991 	netdev_tx_sent_queue(txq, packet->tx_bytes);
1992 
1993 	/* Configure required descriptor fields for transmission */
1994 	hw_if->dev_xmit(channel);
1995 
1996 	if (netif_msg_pktdata(pdata))
1997 		xgbe_print_pkt(netdev, skb, true);
1998 
1999 	/* Stop the queue in advance if there may not be enough descriptors */
2000 	xgbe_maybe_stop_tx_queue(channel, ring, XGBE_TX_MAX_DESCS);
2001 
2002 	ret = NETDEV_TX_OK;
2003 
2004 tx_netdev_return:
2005 	return ret;
2006 }
2007 
2008 static void xgbe_set_rx_mode(struct net_device *netdev)
2009 {
2010 	struct xgbe_prv_data *pdata = netdev_priv(netdev);
2011 	struct xgbe_hw_if *hw_if = &pdata->hw_if;
2012 
2013 	DBGPR("-->xgbe_set_rx_mode\n");
2014 
2015 	hw_if->config_rx_mode(pdata);
2016 
2017 	DBGPR("<--xgbe_set_rx_mode\n");
2018 }
2019 
2020 static int xgbe_set_mac_address(struct net_device *netdev, void *addr)
2021 {
2022 	struct xgbe_prv_data *pdata = netdev_priv(netdev);
2023 	struct xgbe_hw_if *hw_if = &pdata->hw_if;
2024 	struct sockaddr *saddr = addr;
2025 
2026 	DBGPR("-->xgbe_set_mac_address\n");
2027 
2028 	if (!is_valid_ether_addr(saddr->sa_data))
2029 		return -EADDRNOTAVAIL;
2030 
2031 	eth_hw_addr_set(netdev, saddr->sa_data);
2032 
2033 	hw_if->set_mac_address(pdata, netdev->dev_addr);
2034 
2035 	DBGPR("<--xgbe_set_mac_address\n");
2036 
2037 	return 0;
2038 }
2039 
2040 static int xgbe_ioctl(struct net_device *netdev, struct ifreq *ifreq, int cmd)
2041 {
2042 	struct xgbe_prv_data *pdata = netdev_priv(netdev);
2043 	int ret;
2044 
2045 	switch (cmd) {
2046 	case SIOCGHWTSTAMP:
2047 		ret = xgbe_get_hwtstamp_settings(pdata, ifreq);
2048 		break;
2049 
2050 	case SIOCSHWTSTAMP:
2051 		ret = xgbe_set_hwtstamp_settings(pdata, ifreq);
2052 		break;
2053 
2054 	default:
2055 		ret = -EOPNOTSUPP;
2056 	}
2057 
2058 	return ret;
2059 }
2060 
2061 static int xgbe_change_mtu(struct net_device *netdev, int mtu)
2062 {
2063 	struct xgbe_prv_data *pdata = netdev_priv(netdev);
2064 	int ret;
2065 
2066 	DBGPR("-->xgbe_change_mtu\n");
2067 
2068 	ret = xgbe_calc_rx_buf_size(netdev, mtu);
2069 	if (ret < 0)
2070 		return ret;
2071 
2072 	pdata->rx_buf_size = ret;
2073 	netdev->mtu = mtu;
2074 
2075 	xgbe_restart_dev(pdata);
2076 
2077 	DBGPR("<--xgbe_change_mtu\n");
2078 
2079 	return 0;
2080 }
2081 
2082 static void xgbe_tx_timeout(struct net_device *netdev, unsigned int txqueue)
2083 {
2084 	struct xgbe_prv_data *pdata = netdev_priv(netdev);
2085 
2086 	netdev_warn(netdev, "tx timeout, device restarting\n");
2087 	schedule_work(&pdata->restart_work);
2088 }
2089 
2090 static void xgbe_get_stats64(struct net_device *netdev,
2091 			     struct rtnl_link_stats64 *s)
2092 {
2093 	struct xgbe_prv_data *pdata = netdev_priv(netdev);
2094 	struct xgbe_mmc_stats *pstats = &pdata->mmc_stats;
2095 
2096 	DBGPR("-->%s\n", __func__);
2097 
2098 	pdata->hw_if.read_mmc_stats(pdata);
2099 
2100 	s->rx_packets = pstats->rxframecount_gb;
2101 	s->rx_bytes = pstats->rxoctetcount_gb;
2102 	s->rx_errors = pstats->rxframecount_gb -
2103 		       pstats->rxbroadcastframes_g -
2104 		       pstats->rxmulticastframes_g -
2105 		       pstats->rxunicastframes_g;
2106 	s->multicast = pstats->rxmulticastframes_g;
2107 	s->rx_length_errors = pstats->rxlengtherror;
2108 	s->rx_crc_errors = pstats->rxcrcerror;
2109 	s->rx_fifo_errors = pstats->rxfifooverflow;
2110 
2111 	s->tx_packets = pstats->txframecount_gb;
2112 	s->tx_bytes = pstats->txoctetcount_gb;
2113 	s->tx_errors = pstats->txframecount_gb - pstats->txframecount_g;
2114 	s->tx_dropped = netdev->stats.tx_dropped;
2115 
2116 	DBGPR("<--%s\n", __func__);
2117 }
2118 
2119 static int xgbe_vlan_rx_add_vid(struct net_device *netdev, __be16 proto,
2120 				u16 vid)
2121 {
2122 	struct xgbe_prv_data *pdata = netdev_priv(netdev);
2123 	struct xgbe_hw_if *hw_if = &pdata->hw_if;
2124 
2125 	DBGPR("-->%s\n", __func__);
2126 
2127 	set_bit(vid, pdata->active_vlans);
2128 	hw_if->update_vlan_hash_table(pdata);
2129 
2130 	DBGPR("<--%s\n", __func__);
2131 
2132 	return 0;
2133 }
2134 
2135 static int xgbe_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto,
2136 				 u16 vid)
2137 {
2138 	struct xgbe_prv_data *pdata = netdev_priv(netdev);
2139 	struct xgbe_hw_if *hw_if = &pdata->hw_if;
2140 
2141 	DBGPR("-->%s\n", __func__);
2142 
2143 	clear_bit(vid, pdata->active_vlans);
2144 	hw_if->update_vlan_hash_table(pdata);
2145 
2146 	DBGPR("<--%s\n", __func__);
2147 
2148 	return 0;
2149 }
2150 
2151 #ifdef CONFIG_NET_POLL_CONTROLLER
2152 static void xgbe_poll_controller(struct net_device *netdev)
2153 {
2154 	struct xgbe_prv_data *pdata = netdev_priv(netdev);
2155 	struct xgbe_channel *channel;
2156 	unsigned int i;
2157 
2158 	DBGPR("-->xgbe_poll_controller\n");
2159 
2160 	if (pdata->per_channel_irq) {
2161 		for (i = 0; i < pdata->channel_count; i++) {
2162 			channel = pdata->channel[i];
2163 			xgbe_dma_isr(channel->dma_irq, channel);
2164 		}
2165 	} else {
2166 		disable_irq(pdata->dev_irq);
2167 		xgbe_isr(pdata->dev_irq, pdata);
2168 		enable_irq(pdata->dev_irq);
2169 	}
2170 
2171 	DBGPR("<--xgbe_poll_controller\n");
2172 }
2173 #endif /* End CONFIG_NET_POLL_CONTROLLER */
2174 
2175 static int xgbe_setup_tc(struct net_device *netdev, enum tc_setup_type type,
2176 			 void *type_data)
2177 {
2178 	struct xgbe_prv_data *pdata = netdev_priv(netdev);
2179 	struct tc_mqprio_qopt *mqprio = type_data;
2180 	u8 tc;
2181 
2182 	if (type != TC_SETUP_QDISC_MQPRIO)
2183 		return -EOPNOTSUPP;
2184 
2185 	mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
2186 	tc = mqprio->num_tc;
2187 
2188 	if (tc > pdata->hw_feat.tc_cnt)
2189 		return -EINVAL;
2190 
2191 	pdata->num_tcs = tc;
2192 	pdata->hw_if.config_tc(pdata);
2193 
2194 	return 0;
2195 }
2196 
2197 static netdev_features_t xgbe_fix_features(struct net_device *netdev,
2198 					   netdev_features_t features)
2199 {
2200 	struct xgbe_prv_data *pdata = netdev_priv(netdev);
2201 	netdev_features_t vxlan_base;
2202 
2203 	vxlan_base = NETIF_F_GSO_UDP_TUNNEL | NETIF_F_RX_UDP_TUNNEL_PORT;
2204 
2205 	if (!pdata->hw_feat.vxn)
2206 		return features;
2207 
2208 	/* VXLAN CSUM requires VXLAN base */
2209 	if ((features & NETIF_F_GSO_UDP_TUNNEL_CSUM) &&
2210 	    !(features & NETIF_F_GSO_UDP_TUNNEL)) {
2211 		netdev_notice(netdev,
2212 			      "forcing tx udp tunnel support\n");
2213 		features |= NETIF_F_GSO_UDP_TUNNEL;
2214 	}
2215 
2216 	/* Can't do one without doing the other */
2217 	if ((features & vxlan_base) != vxlan_base) {
2218 		netdev_notice(netdev,
2219 			      "forcing both tx and rx udp tunnel support\n");
2220 		features |= vxlan_base;
2221 	}
2222 
2223 	if (features & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)) {
2224 		if (!(features & NETIF_F_GSO_UDP_TUNNEL_CSUM)) {
2225 			netdev_notice(netdev,
2226 				      "forcing tx udp tunnel checksumming on\n");
2227 			features |= NETIF_F_GSO_UDP_TUNNEL_CSUM;
2228 		}
2229 	} else {
2230 		if (features & NETIF_F_GSO_UDP_TUNNEL_CSUM) {
2231 			netdev_notice(netdev,
2232 				      "forcing tx udp tunnel checksumming off\n");
2233 			features &= ~NETIF_F_GSO_UDP_TUNNEL_CSUM;
2234 		}
2235 	}
2236 
2237 	return features;
2238 }
2239 
2240 static int xgbe_set_features(struct net_device *netdev,
2241 			     netdev_features_t features)
2242 {
2243 	struct xgbe_prv_data *pdata = netdev_priv(netdev);
2244 	struct xgbe_hw_if *hw_if = &pdata->hw_if;
2245 	netdev_features_t rxhash, rxcsum, rxvlan, rxvlan_filter;
2246 	int ret = 0;
2247 
2248 	rxhash = pdata->netdev_features & NETIF_F_RXHASH;
2249 	rxcsum = pdata->netdev_features & NETIF_F_RXCSUM;
2250 	rxvlan = pdata->netdev_features & NETIF_F_HW_VLAN_CTAG_RX;
2251 	rxvlan_filter = pdata->netdev_features & NETIF_F_HW_VLAN_CTAG_FILTER;
2252 
2253 	if ((features & NETIF_F_RXHASH) && !rxhash)
2254 		ret = hw_if->enable_rss(pdata);
2255 	else if (!(features & NETIF_F_RXHASH) && rxhash)
2256 		ret = hw_if->disable_rss(pdata);
2257 	if (ret)
2258 		return ret;
2259 
2260 	if ((features & NETIF_F_RXCSUM) && !rxcsum)
2261 		hw_if->enable_rx_csum(pdata);
2262 	else if (!(features & NETIF_F_RXCSUM) && rxcsum)
2263 		hw_if->disable_rx_csum(pdata);
2264 
2265 	if ((features & NETIF_F_HW_VLAN_CTAG_RX) && !rxvlan)
2266 		hw_if->enable_rx_vlan_stripping(pdata);
2267 	else if (!(features & NETIF_F_HW_VLAN_CTAG_RX) && rxvlan)
2268 		hw_if->disable_rx_vlan_stripping(pdata);
2269 
2270 	if ((features & NETIF_F_HW_VLAN_CTAG_FILTER) && !rxvlan_filter)
2271 		hw_if->enable_rx_vlan_filtering(pdata);
2272 	else if (!(features & NETIF_F_HW_VLAN_CTAG_FILTER) && rxvlan_filter)
2273 		hw_if->disable_rx_vlan_filtering(pdata);
2274 
2275 	pdata->netdev_features = features;
2276 
2277 	DBGPR("<--xgbe_set_features\n");
2278 
2279 	return 0;
2280 }
2281 
2282 static netdev_features_t xgbe_features_check(struct sk_buff *skb,
2283 					     struct net_device *netdev,
2284 					     netdev_features_t features)
2285 {
2286 	features = vlan_features_check(skb, features);
2287 	features = vxlan_features_check(skb, features);
2288 
2289 	return features;
2290 }
2291 
2292 static const struct net_device_ops xgbe_netdev_ops = {
2293 	.ndo_open		= xgbe_open,
2294 	.ndo_stop		= xgbe_close,
2295 	.ndo_start_xmit		= xgbe_xmit,
2296 	.ndo_set_rx_mode	= xgbe_set_rx_mode,
2297 	.ndo_set_mac_address	= xgbe_set_mac_address,
2298 	.ndo_validate_addr	= eth_validate_addr,
2299 	.ndo_eth_ioctl		= xgbe_ioctl,
2300 	.ndo_change_mtu		= xgbe_change_mtu,
2301 	.ndo_tx_timeout		= xgbe_tx_timeout,
2302 	.ndo_get_stats64	= xgbe_get_stats64,
2303 	.ndo_vlan_rx_add_vid	= xgbe_vlan_rx_add_vid,
2304 	.ndo_vlan_rx_kill_vid	= xgbe_vlan_rx_kill_vid,
2305 #ifdef CONFIG_NET_POLL_CONTROLLER
2306 	.ndo_poll_controller	= xgbe_poll_controller,
2307 #endif
2308 	.ndo_setup_tc		= xgbe_setup_tc,
2309 	.ndo_fix_features	= xgbe_fix_features,
2310 	.ndo_set_features	= xgbe_set_features,
2311 	.ndo_features_check	= xgbe_features_check,
2312 };
2313 
2314 const struct net_device_ops *xgbe_get_netdev_ops(void)
2315 {
2316 	return &xgbe_netdev_ops;
2317 }
2318 
2319 static void xgbe_rx_refresh(struct xgbe_channel *channel)
2320 {
2321 	struct xgbe_prv_data *pdata = channel->pdata;
2322 	struct xgbe_hw_if *hw_if = &pdata->hw_if;
2323 	struct xgbe_desc_if *desc_if = &pdata->desc_if;
2324 	struct xgbe_ring *ring = channel->rx_ring;
2325 	struct xgbe_ring_data *rdata;
2326 
2327 	while (ring->dirty != ring->cur) {
2328 		rdata = XGBE_GET_DESC_DATA(ring, ring->dirty);
2329 
2330 		/* Reset rdata values */
2331 		desc_if->unmap_rdata(pdata, rdata);
2332 
2333 		if (desc_if->map_rx_buffer(pdata, ring, rdata))
2334 			break;
2335 
2336 		hw_if->rx_desc_reset(pdata, rdata, ring->dirty);
2337 
2338 		ring->dirty++;
2339 	}
2340 
2341 	/* Make sure everything is written before the register write */
2342 	wmb();
2343 
2344 	/* Update the Rx Tail Pointer Register with address of
2345 	 * the last cleaned entry */
2346 	rdata = XGBE_GET_DESC_DATA(ring, ring->dirty - 1);
2347 	XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO,
2348 			  lower_32_bits(rdata->rdesc_dma));
2349 }
2350 
2351 static struct sk_buff *xgbe_create_skb(struct xgbe_prv_data *pdata,
2352 				       struct napi_struct *napi,
2353 				       struct xgbe_ring_data *rdata,
2354 				       unsigned int len)
2355 {
2356 	struct sk_buff *skb;
2357 	u8 *packet;
2358 
2359 	skb = napi_alloc_skb(napi, rdata->rx.hdr.dma_len);
2360 	if (!skb)
2361 		return NULL;
2362 
2363 	/* Pull in the header buffer which may contain just the header
2364 	 * or the header plus data
2365 	 */
2366 	dma_sync_single_range_for_cpu(pdata->dev, rdata->rx.hdr.dma_base,
2367 				      rdata->rx.hdr.dma_off,
2368 				      rdata->rx.hdr.dma_len, DMA_FROM_DEVICE);
2369 
2370 	packet = page_address(rdata->rx.hdr.pa.pages) +
2371 		 rdata->rx.hdr.pa.pages_offset;
2372 	skb_copy_to_linear_data(skb, packet, len);
2373 	skb_put(skb, len);
2374 
2375 	return skb;
2376 }
2377 
2378 static unsigned int xgbe_rx_buf1_len(struct xgbe_ring_data *rdata,
2379 				     struct xgbe_packet_data *packet)
2380 {
2381 	/* Always zero if not the first descriptor */
2382 	if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, FIRST))
2383 		return 0;
2384 
2385 	/* First descriptor with split header, return header length */
2386 	if (rdata->rx.hdr_len)
2387 		return rdata->rx.hdr_len;
2388 
2389 	/* First descriptor but not the last descriptor and no split header,
2390 	 * so the full buffer was used
2391 	 */
2392 	if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, LAST))
2393 		return rdata->rx.hdr.dma_len;
2394 
2395 	/* First descriptor and last descriptor and no split header, so
2396 	 * calculate how much of the buffer was used
2397 	 */
2398 	return min_t(unsigned int, rdata->rx.hdr.dma_len, rdata->rx.len);
2399 }
2400 
2401 static unsigned int xgbe_rx_buf2_len(struct xgbe_ring_data *rdata,
2402 				     struct xgbe_packet_data *packet,
2403 				     unsigned int len)
2404 {
2405 	/* Always the full buffer if not the last descriptor */
2406 	if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, LAST))
2407 		return rdata->rx.buf.dma_len;
2408 
2409 	/* Last descriptor so calculate how much of the buffer was used
2410 	 * for the last bit of data
2411 	 */
2412 	return rdata->rx.len - len;
2413 }
2414 
2415 static int xgbe_tx_poll(struct xgbe_channel *channel)
2416 {
2417 	struct xgbe_prv_data *pdata = channel->pdata;
2418 	struct xgbe_hw_if *hw_if = &pdata->hw_if;
2419 	struct xgbe_desc_if *desc_if = &pdata->desc_if;
2420 	struct xgbe_ring *ring = channel->tx_ring;
2421 	struct xgbe_ring_data *rdata;
2422 	struct xgbe_ring_desc *rdesc;
2423 	struct net_device *netdev = pdata->netdev;
2424 	struct netdev_queue *txq;
2425 	int processed = 0;
2426 	unsigned int tx_packets = 0, tx_bytes = 0;
2427 	unsigned int cur;
2428 
2429 	DBGPR("-->xgbe_tx_poll\n");
2430 
2431 	/* Nothing to do if there isn't a Tx ring for this channel */
2432 	if (!ring)
2433 		return 0;
2434 
2435 	cur = ring->cur;
2436 
2437 	/* Be sure we get ring->cur before accessing descriptor data */
2438 	smp_rmb();
2439 
2440 	txq = netdev_get_tx_queue(netdev, channel->queue_index);
2441 
2442 	while ((processed < XGBE_TX_DESC_MAX_PROC) &&
2443 	       (ring->dirty != cur)) {
2444 		rdata = XGBE_GET_DESC_DATA(ring, ring->dirty);
2445 		rdesc = rdata->rdesc;
2446 
2447 		if (!hw_if->tx_complete(rdesc))
2448 			break;
2449 
2450 		/* Make sure descriptor fields are read after reading the OWN
2451 		 * bit */
2452 		dma_rmb();
2453 
2454 		if (netif_msg_tx_done(pdata))
2455 			xgbe_dump_tx_desc(pdata, ring, ring->dirty, 1, 0);
2456 
2457 		if (hw_if->is_last_desc(rdesc)) {
2458 			tx_packets += rdata->tx.packets;
2459 			tx_bytes += rdata->tx.bytes;
2460 		}
2461 
2462 		/* Free the SKB and reset the descriptor for re-use */
2463 		desc_if->unmap_rdata(pdata, rdata);
2464 		hw_if->tx_desc_reset(rdata);
2465 
2466 		processed++;
2467 		ring->dirty++;
2468 	}
2469 
2470 	if (!processed)
2471 		return 0;
2472 
2473 	netdev_tx_completed_queue(txq, tx_packets, tx_bytes);
2474 
2475 	if ((ring->tx.queue_stopped == 1) &&
2476 	    (xgbe_tx_avail_desc(ring) > XGBE_TX_DESC_MIN_FREE)) {
2477 		ring->tx.queue_stopped = 0;
2478 		netif_tx_wake_queue(txq);
2479 	}
2480 
2481 	DBGPR("<--xgbe_tx_poll: processed=%d\n", processed);
2482 
2483 	return processed;
2484 }
2485 
2486 static int xgbe_rx_poll(struct xgbe_channel *channel, int budget)
2487 {
2488 	struct xgbe_prv_data *pdata = channel->pdata;
2489 	struct xgbe_hw_if *hw_if = &pdata->hw_if;
2490 	struct xgbe_ring *ring = channel->rx_ring;
2491 	struct xgbe_ring_data *rdata;
2492 	struct xgbe_packet_data *packet;
2493 	struct net_device *netdev = pdata->netdev;
2494 	struct napi_struct *napi;
2495 	struct sk_buff *skb;
2496 	struct skb_shared_hwtstamps *hwtstamps;
2497 	unsigned int last, error, context_next, context;
2498 	unsigned int len, buf1_len, buf2_len, max_len;
2499 	unsigned int received = 0;
2500 	int packet_count = 0;
2501 
2502 	DBGPR("-->xgbe_rx_poll: budget=%d\n", budget);
2503 
2504 	/* Nothing to do if there isn't a Rx ring for this channel */
2505 	if (!ring)
2506 		return 0;
2507 
2508 	last = 0;
2509 	context_next = 0;
2510 
2511 	napi = (pdata->per_channel_irq) ? &channel->napi : &pdata->napi;
2512 
2513 	rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
2514 	packet = &ring->packet_data;
2515 	while (packet_count < budget) {
2516 		DBGPR("  cur = %d\n", ring->cur);
2517 
2518 		/* First time in loop see if we need to restore state */
2519 		if (!received && rdata->state_saved) {
2520 			skb = rdata->state.skb;
2521 			error = rdata->state.error;
2522 			len = rdata->state.len;
2523 		} else {
2524 			memset(packet, 0, sizeof(*packet));
2525 			skb = NULL;
2526 			error = 0;
2527 			len = 0;
2528 		}
2529 
2530 read_again:
2531 		rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
2532 
2533 		if (xgbe_rx_dirty_desc(ring) > (XGBE_RX_DESC_CNT >> 3))
2534 			xgbe_rx_refresh(channel);
2535 
2536 		if (hw_if->dev_read(channel))
2537 			break;
2538 
2539 		received++;
2540 		ring->cur++;
2541 
2542 		last = XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
2543 				      LAST);
2544 		context_next = XGMAC_GET_BITS(packet->attributes,
2545 					      RX_PACKET_ATTRIBUTES,
2546 					      CONTEXT_NEXT);
2547 		context = XGMAC_GET_BITS(packet->attributes,
2548 					 RX_PACKET_ATTRIBUTES,
2549 					 CONTEXT);
2550 
2551 		/* Earlier error, just drain the remaining data */
2552 		if ((!last || context_next) && error)
2553 			goto read_again;
2554 
2555 		if (error || packet->errors) {
2556 			if (packet->errors)
2557 				netif_err(pdata, rx_err, netdev,
2558 					  "error in received packet\n");
2559 			dev_kfree_skb(skb);
2560 			goto next_packet;
2561 		}
2562 
2563 		if (!context) {
2564 			/* Get the data length in the descriptor buffers */
2565 			buf1_len = xgbe_rx_buf1_len(rdata, packet);
2566 			len += buf1_len;
2567 			buf2_len = xgbe_rx_buf2_len(rdata, packet, len);
2568 			len += buf2_len;
2569 
2570 			if (buf2_len > rdata->rx.buf.dma_len) {
2571 				/* Hardware inconsistency within the descriptors
2572 				 * that has resulted in a length underflow.
2573 				 */
2574 				error = 1;
2575 				goto skip_data;
2576 			}
2577 
2578 			if (!skb) {
2579 				skb = xgbe_create_skb(pdata, napi, rdata,
2580 						      buf1_len);
2581 				if (!skb) {
2582 					error = 1;
2583 					goto skip_data;
2584 				}
2585 			}
2586 
2587 			if (buf2_len) {
2588 				dma_sync_single_range_for_cpu(pdata->dev,
2589 							rdata->rx.buf.dma_base,
2590 							rdata->rx.buf.dma_off,
2591 							rdata->rx.buf.dma_len,
2592 							DMA_FROM_DEVICE);
2593 
2594 				skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
2595 						rdata->rx.buf.pa.pages,
2596 						rdata->rx.buf.pa.pages_offset,
2597 						buf2_len,
2598 						rdata->rx.buf.dma_len);
2599 				rdata->rx.buf.pa.pages = NULL;
2600 			}
2601 		}
2602 
2603 skip_data:
2604 		if (!last || context_next)
2605 			goto read_again;
2606 
2607 		if (!skb || error) {
2608 			dev_kfree_skb(skb);
2609 			goto next_packet;
2610 		}
2611 
2612 		/* Be sure we don't exceed the configured MTU */
2613 		max_len = netdev->mtu + ETH_HLEN;
2614 		if (!(netdev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
2615 		    (skb->protocol == htons(ETH_P_8021Q)))
2616 			max_len += VLAN_HLEN;
2617 
2618 		if (skb->len > max_len) {
2619 			netif_err(pdata, rx_err, netdev,
2620 				  "packet length exceeds configured MTU\n");
2621 			dev_kfree_skb(skb);
2622 			goto next_packet;
2623 		}
2624 
2625 		if (netif_msg_pktdata(pdata))
2626 			xgbe_print_pkt(netdev, skb, false);
2627 
2628 		skb_checksum_none_assert(skb);
2629 		if (XGMAC_GET_BITS(packet->attributes,
2630 				   RX_PACKET_ATTRIBUTES, CSUM_DONE))
2631 			skb->ip_summed = CHECKSUM_UNNECESSARY;
2632 
2633 		if (XGMAC_GET_BITS(packet->attributes,
2634 				   RX_PACKET_ATTRIBUTES, TNP)) {
2635 			skb->encapsulation = 1;
2636 
2637 			if (XGMAC_GET_BITS(packet->attributes,
2638 					   RX_PACKET_ATTRIBUTES, TNPCSUM_DONE))
2639 				skb->csum_level = 1;
2640 		}
2641 
2642 		if (XGMAC_GET_BITS(packet->attributes,
2643 				   RX_PACKET_ATTRIBUTES, VLAN_CTAG))
2644 			__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
2645 					       packet->vlan_ctag);
2646 
2647 		if (XGMAC_GET_BITS(packet->attributes,
2648 				   RX_PACKET_ATTRIBUTES, RX_TSTAMP)) {
2649 			u64 nsec;
2650 
2651 			nsec = timecounter_cyc2time(&pdata->tstamp_tc,
2652 						    packet->rx_tstamp);
2653 			hwtstamps = skb_hwtstamps(skb);
2654 			hwtstamps->hwtstamp = ns_to_ktime(nsec);
2655 		}
2656 
2657 		if (XGMAC_GET_BITS(packet->attributes,
2658 				   RX_PACKET_ATTRIBUTES, RSS_HASH))
2659 			skb_set_hash(skb, packet->rss_hash,
2660 				     packet->rss_hash_type);
2661 
2662 		skb->dev = netdev;
2663 		skb->protocol = eth_type_trans(skb, netdev);
2664 		skb_record_rx_queue(skb, channel->queue_index);
2665 
2666 		napi_gro_receive(napi, skb);
2667 
2668 next_packet:
2669 		packet_count++;
2670 	}
2671 
2672 	/* Check if we need to save state before leaving */
2673 	if (received && (!last || context_next)) {
2674 		rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
2675 		rdata->state_saved = 1;
2676 		rdata->state.skb = skb;
2677 		rdata->state.len = len;
2678 		rdata->state.error = error;
2679 	}
2680 
2681 	DBGPR("<--xgbe_rx_poll: packet_count = %d\n", packet_count);
2682 
2683 	return packet_count;
2684 }
2685 
2686 static int xgbe_one_poll(struct napi_struct *napi, int budget)
2687 {
2688 	struct xgbe_channel *channel = container_of(napi, struct xgbe_channel,
2689 						    napi);
2690 	struct xgbe_prv_data *pdata = channel->pdata;
2691 	int processed = 0;
2692 
2693 	DBGPR("-->xgbe_one_poll: budget=%d\n", budget);
2694 
2695 	/* Cleanup Tx ring first */
2696 	xgbe_tx_poll(channel);
2697 
2698 	/* Process Rx ring next */
2699 	processed = xgbe_rx_poll(channel, budget);
2700 
2701 	/* If we processed everything, we are done */
2702 	if ((processed < budget) && napi_complete_done(napi, processed)) {
2703 		/* Enable Tx and Rx interrupts */
2704 		if (pdata->channel_irq_mode)
2705 			xgbe_enable_rx_tx_int(pdata, channel);
2706 		else
2707 			enable_irq(channel->dma_irq);
2708 	}
2709 
2710 	DBGPR("<--xgbe_one_poll: received = %d\n", processed);
2711 
2712 	return processed;
2713 }
2714 
2715 static int xgbe_all_poll(struct napi_struct *napi, int budget)
2716 {
2717 	struct xgbe_prv_data *pdata = container_of(napi, struct xgbe_prv_data,
2718 						   napi);
2719 	struct xgbe_channel *channel;
2720 	int ring_budget;
2721 	int processed, last_processed;
2722 	unsigned int i;
2723 
2724 	DBGPR("-->xgbe_all_poll: budget=%d\n", budget);
2725 
2726 	processed = 0;
2727 	ring_budget = budget / pdata->rx_ring_count;
2728 	do {
2729 		last_processed = processed;
2730 
2731 		for (i = 0; i < pdata->channel_count; i++) {
2732 			channel = pdata->channel[i];
2733 
2734 			/* Cleanup Tx ring first */
2735 			xgbe_tx_poll(channel);
2736 
2737 			/* Process Rx ring next */
2738 			if (ring_budget > (budget - processed))
2739 				ring_budget = budget - processed;
2740 			processed += xgbe_rx_poll(channel, ring_budget);
2741 		}
2742 	} while ((processed < budget) && (processed != last_processed));
2743 
2744 	/* If we processed everything, we are done */
2745 	if ((processed < budget) && napi_complete_done(napi, processed)) {
2746 		/* Enable Tx and Rx interrupts */
2747 		xgbe_enable_rx_tx_ints(pdata);
2748 	}
2749 
2750 	DBGPR("<--xgbe_all_poll: received = %d\n", processed);
2751 
2752 	return processed;
2753 }
2754 
2755 void xgbe_dump_tx_desc(struct xgbe_prv_data *pdata, struct xgbe_ring *ring,
2756 		       unsigned int idx, unsigned int count, unsigned int flag)
2757 {
2758 	struct xgbe_ring_data *rdata;
2759 	struct xgbe_ring_desc *rdesc;
2760 
2761 	while (count--) {
2762 		rdata = XGBE_GET_DESC_DATA(ring, idx);
2763 		rdesc = rdata->rdesc;
2764 		netdev_dbg(pdata->netdev,
2765 			   "TX_NORMAL_DESC[%d %s] = %08x:%08x:%08x:%08x\n", idx,
2766 			   (flag == 1) ? "QUEUED FOR TX" : "TX BY DEVICE",
2767 			   le32_to_cpu(rdesc->desc0),
2768 			   le32_to_cpu(rdesc->desc1),
2769 			   le32_to_cpu(rdesc->desc2),
2770 			   le32_to_cpu(rdesc->desc3));
2771 		idx++;
2772 	}
2773 }
2774 
2775 void xgbe_dump_rx_desc(struct xgbe_prv_data *pdata, struct xgbe_ring *ring,
2776 		       unsigned int idx)
2777 {
2778 	struct xgbe_ring_data *rdata;
2779 	struct xgbe_ring_desc *rdesc;
2780 
2781 	rdata = XGBE_GET_DESC_DATA(ring, idx);
2782 	rdesc = rdata->rdesc;
2783 	netdev_dbg(pdata->netdev,
2784 		   "RX_NORMAL_DESC[%d RX BY DEVICE] = %08x:%08x:%08x:%08x\n",
2785 		   idx, le32_to_cpu(rdesc->desc0), le32_to_cpu(rdesc->desc1),
2786 		   le32_to_cpu(rdesc->desc2), le32_to_cpu(rdesc->desc3));
2787 }
2788 
2789 void xgbe_print_pkt(struct net_device *netdev, struct sk_buff *skb, bool tx_rx)
2790 {
2791 	struct ethhdr *eth = (struct ethhdr *)skb->data;
2792 	unsigned char buffer[128];
2793 	unsigned int i;
2794 
2795 	netdev_dbg(netdev, "\n************** SKB dump ****************\n");
2796 
2797 	netdev_dbg(netdev, "%s packet of %d bytes\n",
2798 		   (tx_rx ? "TX" : "RX"), skb->len);
2799 
2800 	netdev_dbg(netdev, "Dst MAC addr: %pM\n", eth->h_dest);
2801 	netdev_dbg(netdev, "Src MAC addr: %pM\n", eth->h_source);
2802 	netdev_dbg(netdev, "Protocol: %#06x\n", ntohs(eth->h_proto));
2803 
2804 	for (i = 0; i < skb->len; i += 32) {
2805 		unsigned int len = min(skb->len - i, 32U);
2806 
2807 		hex_dump_to_buffer(&skb->data[i], len, 32, 1,
2808 				   buffer, sizeof(buffer), false);
2809 		netdev_dbg(netdev, "  %#06x: %s\n", i, buffer);
2810 	}
2811 
2812 	netdev_dbg(netdev, "\n************** SKB dump ****************\n");
2813 }
2814