1 /* 2 * AMD 10Gb Ethernet driver 3 * 4 * This file is available to you under your choice of the following two 5 * licenses: 6 * 7 * License 1: GPLv2 8 * 9 * Copyright (c) 2014 Advanced Micro Devices, Inc. 10 * 11 * This file is free software; you may copy, redistribute and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation, either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program. If not, see <http://www.gnu.org/licenses/>. 23 * 24 * This file incorporates work covered by the following copyright and 25 * permission notice: 26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 28 * Inc. unless otherwise expressly agreed to in writing between Synopsys 29 * and you. 30 * 31 * The Software IS NOT an item of Licensed Software or Licensed Product 32 * under any End User Software License Agreement or Agreement for Licensed 33 * Product with Synopsys or any supplement thereto. Permission is hereby 34 * granted, free of charge, to any person obtaining a copy of this software 35 * annotated with this license and the Software, to deal in the Software 36 * without restriction, including without limitation the rights to use, 37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 38 * of the Software, and to permit persons to whom the Software is furnished 39 * to do so, subject to the following conditions: 40 * 41 * The above copyright notice and this permission notice shall be included 42 * in all copies or substantial portions of the Software. 43 * 44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 54 * THE POSSIBILITY OF SUCH DAMAGE. 55 * 56 * 57 * License 2: Modified BSD 58 * 59 * Copyright (c) 2014 Advanced Micro Devices, Inc. 60 * All rights reserved. 61 * 62 * Redistribution and use in source and binary forms, with or without 63 * modification, are permitted provided that the following conditions are met: 64 * * Redistributions of source code must retain the above copyright 65 * notice, this list of conditions and the following disclaimer. 66 * * Redistributions in binary form must reproduce the above copyright 67 * notice, this list of conditions and the following disclaimer in the 68 * documentation and/or other materials provided with the distribution. 69 * * Neither the name of Advanced Micro Devices, Inc. nor the 70 * names of its contributors may be used to endorse or promote products 71 * derived from this software without specific prior written permission. 72 * 73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY 77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 83 * 84 * This file incorporates work covered by the following copyright and 85 * permission notice: 86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 88 * Inc. unless otherwise expressly agreed to in writing between Synopsys 89 * and you. 90 * 91 * The Software IS NOT an item of Licensed Software or Licensed Product 92 * under any End User Software License Agreement or Agreement for Licensed 93 * Product with Synopsys or any supplement thereto. Permission is hereby 94 * granted, free of charge, to any person obtaining a copy of this software 95 * annotated with this license and the Software, to deal in the Software 96 * without restriction, including without limitation the rights to use, 97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 98 * of the Software, and to permit persons to whom the Software is furnished 99 * to do so, subject to the following conditions: 100 * 101 * The above copyright notice and this permission notice shall be included 102 * in all copies or substantial portions of the Software. 103 * 104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 114 * THE POSSIBILITY OF SUCH DAMAGE. 115 */ 116 117 #include <linux/phy.h> 118 #include <linux/clk.h> 119 #include <linux/bitrev.h> 120 #include <linux/crc32.h> 121 122 #include "xgbe.h" 123 #include "xgbe-common.h" 124 125 static unsigned int xgbe_usec_to_riwt(struct xgbe_prv_data *pdata, 126 unsigned int usec) 127 { 128 unsigned long rate; 129 unsigned int ret; 130 131 DBGPR("-->xgbe_usec_to_riwt\n"); 132 133 rate = clk_get_rate(pdata->sysclk); 134 135 /* 136 * Convert the input usec value to the watchdog timer value. Each 137 * watchdog timer value is equivalent to 256 clock cycles. 138 * Calculate the required value as: 139 * ( usec * ( system_clock_mhz / 10^6 ) / 256 140 */ 141 ret = (usec * (rate / 1000000)) / 256; 142 143 DBGPR("<--xgbe_usec_to_riwt\n"); 144 145 return ret; 146 } 147 148 static unsigned int xgbe_riwt_to_usec(struct xgbe_prv_data *pdata, 149 unsigned int riwt) 150 { 151 unsigned long rate; 152 unsigned int ret; 153 154 DBGPR("-->xgbe_riwt_to_usec\n"); 155 156 rate = clk_get_rate(pdata->sysclk); 157 158 /* 159 * Convert the input watchdog timer value to the usec value. Each 160 * watchdog timer value is equivalent to 256 clock cycles. 161 * Calculate the required value as: 162 * ( riwt * 256 ) / ( system_clock_mhz / 10^6 ) 163 */ 164 ret = (riwt * 256) / (rate / 1000000); 165 166 DBGPR("<--xgbe_riwt_to_usec\n"); 167 168 return ret; 169 } 170 171 static int xgbe_config_pblx8(struct xgbe_prv_data *pdata) 172 { 173 struct xgbe_channel *channel; 174 unsigned int i; 175 176 channel = pdata->channel; 177 for (i = 0; i < pdata->channel_count; i++, channel++) 178 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_CR, PBLX8, 179 pdata->pblx8); 180 181 return 0; 182 } 183 184 static int xgbe_get_tx_pbl_val(struct xgbe_prv_data *pdata) 185 { 186 return XGMAC_DMA_IOREAD_BITS(pdata->channel, DMA_CH_TCR, PBL); 187 } 188 189 static int xgbe_config_tx_pbl_val(struct xgbe_prv_data *pdata) 190 { 191 struct xgbe_channel *channel; 192 unsigned int i; 193 194 channel = pdata->channel; 195 for (i = 0; i < pdata->channel_count; i++, channel++) { 196 if (!channel->tx_ring) 197 break; 198 199 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, PBL, 200 pdata->tx_pbl); 201 } 202 203 return 0; 204 } 205 206 static int xgbe_get_rx_pbl_val(struct xgbe_prv_data *pdata) 207 { 208 return XGMAC_DMA_IOREAD_BITS(pdata->channel, DMA_CH_RCR, PBL); 209 } 210 211 static int xgbe_config_rx_pbl_val(struct xgbe_prv_data *pdata) 212 { 213 struct xgbe_channel *channel; 214 unsigned int i; 215 216 channel = pdata->channel; 217 for (i = 0; i < pdata->channel_count; i++, channel++) { 218 if (!channel->rx_ring) 219 break; 220 221 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, PBL, 222 pdata->rx_pbl); 223 } 224 225 return 0; 226 } 227 228 static int xgbe_config_osp_mode(struct xgbe_prv_data *pdata) 229 { 230 struct xgbe_channel *channel; 231 unsigned int i; 232 233 channel = pdata->channel; 234 for (i = 0; i < pdata->channel_count; i++, channel++) { 235 if (!channel->tx_ring) 236 break; 237 238 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, OSP, 239 pdata->tx_osp_mode); 240 } 241 242 return 0; 243 } 244 245 static int xgbe_config_rsf_mode(struct xgbe_prv_data *pdata, unsigned int val) 246 { 247 unsigned int i; 248 249 for (i = 0; i < pdata->rx_q_count; i++) 250 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RSF, val); 251 252 return 0; 253 } 254 255 static int xgbe_config_tsf_mode(struct xgbe_prv_data *pdata, unsigned int val) 256 { 257 unsigned int i; 258 259 for (i = 0; i < pdata->tx_q_count; i++) 260 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TSF, val); 261 262 return 0; 263 } 264 265 static int xgbe_config_rx_threshold(struct xgbe_prv_data *pdata, 266 unsigned int val) 267 { 268 unsigned int i; 269 270 for (i = 0; i < pdata->rx_q_count; i++) 271 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RTC, val); 272 273 return 0; 274 } 275 276 static int xgbe_config_tx_threshold(struct xgbe_prv_data *pdata, 277 unsigned int val) 278 { 279 unsigned int i; 280 281 for (i = 0; i < pdata->tx_q_count; i++) 282 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TTC, val); 283 284 return 0; 285 } 286 287 static int xgbe_config_rx_coalesce(struct xgbe_prv_data *pdata) 288 { 289 struct xgbe_channel *channel; 290 unsigned int i; 291 292 channel = pdata->channel; 293 for (i = 0; i < pdata->channel_count; i++, channel++) { 294 if (!channel->rx_ring) 295 break; 296 297 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RIWT, RWT, 298 pdata->rx_riwt); 299 } 300 301 return 0; 302 } 303 304 static int xgbe_config_tx_coalesce(struct xgbe_prv_data *pdata) 305 { 306 return 0; 307 } 308 309 static void xgbe_config_rx_buffer_size(struct xgbe_prv_data *pdata) 310 { 311 struct xgbe_channel *channel; 312 unsigned int i; 313 314 channel = pdata->channel; 315 for (i = 0; i < pdata->channel_count; i++, channel++) { 316 if (!channel->rx_ring) 317 break; 318 319 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, RBSZ, 320 pdata->rx_buf_size); 321 } 322 } 323 324 static void xgbe_config_tso_mode(struct xgbe_prv_data *pdata) 325 { 326 struct xgbe_channel *channel; 327 unsigned int i; 328 329 channel = pdata->channel; 330 for (i = 0; i < pdata->channel_count; i++, channel++) { 331 if (!channel->tx_ring) 332 break; 333 334 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, TSE, 1); 335 } 336 } 337 338 static void xgbe_config_sph_mode(struct xgbe_prv_data *pdata) 339 { 340 struct xgbe_channel *channel; 341 unsigned int i; 342 343 channel = pdata->channel; 344 for (i = 0; i < pdata->channel_count; i++, channel++) { 345 if (!channel->rx_ring) 346 break; 347 348 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_CR, SPH, 1); 349 } 350 351 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, HDSMS, XGBE_SPH_HDSMS_SIZE); 352 } 353 354 static int xgbe_write_rss_reg(struct xgbe_prv_data *pdata, unsigned int type, 355 unsigned int index, unsigned int val) 356 { 357 unsigned int wait; 358 int ret = 0; 359 360 mutex_lock(&pdata->rss_mutex); 361 362 if (XGMAC_IOREAD_BITS(pdata, MAC_RSSAR, OB)) { 363 ret = -EBUSY; 364 goto unlock; 365 } 366 367 XGMAC_IOWRITE(pdata, MAC_RSSDR, val); 368 369 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, RSSIA, index); 370 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, ADDRT, type); 371 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, CT, 0); 372 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, OB, 1); 373 374 wait = 1000; 375 while (wait--) { 376 if (!XGMAC_IOREAD_BITS(pdata, MAC_RSSAR, OB)) 377 goto unlock; 378 379 usleep_range(1000, 1500); 380 } 381 382 ret = -EBUSY; 383 384 unlock: 385 mutex_unlock(&pdata->rss_mutex); 386 387 return ret; 388 } 389 390 static int xgbe_write_rss_hash_key(struct xgbe_prv_data *pdata) 391 { 392 unsigned int key_regs = sizeof(pdata->rss_key) / sizeof(u32); 393 unsigned int *key = (unsigned int *)&pdata->rss_key; 394 int ret; 395 396 while (key_regs--) { 397 ret = xgbe_write_rss_reg(pdata, XGBE_RSS_HASH_KEY_TYPE, 398 key_regs, *key++); 399 if (ret) 400 return ret; 401 } 402 403 return 0; 404 } 405 406 static int xgbe_write_rss_lookup_table(struct xgbe_prv_data *pdata) 407 { 408 unsigned int i; 409 int ret; 410 411 for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++) { 412 ret = xgbe_write_rss_reg(pdata, 413 XGBE_RSS_LOOKUP_TABLE_TYPE, i, 414 pdata->rss_table[i]); 415 if (ret) 416 return ret; 417 } 418 419 return 0; 420 } 421 422 static int xgbe_set_rss_hash_key(struct xgbe_prv_data *pdata, const u8 *key) 423 { 424 memcpy(pdata->rss_key, key, sizeof(pdata->rss_key)); 425 426 return xgbe_write_rss_hash_key(pdata); 427 } 428 429 static int xgbe_set_rss_lookup_table(struct xgbe_prv_data *pdata, 430 const u32 *table) 431 { 432 unsigned int i; 433 434 for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++) 435 XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH, table[i]); 436 437 return xgbe_write_rss_lookup_table(pdata); 438 } 439 440 static int xgbe_enable_rss(struct xgbe_prv_data *pdata) 441 { 442 int ret; 443 444 if (!pdata->hw_feat.rss) 445 return -EOPNOTSUPP; 446 447 /* Program the hash key */ 448 ret = xgbe_write_rss_hash_key(pdata); 449 if (ret) 450 return ret; 451 452 /* Program the lookup table */ 453 ret = xgbe_write_rss_lookup_table(pdata); 454 if (ret) 455 return ret; 456 457 /* Set the RSS options */ 458 XGMAC_IOWRITE(pdata, MAC_RSSCR, pdata->rss_options); 459 460 /* Enable RSS */ 461 XGMAC_IOWRITE_BITS(pdata, MAC_RSSCR, RSSE, 1); 462 463 return 0; 464 } 465 466 static int xgbe_disable_rss(struct xgbe_prv_data *pdata) 467 { 468 if (!pdata->hw_feat.rss) 469 return -EOPNOTSUPP; 470 471 XGMAC_IOWRITE_BITS(pdata, MAC_RSSCR, RSSE, 0); 472 473 return 0; 474 } 475 476 static void xgbe_config_rss(struct xgbe_prv_data *pdata) 477 { 478 int ret; 479 480 if (!pdata->hw_feat.rss) 481 return; 482 483 if (pdata->netdev->features & NETIF_F_RXHASH) 484 ret = xgbe_enable_rss(pdata); 485 else 486 ret = xgbe_disable_rss(pdata); 487 488 if (ret) 489 netdev_err(pdata->netdev, 490 "error configuring RSS, RSS disabled\n"); 491 } 492 493 static int xgbe_disable_tx_flow_control(struct xgbe_prv_data *pdata) 494 { 495 unsigned int max_q_count, q_count; 496 unsigned int reg, reg_val; 497 unsigned int i; 498 499 /* Clear MTL flow control */ 500 for (i = 0; i < pdata->rx_q_count; i++) 501 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, 0); 502 503 /* Clear MAC flow control */ 504 max_q_count = XGMAC_MAX_FLOW_CONTROL_QUEUES; 505 q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count); 506 reg = MAC_Q0TFCR; 507 for (i = 0; i < q_count; i++) { 508 reg_val = XGMAC_IOREAD(pdata, reg); 509 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 0); 510 XGMAC_IOWRITE(pdata, reg, reg_val); 511 512 reg += MAC_QTFCR_INC; 513 } 514 515 return 0; 516 } 517 518 static int xgbe_enable_tx_flow_control(struct xgbe_prv_data *pdata) 519 { 520 unsigned int max_q_count, q_count; 521 unsigned int reg, reg_val; 522 unsigned int i; 523 524 /* Set MTL flow control */ 525 for (i = 0; i < pdata->rx_q_count; i++) 526 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, 1); 527 528 /* Set MAC flow control */ 529 max_q_count = XGMAC_MAX_FLOW_CONTROL_QUEUES; 530 q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count); 531 reg = MAC_Q0TFCR; 532 for (i = 0; i < q_count; i++) { 533 reg_val = XGMAC_IOREAD(pdata, reg); 534 535 /* Enable transmit flow control */ 536 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 1); 537 /* Set pause time */ 538 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, PT, 0xffff); 539 540 XGMAC_IOWRITE(pdata, reg, reg_val); 541 542 reg += MAC_QTFCR_INC; 543 } 544 545 return 0; 546 } 547 548 static int xgbe_disable_rx_flow_control(struct xgbe_prv_data *pdata) 549 { 550 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 0); 551 552 return 0; 553 } 554 555 static int xgbe_enable_rx_flow_control(struct xgbe_prv_data *pdata) 556 { 557 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 1); 558 559 return 0; 560 } 561 562 static int xgbe_config_tx_flow_control(struct xgbe_prv_data *pdata) 563 { 564 struct ieee_pfc *pfc = pdata->pfc; 565 566 if (pdata->tx_pause || (pfc && pfc->pfc_en)) 567 xgbe_enable_tx_flow_control(pdata); 568 else 569 xgbe_disable_tx_flow_control(pdata); 570 571 return 0; 572 } 573 574 static int xgbe_config_rx_flow_control(struct xgbe_prv_data *pdata) 575 { 576 struct ieee_pfc *pfc = pdata->pfc; 577 578 if (pdata->rx_pause || (pfc && pfc->pfc_en)) 579 xgbe_enable_rx_flow_control(pdata); 580 else 581 xgbe_disable_rx_flow_control(pdata); 582 583 return 0; 584 } 585 586 static void xgbe_config_flow_control(struct xgbe_prv_data *pdata) 587 { 588 struct ieee_pfc *pfc = pdata->pfc; 589 590 xgbe_config_tx_flow_control(pdata); 591 xgbe_config_rx_flow_control(pdata); 592 593 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 594 (pfc && pfc->pfc_en) ? 1 : 0); 595 } 596 597 static void xgbe_enable_dma_interrupts(struct xgbe_prv_data *pdata) 598 { 599 struct xgbe_channel *channel; 600 unsigned int dma_ch_isr, dma_ch_ier; 601 unsigned int i; 602 603 channel = pdata->channel; 604 for (i = 0; i < pdata->channel_count; i++, channel++) { 605 /* Clear all the interrupts which are set */ 606 dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR); 607 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr); 608 609 /* Clear all interrupt enable bits */ 610 dma_ch_ier = 0; 611 612 /* Enable following interrupts 613 * NIE - Normal Interrupt Summary Enable 614 * AIE - Abnormal Interrupt Summary Enable 615 * FBEE - Fatal Bus Error Enable 616 */ 617 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, NIE, 1); 618 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, AIE, 1); 619 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, FBEE, 1); 620 621 if (channel->tx_ring) { 622 /* Enable the following Tx interrupts 623 * TIE - Transmit Interrupt Enable (unless using 624 * per channel interrupts) 625 */ 626 if (!pdata->per_channel_irq) 627 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 1); 628 } 629 if (channel->rx_ring) { 630 /* Enable following Rx interrupts 631 * RBUE - Receive Buffer Unavailable Enable 632 * RIE - Receive Interrupt Enable (unless using 633 * per channel interrupts) 634 */ 635 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RBUE, 1); 636 if (!pdata->per_channel_irq) 637 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 1); 638 } 639 640 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, dma_ch_ier); 641 } 642 } 643 644 static void xgbe_enable_mtl_interrupts(struct xgbe_prv_data *pdata) 645 { 646 unsigned int mtl_q_isr; 647 unsigned int q_count, i; 648 649 q_count = max(pdata->hw_feat.tx_q_cnt, pdata->hw_feat.rx_q_cnt); 650 for (i = 0; i < q_count; i++) { 651 /* Clear all the interrupts which are set */ 652 mtl_q_isr = XGMAC_MTL_IOREAD(pdata, i, MTL_Q_ISR); 653 XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_ISR, mtl_q_isr); 654 655 /* No MTL interrupts to be enabled */ 656 XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_IER, 0); 657 } 658 } 659 660 static void xgbe_enable_mac_interrupts(struct xgbe_prv_data *pdata) 661 { 662 unsigned int mac_ier = 0; 663 664 /* Enable Timestamp interrupt */ 665 XGMAC_SET_BITS(mac_ier, MAC_IER, TSIE, 1); 666 667 XGMAC_IOWRITE(pdata, MAC_IER, mac_ier); 668 669 /* Enable all counter interrupts */ 670 XGMAC_IOWRITE_BITS(pdata, MMC_RIER, ALL_INTERRUPTS, 0xffffffff); 671 XGMAC_IOWRITE_BITS(pdata, MMC_TIER, ALL_INTERRUPTS, 0xffffffff); 672 } 673 674 static int xgbe_set_gmii_speed(struct xgbe_prv_data *pdata) 675 { 676 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, 0x3); 677 678 return 0; 679 } 680 681 static int xgbe_set_gmii_2500_speed(struct xgbe_prv_data *pdata) 682 { 683 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, 0x2); 684 685 return 0; 686 } 687 688 static int xgbe_set_xgmii_speed(struct xgbe_prv_data *pdata) 689 { 690 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, 0); 691 692 return 0; 693 } 694 695 static int xgbe_set_promiscuous_mode(struct xgbe_prv_data *pdata, 696 unsigned int enable) 697 { 698 unsigned int val = enable ? 1 : 0; 699 700 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PR) == val) 701 return 0; 702 703 DBGPR(" %s promiscuous mode\n", enable ? "entering" : "leaving"); 704 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, val); 705 706 return 0; 707 } 708 709 static int xgbe_set_all_multicast_mode(struct xgbe_prv_data *pdata, 710 unsigned int enable) 711 { 712 unsigned int val = enable ? 1 : 0; 713 714 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PM) == val) 715 return 0; 716 717 DBGPR(" %s allmulti mode\n", enable ? "entering" : "leaving"); 718 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, val); 719 720 return 0; 721 } 722 723 static void xgbe_set_mac_reg(struct xgbe_prv_data *pdata, 724 struct netdev_hw_addr *ha, unsigned int *mac_reg) 725 { 726 unsigned int mac_addr_hi, mac_addr_lo; 727 u8 *mac_addr; 728 729 mac_addr_lo = 0; 730 mac_addr_hi = 0; 731 732 if (ha) { 733 mac_addr = (u8 *)&mac_addr_lo; 734 mac_addr[0] = ha->addr[0]; 735 mac_addr[1] = ha->addr[1]; 736 mac_addr[2] = ha->addr[2]; 737 mac_addr[3] = ha->addr[3]; 738 mac_addr = (u8 *)&mac_addr_hi; 739 mac_addr[0] = ha->addr[4]; 740 mac_addr[1] = ha->addr[5]; 741 742 DBGPR(" adding mac address %pM at 0x%04x\n", ha->addr, 743 *mac_reg); 744 745 XGMAC_SET_BITS(mac_addr_hi, MAC_MACA1HR, AE, 1); 746 } 747 748 XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_hi); 749 *mac_reg += MAC_MACA_INC; 750 XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_lo); 751 *mac_reg += MAC_MACA_INC; 752 } 753 754 static void xgbe_set_mac_addn_addrs(struct xgbe_prv_data *pdata) 755 { 756 struct net_device *netdev = pdata->netdev; 757 struct netdev_hw_addr *ha; 758 unsigned int mac_reg; 759 unsigned int addn_macs; 760 761 mac_reg = MAC_MACA1HR; 762 addn_macs = pdata->hw_feat.addn_mac; 763 764 if (netdev_uc_count(netdev) > addn_macs) { 765 xgbe_set_promiscuous_mode(pdata, 1); 766 } else { 767 netdev_for_each_uc_addr(ha, netdev) { 768 xgbe_set_mac_reg(pdata, ha, &mac_reg); 769 addn_macs--; 770 } 771 772 if (netdev_mc_count(netdev) > addn_macs) { 773 xgbe_set_all_multicast_mode(pdata, 1); 774 } else { 775 netdev_for_each_mc_addr(ha, netdev) { 776 xgbe_set_mac_reg(pdata, ha, &mac_reg); 777 addn_macs--; 778 } 779 } 780 } 781 782 /* Clear remaining additional MAC address entries */ 783 while (addn_macs--) 784 xgbe_set_mac_reg(pdata, NULL, &mac_reg); 785 } 786 787 static void xgbe_set_mac_hash_table(struct xgbe_prv_data *pdata) 788 { 789 struct net_device *netdev = pdata->netdev; 790 struct netdev_hw_addr *ha; 791 unsigned int hash_reg; 792 unsigned int hash_table_shift, hash_table_count; 793 u32 hash_table[XGBE_MAC_HASH_TABLE_SIZE]; 794 u32 crc; 795 unsigned int i; 796 797 hash_table_shift = 26 - (pdata->hw_feat.hash_table_size >> 7); 798 hash_table_count = pdata->hw_feat.hash_table_size / 32; 799 memset(hash_table, 0, sizeof(hash_table)); 800 801 /* Build the MAC Hash Table register values */ 802 netdev_for_each_uc_addr(ha, netdev) { 803 crc = bitrev32(~crc32_le(~0, ha->addr, ETH_ALEN)); 804 crc >>= hash_table_shift; 805 hash_table[crc >> 5] |= (1 << (crc & 0x1f)); 806 } 807 808 netdev_for_each_mc_addr(ha, netdev) { 809 crc = bitrev32(~crc32_le(~0, ha->addr, ETH_ALEN)); 810 crc >>= hash_table_shift; 811 hash_table[crc >> 5] |= (1 << (crc & 0x1f)); 812 } 813 814 /* Set the MAC Hash Table registers */ 815 hash_reg = MAC_HTR0; 816 for (i = 0; i < hash_table_count; i++) { 817 XGMAC_IOWRITE(pdata, hash_reg, hash_table[i]); 818 hash_reg += MAC_HTR_INC; 819 } 820 } 821 822 static int xgbe_add_mac_addresses(struct xgbe_prv_data *pdata) 823 { 824 if (pdata->hw_feat.hash_table_size) 825 xgbe_set_mac_hash_table(pdata); 826 else 827 xgbe_set_mac_addn_addrs(pdata); 828 829 return 0; 830 } 831 832 static int xgbe_set_mac_address(struct xgbe_prv_data *pdata, u8 *addr) 833 { 834 unsigned int mac_addr_hi, mac_addr_lo; 835 836 mac_addr_hi = (addr[5] << 8) | (addr[4] << 0); 837 mac_addr_lo = (addr[3] << 24) | (addr[2] << 16) | 838 (addr[1] << 8) | (addr[0] << 0); 839 840 XGMAC_IOWRITE(pdata, MAC_MACA0HR, mac_addr_hi); 841 XGMAC_IOWRITE(pdata, MAC_MACA0LR, mac_addr_lo); 842 843 return 0; 844 } 845 846 static int xgbe_read_mmd_regs(struct xgbe_prv_data *pdata, int prtad, 847 int mmd_reg) 848 { 849 unsigned int mmd_address; 850 int mmd_data; 851 852 if (mmd_reg & MII_ADDR_C45) 853 mmd_address = mmd_reg & ~MII_ADDR_C45; 854 else 855 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); 856 857 /* The PCS registers are accessed using mmio. The underlying APB3 858 * management interface uses indirect addressing to access the MMD 859 * register sets. This requires accessing of the PCS register in two 860 * phases, an address phase and a data phase. 861 * 862 * The mmio interface is based on 32-bit offsets and values. All 863 * register offsets must therefore be adjusted by left shifting the 864 * offset 2 bits and reading 32 bits of data. 865 */ 866 mutex_lock(&pdata->xpcs_mutex); 867 XPCS_IOWRITE(pdata, PCS_MMD_SELECT << 2, mmd_address >> 8); 868 mmd_data = XPCS_IOREAD(pdata, (mmd_address & 0xff) << 2); 869 mutex_unlock(&pdata->xpcs_mutex); 870 871 return mmd_data; 872 } 873 874 static void xgbe_write_mmd_regs(struct xgbe_prv_data *pdata, int prtad, 875 int mmd_reg, int mmd_data) 876 { 877 unsigned int mmd_address; 878 879 if (mmd_reg & MII_ADDR_C45) 880 mmd_address = mmd_reg & ~MII_ADDR_C45; 881 else 882 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); 883 884 /* The PCS registers are accessed using mmio. The underlying APB3 885 * management interface uses indirect addressing to access the MMD 886 * register sets. This requires accessing of the PCS register in two 887 * phases, an address phase and a data phase. 888 * 889 * The mmio interface is based on 32-bit offsets and values. All 890 * register offsets must therefore be adjusted by left shifting the 891 * offset 2 bits and reading 32 bits of data. 892 */ 893 mutex_lock(&pdata->xpcs_mutex); 894 XPCS_IOWRITE(pdata, PCS_MMD_SELECT << 2, mmd_address >> 8); 895 XPCS_IOWRITE(pdata, (mmd_address & 0xff) << 2, mmd_data); 896 mutex_unlock(&pdata->xpcs_mutex); 897 } 898 899 static int xgbe_tx_complete(struct xgbe_ring_desc *rdesc) 900 { 901 return !XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN); 902 } 903 904 static int xgbe_disable_rx_csum(struct xgbe_prv_data *pdata) 905 { 906 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 0); 907 908 return 0; 909 } 910 911 static int xgbe_enable_rx_csum(struct xgbe_prv_data *pdata) 912 { 913 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 1); 914 915 return 0; 916 } 917 918 static int xgbe_enable_rx_vlan_stripping(struct xgbe_prv_data *pdata) 919 { 920 /* Put the VLAN tag in the Rx descriptor */ 921 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLRXS, 1); 922 923 /* Don't check the VLAN type */ 924 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, DOVLTC, 1); 925 926 /* Check only C-TAG (0x8100) packets */ 927 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ERSVLM, 0); 928 929 /* Don't consider an S-TAG (0x88A8) packet as a VLAN packet */ 930 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ESVL, 0); 931 932 /* Enable VLAN tag stripping */ 933 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0x3); 934 935 return 0; 936 } 937 938 static int xgbe_disable_rx_vlan_stripping(struct xgbe_prv_data *pdata) 939 { 940 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0); 941 942 return 0; 943 } 944 945 static int xgbe_enable_rx_vlan_filtering(struct xgbe_prv_data *pdata) 946 { 947 /* Enable VLAN filtering */ 948 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 1); 949 950 /* Enable VLAN Hash Table filtering */ 951 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTHM, 1); 952 953 /* Disable VLAN tag inverse matching */ 954 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTIM, 0); 955 956 /* Only filter on the lower 12-bits of the VLAN tag */ 957 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ETV, 1); 958 959 /* In order for the VLAN Hash Table filtering to be effective, 960 * the VLAN tag identifier in the VLAN Tag Register must not 961 * be zero. Set the VLAN tag identifier to "1" to enable the 962 * VLAN Hash Table filtering. This implies that a VLAN tag of 963 * 1 will always pass filtering. 964 */ 965 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VL, 1); 966 967 return 0; 968 } 969 970 static int xgbe_disable_rx_vlan_filtering(struct xgbe_prv_data *pdata) 971 { 972 /* Disable VLAN filtering */ 973 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 0); 974 975 return 0; 976 } 977 978 #ifndef CRCPOLY_LE 979 #define CRCPOLY_LE 0xedb88320 980 #endif 981 static u32 xgbe_vid_crc32_le(__le16 vid_le) 982 { 983 u32 poly = CRCPOLY_LE; 984 u32 crc = ~0; 985 u32 temp = 0; 986 unsigned char *data = (unsigned char *)&vid_le; 987 unsigned char data_byte = 0; 988 int i, bits; 989 990 bits = get_bitmask_order(VLAN_VID_MASK); 991 for (i = 0; i < bits; i++) { 992 if ((i % 8) == 0) 993 data_byte = data[i / 8]; 994 995 temp = ((crc & 1) ^ data_byte) & 1; 996 crc >>= 1; 997 data_byte >>= 1; 998 999 if (temp) 1000 crc ^= poly; 1001 } 1002 1003 return crc; 1004 } 1005 1006 static int xgbe_update_vlan_hash_table(struct xgbe_prv_data *pdata) 1007 { 1008 u32 crc; 1009 u16 vid; 1010 __le16 vid_le; 1011 u16 vlan_hash_table = 0; 1012 1013 /* Generate the VLAN Hash Table value */ 1014 for_each_set_bit(vid, pdata->active_vlans, VLAN_N_VID) { 1015 /* Get the CRC32 value of the VLAN ID */ 1016 vid_le = cpu_to_le16(vid); 1017 crc = bitrev32(~xgbe_vid_crc32_le(vid_le)) >> 28; 1018 1019 vlan_hash_table |= (1 << crc); 1020 } 1021 1022 /* Set the VLAN Hash Table filtering register */ 1023 XGMAC_IOWRITE_BITS(pdata, MAC_VLANHTR, VLHT, vlan_hash_table); 1024 1025 return 0; 1026 } 1027 1028 static void xgbe_tx_desc_reset(struct xgbe_ring_data *rdata) 1029 { 1030 struct xgbe_ring_desc *rdesc = rdata->rdesc; 1031 1032 /* Reset the Tx descriptor 1033 * Set buffer 1 (lo) address to zero 1034 * Set buffer 1 (hi) address to zero 1035 * Reset all other control bits (IC, TTSE, B2L & B1L) 1036 * Reset all other control bits (OWN, CTXT, FD, LD, CPC, CIC, etc) 1037 */ 1038 rdesc->desc0 = 0; 1039 rdesc->desc1 = 0; 1040 rdesc->desc2 = 0; 1041 rdesc->desc3 = 0; 1042 1043 /* Make sure ownership is written to the descriptor */ 1044 wmb(); 1045 } 1046 1047 static void xgbe_tx_desc_init(struct xgbe_channel *channel) 1048 { 1049 struct xgbe_ring *ring = channel->tx_ring; 1050 struct xgbe_ring_data *rdata; 1051 int i; 1052 int start_index = ring->cur; 1053 1054 DBGPR("-->tx_desc_init\n"); 1055 1056 /* Initialze all descriptors */ 1057 for (i = 0; i < ring->rdesc_count; i++) { 1058 rdata = XGBE_GET_DESC_DATA(ring, i); 1059 1060 /* Initialize Tx descriptor */ 1061 xgbe_tx_desc_reset(rdata); 1062 } 1063 1064 /* Update the total number of Tx descriptors */ 1065 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDRLR, ring->rdesc_count - 1); 1066 1067 /* Update the starting address of descriptor ring */ 1068 rdata = XGBE_GET_DESC_DATA(ring, start_index); 1069 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDLR_HI, 1070 upper_32_bits(rdata->rdesc_dma)); 1071 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDLR_LO, 1072 lower_32_bits(rdata->rdesc_dma)); 1073 1074 DBGPR("<--tx_desc_init\n"); 1075 } 1076 1077 static void xgbe_rx_desc_reset(struct xgbe_ring_data *rdata) 1078 { 1079 struct xgbe_ring_desc *rdesc = rdata->rdesc; 1080 1081 /* Reset the Rx descriptor 1082 * Set buffer 1 (lo) address to header dma address (lo) 1083 * Set buffer 1 (hi) address to header dma address (hi) 1084 * Set buffer 2 (lo) address to buffer dma address (lo) 1085 * Set buffer 2 (hi) address to buffer dma address (hi) and 1086 * set control bits OWN and INTE 1087 */ 1088 rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->rx.hdr.dma)); 1089 rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->rx.hdr.dma)); 1090 rdesc->desc2 = cpu_to_le32(lower_32_bits(rdata->rx.buf.dma)); 1091 rdesc->desc3 = cpu_to_le32(upper_32_bits(rdata->rx.buf.dma)); 1092 1093 XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, INTE, 1094 rdata->interrupt ? 1 : 0); 1095 1096 /* Since the Rx DMA engine is likely running, make sure everything 1097 * is written to the descriptor(s) before setting the OWN bit 1098 * for the descriptor 1099 */ 1100 wmb(); 1101 1102 XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN, 1); 1103 1104 /* Make sure ownership is written to the descriptor */ 1105 wmb(); 1106 } 1107 1108 static void xgbe_rx_desc_init(struct xgbe_channel *channel) 1109 { 1110 struct xgbe_prv_data *pdata = channel->pdata; 1111 struct xgbe_ring *ring = channel->rx_ring; 1112 struct xgbe_ring_data *rdata; 1113 unsigned int start_index = ring->cur; 1114 unsigned int rx_coalesce, rx_frames; 1115 unsigned int i; 1116 1117 DBGPR("-->rx_desc_init\n"); 1118 1119 rx_coalesce = (pdata->rx_riwt || pdata->rx_frames) ? 1 : 0; 1120 rx_frames = pdata->rx_frames; 1121 1122 /* Initialize all descriptors */ 1123 for (i = 0; i < ring->rdesc_count; i++) { 1124 rdata = XGBE_GET_DESC_DATA(ring, i); 1125 1126 /* Set interrupt on completion bit as appropriate */ 1127 if (rx_coalesce && (!rx_frames || ((i + 1) % rx_frames))) 1128 rdata->interrupt = 0; 1129 else 1130 rdata->interrupt = 1; 1131 1132 /* Initialize Rx descriptor */ 1133 xgbe_rx_desc_reset(rdata); 1134 } 1135 1136 /* Update the total number of Rx descriptors */ 1137 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDRLR, ring->rdesc_count - 1); 1138 1139 /* Update the starting address of descriptor ring */ 1140 rdata = XGBE_GET_DESC_DATA(ring, start_index); 1141 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDLR_HI, 1142 upper_32_bits(rdata->rdesc_dma)); 1143 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDLR_LO, 1144 lower_32_bits(rdata->rdesc_dma)); 1145 1146 /* Update the Rx Descriptor Tail Pointer */ 1147 rdata = XGBE_GET_DESC_DATA(ring, start_index + ring->rdesc_count - 1); 1148 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO, 1149 lower_32_bits(rdata->rdesc_dma)); 1150 1151 DBGPR("<--rx_desc_init\n"); 1152 } 1153 1154 static void xgbe_update_tstamp_addend(struct xgbe_prv_data *pdata, 1155 unsigned int addend) 1156 { 1157 /* Set the addend register value and tell the device */ 1158 XGMAC_IOWRITE(pdata, MAC_TSAR, addend); 1159 XGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSADDREG, 1); 1160 1161 /* Wait for addend update to complete */ 1162 while (XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSADDREG)) 1163 udelay(5); 1164 } 1165 1166 static void xgbe_set_tstamp_time(struct xgbe_prv_data *pdata, unsigned int sec, 1167 unsigned int nsec) 1168 { 1169 /* Set the time values and tell the device */ 1170 XGMAC_IOWRITE(pdata, MAC_STSUR, sec); 1171 XGMAC_IOWRITE(pdata, MAC_STNUR, nsec); 1172 XGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSINIT, 1); 1173 1174 /* Wait for time update to complete */ 1175 while (XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSINIT)) 1176 udelay(5); 1177 } 1178 1179 static u64 xgbe_get_tstamp_time(struct xgbe_prv_data *pdata) 1180 { 1181 u64 nsec; 1182 1183 nsec = XGMAC_IOREAD(pdata, MAC_STSR); 1184 nsec *= NSEC_PER_SEC; 1185 nsec += XGMAC_IOREAD(pdata, MAC_STNR); 1186 1187 return nsec; 1188 } 1189 1190 static u64 xgbe_get_tx_tstamp(struct xgbe_prv_data *pdata) 1191 { 1192 unsigned int tx_snr; 1193 u64 nsec; 1194 1195 tx_snr = XGMAC_IOREAD(pdata, MAC_TXSNR); 1196 if (XGMAC_GET_BITS(tx_snr, MAC_TXSNR, TXTSSTSMIS)) 1197 return 0; 1198 1199 nsec = XGMAC_IOREAD(pdata, MAC_TXSSR); 1200 nsec *= NSEC_PER_SEC; 1201 nsec += tx_snr; 1202 1203 return nsec; 1204 } 1205 1206 static void xgbe_get_rx_tstamp(struct xgbe_packet_data *packet, 1207 struct xgbe_ring_desc *rdesc) 1208 { 1209 u64 nsec; 1210 1211 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_CONTEXT_DESC3, TSA) && 1212 !XGMAC_GET_BITS_LE(rdesc->desc3, RX_CONTEXT_DESC3, TSD)) { 1213 nsec = le32_to_cpu(rdesc->desc1); 1214 nsec <<= 32; 1215 nsec |= le32_to_cpu(rdesc->desc0); 1216 if (nsec != 0xffffffffffffffffULL) { 1217 packet->rx_tstamp = nsec; 1218 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1219 RX_TSTAMP, 1); 1220 } 1221 } 1222 } 1223 1224 static int xgbe_config_tstamp(struct xgbe_prv_data *pdata, 1225 unsigned int mac_tscr) 1226 { 1227 /* Set one nano-second accuracy */ 1228 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCTRLSSR, 1); 1229 1230 /* Set fine timestamp update */ 1231 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCFUPDT, 1); 1232 1233 /* Overwrite earlier timestamps */ 1234 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TXTSSTSM, 1); 1235 1236 XGMAC_IOWRITE(pdata, MAC_TSCR, mac_tscr); 1237 1238 /* Exit if timestamping is not enabled */ 1239 if (!XGMAC_GET_BITS(mac_tscr, MAC_TSCR, TSENA)) 1240 return 0; 1241 1242 /* Initialize time registers */ 1243 XGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SSINC, XGBE_TSTAMP_SSINC); 1244 XGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SNSINC, XGBE_TSTAMP_SNSINC); 1245 xgbe_update_tstamp_addend(pdata, pdata->tstamp_addend); 1246 xgbe_set_tstamp_time(pdata, 0, 0); 1247 1248 /* Initialize the timecounter */ 1249 timecounter_init(&pdata->tstamp_tc, &pdata->tstamp_cc, 1250 ktime_to_ns(ktime_get_real())); 1251 1252 return 0; 1253 } 1254 1255 static void xgbe_config_dcb_tc(struct xgbe_prv_data *pdata) 1256 { 1257 struct ieee_ets *ets = pdata->ets; 1258 unsigned int total_weight, min_weight, weight; 1259 unsigned int i; 1260 1261 if (!ets) 1262 return; 1263 1264 /* Set Tx to deficit weighted round robin scheduling algorithm (when 1265 * traffic class is using ETS algorithm) 1266 */ 1267 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_DWRR); 1268 1269 /* Set Traffic Class algorithms */ 1270 total_weight = pdata->netdev->mtu * pdata->hw_feat.tc_cnt; 1271 min_weight = total_weight / 100; 1272 if (!min_weight) 1273 min_weight = 1; 1274 1275 for (i = 0; i < pdata->hw_feat.tc_cnt; i++) { 1276 switch (ets->tc_tsa[i]) { 1277 case IEEE_8021QAZ_TSA_STRICT: 1278 DBGPR(" TC%u using SP\n", i); 1279 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA, 1280 MTL_TSA_SP); 1281 break; 1282 case IEEE_8021QAZ_TSA_ETS: 1283 weight = total_weight * ets->tc_tx_bw[i] / 100; 1284 weight = clamp(weight, min_weight, total_weight); 1285 1286 DBGPR(" TC%u using DWRR (weight %u)\n", i, weight); 1287 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA, 1288 MTL_TSA_ETS); 1289 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW, 1290 weight); 1291 break; 1292 } 1293 } 1294 } 1295 1296 static void xgbe_config_dcb_pfc(struct xgbe_prv_data *pdata) 1297 { 1298 struct ieee_pfc *pfc = pdata->pfc; 1299 struct ieee_ets *ets = pdata->ets; 1300 unsigned int mask, reg, reg_val; 1301 unsigned int tc, prio; 1302 1303 if (!pfc || !ets) 1304 return; 1305 1306 for (tc = 0; tc < pdata->hw_feat.tc_cnt; tc++) { 1307 mask = 0; 1308 for (prio = 0; prio < IEEE_8021QAZ_MAX_TCS; prio++) { 1309 if ((pfc->pfc_en & (1 << prio)) && 1310 (ets->prio_tc[prio] == tc)) 1311 mask |= (1 << prio); 1312 } 1313 mask &= 0xff; 1314 1315 DBGPR(" TC%u PFC mask=%#x\n", tc, mask); 1316 reg = MTL_TCPM0R + (MTL_TCPM_INC * (tc / MTL_TCPM_TC_PER_REG)); 1317 reg_val = XGMAC_IOREAD(pdata, reg); 1318 1319 reg_val &= ~(0xff << ((tc % MTL_TCPM_TC_PER_REG) << 3)); 1320 reg_val |= (mask << ((tc % MTL_TCPM_TC_PER_REG) << 3)); 1321 1322 XGMAC_IOWRITE(pdata, reg, reg_val); 1323 } 1324 1325 xgbe_config_flow_control(pdata); 1326 } 1327 1328 static void xgbe_tx_start_xmit(struct xgbe_channel *channel, 1329 struct xgbe_ring *ring) 1330 { 1331 struct xgbe_prv_data *pdata = channel->pdata; 1332 struct xgbe_ring_data *rdata; 1333 1334 /* Issue a poll command to Tx DMA by writing address 1335 * of next immediate free descriptor */ 1336 rdata = XGBE_GET_DESC_DATA(ring, ring->cur); 1337 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDTR_LO, 1338 lower_32_bits(rdata->rdesc_dma)); 1339 1340 /* Start the Tx coalescing timer */ 1341 if (pdata->tx_usecs && !channel->tx_timer_active) { 1342 channel->tx_timer_active = 1; 1343 hrtimer_start(&channel->tx_timer, 1344 ktime_set(0, pdata->tx_usecs * NSEC_PER_USEC), 1345 HRTIMER_MODE_REL); 1346 } 1347 1348 ring->tx.xmit_more = 0; 1349 } 1350 1351 static void xgbe_dev_xmit(struct xgbe_channel *channel) 1352 { 1353 struct xgbe_prv_data *pdata = channel->pdata; 1354 struct xgbe_ring *ring = channel->tx_ring; 1355 struct xgbe_ring_data *rdata; 1356 struct xgbe_ring_desc *rdesc; 1357 struct xgbe_packet_data *packet = &ring->packet_data; 1358 unsigned int csum, tso, vlan; 1359 unsigned int tso_context, vlan_context; 1360 unsigned int tx_set_ic; 1361 int start_index = ring->cur; 1362 int i; 1363 1364 DBGPR("-->xgbe_dev_xmit\n"); 1365 1366 csum = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, 1367 CSUM_ENABLE); 1368 tso = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, 1369 TSO_ENABLE); 1370 vlan = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, 1371 VLAN_CTAG); 1372 1373 if (tso && (packet->mss != ring->tx.cur_mss)) 1374 tso_context = 1; 1375 else 1376 tso_context = 0; 1377 1378 if (vlan && (packet->vlan_ctag != ring->tx.cur_vlan_ctag)) 1379 vlan_context = 1; 1380 else 1381 vlan_context = 0; 1382 1383 /* Determine if an interrupt should be generated for this Tx: 1384 * Interrupt: 1385 * - Tx frame count exceeds the frame count setting 1386 * - Addition of Tx frame count to the frame count since the 1387 * last interrupt was set exceeds the frame count setting 1388 * No interrupt: 1389 * - No frame count setting specified (ethtool -C ethX tx-frames 0) 1390 * - Addition of Tx frame count to the frame count since the 1391 * last interrupt was set does not exceed the frame count setting 1392 */ 1393 ring->coalesce_count += packet->tx_packets; 1394 if (!pdata->tx_frames) 1395 tx_set_ic = 0; 1396 else if (packet->tx_packets > pdata->tx_frames) 1397 tx_set_ic = 1; 1398 else if ((ring->coalesce_count % pdata->tx_frames) < 1399 packet->tx_packets) 1400 tx_set_ic = 1; 1401 else 1402 tx_set_ic = 0; 1403 1404 rdata = XGBE_GET_DESC_DATA(ring, ring->cur); 1405 rdesc = rdata->rdesc; 1406 1407 /* Create a context descriptor if this is a TSO packet */ 1408 if (tso_context || vlan_context) { 1409 if (tso_context) { 1410 DBGPR(" TSO context descriptor, mss=%u\n", 1411 packet->mss); 1412 1413 /* Set the MSS size */ 1414 XGMAC_SET_BITS_LE(rdesc->desc2, TX_CONTEXT_DESC2, 1415 MSS, packet->mss); 1416 1417 /* Mark it as a CONTEXT descriptor */ 1418 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, 1419 CTXT, 1); 1420 1421 /* Indicate this descriptor contains the MSS */ 1422 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, 1423 TCMSSV, 1); 1424 1425 ring->tx.cur_mss = packet->mss; 1426 } 1427 1428 if (vlan_context) { 1429 DBGPR(" VLAN context descriptor, ctag=%u\n", 1430 packet->vlan_ctag); 1431 1432 /* Mark it as a CONTEXT descriptor */ 1433 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, 1434 CTXT, 1); 1435 1436 /* Set the VLAN tag */ 1437 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, 1438 VT, packet->vlan_ctag); 1439 1440 /* Indicate this descriptor contains the VLAN tag */ 1441 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, 1442 VLTV, 1); 1443 1444 ring->tx.cur_vlan_ctag = packet->vlan_ctag; 1445 } 1446 1447 ring->cur++; 1448 rdata = XGBE_GET_DESC_DATA(ring, ring->cur); 1449 rdesc = rdata->rdesc; 1450 } 1451 1452 /* Update buffer address (for TSO this is the header) */ 1453 rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->skb_dma)); 1454 rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->skb_dma)); 1455 1456 /* Update the buffer length */ 1457 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, HL_B1L, 1458 rdata->skb_dma_len); 1459 1460 /* VLAN tag insertion check */ 1461 if (vlan) 1462 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, VTIR, 1463 TX_NORMAL_DESC2_VLAN_INSERT); 1464 1465 /* Timestamp enablement check */ 1466 if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP)) 1467 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, TTSE, 1); 1468 1469 /* Mark it as First Descriptor */ 1470 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, FD, 1); 1471 1472 /* Mark it as a NORMAL descriptor */ 1473 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT, 0); 1474 1475 /* Set OWN bit if not the first descriptor */ 1476 if (ring->cur != start_index) 1477 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1); 1478 1479 if (tso) { 1480 /* Enable TSO */ 1481 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TSE, 1); 1482 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TCPPL, 1483 packet->tcp_payload_len); 1484 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TCPHDRLEN, 1485 packet->tcp_header_len / 4); 1486 } else { 1487 /* Enable CRC and Pad Insertion */ 1488 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CPC, 0); 1489 1490 /* Enable HW CSUM */ 1491 if (csum) 1492 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, 1493 CIC, 0x3); 1494 1495 /* Set the total length to be transmitted */ 1496 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, FL, 1497 packet->length); 1498 } 1499 1500 for (i = ring->cur - start_index + 1; i < packet->rdesc_count; i++) { 1501 ring->cur++; 1502 rdata = XGBE_GET_DESC_DATA(ring, ring->cur); 1503 rdesc = rdata->rdesc; 1504 1505 /* Update buffer address */ 1506 rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->skb_dma)); 1507 rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->skb_dma)); 1508 1509 /* Update the buffer length */ 1510 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, HL_B1L, 1511 rdata->skb_dma_len); 1512 1513 /* Set OWN bit */ 1514 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1); 1515 1516 /* Mark it as NORMAL descriptor */ 1517 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT, 0); 1518 1519 /* Enable HW CSUM */ 1520 if (csum) 1521 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, 1522 CIC, 0x3); 1523 } 1524 1525 /* Set LAST bit for the last descriptor */ 1526 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, LD, 1); 1527 1528 /* Set IC bit based on Tx coalescing settings */ 1529 if (tx_set_ic) 1530 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, IC, 1); 1531 1532 /* Save the Tx info to report back during cleanup */ 1533 rdata->tx.packets = packet->tx_packets; 1534 rdata->tx.bytes = packet->tx_bytes; 1535 1536 /* In case the Tx DMA engine is running, make sure everything 1537 * is written to the descriptor(s) before setting the OWN bit 1538 * for the first descriptor 1539 */ 1540 wmb(); 1541 1542 /* Set OWN bit for the first descriptor */ 1543 rdata = XGBE_GET_DESC_DATA(ring, start_index); 1544 rdesc = rdata->rdesc; 1545 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1); 1546 1547 #ifdef XGMAC_ENABLE_TX_DESC_DUMP 1548 xgbe_dump_tx_desc(ring, start_index, packet->rdesc_count, 1); 1549 #endif 1550 1551 /* Make sure ownership is written to the descriptor */ 1552 wmb(); 1553 1554 ring->cur++; 1555 if (!packet->skb->xmit_more || 1556 netif_xmit_stopped(netdev_get_tx_queue(pdata->netdev, 1557 channel->queue_index))) 1558 xgbe_tx_start_xmit(channel, ring); 1559 else 1560 ring->tx.xmit_more = 1; 1561 1562 DBGPR(" %s: descriptors %u to %u written\n", 1563 channel->name, start_index & (ring->rdesc_count - 1), 1564 (ring->cur - 1) & (ring->rdesc_count - 1)); 1565 1566 DBGPR("<--xgbe_dev_xmit\n"); 1567 } 1568 1569 static int xgbe_dev_read(struct xgbe_channel *channel) 1570 { 1571 struct xgbe_ring *ring = channel->rx_ring; 1572 struct xgbe_ring_data *rdata; 1573 struct xgbe_ring_desc *rdesc; 1574 struct xgbe_packet_data *packet = &ring->packet_data; 1575 struct net_device *netdev = channel->pdata->netdev; 1576 unsigned int err, etlt, l34t; 1577 1578 DBGPR("-->xgbe_dev_read: cur = %d\n", ring->cur); 1579 1580 rdata = XGBE_GET_DESC_DATA(ring, ring->cur); 1581 rdesc = rdata->rdesc; 1582 1583 /* Check for data availability */ 1584 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN)) 1585 return 1; 1586 1587 /* Make sure descriptor fields are read after reading the OWN bit */ 1588 rmb(); 1589 1590 #ifdef XGMAC_ENABLE_RX_DESC_DUMP 1591 xgbe_dump_rx_desc(ring, rdesc, ring->cur); 1592 #endif 1593 1594 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CTXT)) { 1595 /* Timestamp Context Descriptor */ 1596 xgbe_get_rx_tstamp(packet, rdesc); 1597 1598 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1599 CONTEXT, 1); 1600 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1601 CONTEXT_NEXT, 0); 1602 return 0; 1603 } 1604 1605 /* Normal Descriptor, be sure Context Descriptor bit is off */ 1606 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, CONTEXT, 0); 1607 1608 /* Indicate if a Context Descriptor is next */ 1609 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CDA)) 1610 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1611 CONTEXT_NEXT, 1); 1612 1613 /* Get the header length */ 1614 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, FD)) 1615 rdata->rx.hdr_len = XGMAC_GET_BITS_LE(rdesc->desc2, 1616 RX_NORMAL_DESC2, HL); 1617 1618 /* Get the RSS hash */ 1619 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, RSV)) { 1620 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1621 RSS_HASH, 1); 1622 1623 packet->rss_hash = le32_to_cpu(rdesc->desc1); 1624 1625 l34t = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, L34T); 1626 switch (l34t) { 1627 case RX_DESC3_L34T_IPV4_TCP: 1628 case RX_DESC3_L34T_IPV4_UDP: 1629 case RX_DESC3_L34T_IPV6_TCP: 1630 case RX_DESC3_L34T_IPV6_UDP: 1631 packet->rss_hash_type = PKT_HASH_TYPE_L4; 1632 break; 1633 default: 1634 packet->rss_hash_type = PKT_HASH_TYPE_L3; 1635 } 1636 } 1637 1638 /* Get the packet length */ 1639 rdata->rx.len = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, PL); 1640 1641 if (!XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, LD)) { 1642 /* Not all the data has been transferred for this packet */ 1643 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1644 INCOMPLETE, 1); 1645 return 0; 1646 } 1647 1648 /* This is the last of the data for this packet */ 1649 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1650 INCOMPLETE, 0); 1651 1652 /* Set checksum done indicator as appropriate */ 1653 if (channel->pdata->netdev->features & NETIF_F_RXCSUM) 1654 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1655 CSUM_DONE, 1); 1656 1657 /* Check for errors (only valid in last descriptor) */ 1658 err = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ES); 1659 etlt = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ETLT); 1660 DBGPR(" err=%u, etlt=%#x\n", err, etlt); 1661 1662 if (!err || !etlt) { 1663 /* No error if err is 0 or etlt is 0 */ 1664 if ((etlt == 0x09) && 1665 (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)) { 1666 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1667 VLAN_CTAG, 1); 1668 packet->vlan_ctag = XGMAC_GET_BITS_LE(rdesc->desc0, 1669 RX_NORMAL_DESC0, 1670 OVT); 1671 DBGPR(" vlan-ctag=0x%04x\n", packet->vlan_ctag); 1672 } 1673 } else { 1674 if ((etlt == 0x05) || (etlt == 0x06)) 1675 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1676 CSUM_DONE, 0); 1677 else 1678 XGMAC_SET_BITS(packet->errors, RX_PACKET_ERRORS, 1679 FRAME, 1); 1680 } 1681 1682 DBGPR("<--xgbe_dev_read: %s - descriptor=%u (cur=%d)\n", channel->name, 1683 ring->cur & (ring->rdesc_count - 1), ring->cur); 1684 1685 return 0; 1686 } 1687 1688 static int xgbe_is_context_desc(struct xgbe_ring_desc *rdesc) 1689 { 1690 /* Rx and Tx share CTXT bit, so check TDES3.CTXT bit */ 1691 return XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT); 1692 } 1693 1694 static int xgbe_is_last_desc(struct xgbe_ring_desc *rdesc) 1695 { 1696 /* Rx and Tx share LD bit, so check TDES3.LD bit */ 1697 return XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, LD); 1698 } 1699 1700 static int xgbe_enable_int(struct xgbe_channel *channel, 1701 enum xgbe_int int_id) 1702 { 1703 unsigned int dma_ch_ier; 1704 1705 dma_ch_ier = XGMAC_DMA_IOREAD(channel, DMA_CH_IER); 1706 1707 switch (int_id) { 1708 case XGMAC_INT_DMA_CH_SR_TI: 1709 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 1); 1710 break; 1711 case XGMAC_INT_DMA_CH_SR_TPS: 1712 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TXSE, 1); 1713 break; 1714 case XGMAC_INT_DMA_CH_SR_TBU: 1715 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TBUE, 1); 1716 break; 1717 case XGMAC_INT_DMA_CH_SR_RI: 1718 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 1); 1719 break; 1720 case XGMAC_INT_DMA_CH_SR_RBU: 1721 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RBUE, 1); 1722 break; 1723 case XGMAC_INT_DMA_CH_SR_RPS: 1724 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RSE, 1); 1725 break; 1726 case XGMAC_INT_DMA_CH_SR_TI_RI: 1727 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 1); 1728 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 1); 1729 break; 1730 case XGMAC_INT_DMA_CH_SR_FBE: 1731 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, FBEE, 1); 1732 break; 1733 case XGMAC_INT_DMA_ALL: 1734 dma_ch_ier |= channel->saved_ier; 1735 break; 1736 default: 1737 return -1; 1738 } 1739 1740 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, dma_ch_ier); 1741 1742 return 0; 1743 } 1744 1745 static int xgbe_disable_int(struct xgbe_channel *channel, 1746 enum xgbe_int int_id) 1747 { 1748 unsigned int dma_ch_ier; 1749 1750 dma_ch_ier = XGMAC_DMA_IOREAD(channel, DMA_CH_IER); 1751 1752 switch (int_id) { 1753 case XGMAC_INT_DMA_CH_SR_TI: 1754 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 0); 1755 break; 1756 case XGMAC_INT_DMA_CH_SR_TPS: 1757 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TXSE, 0); 1758 break; 1759 case XGMAC_INT_DMA_CH_SR_TBU: 1760 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TBUE, 0); 1761 break; 1762 case XGMAC_INT_DMA_CH_SR_RI: 1763 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 0); 1764 break; 1765 case XGMAC_INT_DMA_CH_SR_RBU: 1766 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RBUE, 0); 1767 break; 1768 case XGMAC_INT_DMA_CH_SR_RPS: 1769 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RSE, 0); 1770 break; 1771 case XGMAC_INT_DMA_CH_SR_TI_RI: 1772 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 0); 1773 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 0); 1774 break; 1775 case XGMAC_INT_DMA_CH_SR_FBE: 1776 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, FBEE, 0); 1777 break; 1778 case XGMAC_INT_DMA_ALL: 1779 channel->saved_ier = dma_ch_ier & XGBE_DMA_INTERRUPT_MASK; 1780 dma_ch_ier &= ~XGBE_DMA_INTERRUPT_MASK; 1781 break; 1782 default: 1783 return -1; 1784 } 1785 1786 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, dma_ch_ier); 1787 1788 return 0; 1789 } 1790 1791 static int xgbe_exit(struct xgbe_prv_data *pdata) 1792 { 1793 unsigned int count = 2000; 1794 1795 DBGPR("-->xgbe_exit\n"); 1796 1797 /* Issue a software reset */ 1798 XGMAC_IOWRITE_BITS(pdata, DMA_MR, SWR, 1); 1799 usleep_range(10, 15); 1800 1801 /* Poll Until Poll Condition */ 1802 while (count-- && XGMAC_IOREAD_BITS(pdata, DMA_MR, SWR)) 1803 usleep_range(500, 600); 1804 1805 if (!count) 1806 return -EBUSY; 1807 1808 DBGPR("<--xgbe_exit\n"); 1809 1810 return 0; 1811 } 1812 1813 static int xgbe_flush_tx_queues(struct xgbe_prv_data *pdata) 1814 { 1815 unsigned int i, count; 1816 1817 if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) < 0x21) 1818 return 0; 1819 1820 for (i = 0; i < pdata->tx_q_count; i++) 1821 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, FTQ, 1); 1822 1823 /* Poll Until Poll Condition */ 1824 for (i = 0; i < pdata->tx_q_count; i++) { 1825 count = 2000; 1826 while (count-- && XGMAC_MTL_IOREAD_BITS(pdata, i, 1827 MTL_Q_TQOMR, FTQ)) 1828 usleep_range(500, 600); 1829 1830 if (!count) 1831 return -EBUSY; 1832 } 1833 1834 return 0; 1835 } 1836 1837 static void xgbe_config_dma_bus(struct xgbe_prv_data *pdata) 1838 { 1839 /* Set enhanced addressing mode */ 1840 XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, EAME, 1); 1841 1842 /* Set the System Bus mode */ 1843 XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, UNDEF, 1); 1844 XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, BLEN_256, 1); 1845 } 1846 1847 static void xgbe_config_dma_cache(struct xgbe_prv_data *pdata) 1848 { 1849 unsigned int arcache, awcache; 1850 1851 arcache = 0; 1852 XGMAC_SET_BITS(arcache, DMA_AXIARCR, DRC, pdata->arcache); 1853 XGMAC_SET_BITS(arcache, DMA_AXIARCR, DRD, pdata->axdomain); 1854 XGMAC_SET_BITS(arcache, DMA_AXIARCR, TEC, pdata->arcache); 1855 XGMAC_SET_BITS(arcache, DMA_AXIARCR, TED, pdata->axdomain); 1856 XGMAC_SET_BITS(arcache, DMA_AXIARCR, THC, pdata->arcache); 1857 XGMAC_SET_BITS(arcache, DMA_AXIARCR, THD, pdata->axdomain); 1858 XGMAC_IOWRITE(pdata, DMA_AXIARCR, arcache); 1859 1860 awcache = 0; 1861 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, DWC, pdata->awcache); 1862 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, DWD, pdata->axdomain); 1863 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RPC, pdata->awcache); 1864 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RPD, pdata->axdomain); 1865 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RHC, pdata->awcache); 1866 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RHD, pdata->axdomain); 1867 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, TDC, pdata->awcache); 1868 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, TDD, pdata->axdomain); 1869 XGMAC_IOWRITE(pdata, DMA_AXIAWCR, awcache); 1870 } 1871 1872 static void xgbe_config_mtl_mode(struct xgbe_prv_data *pdata) 1873 { 1874 unsigned int i; 1875 1876 /* Set Tx to weighted round robin scheduling algorithm */ 1877 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_WRR); 1878 1879 /* Set Tx traffic classes to use WRR algorithm with equal weights */ 1880 for (i = 0; i < pdata->hw_feat.tc_cnt; i++) { 1881 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA, 1882 MTL_TSA_ETS); 1883 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW, 1); 1884 } 1885 1886 /* Set Rx to strict priority algorithm */ 1887 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, RAA, MTL_RAA_SP); 1888 } 1889 1890 static unsigned int xgbe_calculate_per_queue_fifo(unsigned int fifo_size, 1891 unsigned int queue_count) 1892 { 1893 unsigned int q_fifo_size = 0; 1894 enum xgbe_mtl_fifo_size p_fifo = XGMAC_MTL_FIFO_SIZE_256; 1895 1896 /* Calculate Tx/Rx fifo share per queue */ 1897 switch (fifo_size) { 1898 case 0: 1899 q_fifo_size = XGBE_FIFO_SIZE_B(128); 1900 break; 1901 case 1: 1902 q_fifo_size = XGBE_FIFO_SIZE_B(256); 1903 break; 1904 case 2: 1905 q_fifo_size = XGBE_FIFO_SIZE_B(512); 1906 break; 1907 case 3: 1908 q_fifo_size = XGBE_FIFO_SIZE_KB(1); 1909 break; 1910 case 4: 1911 q_fifo_size = XGBE_FIFO_SIZE_KB(2); 1912 break; 1913 case 5: 1914 q_fifo_size = XGBE_FIFO_SIZE_KB(4); 1915 break; 1916 case 6: 1917 q_fifo_size = XGBE_FIFO_SIZE_KB(8); 1918 break; 1919 case 7: 1920 q_fifo_size = XGBE_FIFO_SIZE_KB(16); 1921 break; 1922 case 8: 1923 q_fifo_size = XGBE_FIFO_SIZE_KB(32); 1924 break; 1925 case 9: 1926 q_fifo_size = XGBE_FIFO_SIZE_KB(64); 1927 break; 1928 case 10: 1929 q_fifo_size = XGBE_FIFO_SIZE_KB(128); 1930 break; 1931 case 11: 1932 q_fifo_size = XGBE_FIFO_SIZE_KB(256); 1933 break; 1934 } 1935 1936 /* The configured value is not the actual amount of fifo RAM */ 1937 q_fifo_size = min_t(unsigned int, XGBE_FIFO_MAX, q_fifo_size); 1938 1939 q_fifo_size = q_fifo_size / queue_count; 1940 1941 /* Set the queue fifo size programmable value */ 1942 if (q_fifo_size >= XGBE_FIFO_SIZE_KB(256)) 1943 p_fifo = XGMAC_MTL_FIFO_SIZE_256K; 1944 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(128)) 1945 p_fifo = XGMAC_MTL_FIFO_SIZE_128K; 1946 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(64)) 1947 p_fifo = XGMAC_MTL_FIFO_SIZE_64K; 1948 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(32)) 1949 p_fifo = XGMAC_MTL_FIFO_SIZE_32K; 1950 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(16)) 1951 p_fifo = XGMAC_MTL_FIFO_SIZE_16K; 1952 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(8)) 1953 p_fifo = XGMAC_MTL_FIFO_SIZE_8K; 1954 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(4)) 1955 p_fifo = XGMAC_MTL_FIFO_SIZE_4K; 1956 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(2)) 1957 p_fifo = XGMAC_MTL_FIFO_SIZE_2K; 1958 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(1)) 1959 p_fifo = XGMAC_MTL_FIFO_SIZE_1K; 1960 else if (q_fifo_size >= XGBE_FIFO_SIZE_B(512)) 1961 p_fifo = XGMAC_MTL_FIFO_SIZE_512; 1962 else if (q_fifo_size >= XGBE_FIFO_SIZE_B(256)) 1963 p_fifo = XGMAC_MTL_FIFO_SIZE_256; 1964 1965 return p_fifo; 1966 } 1967 1968 static void xgbe_config_tx_fifo_size(struct xgbe_prv_data *pdata) 1969 { 1970 enum xgbe_mtl_fifo_size fifo_size; 1971 unsigned int i; 1972 1973 fifo_size = xgbe_calculate_per_queue_fifo(pdata->hw_feat.tx_fifo_size, 1974 pdata->tx_q_count); 1975 1976 for (i = 0; i < pdata->tx_q_count; i++) 1977 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TQS, fifo_size); 1978 1979 netdev_notice(pdata->netdev, "%d Tx queues, %d byte fifo per queue\n", 1980 pdata->tx_q_count, ((fifo_size + 1) * 256)); 1981 } 1982 1983 static void xgbe_config_rx_fifo_size(struct xgbe_prv_data *pdata) 1984 { 1985 enum xgbe_mtl_fifo_size fifo_size; 1986 unsigned int i; 1987 1988 fifo_size = xgbe_calculate_per_queue_fifo(pdata->hw_feat.rx_fifo_size, 1989 pdata->rx_q_count); 1990 1991 for (i = 0; i < pdata->rx_q_count; i++) 1992 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RQS, fifo_size); 1993 1994 netdev_notice(pdata->netdev, "%d Rx queues, %d byte fifo per queue\n", 1995 pdata->rx_q_count, ((fifo_size + 1) * 256)); 1996 } 1997 1998 static void xgbe_config_queue_mapping(struct xgbe_prv_data *pdata) 1999 { 2000 unsigned int qptc, qptc_extra, queue; 2001 unsigned int prio_queues; 2002 unsigned int ppq, ppq_extra, prio; 2003 unsigned int mask; 2004 unsigned int i, j, reg, reg_val; 2005 2006 /* Map the MTL Tx Queues to Traffic Classes 2007 * Note: Tx Queues >= Traffic Classes 2008 */ 2009 qptc = pdata->tx_q_count / pdata->hw_feat.tc_cnt; 2010 qptc_extra = pdata->tx_q_count % pdata->hw_feat.tc_cnt; 2011 2012 for (i = 0, queue = 0; i < pdata->hw_feat.tc_cnt; i++) { 2013 for (j = 0; j < qptc; j++) { 2014 DBGPR(" TXq%u mapped to TC%u\n", queue, i); 2015 XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR, 2016 Q2TCMAP, i); 2017 pdata->q2tc_map[queue++] = i; 2018 } 2019 2020 if (i < qptc_extra) { 2021 DBGPR(" TXq%u mapped to TC%u\n", queue, i); 2022 XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR, 2023 Q2TCMAP, i); 2024 pdata->q2tc_map[queue++] = i; 2025 } 2026 } 2027 2028 /* Map the 8 VLAN priority values to available MTL Rx queues */ 2029 prio_queues = min_t(unsigned int, IEEE_8021QAZ_MAX_TCS, 2030 pdata->rx_q_count); 2031 ppq = IEEE_8021QAZ_MAX_TCS / prio_queues; 2032 ppq_extra = IEEE_8021QAZ_MAX_TCS % prio_queues; 2033 2034 reg = MAC_RQC2R; 2035 reg_val = 0; 2036 for (i = 0, prio = 0; i < prio_queues;) { 2037 mask = 0; 2038 for (j = 0; j < ppq; j++) { 2039 DBGPR(" PRIO%u mapped to RXq%u\n", prio, i); 2040 mask |= (1 << prio); 2041 pdata->prio2q_map[prio++] = i; 2042 } 2043 2044 if (i < ppq_extra) { 2045 DBGPR(" PRIO%u mapped to RXq%u\n", prio, i); 2046 mask |= (1 << prio); 2047 pdata->prio2q_map[prio++] = i; 2048 } 2049 2050 reg_val |= (mask << ((i++ % MAC_RQC2_Q_PER_REG) << 3)); 2051 2052 if ((i % MAC_RQC2_Q_PER_REG) && (i != prio_queues)) 2053 continue; 2054 2055 XGMAC_IOWRITE(pdata, reg, reg_val); 2056 reg += MAC_RQC2_INC; 2057 reg_val = 0; 2058 } 2059 2060 /* Select dynamic mapping of MTL Rx queue to DMA Rx channel */ 2061 reg = MTL_RQDCM0R; 2062 reg_val = 0; 2063 for (i = 0; i < pdata->rx_q_count;) { 2064 reg_val |= (0x80 << ((i++ % MTL_RQDCM_Q_PER_REG) << 3)); 2065 2066 if ((i % MTL_RQDCM_Q_PER_REG) && (i != pdata->rx_q_count)) 2067 continue; 2068 2069 XGMAC_IOWRITE(pdata, reg, reg_val); 2070 2071 reg += MTL_RQDCM_INC; 2072 reg_val = 0; 2073 } 2074 } 2075 2076 static void xgbe_config_flow_control_threshold(struct xgbe_prv_data *pdata) 2077 { 2078 unsigned int i; 2079 2080 for (i = 0; i < pdata->rx_q_count; i++) { 2081 /* Activate flow control when less than 4k left in fifo */ 2082 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RFA, 2); 2083 2084 /* De-activate flow control when more than 6k left in fifo */ 2085 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RFD, 4); 2086 } 2087 } 2088 2089 static void xgbe_config_mac_address(struct xgbe_prv_data *pdata) 2090 { 2091 xgbe_set_mac_address(pdata, pdata->netdev->dev_addr); 2092 2093 /* Filtering is done using perfect filtering and hash filtering */ 2094 if (pdata->hw_feat.hash_table_size) { 2095 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 1); 2096 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 1); 2097 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HMC, 1); 2098 } 2099 } 2100 2101 static void xgbe_config_jumbo_enable(struct xgbe_prv_data *pdata) 2102 { 2103 unsigned int val; 2104 2105 val = (pdata->netdev->mtu > XGMAC_STD_PACKET_MTU) ? 1 : 0; 2106 2107 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, JE, val); 2108 } 2109 2110 static void xgbe_config_checksum_offload(struct xgbe_prv_data *pdata) 2111 { 2112 if (pdata->netdev->features & NETIF_F_RXCSUM) 2113 xgbe_enable_rx_csum(pdata); 2114 else 2115 xgbe_disable_rx_csum(pdata); 2116 } 2117 2118 static void xgbe_config_vlan_support(struct xgbe_prv_data *pdata) 2119 { 2120 /* Indicate that VLAN Tx CTAGs come from context descriptors */ 2121 XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, CSVL, 0); 2122 XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, VLTI, 1); 2123 2124 /* Set the current VLAN Hash Table register value */ 2125 xgbe_update_vlan_hash_table(pdata); 2126 2127 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER) 2128 xgbe_enable_rx_vlan_filtering(pdata); 2129 else 2130 xgbe_disable_rx_vlan_filtering(pdata); 2131 2132 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) 2133 xgbe_enable_rx_vlan_stripping(pdata); 2134 else 2135 xgbe_disable_rx_vlan_stripping(pdata); 2136 } 2137 2138 static u64 xgbe_mmc_read(struct xgbe_prv_data *pdata, unsigned int reg_lo) 2139 { 2140 bool read_hi; 2141 u64 val; 2142 2143 switch (reg_lo) { 2144 /* These registers are always 64 bit */ 2145 case MMC_TXOCTETCOUNT_GB_LO: 2146 case MMC_TXOCTETCOUNT_G_LO: 2147 case MMC_RXOCTETCOUNT_GB_LO: 2148 case MMC_RXOCTETCOUNT_G_LO: 2149 read_hi = true; 2150 break; 2151 2152 default: 2153 read_hi = false; 2154 }; 2155 2156 val = XGMAC_IOREAD(pdata, reg_lo); 2157 2158 if (read_hi) 2159 val |= ((u64)XGMAC_IOREAD(pdata, reg_lo + 4) << 32); 2160 2161 return val; 2162 } 2163 2164 static void xgbe_tx_mmc_int(struct xgbe_prv_data *pdata) 2165 { 2166 struct xgbe_mmc_stats *stats = &pdata->mmc_stats; 2167 unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_TISR); 2168 2169 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXOCTETCOUNT_GB)) 2170 stats->txoctetcount_gb += 2171 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO); 2172 2173 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXFRAMECOUNT_GB)) 2174 stats->txframecount_gb += 2175 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO); 2176 2177 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXBROADCASTFRAMES_G)) 2178 stats->txbroadcastframes_g += 2179 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO); 2180 2181 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXMULTICASTFRAMES_G)) 2182 stats->txmulticastframes_g += 2183 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO); 2184 2185 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX64OCTETS_GB)) 2186 stats->tx64octets_gb += 2187 xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO); 2188 2189 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX65TO127OCTETS_GB)) 2190 stats->tx65to127octets_gb += 2191 xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO); 2192 2193 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX128TO255OCTETS_GB)) 2194 stats->tx128to255octets_gb += 2195 xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO); 2196 2197 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX256TO511OCTETS_GB)) 2198 stats->tx256to511octets_gb += 2199 xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO); 2200 2201 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX512TO1023OCTETS_GB)) 2202 stats->tx512to1023octets_gb += 2203 xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO); 2204 2205 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX1024TOMAXOCTETS_GB)) 2206 stats->tx1024tomaxoctets_gb += 2207 xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO); 2208 2209 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXUNICASTFRAMES_GB)) 2210 stats->txunicastframes_gb += 2211 xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO); 2212 2213 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXMULTICASTFRAMES_GB)) 2214 stats->txmulticastframes_gb += 2215 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO); 2216 2217 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXBROADCASTFRAMES_GB)) 2218 stats->txbroadcastframes_g += 2219 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO); 2220 2221 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXUNDERFLOWERROR)) 2222 stats->txunderflowerror += 2223 xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO); 2224 2225 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXOCTETCOUNT_G)) 2226 stats->txoctetcount_g += 2227 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO); 2228 2229 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXFRAMECOUNT_G)) 2230 stats->txframecount_g += 2231 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO); 2232 2233 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXPAUSEFRAMES)) 2234 stats->txpauseframes += 2235 xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO); 2236 2237 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXVLANFRAMES_G)) 2238 stats->txvlanframes_g += 2239 xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO); 2240 } 2241 2242 static void xgbe_rx_mmc_int(struct xgbe_prv_data *pdata) 2243 { 2244 struct xgbe_mmc_stats *stats = &pdata->mmc_stats; 2245 unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_RISR); 2246 2247 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXFRAMECOUNT_GB)) 2248 stats->rxframecount_gb += 2249 xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO); 2250 2251 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOCTETCOUNT_GB)) 2252 stats->rxoctetcount_gb += 2253 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO); 2254 2255 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOCTETCOUNT_G)) 2256 stats->rxoctetcount_g += 2257 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO); 2258 2259 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXBROADCASTFRAMES_G)) 2260 stats->rxbroadcastframes_g += 2261 xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO); 2262 2263 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXMULTICASTFRAMES_G)) 2264 stats->rxmulticastframes_g += 2265 xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO); 2266 2267 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXCRCERROR)) 2268 stats->rxcrcerror += 2269 xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO); 2270 2271 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXRUNTERROR)) 2272 stats->rxrunterror += 2273 xgbe_mmc_read(pdata, MMC_RXRUNTERROR); 2274 2275 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXJABBERERROR)) 2276 stats->rxjabbererror += 2277 xgbe_mmc_read(pdata, MMC_RXJABBERERROR); 2278 2279 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXUNDERSIZE_G)) 2280 stats->rxundersize_g += 2281 xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G); 2282 2283 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOVERSIZE_G)) 2284 stats->rxoversize_g += 2285 xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G); 2286 2287 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX64OCTETS_GB)) 2288 stats->rx64octets_gb += 2289 xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO); 2290 2291 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX65TO127OCTETS_GB)) 2292 stats->rx65to127octets_gb += 2293 xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO); 2294 2295 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX128TO255OCTETS_GB)) 2296 stats->rx128to255octets_gb += 2297 xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO); 2298 2299 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX256TO511OCTETS_GB)) 2300 stats->rx256to511octets_gb += 2301 xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO); 2302 2303 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX512TO1023OCTETS_GB)) 2304 stats->rx512to1023octets_gb += 2305 xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO); 2306 2307 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX1024TOMAXOCTETS_GB)) 2308 stats->rx1024tomaxoctets_gb += 2309 xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO); 2310 2311 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXUNICASTFRAMES_G)) 2312 stats->rxunicastframes_g += 2313 xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO); 2314 2315 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXLENGTHERROR)) 2316 stats->rxlengtherror += 2317 xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO); 2318 2319 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOUTOFRANGETYPE)) 2320 stats->rxoutofrangetype += 2321 xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO); 2322 2323 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXPAUSEFRAMES)) 2324 stats->rxpauseframes += 2325 xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO); 2326 2327 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXFIFOOVERFLOW)) 2328 stats->rxfifooverflow += 2329 xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO); 2330 2331 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXVLANFRAMES_GB)) 2332 stats->rxvlanframes_gb += 2333 xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO); 2334 2335 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXWATCHDOGERROR)) 2336 stats->rxwatchdogerror += 2337 xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR); 2338 } 2339 2340 static void xgbe_read_mmc_stats(struct xgbe_prv_data *pdata) 2341 { 2342 struct xgbe_mmc_stats *stats = &pdata->mmc_stats; 2343 2344 /* Freeze counters */ 2345 XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 1); 2346 2347 stats->txoctetcount_gb += 2348 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO); 2349 2350 stats->txframecount_gb += 2351 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO); 2352 2353 stats->txbroadcastframes_g += 2354 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO); 2355 2356 stats->txmulticastframes_g += 2357 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO); 2358 2359 stats->tx64octets_gb += 2360 xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO); 2361 2362 stats->tx65to127octets_gb += 2363 xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO); 2364 2365 stats->tx128to255octets_gb += 2366 xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO); 2367 2368 stats->tx256to511octets_gb += 2369 xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO); 2370 2371 stats->tx512to1023octets_gb += 2372 xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO); 2373 2374 stats->tx1024tomaxoctets_gb += 2375 xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO); 2376 2377 stats->txunicastframes_gb += 2378 xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO); 2379 2380 stats->txmulticastframes_gb += 2381 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO); 2382 2383 stats->txbroadcastframes_g += 2384 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO); 2385 2386 stats->txunderflowerror += 2387 xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO); 2388 2389 stats->txoctetcount_g += 2390 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO); 2391 2392 stats->txframecount_g += 2393 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO); 2394 2395 stats->txpauseframes += 2396 xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO); 2397 2398 stats->txvlanframes_g += 2399 xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO); 2400 2401 stats->rxframecount_gb += 2402 xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO); 2403 2404 stats->rxoctetcount_gb += 2405 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO); 2406 2407 stats->rxoctetcount_g += 2408 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO); 2409 2410 stats->rxbroadcastframes_g += 2411 xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO); 2412 2413 stats->rxmulticastframes_g += 2414 xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO); 2415 2416 stats->rxcrcerror += 2417 xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO); 2418 2419 stats->rxrunterror += 2420 xgbe_mmc_read(pdata, MMC_RXRUNTERROR); 2421 2422 stats->rxjabbererror += 2423 xgbe_mmc_read(pdata, MMC_RXJABBERERROR); 2424 2425 stats->rxundersize_g += 2426 xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G); 2427 2428 stats->rxoversize_g += 2429 xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G); 2430 2431 stats->rx64octets_gb += 2432 xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO); 2433 2434 stats->rx65to127octets_gb += 2435 xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO); 2436 2437 stats->rx128to255octets_gb += 2438 xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO); 2439 2440 stats->rx256to511octets_gb += 2441 xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO); 2442 2443 stats->rx512to1023octets_gb += 2444 xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO); 2445 2446 stats->rx1024tomaxoctets_gb += 2447 xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO); 2448 2449 stats->rxunicastframes_g += 2450 xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO); 2451 2452 stats->rxlengtherror += 2453 xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO); 2454 2455 stats->rxoutofrangetype += 2456 xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO); 2457 2458 stats->rxpauseframes += 2459 xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO); 2460 2461 stats->rxfifooverflow += 2462 xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO); 2463 2464 stats->rxvlanframes_gb += 2465 xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO); 2466 2467 stats->rxwatchdogerror += 2468 xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR); 2469 2470 /* Un-freeze counters */ 2471 XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 0); 2472 } 2473 2474 static void xgbe_config_mmc(struct xgbe_prv_data *pdata) 2475 { 2476 /* Set counters to reset on read */ 2477 XGMAC_IOWRITE_BITS(pdata, MMC_CR, ROR, 1); 2478 2479 /* Reset the counters */ 2480 XGMAC_IOWRITE_BITS(pdata, MMC_CR, CR, 1); 2481 } 2482 2483 static void xgbe_prepare_tx_stop(struct xgbe_prv_data *pdata, 2484 struct xgbe_channel *channel) 2485 { 2486 unsigned int tx_dsr, tx_pos, tx_qidx; 2487 unsigned int tx_status; 2488 unsigned long tx_timeout; 2489 2490 /* Calculate the status register to read and the position within */ 2491 if (channel->queue_index < DMA_DSRX_FIRST_QUEUE) { 2492 tx_dsr = DMA_DSR0; 2493 tx_pos = (channel->queue_index * DMA_DSR_Q_WIDTH) + 2494 DMA_DSR0_TPS_START; 2495 } else { 2496 tx_qidx = channel->queue_index - DMA_DSRX_FIRST_QUEUE; 2497 2498 tx_dsr = DMA_DSR1 + ((tx_qidx / DMA_DSRX_QPR) * DMA_DSRX_INC); 2499 tx_pos = ((tx_qidx % DMA_DSRX_QPR) * DMA_DSR_Q_WIDTH) + 2500 DMA_DSRX_TPS_START; 2501 } 2502 2503 /* The Tx engine cannot be stopped if it is actively processing 2504 * descriptors. Wait for the Tx engine to enter the stopped or 2505 * suspended state. Don't wait forever though... 2506 */ 2507 tx_timeout = jiffies + (XGBE_DMA_STOP_TIMEOUT * HZ); 2508 while (time_before(jiffies, tx_timeout)) { 2509 tx_status = XGMAC_IOREAD(pdata, tx_dsr); 2510 tx_status = GET_BITS(tx_status, tx_pos, DMA_DSR_TPS_WIDTH); 2511 if ((tx_status == DMA_TPS_STOPPED) || 2512 (tx_status == DMA_TPS_SUSPENDED)) 2513 break; 2514 2515 usleep_range(500, 1000); 2516 } 2517 2518 if (!time_before(jiffies, tx_timeout)) 2519 netdev_info(pdata->netdev, 2520 "timed out waiting for Tx DMA channel %u to stop\n", 2521 channel->queue_index); 2522 } 2523 2524 static void xgbe_enable_tx(struct xgbe_prv_data *pdata) 2525 { 2526 struct xgbe_channel *channel; 2527 unsigned int i; 2528 2529 /* Enable each Tx DMA channel */ 2530 channel = pdata->channel; 2531 for (i = 0; i < pdata->channel_count; i++, channel++) { 2532 if (!channel->tx_ring) 2533 break; 2534 2535 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 1); 2536 } 2537 2538 /* Enable each Tx queue */ 2539 for (i = 0; i < pdata->tx_q_count; i++) 2540 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN, 2541 MTL_Q_ENABLED); 2542 2543 /* Enable MAC Tx */ 2544 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1); 2545 } 2546 2547 static void xgbe_disable_tx(struct xgbe_prv_data *pdata) 2548 { 2549 struct xgbe_channel *channel; 2550 unsigned int i; 2551 2552 /* Prepare for Tx DMA channel stop */ 2553 channel = pdata->channel; 2554 for (i = 0; i < pdata->channel_count; i++, channel++) { 2555 if (!channel->tx_ring) 2556 break; 2557 2558 xgbe_prepare_tx_stop(pdata, channel); 2559 } 2560 2561 /* Disable MAC Tx */ 2562 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0); 2563 2564 /* Disable each Tx queue */ 2565 for (i = 0; i < pdata->tx_q_count; i++) 2566 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN, 0); 2567 2568 /* Disable each Tx DMA channel */ 2569 channel = pdata->channel; 2570 for (i = 0; i < pdata->channel_count; i++, channel++) { 2571 if (!channel->tx_ring) 2572 break; 2573 2574 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 0); 2575 } 2576 } 2577 2578 static void xgbe_enable_rx(struct xgbe_prv_data *pdata) 2579 { 2580 struct xgbe_channel *channel; 2581 unsigned int reg_val, i; 2582 2583 /* Enable each Rx DMA channel */ 2584 channel = pdata->channel; 2585 for (i = 0; i < pdata->channel_count; i++, channel++) { 2586 if (!channel->rx_ring) 2587 break; 2588 2589 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 1); 2590 } 2591 2592 /* Enable each Rx queue */ 2593 reg_val = 0; 2594 for (i = 0; i < pdata->rx_q_count; i++) 2595 reg_val |= (0x02 << (i << 1)); 2596 XGMAC_IOWRITE(pdata, MAC_RQC0R, reg_val); 2597 2598 /* Enable MAC Rx */ 2599 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 1); 2600 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 1); 2601 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 1); 2602 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 1); 2603 } 2604 2605 static void xgbe_disable_rx(struct xgbe_prv_data *pdata) 2606 { 2607 struct xgbe_channel *channel; 2608 unsigned int i; 2609 2610 /* Disable MAC Rx */ 2611 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 0); 2612 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 0); 2613 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 0); 2614 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 0); 2615 2616 /* Disable each Rx queue */ 2617 XGMAC_IOWRITE(pdata, MAC_RQC0R, 0); 2618 2619 /* Disable each Rx DMA channel */ 2620 channel = pdata->channel; 2621 for (i = 0; i < pdata->channel_count; i++, channel++) { 2622 if (!channel->rx_ring) 2623 break; 2624 2625 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 0); 2626 } 2627 } 2628 2629 static void xgbe_powerup_tx(struct xgbe_prv_data *pdata) 2630 { 2631 struct xgbe_channel *channel; 2632 unsigned int i; 2633 2634 /* Enable each Tx DMA channel */ 2635 channel = pdata->channel; 2636 for (i = 0; i < pdata->channel_count; i++, channel++) { 2637 if (!channel->tx_ring) 2638 break; 2639 2640 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 1); 2641 } 2642 2643 /* Enable MAC Tx */ 2644 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1); 2645 } 2646 2647 static void xgbe_powerdown_tx(struct xgbe_prv_data *pdata) 2648 { 2649 struct xgbe_channel *channel; 2650 unsigned int i; 2651 2652 /* Prepare for Tx DMA channel stop */ 2653 channel = pdata->channel; 2654 for (i = 0; i < pdata->channel_count; i++, channel++) { 2655 if (!channel->tx_ring) 2656 break; 2657 2658 xgbe_prepare_tx_stop(pdata, channel); 2659 } 2660 2661 /* Disable MAC Tx */ 2662 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0); 2663 2664 /* Disable each Tx DMA channel */ 2665 channel = pdata->channel; 2666 for (i = 0; i < pdata->channel_count; i++, channel++) { 2667 if (!channel->tx_ring) 2668 break; 2669 2670 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 0); 2671 } 2672 } 2673 2674 static void xgbe_powerup_rx(struct xgbe_prv_data *pdata) 2675 { 2676 struct xgbe_channel *channel; 2677 unsigned int i; 2678 2679 /* Enable each Rx DMA channel */ 2680 channel = pdata->channel; 2681 for (i = 0; i < pdata->channel_count; i++, channel++) { 2682 if (!channel->rx_ring) 2683 break; 2684 2685 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 1); 2686 } 2687 } 2688 2689 static void xgbe_powerdown_rx(struct xgbe_prv_data *pdata) 2690 { 2691 struct xgbe_channel *channel; 2692 unsigned int i; 2693 2694 /* Disable each Rx DMA channel */ 2695 channel = pdata->channel; 2696 for (i = 0; i < pdata->channel_count; i++, channel++) { 2697 if (!channel->rx_ring) 2698 break; 2699 2700 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 0); 2701 } 2702 } 2703 2704 static int xgbe_init(struct xgbe_prv_data *pdata) 2705 { 2706 struct xgbe_desc_if *desc_if = &pdata->desc_if; 2707 int ret; 2708 2709 DBGPR("-->xgbe_init\n"); 2710 2711 /* Flush Tx queues */ 2712 ret = xgbe_flush_tx_queues(pdata); 2713 if (ret) 2714 return ret; 2715 2716 /* 2717 * Initialize DMA related features 2718 */ 2719 xgbe_config_dma_bus(pdata); 2720 xgbe_config_dma_cache(pdata); 2721 xgbe_config_osp_mode(pdata); 2722 xgbe_config_pblx8(pdata); 2723 xgbe_config_tx_pbl_val(pdata); 2724 xgbe_config_rx_pbl_val(pdata); 2725 xgbe_config_rx_coalesce(pdata); 2726 xgbe_config_tx_coalesce(pdata); 2727 xgbe_config_rx_buffer_size(pdata); 2728 xgbe_config_tso_mode(pdata); 2729 xgbe_config_sph_mode(pdata); 2730 xgbe_config_rss(pdata); 2731 desc_if->wrapper_tx_desc_init(pdata); 2732 desc_if->wrapper_rx_desc_init(pdata); 2733 xgbe_enable_dma_interrupts(pdata); 2734 2735 /* 2736 * Initialize MTL related features 2737 */ 2738 xgbe_config_mtl_mode(pdata); 2739 xgbe_config_queue_mapping(pdata); 2740 xgbe_config_tsf_mode(pdata, pdata->tx_sf_mode); 2741 xgbe_config_rsf_mode(pdata, pdata->rx_sf_mode); 2742 xgbe_config_tx_threshold(pdata, pdata->tx_threshold); 2743 xgbe_config_rx_threshold(pdata, pdata->rx_threshold); 2744 xgbe_config_tx_fifo_size(pdata); 2745 xgbe_config_rx_fifo_size(pdata); 2746 xgbe_config_flow_control_threshold(pdata); 2747 /*TODO: Error Packet and undersized good Packet forwarding enable 2748 (FEP and FUP) 2749 */ 2750 xgbe_config_dcb_tc(pdata); 2751 xgbe_config_dcb_pfc(pdata); 2752 xgbe_enable_mtl_interrupts(pdata); 2753 2754 /* 2755 * Initialize MAC related features 2756 */ 2757 xgbe_config_mac_address(pdata); 2758 xgbe_config_jumbo_enable(pdata); 2759 xgbe_config_flow_control(pdata); 2760 xgbe_config_checksum_offload(pdata); 2761 xgbe_config_vlan_support(pdata); 2762 xgbe_config_mmc(pdata); 2763 xgbe_enable_mac_interrupts(pdata); 2764 2765 DBGPR("<--xgbe_init\n"); 2766 2767 return 0; 2768 } 2769 2770 void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *hw_if) 2771 { 2772 DBGPR("-->xgbe_init_function_ptrs\n"); 2773 2774 hw_if->tx_complete = xgbe_tx_complete; 2775 2776 hw_if->set_promiscuous_mode = xgbe_set_promiscuous_mode; 2777 hw_if->set_all_multicast_mode = xgbe_set_all_multicast_mode; 2778 hw_if->add_mac_addresses = xgbe_add_mac_addresses; 2779 hw_if->set_mac_address = xgbe_set_mac_address; 2780 2781 hw_if->enable_rx_csum = xgbe_enable_rx_csum; 2782 hw_if->disable_rx_csum = xgbe_disable_rx_csum; 2783 2784 hw_if->enable_rx_vlan_stripping = xgbe_enable_rx_vlan_stripping; 2785 hw_if->disable_rx_vlan_stripping = xgbe_disable_rx_vlan_stripping; 2786 hw_if->enable_rx_vlan_filtering = xgbe_enable_rx_vlan_filtering; 2787 hw_if->disable_rx_vlan_filtering = xgbe_disable_rx_vlan_filtering; 2788 hw_if->update_vlan_hash_table = xgbe_update_vlan_hash_table; 2789 2790 hw_if->read_mmd_regs = xgbe_read_mmd_regs; 2791 hw_if->write_mmd_regs = xgbe_write_mmd_regs; 2792 2793 hw_if->set_gmii_speed = xgbe_set_gmii_speed; 2794 hw_if->set_gmii_2500_speed = xgbe_set_gmii_2500_speed; 2795 hw_if->set_xgmii_speed = xgbe_set_xgmii_speed; 2796 2797 hw_if->enable_tx = xgbe_enable_tx; 2798 hw_if->disable_tx = xgbe_disable_tx; 2799 hw_if->enable_rx = xgbe_enable_rx; 2800 hw_if->disable_rx = xgbe_disable_rx; 2801 2802 hw_if->powerup_tx = xgbe_powerup_tx; 2803 hw_if->powerdown_tx = xgbe_powerdown_tx; 2804 hw_if->powerup_rx = xgbe_powerup_rx; 2805 hw_if->powerdown_rx = xgbe_powerdown_rx; 2806 2807 hw_if->dev_xmit = xgbe_dev_xmit; 2808 hw_if->dev_read = xgbe_dev_read; 2809 hw_if->enable_int = xgbe_enable_int; 2810 hw_if->disable_int = xgbe_disable_int; 2811 hw_if->init = xgbe_init; 2812 hw_if->exit = xgbe_exit; 2813 2814 /* Descriptor related Sequences have to be initialized here */ 2815 hw_if->tx_desc_init = xgbe_tx_desc_init; 2816 hw_if->rx_desc_init = xgbe_rx_desc_init; 2817 hw_if->tx_desc_reset = xgbe_tx_desc_reset; 2818 hw_if->rx_desc_reset = xgbe_rx_desc_reset; 2819 hw_if->is_last_desc = xgbe_is_last_desc; 2820 hw_if->is_context_desc = xgbe_is_context_desc; 2821 hw_if->tx_start_xmit = xgbe_tx_start_xmit; 2822 2823 /* For FLOW ctrl */ 2824 hw_if->config_tx_flow_control = xgbe_config_tx_flow_control; 2825 hw_if->config_rx_flow_control = xgbe_config_rx_flow_control; 2826 2827 /* For RX coalescing */ 2828 hw_if->config_rx_coalesce = xgbe_config_rx_coalesce; 2829 hw_if->config_tx_coalesce = xgbe_config_tx_coalesce; 2830 hw_if->usec_to_riwt = xgbe_usec_to_riwt; 2831 hw_if->riwt_to_usec = xgbe_riwt_to_usec; 2832 2833 /* For RX and TX threshold config */ 2834 hw_if->config_rx_threshold = xgbe_config_rx_threshold; 2835 hw_if->config_tx_threshold = xgbe_config_tx_threshold; 2836 2837 /* For RX and TX Store and Forward Mode config */ 2838 hw_if->config_rsf_mode = xgbe_config_rsf_mode; 2839 hw_if->config_tsf_mode = xgbe_config_tsf_mode; 2840 2841 /* For TX DMA Operating on Second Frame config */ 2842 hw_if->config_osp_mode = xgbe_config_osp_mode; 2843 2844 /* For RX and TX PBL config */ 2845 hw_if->config_rx_pbl_val = xgbe_config_rx_pbl_val; 2846 hw_if->get_rx_pbl_val = xgbe_get_rx_pbl_val; 2847 hw_if->config_tx_pbl_val = xgbe_config_tx_pbl_val; 2848 hw_if->get_tx_pbl_val = xgbe_get_tx_pbl_val; 2849 hw_if->config_pblx8 = xgbe_config_pblx8; 2850 2851 /* For MMC statistics support */ 2852 hw_if->tx_mmc_int = xgbe_tx_mmc_int; 2853 hw_if->rx_mmc_int = xgbe_rx_mmc_int; 2854 hw_if->read_mmc_stats = xgbe_read_mmc_stats; 2855 2856 /* For PTP config */ 2857 hw_if->config_tstamp = xgbe_config_tstamp; 2858 hw_if->update_tstamp_addend = xgbe_update_tstamp_addend; 2859 hw_if->set_tstamp_time = xgbe_set_tstamp_time; 2860 hw_if->get_tstamp_time = xgbe_get_tstamp_time; 2861 hw_if->get_tx_tstamp = xgbe_get_tx_tstamp; 2862 2863 /* For Data Center Bridging config */ 2864 hw_if->config_dcb_tc = xgbe_config_dcb_tc; 2865 hw_if->config_dcb_pfc = xgbe_config_dcb_pfc; 2866 2867 /* For Receive Side Scaling */ 2868 hw_if->enable_rss = xgbe_enable_rss; 2869 hw_if->disable_rss = xgbe_disable_rss; 2870 hw_if->set_rss_hash_key = xgbe_set_rss_hash_key; 2871 hw_if->set_rss_lookup_table = xgbe_set_rss_lookup_table; 2872 2873 DBGPR("<--xgbe_init_function_ptrs\n"); 2874 } 2875