1 /* 2 * AMD 10Gb Ethernet driver 3 * 4 * This file is available to you under your choice of the following two 5 * licenses: 6 * 7 * License 1: GPLv2 8 * 9 * Copyright (c) 2014 Advanced Micro Devices, Inc. 10 * 11 * This file is free software; you may copy, redistribute and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation, either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program. If not, see <http://www.gnu.org/licenses/>. 23 * 24 * This file incorporates work covered by the following copyright and 25 * permission notice: 26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 28 * Inc. unless otherwise expressly agreed to in writing between Synopsys 29 * and you. 30 * 31 * The Software IS NOT an item of Licensed Software or Licensed Product 32 * under any End User Software License Agreement or Agreement for Licensed 33 * Product with Synopsys or any supplement thereto. Permission is hereby 34 * granted, free of charge, to any person obtaining a copy of this software 35 * annotated with this license and the Software, to deal in the Software 36 * without restriction, including without limitation the rights to use, 37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 38 * of the Software, and to permit persons to whom the Software is furnished 39 * to do so, subject to the following conditions: 40 * 41 * The above copyright notice and this permission notice shall be included 42 * in all copies or substantial portions of the Software. 43 * 44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 54 * THE POSSIBILITY OF SUCH DAMAGE. 55 * 56 * 57 * License 2: Modified BSD 58 * 59 * Copyright (c) 2014 Advanced Micro Devices, Inc. 60 * All rights reserved. 61 * 62 * Redistribution and use in source and binary forms, with or without 63 * modification, are permitted provided that the following conditions are met: 64 * * Redistributions of source code must retain the above copyright 65 * notice, this list of conditions and the following disclaimer. 66 * * Redistributions in binary form must reproduce the above copyright 67 * notice, this list of conditions and the following disclaimer in the 68 * documentation and/or other materials provided with the distribution. 69 * * Neither the name of Advanced Micro Devices, Inc. nor the 70 * names of its contributors may be used to endorse or promote products 71 * derived from this software without specific prior written permission. 72 * 73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY 77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 83 * 84 * This file incorporates work covered by the following copyright and 85 * permission notice: 86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 88 * Inc. unless otherwise expressly agreed to in writing between Synopsys 89 * and you. 90 * 91 * The Software IS NOT an item of Licensed Software or Licensed Product 92 * under any End User Software License Agreement or Agreement for Licensed 93 * Product with Synopsys or any supplement thereto. Permission is hereby 94 * granted, free of charge, to any person obtaining a copy of this software 95 * annotated with this license and the Software, to deal in the Software 96 * without restriction, including without limitation the rights to use, 97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 98 * of the Software, and to permit persons to whom the Software is furnished 99 * to do so, subject to the following conditions: 100 * 101 * The above copyright notice and this permission notice shall be included 102 * in all copies or substantial portions of the Software. 103 * 104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 114 * THE POSSIBILITY OF SUCH DAMAGE. 115 */ 116 117 #include <linux/phy.h> 118 #include <linux/clk.h> 119 #include <linux/bitrev.h> 120 #include <linux/crc32.h> 121 122 #include "xgbe.h" 123 #include "xgbe-common.h" 124 125 126 static unsigned int xgbe_usec_to_riwt(struct xgbe_prv_data *pdata, 127 unsigned int usec) 128 { 129 unsigned long rate; 130 unsigned int ret; 131 132 DBGPR("-->xgbe_usec_to_riwt\n"); 133 134 rate = clk_get_rate(pdata->sysclk); 135 136 /* 137 * Convert the input usec value to the watchdog timer value. Each 138 * watchdog timer value is equivalent to 256 clock cycles. 139 * Calculate the required value as: 140 * ( usec * ( system_clock_mhz / 10^6 ) / 256 141 */ 142 ret = (usec * (rate / 1000000)) / 256; 143 144 DBGPR("<--xgbe_usec_to_riwt\n"); 145 146 return ret; 147 } 148 149 static unsigned int xgbe_riwt_to_usec(struct xgbe_prv_data *pdata, 150 unsigned int riwt) 151 { 152 unsigned long rate; 153 unsigned int ret; 154 155 DBGPR("-->xgbe_riwt_to_usec\n"); 156 157 rate = clk_get_rate(pdata->sysclk); 158 159 /* 160 * Convert the input watchdog timer value to the usec value. Each 161 * watchdog timer value is equivalent to 256 clock cycles. 162 * Calculate the required value as: 163 * ( riwt * 256 ) / ( system_clock_mhz / 10^6 ) 164 */ 165 ret = (riwt * 256) / (rate / 1000000); 166 167 DBGPR("<--xgbe_riwt_to_usec\n"); 168 169 return ret; 170 } 171 172 static int xgbe_config_pblx8(struct xgbe_prv_data *pdata) 173 { 174 struct xgbe_channel *channel; 175 unsigned int i; 176 177 channel = pdata->channel; 178 for (i = 0; i < pdata->channel_count; i++, channel++) 179 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_CR, PBLX8, 180 pdata->pblx8); 181 182 return 0; 183 } 184 185 static int xgbe_get_tx_pbl_val(struct xgbe_prv_data *pdata) 186 { 187 return XGMAC_DMA_IOREAD_BITS(pdata->channel, DMA_CH_TCR, PBL); 188 } 189 190 static int xgbe_config_tx_pbl_val(struct xgbe_prv_data *pdata) 191 { 192 struct xgbe_channel *channel; 193 unsigned int i; 194 195 channel = pdata->channel; 196 for (i = 0; i < pdata->channel_count; i++, channel++) { 197 if (!channel->tx_ring) 198 break; 199 200 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, PBL, 201 pdata->tx_pbl); 202 } 203 204 return 0; 205 } 206 207 static int xgbe_get_rx_pbl_val(struct xgbe_prv_data *pdata) 208 { 209 return XGMAC_DMA_IOREAD_BITS(pdata->channel, DMA_CH_RCR, PBL); 210 } 211 212 static int xgbe_config_rx_pbl_val(struct xgbe_prv_data *pdata) 213 { 214 struct xgbe_channel *channel; 215 unsigned int i; 216 217 channel = pdata->channel; 218 for (i = 0; i < pdata->channel_count; i++, channel++) { 219 if (!channel->rx_ring) 220 break; 221 222 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, PBL, 223 pdata->rx_pbl); 224 } 225 226 return 0; 227 } 228 229 static int xgbe_config_osp_mode(struct xgbe_prv_data *pdata) 230 { 231 struct xgbe_channel *channel; 232 unsigned int i; 233 234 channel = pdata->channel; 235 for (i = 0; i < pdata->channel_count; i++, channel++) { 236 if (!channel->tx_ring) 237 break; 238 239 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, OSP, 240 pdata->tx_osp_mode); 241 } 242 243 return 0; 244 } 245 246 static int xgbe_config_rsf_mode(struct xgbe_prv_data *pdata, unsigned int val) 247 { 248 unsigned int i; 249 250 for (i = 0; i < pdata->rx_q_count; i++) 251 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RSF, val); 252 253 return 0; 254 } 255 256 static int xgbe_config_tsf_mode(struct xgbe_prv_data *pdata, unsigned int val) 257 { 258 unsigned int i; 259 260 for (i = 0; i < pdata->tx_q_count; i++) 261 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TSF, val); 262 263 return 0; 264 } 265 266 static int xgbe_config_rx_threshold(struct xgbe_prv_data *pdata, 267 unsigned int val) 268 { 269 unsigned int i; 270 271 for (i = 0; i < pdata->rx_q_count; i++) 272 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RTC, val); 273 274 return 0; 275 } 276 277 static int xgbe_config_tx_threshold(struct xgbe_prv_data *pdata, 278 unsigned int val) 279 { 280 unsigned int i; 281 282 for (i = 0; i < pdata->tx_q_count; i++) 283 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TTC, val); 284 285 return 0; 286 } 287 288 static int xgbe_config_rx_coalesce(struct xgbe_prv_data *pdata) 289 { 290 struct xgbe_channel *channel; 291 unsigned int i; 292 293 channel = pdata->channel; 294 for (i = 0; i < pdata->channel_count; i++, channel++) { 295 if (!channel->rx_ring) 296 break; 297 298 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RIWT, RWT, 299 pdata->rx_riwt); 300 } 301 302 return 0; 303 } 304 305 static int xgbe_config_tx_coalesce(struct xgbe_prv_data *pdata) 306 { 307 return 0; 308 } 309 310 static void xgbe_config_rx_buffer_size(struct xgbe_prv_data *pdata) 311 { 312 struct xgbe_channel *channel; 313 unsigned int i; 314 315 channel = pdata->channel; 316 for (i = 0; i < pdata->channel_count; i++, channel++) { 317 if (!channel->rx_ring) 318 break; 319 320 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, RBSZ, 321 pdata->rx_buf_size); 322 } 323 } 324 325 static void xgbe_config_tso_mode(struct xgbe_prv_data *pdata) 326 { 327 struct xgbe_channel *channel; 328 unsigned int i; 329 330 channel = pdata->channel; 331 for (i = 0; i < pdata->channel_count; i++, channel++) { 332 if (!channel->tx_ring) 333 break; 334 335 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, TSE, 1); 336 } 337 } 338 339 static int xgbe_disable_tx_flow_control(struct xgbe_prv_data *pdata) 340 { 341 unsigned int max_q_count, q_count; 342 unsigned int reg, reg_val; 343 unsigned int i; 344 345 /* Clear MTL flow control */ 346 for (i = 0; i < pdata->rx_q_count; i++) 347 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, 0); 348 349 /* Clear MAC flow control */ 350 max_q_count = XGMAC_MAX_FLOW_CONTROL_QUEUES; 351 q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count); 352 reg = MAC_Q0TFCR; 353 for (i = 0; i < q_count; i++) { 354 reg_val = XGMAC_IOREAD(pdata, reg); 355 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 0); 356 XGMAC_IOWRITE(pdata, reg, reg_val); 357 358 reg += MAC_QTFCR_INC; 359 } 360 361 return 0; 362 } 363 364 static int xgbe_enable_tx_flow_control(struct xgbe_prv_data *pdata) 365 { 366 unsigned int max_q_count, q_count; 367 unsigned int reg, reg_val; 368 unsigned int i; 369 370 /* Set MTL flow control */ 371 for (i = 0; i < pdata->rx_q_count; i++) 372 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, 1); 373 374 /* Set MAC flow control */ 375 max_q_count = XGMAC_MAX_FLOW_CONTROL_QUEUES; 376 q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count); 377 reg = MAC_Q0TFCR; 378 for (i = 0; i < q_count; i++) { 379 reg_val = XGMAC_IOREAD(pdata, reg); 380 381 /* Enable transmit flow control */ 382 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 1); 383 /* Set pause time */ 384 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, PT, 0xffff); 385 386 XGMAC_IOWRITE(pdata, reg, reg_val); 387 388 reg += MAC_QTFCR_INC; 389 } 390 391 return 0; 392 } 393 394 static int xgbe_disable_rx_flow_control(struct xgbe_prv_data *pdata) 395 { 396 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 0); 397 398 return 0; 399 } 400 401 static int xgbe_enable_rx_flow_control(struct xgbe_prv_data *pdata) 402 { 403 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 1); 404 405 return 0; 406 } 407 408 static int xgbe_config_tx_flow_control(struct xgbe_prv_data *pdata) 409 { 410 struct ieee_pfc *pfc = pdata->pfc; 411 412 if (pdata->tx_pause || (pfc && pfc->pfc_en)) 413 xgbe_enable_tx_flow_control(pdata); 414 else 415 xgbe_disable_tx_flow_control(pdata); 416 417 return 0; 418 } 419 420 static int xgbe_config_rx_flow_control(struct xgbe_prv_data *pdata) 421 { 422 struct ieee_pfc *pfc = pdata->pfc; 423 424 if (pdata->rx_pause || (pfc && pfc->pfc_en)) 425 xgbe_enable_rx_flow_control(pdata); 426 else 427 xgbe_disable_rx_flow_control(pdata); 428 429 return 0; 430 } 431 432 static void xgbe_config_flow_control(struct xgbe_prv_data *pdata) 433 { 434 struct ieee_pfc *pfc = pdata->pfc; 435 436 xgbe_config_tx_flow_control(pdata); 437 xgbe_config_rx_flow_control(pdata); 438 439 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 440 (pfc && pfc->pfc_en) ? 1 : 0); 441 } 442 443 static void xgbe_enable_dma_interrupts(struct xgbe_prv_data *pdata) 444 { 445 struct xgbe_channel *channel; 446 unsigned int dma_ch_isr, dma_ch_ier; 447 unsigned int i; 448 449 channel = pdata->channel; 450 for (i = 0; i < pdata->channel_count; i++, channel++) { 451 /* Clear all the interrupts which are set */ 452 dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR); 453 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr); 454 455 /* Clear all interrupt enable bits */ 456 dma_ch_ier = 0; 457 458 /* Enable following interrupts 459 * NIE - Normal Interrupt Summary Enable 460 * AIE - Abnormal Interrupt Summary Enable 461 * FBEE - Fatal Bus Error Enable 462 */ 463 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, NIE, 1); 464 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, AIE, 1); 465 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, FBEE, 1); 466 467 if (channel->tx_ring) { 468 /* Enable the following Tx interrupts 469 * TIE - Transmit Interrupt Enable (unless polling) 470 */ 471 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 1); 472 } 473 if (channel->rx_ring) { 474 /* Enable following Rx interrupts 475 * RBUE - Receive Buffer Unavailable Enable 476 * RIE - Receive Interrupt Enable 477 */ 478 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RBUE, 1); 479 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 1); 480 } 481 482 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, dma_ch_ier); 483 } 484 } 485 486 static void xgbe_enable_mtl_interrupts(struct xgbe_prv_data *pdata) 487 { 488 unsigned int mtl_q_isr; 489 unsigned int q_count, i; 490 491 q_count = max(pdata->hw_feat.tx_q_cnt, pdata->hw_feat.rx_q_cnt); 492 for (i = 0; i < q_count; i++) { 493 /* Clear all the interrupts which are set */ 494 mtl_q_isr = XGMAC_MTL_IOREAD(pdata, i, MTL_Q_ISR); 495 XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_ISR, mtl_q_isr); 496 497 /* No MTL interrupts to be enabled */ 498 XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_IER, 0); 499 } 500 } 501 502 static void xgbe_enable_mac_interrupts(struct xgbe_prv_data *pdata) 503 { 504 unsigned int mac_ier = 0; 505 506 /* Enable Timestamp interrupt */ 507 XGMAC_SET_BITS(mac_ier, MAC_IER, TSIE, 1); 508 509 XGMAC_IOWRITE(pdata, MAC_IER, mac_ier); 510 511 /* Enable all counter interrupts */ 512 XGMAC_IOWRITE_BITS(pdata, MMC_RIER, ALL_INTERRUPTS, 0xffffffff); 513 XGMAC_IOWRITE_BITS(pdata, MMC_TIER, ALL_INTERRUPTS, 0xffffffff); 514 } 515 516 static int xgbe_set_gmii_speed(struct xgbe_prv_data *pdata) 517 { 518 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, 0x3); 519 520 return 0; 521 } 522 523 static int xgbe_set_gmii_2500_speed(struct xgbe_prv_data *pdata) 524 { 525 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, 0x2); 526 527 return 0; 528 } 529 530 static int xgbe_set_xgmii_speed(struct xgbe_prv_data *pdata) 531 { 532 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, 0); 533 534 return 0; 535 } 536 537 static int xgbe_set_promiscuous_mode(struct xgbe_prv_data *pdata, 538 unsigned int enable) 539 { 540 unsigned int val = enable ? 1 : 0; 541 542 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PR) == val) 543 return 0; 544 545 DBGPR(" %s promiscuous mode\n", enable ? "entering" : "leaving"); 546 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, val); 547 548 return 0; 549 } 550 551 static int xgbe_set_all_multicast_mode(struct xgbe_prv_data *pdata, 552 unsigned int enable) 553 { 554 unsigned int val = enable ? 1 : 0; 555 556 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PM) == val) 557 return 0; 558 559 DBGPR(" %s allmulti mode\n", enable ? "entering" : "leaving"); 560 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, val); 561 562 return 0; 563 } 564 565 static void xgbe_set_mac_reg(struct xgbe_prv_data *pdata, 566 struct netdev_hw_addr *ha, unsigned int *mac_reg) 567 { 568 unsigned int mac_addr_hi, mac_addr_lo; 569 u8 *mac_addr; 570 571 mac_addr_lo = 0; 572 mac_addr_hi = 0; 573 574 if (ha) { 575 mac_addr = (u8 *)&mac_addr_lo; 576 mac_addr[0] = ha->addr[0]; 577 mac_addr[1] = ha->addr[1]; 578 mac_addr[2] = ha->addr[2]; 579 mac_addr[3] = ha->addr[3]; 580 mac_addr = (u8 *)&mac_addr_hi; 581 mac_addr[0] = ha->addr[4]; 582 mac_addr[1] = ha->addr[5]; 583 584 DBGPR(" adding mac address %pM at 0x%04x\n", ha->addr, 585 *mac_reg); 586 587 XGMAC_SET_BITS(mac_addr_hi, MAC_MACA1HR, AE, 1); 588 } 589 590 XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_hi); 591 *mac_reg += MAC_MACA_INC; 592 XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_lo); 593 *mac_reg += MAC_MACA_INC; 594 } 595 596 static void xgbe_set_mac_addn_addrs(struct xgbe_prv_data *pdata) 597 { 598 struct net_device *netdev = pdata->netdev; 599 struct netdev_hw_addr *ha; 600 unsigned int mac_reg; 601 unsigned int addn_macs; 602 603 mac_reg = MAC_MACA1HR; 604 addn_macs = pdata->hw_feat.addn_mac; 605 606 if (netdev_uc_count(netdev) > addn_macs) { 607 xgbe_set_promiscuous_mode(pdata, 1); 608 } else { 609 netdev_for_each_uc_addr(ha, netdev) { 610 xgbe_set_mac_reg(pdata, ha, &mac_reg); 611 addn_macs--; 612 } 613 614 if (netdev_mc_count(netdev) > addn_macs) { 615 xgbe_set_all_multicast_mode(pdata, 1); 616 } else { 617 netdev_for_each_mc_addr(ha, netdev) { 618 xgbe_set_mac_reg(pdata, ha, &mac_reg); 619 addn_macs--; 620 } 621 } 622 } 623 624 /* Clear remaining additional MAC address entries */ 625 while (addn_macs--) 626 xgbe_set_mac_reg(pdata, NULL, &mac_reg); 627 } 628 629 static void xgbe_set_mac_hash_table(struct xgbe_prv_data *pdata) 630 { 631 struct net_device *netdev = pdata->netdev; 632 struct netdev_hw_addr *ha; 633 unsigned int hash_reg; 634 unsigned int hash_table_shift, hash_table_count; 635 u32 hash_table[XGBE_MAC_HASH_TABLE_SIZE]; 636 u32 crc; 637 unsigned int i; 638 639 hash_table_shift = 26 - (pdata->hw_feat.hash_table_size >> 7); 640 hash_table_count = pdata->hw_feat.hash_table_size / 32; 641 memset(hash_table, 0, sizeof(hash_table)); 642 643 /* Build the MAC Hash Table register values */ 644 netdev_for_each_uc_addr(ha, netdev) { 645 crc = bitrev32(~crc32_le(~0, ha->addr, ETH_ALEN)); 646 crc >>= hash_table_shift; 647 hash_table[crc >> 5] |= (1 << (crc & 0x1f)); 648 } 649 650 netdev_for_each_mc_addr(ha, netdev) { 651 crc = bitrev32(~crc32_le(~0, ha->addr, ETH_ALEN)); 652 crc >>= hash_table_shift; 653 hash_table[crc >> 5] |= (1 << (crc & 0x1f)); 654 } 655 656 /* Set the MAC Hash Table registers */ 657 hash_reg = MAC_HTR0; 658 for (i = 0; i < hash_table_count; i++) { 659 XGMAC_IOWRITE(pdata, hash_reg, hash_table[i]); 660 hash_reg += MAC_HTR_INC; 661 } 662 } 663 664 static int xgbe_add_mac_addresses(struct xgbe_prv_data *pdata) 665 { 666 if (pdata->hw_feat.hash_table_size) 667 xgbe_set_mac_hash_table(pdata); 668 else 669 xgbe_set_mac_addn_addrs(pdata); 670 671 return 0; 672 } 673 674 static int xgbe_set_mac_address(struct xgbe_prv_data *pdata, u8 *addr) 675 { 676 unsigned int mac_addr_hi, mac_addr_lo; 677 678 mac_addr_hi = (addr[5] << 8) | (addr[4] << 0); 679 mac_addr_lo = (addr[3] << 24) | (addr[2] << 16) | 680 (addr[1] << 8) | (addr[0] << 0); 681 682 XGMAC_IOWRITE(pdata, MAC_MACA0HR, mac_addr_hi); 683 XGMAC_IOWRITE(pdata, MAC_MACA0LR, mac_addr_lo); 684 685 return 0; 686 } 687 688 static int xgbe_read_mmd_regs(struct xgbe_prv_data *pdata, int prtad, 689 int mmd_reg) 690 { 691 unsigned int mmd_address; 692 int mmd_data; 693 694 if (mmd_reg & MII_ADDR_C45) 695 mmd_address = mmd_reg & ~MII_ADDR_C45; 696 else 697 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); 698 699 /* The PCS registers are accessed using mmio. The underlying APB3 700 * management interface uses indirect addressing to access the MMD 701 * register sets. This requires accessing of the PCS register in two 702 * phases, an address phase and a data phase. 703 * 704 * The mmio interface is based on 32-bit offsets and values. All 705 * register offsets must therefore be adjusted by left shifting the 706 * offset 2 bits and reading 32 bits of data. 707 */ 708 mutex_lock(&pdata->xpcs_mutex); 709 XPCS_IOWRITE(pdata, PCS_MMD_SELECT << 2, mmd_address >> 8); 710 mmd_data = XPCS_IOREAD(pdata, (mmd_address & 0xff) << 2); 711 mutex_unlock(&pdata->xpcs_mutex); 712 713 return mmd_data; 714 } 715 716 static void xgbe_write_mmd_regs(struct xgbe_prv_data *pdata, int prtad, 717 int mmd_reg, int mmd_data) 718 { 719 unsigned int mmd_address; 720 721 if (mmd_reg & MII_ADDR_C45) 722 mmd_address = mmd_reg & ~MII_ADDR_C45; 723 else 724 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); 725 726 /* The PCS registers are accessed using mmio. The underlying APB3 727 * management interface uses indirect addressing to access the MMD 728 * register sets. This requires accessing of the PCS register in two 729 * phases, an address phase and a data phase. 730 * 731 * The mmio interface is based on 32-bit offsets and values. All 732 * register offsets must therefore be adjusted by left shifting the 733 * offset 2 bits and reading 32 bits of data. 734 */ 735 mutex_lock(&pdata->xpcs_mutex); 736 XPCS_IOWRITE(pdata, PCS_MMD_SELECT << 2, mmd_address >> 8); 737 XPCS_IOWRITE(pdata, (mmd_address & 0xff) << 2, mmd_data); 738 mutex_unlock(&pdata->xpcs_mutex); 739 } 740 741 static int xgbe_tx_complete(struct xgbe_ring_desc *rdesc) 742 { 743 return !XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN); 744 } 745 746 static int xgbe_disable_rx_csum(struct xgbe_prv_data *pdata) 747 { 748 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 0); 749 750 return 0; 751 } 752 753 static int xgbe_enable_rx_csum(struct xgbe_prv_data *pdata) 754 { 755 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 1); 756 757 return 0; 758 } 759 760 static int xgbe_enable_rx_vlan_stripping(struct xgbe_prv_data *pdata) 761 { 762 /* Put the VLAN tag in the Rx descriptor */ 763 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLRXS, 1); 764 765 /* Don't check the VLAN type */ 766 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, DOVLTC, 1); 767 768 /* Check only C-TAG (0x8100) packets */ 769 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ERSVLM, 0); 770 771 /* Don't consider an S-TAG (0x88A8) packet as a VLAN packet */ 772 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ESVL, 0); 773 774 /* Enable VLAN tag stripping */ 775 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0x3); 776 777 return 0; 778 } 779 780 static int xgbe_disable_rx_vlan_stripping(struct xgbe_prv_data *pdata) 781 { 782 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0); 783 784 return 0; 785 } 786 787 static int xgbe_enable_rx_vlan_filtering(struct xgbe_prv_data *pdata) 788 { 789 /* Enable VLAN filtering */ 790 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 1); 791 792 /* Enable VLAN Hash Table filtering */ 793 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTHM, 1); 794 795 /* Disable VLAN tag inverse matching */ 796 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTIM, 0); 797 798 /* Only filter on the lower 12-bits of the VLAN tag */ 799 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ETV, 1); 800 801 /* In order for the VLAN Hash Table filtering to be effective, 802 * the VLAN tag identifier in the VLAN Tag Register must not 803 * be zero. Set the VLAN tag identifier to "1" to enable the 804 * VLAN Hash Table filtering. This implies that a VLAN tag of 805 * 1 will always pass filtering. 806 */ 807 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VL, 1); 808 809 return 0; 810 } 811 812 static int xgbe_disable_rx_vlan_filtering(struct xgbe_prv_data *pdata) 813 { 814 /* Disable VLAN filtering */ 815 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 0); 816 817 return 0; 818 } 819 820 #ifndef CRCPOLY_LE 821 #define CRCPOLY_LE 0xedb88320 822 #endif 823 static u32 xgbe_vid_crc32_le(__le16 vid_le) 824 { 825 u32 poly = CRCPOLY_LE; 826 u32 crc = ~0; 827 u32 temp = 0; 828 unsigned char *data = (unsigned char *)&vid_le; 829 unsigned char data_byte = 0; 830 int i, bits; 831 832 bits = get_bitmask_order(VLAN_VID_MASK); 833 for (i = 0; i < bits; i++) { 834 if ((i % 8) == 0) 835 data_byte = data[i / 8]; 836 837 temp = ((crc & 1) ^ data_byte) & 1; 838 crc >>= 1; 839 data_byte >>= 1; 840 841 if (temp) 842 crc ^= poly; 843 } 844 845 return crc; 846 } 847 848 static int xgbe_update_vlan_hash_table(struct xgbe_prv_data *pdata) 849 { 850 u32 crc; 851 u16 vid; 852 __le16 vid_le; 853 u16 vlan_hash_table = 0; 854 855 /* Generate the VLAN Hash Table value */ 856 for_each_set_bit(vid, pdata->active_vlans, VLAN_N_VID) { 857 /* Get the CRC32 value of the VLAN ID */ 858 vid_le = cpu_to_le16(vid); 859 crc = bitrev32(~xgbe_vid_crc32_le(vid_le)) >> 28; 860 861 vlan_hash_table |= (1 << crc); 862 } 863 864 /* Set the VLAN Hash Table filtering register */ 865 XGMAC_IOWRITE_BITS(pdata, MAC_VLANHTR, VLHT, vlan_hash_table); 866 867 return 0; 868 } 869 870 static void xgbe_tx_desc_reset(struct xgbe_ring_data *rdata) 871 { 872 struct xgbe_ring_desc *rdesc = rdata->rdesc; 873 874 /* Reset the Tx descriptor 875 * Set buffer 1 (lo) address to zero 876 * Set buffer 1 (hi) address to zero 877 * Reset all other control bits (IC, TTSE, B2L & B1L) 878 * Reset all other control bits (OWN, CTXT, FD, LD, CPC, CIC, etc) 879 */ 880 rdesc->desc0 = 0; 881 rdesc->desc1 = 0; 882 rdesc->desc2 = 0; 883 rdesc->desc3 = 0; 884 } 885 886 static void xgbe_tx_desc_init(struct xgbe_channel *channel) 887 { 888 struct xgbe_ring *ring = channel->tx_ring; 889 struct xgbe_ring_data *rdata; 890 struct xgbe_ring_desc *rdesc; 891 int i; 892 int start_index = ring->cur; 893 894 DBGPR("-->tx_desc_init\n"); 895 896 /* Initialze all descriptors */ 897 for (i = 0; i < ring->rdesc_count; i++) { 898 rdata = XGBE_GET_DESC_DATA(ring, i); 899 rdesc = rdata->rdesc; 900 901 /* Initialize Tx descriptor 902 * Set buffer 1 (lo) address to zero 903 * Set buffer 1 (hi) address to zero 904 * Reset all other control bits (IC, TTSE, B2L & B1L) 905 * Reset all other control bits (OWN, CTXT, FD, LD, CPC, CIC, 906 * etc) 907 */ 908 rdesc->desc0 = 0; 909 rdesc->desc1 = 0; 910 rdesc->desc2 = 0; 911 rdesc->desc3 = 0; 912 } 913 914 /* Make sure everything is written to the descriptor(s) before 915 * telling the device about them 916 */ 917 wmb(); 918 919 /* Update the total number of Tx descriptors */ 920 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDRLR, ring->rdesc_count - 1); 921 922 /* Update the starting address of descriptor ring */ 923 rdata = XGBE_GET_DESC_DATA(ring, start_index); 924 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDLR_HI, 925 upper_32_bits(rdata->rdesc_dma)); 926 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDLR_LO, 927 lower_32_bits(rdata->rdesc_dma)); 928 929 DBGPR("<--tx_desc_init\n"); 930 } 931 932 static void xgbe_rx_desc_reset(struct xgbe_ring_data *rdata) 933 { 934 struct xgbe_ring_desc *rdesc = rdata->rdesc; 935 936 /* Reset the Rx descriptor 937 * Set buffer 1 (lo) address to dma address (lo) 938 * Set buffer 1 (hi) address to dma address (hi) 939 * Set buffer 2 (lo) address to zero 940 * Set buffer 2 (hi) address to zero and set control bits 941 * OWN and INTE 942 */ 943 rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->skb_dma)); 944 rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->skb_dma)); 945 rdesc->desc2 = 0; 946 947 rdesc->desc3 = 0; 948 if (rdata->interrupt) 949 XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, INTE, 1); 950 951 /* Since the Rx DMA engine is likely running, make sure everything 952 * is written to the descriptor(s) before setting the OWN bit 953 * for the descriptor 954 */ 955 wmb(); 956 957 XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN, 1); 958 959 /* Make sure ownership is written to the descriptor */ 960 wmb(); 961 } 962 963 static void xgbe_rx_desc_init(struct xgbe_channel *channel) 964 { 965 struct xgbe_prv_data *pdata = channel->pdata; 966 struct xgbe_ring *ring = channel->rx_ring; 967 struct xgbe_ring_data *rdata; 968 struct xgbe_ring_desc *rdesc; 969 unsigned int start_index = ring->cur; 970 unsigned int rx_coalesce, rx_frames; 971 unsigned int i; 972 973 DBGPR("-->rx_desc_init\n"); 974 975 rx_coalesce = (pdata->rx_riwt || pdata->rx_frames) ? 1 : 0; 976 rx_frames = pdata->rx_frames; 977 978 /* Initialize all descriptors */ 979 for (i = 0; i < ring->rdesc_count; i++) { 980 rdata = XGBE_GET_DESC_DATA(ring, i); 981 rdesc = rdata->rdesc; 982 983 /* Initialize Rx descriptor 984 * Set buffer 1 (lo) address to dma address (lo) 985 * Set buffer 1 (hi) address to dma address (hi) 986 * Set buffer 2 (lo) address to zero 987 * Set buffer 2 (hi) address to zero and set control 988 * bits OWN and INTE appropriateley 989 */ 990 rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->skb_dma)); 991 rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->skb_dma)); 992 rdesc->desc2 = 0; 993 rdesc->desc3 = 0; 994 XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN, 1); 995 XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, INTE, 1); 996 rdata->interrupt = 1; 997 if (rx_coalesce && (!rx_frames || ((i + 1) % rx_frames))) { 998 /* Clear interrupt on completion bit */ 999 XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, INTE, 1000 0); 1001 rdata->interrupt = 0; 1002 } 1003 } 1004 1005 /* Make sure everything is written to the descriptors before 1006 * telling the device about them 1007 */ 1008 wmb(); 1009 1010 /* Update the total number of Rx descriptors */ 1011 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDRLR, ring->rdesc_count - 1); 1012 1013 /* Update the starting address of descriptor ring */ 1014 rdata = XGBE_GET_DESC_DATA(ring, start_index); 1015 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDLR_HI, 1016 upper_32_bits(rdata->rdesc_dma)); 1017 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDLR_LO, 1018 lower_32_bits(rdata->rdesc_dma)); 1019 1020 /* Update the Rx Descriptor Tail Pointer */ 1021 rdata = XGBE_GET_DESC_DATA(ring, start_index + ring->rdesc_count - 1); 1022 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO, 1023 lower_32_bits(rdata->rdesc_dma)); 1024 1025 DBGPR("<--rx_desc_init\n"); 1026 } 1027 1028 static void xgbe_update_tstamp_addend(struct xgbe_prv_data *pdata, 1029 unsigned int addend) 1030 { 1031 /* Set the addend register value and tell the device */ 1032 XGMAC_IOWRITE(pdata, MAC_TSAR, addend); 1033 XGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSADDREG, 1); 1034 1035 /* Wait for addend update to complete */ 1036 while (XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSADDREG)) 1037 udelay(5); 1038 } 1039 1040 static void xgbe_set_tstamp_time(struct xgbe_prv_data *pdata, unsigned int sec, 1041 unsigned int nsec) 1042 { 1043 /* Set the time values and tell the device */ 1044 XGMAC_IOWRITE(pdata, MAC_STSUR, sec); 1045 XGMAC_IOWRITE(pdata, MAC_STNUR, nsec); 1046 XGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSINIT, 1); 1047 1048 /* Wait for time update to complete */ 1049 while (XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSINIT)) 1050 udelay(5); 1051 } 1052 1053 static u64 xgbe_get_tstamp_time(struct xgbe_prv_data *pdata) 1054 { 1055 u64 nsec; 1056 1057 nsec = XGMAC_IOREAD(pdata, MAC_STSR); 1058 nsec *= NSEC_PER_SEC; 1059 nsec += XGMAC_IOREAD(pdata, MAC_STNR); 1060 1061 return nsec; 1062 } 1063 1064 static u64 xgbe_get_tx_tstamp(struct xgbe_prv_data *pdata) 1065 { 1066 unsigned int tx_snr; 1067 u64 nsec; 1068 1069 tx_snr = XGMAC_IOREAD(pdata, MAC_TXSNR); 1070 if (XGMAC_GET_BITS(tx_snr, MAC_TXSNR, TXTSSTSMIS)) 1071 return 0; 1072 1073 nsec = XGMAC_IOREAD(pdata, MAC_TXSSR); 1074 nsec *= NSEC_PER_SEC; 1075 nsec += tx_snr; 1076 1077 return nsec; 1078 } 1079 1080 static void xgbe_get_rx_tstamp(struct xgbe_packet_data *packet, 1081 struct xgbe_ring_desc *rdesc) 1082 { 1083 u64 nsec; 1084 1085 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_CONTEXT_DESC3, TSA) && 1086 !XGMAC_GET_BITS_LE(rdesc->desc3, RX_CONTEXT_DESC3, TSD)) { 1087 nsec = le32_to_cpu(rdesc->desc1); 1088 nsec <<= 32; 1089 nsec |= le32_to_cpu(rdesc->desc0); 1090 if (nsec != 0xffffffffffffffffULL) { 1091 packet->rx_tstamp = nsec; 1092 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1093 RX_TSTAMP, 1); 1094 } 1095 } 1096 } 1097 1098 static int xgbe_config_tstamp(struct xgbe_prv_data *pdata, 1099 unsigned int mac_tscr) 1100 { 1101 /* Set one nano-second accuracy */ 1102 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCTRLSSR, 1); 1103 1104 /* Set fine timestamp update */ 1105 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCFUPDT, 1); 1106 1107 /* Overwrite earlier timestamps */ 1108 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TXTSSTSM, 1); 1109 1110 XGMAC_IOWRITE(pdata, MAC_TSCR, mac_tscr); 1111 1112 /* Exit if timestamping is not enabled */ 1113 if (!XGMAC_GET_BITS(mac_tscr, MAC_TSCR, TSENA)) 1114 return 0; 1115 1116 /* Initialize time registers */ 1117 XGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SSINC, XGBE_TSTAMP_SSINC); 1118 XGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SNSINC, XGBE_TSTAMP_SNSINC); 1119 xgbe_update_tstamp_addend(pdata, pdata->tstamp_addend); 1120 xgbe_set_tstamp_time(pdata, 0, 0); 1121 1122 /* Initialize the timecounter */ 1123 timecounter_init(&pdata->tstamp_tc, &pdata->tstamp_cc, 1124 ktime_to_ns(ktime_get_real())); 1125 1126 return 0; 1127 } 1128 1129 static void xgbe_config_dcb_tc(struct xgbe_prv_data *pdata) 1130 { 1131 struct ieee_ets *ets = pdata->ets; 1132 unsigned int total_weight, min_weight, weight; 1133 unsigned int i; 1134 1135 if (!ets) 1136 return; 1137 1138 /* Set Tx to deficit weighted round robin scheduling algorithm (when 1139 * traffic class is using ETS algorithm) 1140 */ 1141 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_DWRR); 1142 1143 /* Set Traffic Class algorithms */ 1144 total_weight = pdata->netdev->mtu * pdata->hw_feat.tc_cnt; 1145 min_weight = total_weight / 100; 1146 if (!min_weight) 1147 min_weight = 1; 1148 1149 for (i = 0; i < pdata->hw_feat.tc_cnt; i++) { 1150 switch (ets->tc_tsa[i]) { 1151 case IEEE_8021QAZ_TSA_STRICT: 1152 DBGPR(" TC%u using SP\n", i); 1153 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA, 1154 MTL_TSA_SP); 1155 break; 1156 case IEEE_8021QAZ_TSA_ETS: 1157 weight = total_weight * ets->tc_tx_bw[i] / 100; 1158 weight = clamp(weight, min_weight, total_weight); 1159 1160 DBGPR(" TC%u using DWRR (weight %u)\n", i, weight); 1161 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA, 1162 MTL_TSA_ETS); 1163 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW, 1164 weight); 1165 break; 1166 } 1167 } 1168 } 1169 1170 static void xgbe_config_dcb_pfc(struct xgbe_prv_data *pdata) 1171 { 1172 struct ieee_pfc *pfc = pdata->pfc; 1173 struct ieee_ets *ets = pdata->ets; 1174 unsigned int mask, reg, reg_val; 1175 unsigned int tc, prio; 1176 1177 if (!pfc || !ets) 1178 return; 1179 1180 for (tc = 0; tc < pdata->hw_feat.tc_cnt; tc++) { 1181 mask = 0; 1182 for (prio = 0; prio < IEEE_8021QAZ_MAX_TCS; prio++) { 1183 if ((pfc->pfc_en & (1 << prio)) && 1184 (ets->prio_tc[prio] == tc)) 1185 mask |= (1 << prio); 1186 } 1187 mask &= 0xff; 1188 1189 DBGPR(" TC%u PFC mask=%#x\n", tc, mask); 1190 reg = MTL_TCPM0R + (MTL_TCPM_INC * (tc / MTL_TCPM_TC_PER_REG)); 1191 reg_val = XGMAC_IOREAD(pdata, reg); 1192 1193 reg_val &= ~(0xff << ((tc % MTL_TCPM_TC_PER_REG) << 3)); 1194 reg_val |= (mask << ((tc % MTL_TCPM_TC_PER_REG) << 3)); 1195 1196 XGMAC_IOWRITE(pdata, reg, reg_val); 1197 } 1198 1199 xgbe_config_flow_control(pdata); 1200 } 1201 1202 static void xgbe_pre_xmit(struct xgbe_channel *channel) 1203 { 1204 struct xgbe_prv_data *pdata = channel->pdata; 1205 struct xgbe_ring *ring = channel->tx_ring; 1206 struct xgbe_ring_data *rdata; 1207 struct xgbe_ring_desc *rdesc; 1208 struct xgbe_packet_data *packet = &ring->packet_data; 1209 unsigned int csum, tso, vlan; 1210 unsigned int tso_context, vlan_context; 1211 unsigned int tx_coalesce, tx_frames; 1212 int start_index = ring->cur; 1213 int i; 1214 1215 DBGPR("-->xgbe_pre_xmit\n"); 1216 1217 csum = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, 1218 CSUM_ENABLE); 1219 tso = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, 1220 TSO_ENABLE); 1221 vlan = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, 1222 VLAN_CTAG); 1223 1224 if (tso && (packet->mss != ring->tx.cur_mss)) 1225 tso_context = 1; 1226 else 1227 tso_context = 0; 1228 1229 if (vlan && (packet->vlan_ctag != ring->tx.cur_vlan_ctag)) 1230 vlan_context = 1; 1231 else 1232 vlan_context = 0; 1233 1234 tx_coalesce = (pdata->tx_usecs || pdata->tx_frames) ? 1 : 0; 1235 tx_frames = pdata->tx_frames; 1236 if (tx_coalesce && !channel->tx_timer_active) 1237 ring->coalesce_count = 0; 1238 1239 rdata = XGBE_GET_DESC_DATA(ring, ring->cur); 1240 rdesc = rdata->rdesc; 1241 1242 /* Create a context descriptor if this is a TSO packet */ 1243 if (tso_context || vlan_context) { 1244 if (tso_context) { 1245 DBGPR(" TSO context descriptor, mss=%u\n", 1246 packet->mss); 1247 1248 /* Set the MSS size */ 1249 XGMAC_SET_BITS_LE(rdesc->desc2, TX_CONTEXT_DESC2, 1250 MSS, packet->mss); 1251 1252 /* Mark it as a CONTEXT descriptor */ 1253 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, 1254 CTXT, 1); 1255 1256 /* Indicate this descriptor contains the MSS */ 1257 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, 1258 TCMSSV, 1); 1259 1260 ring->tx.cur_mss = packet->mss; 1261 } 1262 1263 if (vlan_context) { 1264 DBGPR(" VLAN context descriptor, ctag=%u\n", 1265 packet->vlan_ctag); 1266 1267 /* Mark it as a CONTEXT descriptor */ 1268 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, 1269 CTXT, 1); 1270 1271 /* Set the VLAN tag */ 1272 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, 1273 VT, packet->vlan_ctag); 1274 1275 /* Indicate this descriptor contains the VLAN tag */ 1276 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, 1277 VLTV, 1); 1278 1279 ring->tx.cur_vlan_ctag = packet->vlan_ctag; 1280 } 1281 1282 ring->cur++; 1283 rdata = XGBE_GET_DESC_DATA(ring, ring->cur); 1284 rdesc = rdata->rdesc; 1285 } 1286 1287 /* Update buffer address (for TSO this is the header) */ 1288 rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->skb_dma)); 1289 rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->skb_dma)); 1290 1291 /* Update the buffer length */ 1292 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, HL_B1L, 1293 rdata->skb_dma_len); 1294 1295 /* VLAN tag insertion check */ 1296 if (vlan) 1297 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, VTIR, 1298 TX_NORMAL_DESC2_VLAN_INSERT); 1299 1300 /* Timestamp enablement check */ 1301 if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP)) 1302 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, TTSE, 1); 1303 1304 /* Set IC bit based on Tx coalescing settings */ 1305 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, IC, 1); 1306 if (tx_coalesce && (!tx_frames || 1307 (++ring->coalesce_count % tx_frames))) 1308 /* Clear IC bit */ 1309 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, IC, 0); 1310 1311 /* Mark it as First Descriptor */ 1312 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, FD, 1); 1313 1314 /* Mark it as a NORMAL descriptor */ 1315 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT, 0); 1316 1317 /* Set OWN bit if not the first descriptor */ 1318 if (ring->cur != start_index) 1319 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1); 1320 1321 if (tso) { 1322 /* Enable TSO */ 1323 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TSE, 1); 1324 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TCPPL, 1325 packet->tcp_payload_len); 1326 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TCPHDRLEN, 1327 packet->tcp_header_len / 4); 1328 } else { 1329 /* Enable CRC and Pad Insertion */ 1330 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CPC, 0); 1331 1332 /* Enable HW CSUM */ 1333 if (csum) 1334 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, 1335 CIC, 0x3); 1336 1337 /* Set the total length to be transmitted */ 1338 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, FL, 1339 packet->length); 1340 } 1341 1342 for (i = ring->cur - start_index + 1; i < packet->rdesc_count; i++) { 1343 ring->cur++; 1344 rdata = XGBE_GET_DESC_DATA(ring, ring->cur); 1345 rdesc = rdata->rdesc; 1346 1347 /* Update buffer address */ 1348 rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->skb_dma)); 1349 rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->skb_dma)); 1350 1351 /* Update the buffer length */ 1352 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, HL_B1L, 1353 rdata->skb_dma_len); 1354 1355 /* Set IC bit based on Tx coalescing settings */ 1356 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, IC, 1); 1357 if (tx_coalesce && (!tx_frames || 1358 (++ring->coalesce_count % tx_frames))) 1359 /* Clear IC bit */ 1360 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, IC, 0); 1361 1362 /* Set OWN bit */ 1363 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1); 1364 1365 /* Mark it as NORMAL descriptor */ 1366 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT, 0); 1367 1368 /* Enable HW CSUM */ 1369 if (csum) 1370 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, 1371 CIC, 0x3); 1372 } 1373 1374 /* Set LAST bit for the last descriptor */ 1375 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, LD, 1); 1376 1377 /* In case the Tx DMA engine is running, make sure everything 1378 * is written to the descriptor(s) before setting the OWN bit 1379 * for the first descriptor 1380 */ 1381 wmb(); 1382 1383 /* Set OWN bit for the first descriptor */ 1384 rdata = XGBE_GET_DESC_DATA(ring, start_index); 1385 rdesc = rdata->rdesc; 1386 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1); 1387 1388 #ifdef XGMAC_ENABLE_TX_DESC_DUMP 1389 xgbe_dump_tx_desc(ring, start_index, packet->rdesc_count, 1); 1390 #endif 1391 1392 /* Make sure ownership is written to the descriptor */ 1393 wmb(); 1394 1395 /* Issue a poll command to Tx DMA by writing address 1396 * of next immediate free descriptor */ 1397 ring->cur++; 1398 rdata = XGBE_GET_DESC_DATA(ring, ring->cur); 1399 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDTR_LO, 1400 lower_32_bits(rdata->rdesc_dma)); 1401 1402 /* Start the Tx coalescing timer */ 1403 if (tx_coalesce && !channel->tx_timer_active) { 1404 channel->tx_timer_active = 1; 1405 hrtimer_start(&channel->tx_timer, 1406 ktime_set(0, pdata->tx_usecs * NSEC_PER_USEC), 1407 HRTIMER_MODE_REL); 1408 } 1409 1410 DBGPR(" %s: descriptors %u to %u written\n", 1411 channel->name, start_index & (ring->rdesc_count - 1), 1412 (ring->cur - 1) & (ring->rdesc_count - 1)); 1413 1414 DBGPR("<--xgbe_pre_xmit\n"); 1415 } 1416 1417 static int xgbe_dev_read(struct xgbe_channel *channel) 1418 { 1419 struct xgbe_ring *ring = channel->rx_ring; 1420 struct xgbe_ring_data *rdata; 1421 struct xgbe_ring_desc *rdesc; 1422 struct xgbe_packet_data *packet = &ring->packet_data; 1423 struct net_device *netdev = channel->pdata->netdev; 1424 unsigned int err, etlt; 1425 1426 DBGPR("-->xgbe_dev_read: cur = %d\n", ring->cur); 1427 1428 rdata = XGBE_GET_DESC_DATA(ring, ring->cur); 1429 rdesc = rdata->rdesc; 1430 1431 /* Check for data availability */ 1432 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN)) 1433 return 1; 1434 1435 #ifdef XGMAC_ENABLE_RX_DESC_DUMP 1436 xgbe_dump_rx_desc(ring, rdesc, ring->cur); 1437 #endif 1438 1439 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CTXT)) { 1440 /* Timestamp Context Descriptor */ 1441 xgbe_get_rx_tstamp(packet, rdesc); 1442 1443 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1444 CONTEXT, 1); 1445 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1446 CONTEXT_NEXT, 0); 1447 return 0; 1448 } 1449 1450 /* Normal Descriptor, be sure Context Descriptor bit is off */ 1451 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, CONTEXT, 0); 1452 1453 /* Indicate if a Context Descriptor is next */ 1454 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CDA)) 1455 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1456 CONTEXT_NEXT, 1); 1457 1458 /* Get the packet length */ 1459 rdata->len = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, PL); 1460 1461 if (!XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, LD)) { 1462 /* Not all the data has been transferred for this packet */ 1463 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1464 INCOMPLETE, 1); 1465 return 0; 1466 } 1467 1468 /* This is the last of the data for this packet */ 1469 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1470 INCOMPLETE, 0); 1471 1472 /* Set checksum done indicator as appropriate */ 1473 if (channel->pdata->netdev->features & NETIF_F_RXCSUM) 1474 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1475 CSUM_DONE, 1); 1476 1477 /* Check for errors (only valid in last descriptor) */ 1478 err = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ES); 1479 etlt = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ETLT); 1480 DBGPR(" err=%u, etlt=%#x\n", err, etlt); 1481 1482 if (!err || (err && !etlt)) { 1483 if ((etlt == 0x09) && 1484 (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)) { 1485 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1486 VLAN_CTAG, 1); 1487 packet->vlan_ctag = XGMAC_GET_BITS_LE(rdesc->desc0, 1488 RX_NORMAL_DESC0, 1489 OVT); 1490 DBGPR(" vlan-ctag=0x%04x\n", packet->vlan_ctag); 1491 } 1492 } else { 1493 if ((etlt == 0x05) || (etlt == 0x06)) 1494 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1495 CSUM_DONE, 0); 1496 else 1497 XGMAC_SET_BITS(packet->errors, RX_PACKET_ERRORS, 1498 FRAME, 1); 1499 } 1500 1501 DBGPR("<--xgbe_dev_read: %s - descriptor=%u (cur=%d)\n", channel->name, 1502 ring->cur & (ring->rdesc_count - 1), ring->cur); 1503 1504 return 0; 1505 } 1506 1507 static int xgbe_is_context_desc(struct xgbe_ring_desc *rdesc) 1508 { 1509 /* Rx and Tx share CTXT bit, so check TDES3.CTXT bit */ 1510 return XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT); 1511 } 1512 1513 static int xgbe_is_last_desc(struct xgbe_ring_desc *rdesc) 1514 { 1515 /* Rx and Tx share LD bit, so check TDES3.LD bit */ 1516 return XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, LD); 1517 } 1518 1519 static int xgbe_enable_int(struct xgbe_channel *channel, 1520 enum xgbe_int int_id) 1521 { 1522 unsigned int dma_ch_ier; 1523 1524 dma_ch_ier = XGMAC_DMA_IOREAD(channel, DMA_CH_IER); 1525 1526 switch (int_id) { 1527 case XGMAC_INT_DMA_CH_SR_TI: 1528 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 1); 1529 break; 1530 case XGMAC_INT_DMA_CH_SR_TPS: 1531 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TXSE, 1); 1532 break; 1533 case XGMAC_INT_DMA_CH_SR_TBU: 1534 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TBUE, 1); 1535 break; 1536 case XGMAC_INT_DMA_CH_SR_RI: 1537 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 1); 1538 break; 1539 case XGMAC_INT_DMA_CH_SR_RBU: 1540 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RBUE, 1); 1541 break; 1542 case XGMAC_INT_DMA_CH_SR_RPS: 1543 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RSE, 1); 1544 break; 1545 case XGMAC_INT_DMA_CH_SR_TI_RI: 1546 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 1); 1547 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 1); 1548 break; 1549 case XGMAC_INT_DMA_CH_SR_FBE: 1550 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, FBEE, 1); 1551 break; 1552 case XGMAC_INT_DMA_ALL: 1553 dma_ch_ier |= channel->saved_ier; 1554 break; 1555 default: 1556 return -1; 1557 } 1558 1559 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, dma_ch_ier); 1560 1561 return 0; 1562 } 1563 1564 static int xgbe_disable_int(struct xgbe_channel *channel, 1565 enum xgbe_int int_id) 1566 { 1567 unsigned int dma_ch_ier; 1568 1569 dma_ch_ier = XGMAC_DMA_IOREAD(channel, DMA_CH_IER); 1570 1571 switch (int_id) { 1572 case XGMAC_INT_DMA_CH_SR_TI: 1573 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 0); 1574 break; 1575 case XGMAC_INT_DMA_CH_SR_TPS: 1576 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TXSE, 0); 1577 break; 1578 case XGMAC_INT_DMA_CH_SR_TBU: 1579 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TBUE, 0); 1580 break; 1581 case XGMAC_INT_DMA_CH_SR_RI: 1582 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 0); 1583 break; 1584 case XGMAC_INT_DMA_CH_SR_RBU: 1585 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RBUE, 0); 1586 break; 1587 case XGMAC_INT_DMA_CH_SR_RPS: 1588 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RSE, 0); 1589 break; 1590 case XGMAC_INT_DMA_CH_SR_TI_RI: 1591 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 0); 1592 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 0); 1593 break; 1594 case XGMAC_INT_DMA_CH_SR_FBE: 1595 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, FBEE, 0); 1596 break; 1597 case XGMAC_INT_DMA_ALL: 1598 channel->saved_ier = dma_ch_ier & XGBE_DMA_INTERRUPT_MASK; 1599 dma_ch_ier &= ~XGBE_DMA_INTERRUPT_MASK; 1600 break; 1601 default: 1602 return -1; 1603 } 1604 1605 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, dma_ch_ier); 1606 1607 return 0; 1608 } 1609 1610 static int xgbe_exit(struct xgbe_prv_data *pdata) 1611 { 1612 unsigned int count = 2000; 1613 1614 DBGPR("-->xgbe_exit\n"); 1615 1616 /* Issue a software reset */ 1617 XGMAC_IOWRITE_BITS(pdata, DMA_MR, SWR, 1); 1618 usleep_range(10, 15); 1619 1620 /* Poll Until Poll Condition */ 1621 while (count-- && XGMAC_IOREAD_BITS(pdata, DMA_MR, SWR)) 1622 usleep_range(500, 600); 1623 1624 if (!count) 1625 return -EBUSY; 1626 1627 DBGPR("<--xgbe_exit\n"); 1628 1629 return 0; 1630 } 1631 1632 static int xgbe_flush_tx_queues(struct xgbe_prv_data *pdata) 1633 { 1634 unsigned int i, count; 1635 1636 if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) < 0x21) 1637 return 0; 1638 1639 for (i = 0; i < pdata->tx_q_count; i++) 1640 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, FTQ, 1); 1641 1642 /* Poll Until Poll Condition */ 1643 for (i = 0; i < pdata->tx_q_count; i++) { 1644 count = 2000; 1645 while (count-- && XGMAC_MTL_IOREAD_BITS(pdata, i, 1646 MTL_Q_TQOMR, FTQ)) 1647 usleep_range(500, 600); 1648 1649 if (!count) 1650 return -EBUSY; 1651 } 1652 1653 return 0; 1654 } 1655 1656 static void xgbe_config_dma_bus(struct xgbe_prv_data *pdata) 1657 { 1658 /* Set enhanced addressing mode */ 1659 XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, EAME, 1); 1660 1661 /* Set the System Bus mode */ 1662 XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, UNDEF, 1); 1663 XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, BLEN_256, 1); 1664 } 1665 1666 static void xgbe_config_dma_cache(struct xgbe_prv_data *pdata) 1667 { 1668 unsigned int arcache, awcache; 1669 1670 arcache = 0; 1671 XGMAC_SET_BITS(arcache, DMA_AXIARCR, DRC, pdata->arcache); 1672 XGMAC_SET_BITS(arcache, DMA_AXIARCR, DRD, pdata->axdomain); 1673 XGMAC_SET_BITS(arcache, DMA_AXIARCR, TEC, pdata->arcache); 1674 XGMAC_SET_BITS(arcache, DMA_AXIARCR, TED, pdata->axdomain); 1675 XGMAC_SET_BITS(arcache, DMA_AXIARCR, THC, pdata->arcache); 1676 XGMAC_SET_BITS(arcache, DMA_AXIARCR, THD, pdata->axdomain); 1677 XGMAC_IOWRITE(pdata, DMA_AXIARCR, arcache); 1678 1679 awcache = 0; 1680 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, DWC, pdata->awcache); 1681 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, DWD, pdata->axdomain); 1682 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RPC, pdata->awcache); 1683 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RPD, pdata->axdomain); 1684 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RHC, pdata->awcache); 1685 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RHD, pdata->axdomain); 1686 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, TDC, pdata->awcache); 1687 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, TDD, pdata->axdomain); 1688 XGMAC_IOWRITE(pdata, DMA_AXIAWCR, awcache); 1689 } 1690 1691 static void xgbe_config_mtl_mode(struct xgbe_prv_data *pdata) 1692 { 1693 unsigned int i; 1694 1695 /* Set Tx to weighted round robin scheduling algorithm */ 1696 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_WRR); 1697 1698 /* Set Tx traffic classes to use WRR algorithm with equal weights */ 1699 for (i = 0; i < pdata->hw_feat.tc_cnt; i++) { 1700 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA, 1701 MTL_TSA_ETS); 1702 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW, 1); 1703 } 1704 1705 /* Set Rx to strict priority algorithm */ 1706 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, RAA, MTL_RAA_SP); 1707 } 1708 1709 static unsigned int xgbe_calculate_per_queue_fifo(unsigned int fifo_size, 1710 unsigned int queue_count) 1711 { 1712 unsigned int q_fifo_size = 0; 1713 enum xgbe_mtl_fifo_size p_fifo = XGMAC_MTL_FIFO_SIZE_256; 1714 1715 /* Calculate Tx/Rx fifo share per queue */ 1716 switch (fifo_size) { 1717 case 0: 1718 q_fifo_size = XGBE_FIFO_SIZE_B(128); 1719 break; 1720 case 1: 1721 q_fifo_size = XGBE_FIFO_SIZE_B(256); 1722 break; 1723 case 2: 1724 q_fifo_size = XGBE_FIFO_SIZE_B(512); 1725 break; 1726 case 3: 1727 q_fifo_size = XGBE_FIFO_SIZE_KB(1); 1728 break; 1729 case 4: 1730 q_fifo_size = XGBE_FIFO_SIZE_KB(2); 1731 break; 1732 case 5: 1733 q_fifo_size = XGBE_FIFO_SIZE_KB(4); 1734 break; 1735 case 6: 1736 q_fifo_size = XGBE_FIFO_SIZE_KB(8); 1737 break; 1738 case 7: 1739 q_fifo_size = XGBE_FIFO_SIZE_KB(16); 1740 break; 1741 case 8: 1742 q_fifo_size = XGBE_FIFO_SIZE_KB(32); 1743 break; 1744 case 9: 1745 q_fifo_size = XGBE_FIFO_SIZE_KB(64); 1746 break; 1747 case 10: 1748 q_fifo_size = XGBE_FIFO_SIZE_KB(128); 1749 break; 1750 case 11: 1751 q_fifo_size = XGBE_FIFO_SIZE_KB(256); 1752 break; 1753 } 1754 1755 /* The configured value is not the actual amount of fifo RAM */ 1756 q_fifo_size = min_t(unsigned int, XGBE_FIFO_MAX, q_fifo_size); 1757 1758 q_fifo_size = q_fifo_size / queue_count; 1759 1760 /* Set the queue fifo size programmable value */ 1761 if (q_fifo_size >= XGBE_FIFO_SIZE_KB(256)) 1762 p_fifo = XGMAC_MTL_FIFO_SIZE_256K; 1763 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(128)) 1764 p_fifo = XGMAC_MTL_FIFO_SIZE_128K; 1765 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(64)) 1766 p_fifo = XGMAC_MTL_FIFO_SIZE_64K; 1767 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(32)) 1768 p_fifo = XGMAC_MTL_FIFO_SIZE_32K; 1769 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(16)) 1770 p_fifo = XGMAC_MTL_FIFO_SIZE_16K; 1771 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(8)) 1772 p_fifo = XGMAC_MTL_FIFO_SIZE_8K; 1773 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(4)) 1774 p_fifo = XGMAC_MTL_FIFO_SIZE_4K; 1775 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(2)) 1776 p_fifo = XGMAC_MTL_FIFO_SIZE_2K; 1777 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(1)) 1778 p_fifo = XGMAC_MTL_FIFO_SIZE_1K; 1779 else if (q_fifo_size >= XGBE_FIFO_SIZE_B(512)) 1780 p_fifo = XGMAC_MTL_FIFO_SIZE_512; 1781 else if (q_fifo_size >= XGBE_FIFO_SIZE_B(256)) 1782 p_fifo = XGMAC_MTL_FIFO_SIZE_256; 1783 1784 return p_fifo; 1785 } 1786 1787 static void xgbe_config_tx_fifo_size(struct xgbe_prv_data *pdata) 1788 { 1789 enum xgbe_mtl_fifo_size fifo_size; 1790 unsigned int i; 1791 1792 fifo_size = xgbe_calculate_per_queue_fifo(pdata->hw_feat.tx_fifo_size, 1793 pdata->tx_q_count); 1794 1795 for (i = 0; i < pdata->tx_q_count; i++) 1796 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TQS, fifo_size); 1797 1798 netdev_notice(pdata->netdev, "%d Tx queues, %d byte fifo per queue\n", 1799 pdata->tx_q_count, ((fifo_size + 1) * 256)); 1800 } 1801 1802 static void xgbe_config_rx_fifo_size(struct xgbe_prv_data *pdata) 1803 { 1804 enum xgbe_mtl_fifo_size fifo_size; 1805 unsigned int i; 1806 1807 fifo_size = xgbe_calculate_per_queue_fifo(pdata->hw_feat.rx_fifo_size, 1808 pdata->rx_q_count); 1809 1810 for (i = 0; i < pdata->rx_q_count; i++) 1811 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RQS, fifo_size); 1812 1813 netdev_notice(pdata->netdev, "%d Rx queues, %d byte fifo per queue\n", 1814 pdata->rx_q_count, ((fifo_size + 1) * 256)); 1815 } 1816 1817 static void xgbe_config_queue_mapping(struct xgbe_prv_data *pdata) 1818 { 1819 unsigned int qptc, qptc_extra, queue; 1820 unsigned int prio_queues; 1821 unsigned int ppq, ppq_extra, prio; 1822 unsigned int mask; 1823 unsigned int i, j, reg, reg_val; 1824 1825 /* Map the MTL Tx Queues to Traffic Classes 1826 * Note: Tx Queues >= Traffic Classes 1827 */ 1828 qptc = pdata->tx_q_count / pdata->hw_feat.tc_cnt; 1829 qptc_extra = pdata->tx_q_count % pdata->hw_feat.tc_cnt; 1830 1831 for (i = 0, queue = 0; i < pdata->hw_feat.tc_cnt; i++) { 1832 for (j = 0; j < qptc; j++) { 1833 DBGPR(" TXq%u mapped to TC%u\n", queue, i); 1834 XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR, 1835 Q2TCMAP, i); 1836 pdata->q2tc_map[queue++] = i; 1837 } 1838 1839 if (i < qptc_extra) { 1840 DBGPR(" TXq%u mapped to TC%u\n", queue, i); 1841 XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR, 1842 Q2TCMAP, i); 1843 pdata->q2tc_map[queue++] = i; 1844 } 1845 } 1846 1847 /* Map the 8 VLAN priority values to available MTL Rx queues */ 1848 prio_queues = min_t(unsigned int, IEEE_8021QAZ_MAX_TCS, 1849 pdata->rx_q_count); 1850 ppq = IEEE_8021QAZ_MAX_TCS / prio_queues; 1851 ppq_extra = IEEE_8021QAZ_MAX_TCS % prio_queues; 1852 1853 reg = MAC_RQC2R; 1854 reg_val = 0; 1855 for (i = 0, prio = 0; i < prio_queues;) { 1856 mask = 0; 1857 for (j = 0; j < ppq; j++) { 1858 DBGPR(" PRIO%u mapped to RXq%u\n", prio, i); 1859 mask |= (1 << prio); 1860 pdata->prio2q_map[prio++] = i; 1861 } 1862 1863 if (i < ppq_extra) { 1864 DBGPR(" PRIO%u mapped to RXq%u\n", prio, i); 1865 mask |= (1 << prio); 1866 pdata->prio2q_map[prio++] = i; 1867 } 1868 1869 reg_val |= (mask << ((i++ % MAC_RQC2_Q_PER_REG) << 3)); 1870 1871 if ((i % MAC_RQC2_Q_PER_REG) && (i != prio_queues)) 1872 continue; 1873 1874 XGMAC_IOWRITE(pdata, reg, reg_val); 1875 reg += MAC_RQC2_INC; 1876 reg_val = 0; 1877 } 1878 1879 /* Select dynamic mapping of MTL Rx queue to DMA Rx channel */ 1880 reg = MTL_RQDCM0R; 1881 reg_val = 0; 1882 for (i = 0; i < pdata->rx_q_count;) { 1883 reg_val |= (0x80 << ((i++ % MTL_RQDCM_Q_PER_REG) << 3)); 1884 1885 if ((i % MTL_RQDCM_Q_PER_REG) && (i != pdata->rx_q_count)) 1886 continue; 1887 1888 XGMAC_IOWRITE(pdata, reg, reg_val); 1889 1890 reg += MTL_RQDCM_INC; 1891 reg_val = 0; 1892 } 1893 } 1894 1895 static void xgbe_config_flow_control_threshold(struct xgbe_prv_data *pdata) 1896 { 1897 unsigned int i; 1898 1899 for (i = 0; i < pdata->rx_q_count; i++) { 1900 /* Activate flow control when less than 4k left in fifo */ 1901 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RFA, 2); 1902 1903 /* De-activate flow control when more than 6k left in fifo */ 1904 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RFD, 4); 1905 } 1906 } 1907 1908 static void xgbe_config_mac_address(struct xgbe_prv_data *pdata) 1909 { 1910 xgbe_set_mac_address(pdata, pdata->netdev->dev_addr); 1911 1912 /* Filtering is done using perfect filtering and hash filtering */ 1913 if (pdata->hw_feat.hash_table_size) { 1914 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 1); 1915 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 1); 1916 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HMC, 1); 1917 } 1918 } 1919 1920 static void xgbe_config_jumbo_enable(struct xgbe_prv_data *pdata) 1921 { 1922 unsigned int val; 1923 1924 val = (pdata->netdev->mtu > XGMAC_STD_PACKET_MTU) ? 1 : 0; 1925 1926 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, JE, val); 1927 } 1928 1929 static void xgbe_config_checksum_offload(struct xgbe_prv_data *pdata) 1930 { 1931 if (pdata->netdev->features & NETIF_F_RXCSUM) 1932 xgbe_enable_rx_csum(pdata); 1933 else 1934 xgbe_disable_rx_csum(pdata); 1935 } 1936 1937 static void xgbe_config_vlan_support(struct xgbe_prv_data *pdata) 1938 { 1939 /* Indicate that VLAN Tx CTAGs come from context descriptors */ 1940 XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, CSVL, 0); 1941 XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, VLTI, 1); 1942 1943 /* Set the current VLAN Hash Table register value */ 1944 xgbe_update_vlan_hash_table(pdata); 1945 1946 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER) 1947 xgbe_enable_rx_vlan_filtering(pdata); 1948 else 1949 xgbe_disable_rx_vlan_filtering(pdata); 1950 1951 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) 1952 xgbe_enable_rx_vlan_stripping(pdata); 1953 else 1954 xgbe_disable_rx_vlan_stripping(pdata); 1955 } 1956 1957 static u64 xgbe_mmc_read(struct xgbe_prv_data *pdata, unsigned int reg_lo) 1958 { 1959 bool read_hi; 1960 u64 val; 1961 1962 switch (reg_lo) { 1963 /* These registers are always 64 bit */ 1964 case MMC_TXOCTETCOUNT_GB_LO: 1965 case MMC_TXOCTETCOUNT_G_LO: 1966 case MMC_RXOCTETCOUNT_GB_LO: 1967 case MMC_RXOCTETCOUNT_G_LO: 1968 read_hi = true; 1969 break; 1970 1971 default: 1972 read_hi = false; 1973 }; 1974 1975 val = XGMAC_IOREAD(pdata, reg_lo); 1976 1977 if (read_hi) 1978 val |= ((u64)XGMAC_IOREAD(pdata, reg_lo + 4) << 32); 1979 1980 return val; 1981 } 1982 1983 static void xgbe_tx_mmc_int(struct xgbe_prv_data *pdata) 1984 { 1985 struct xgbe_mmc_stats *stats = &pdata->mmc_stats; 1986 unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_TISR); 1987 1988 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXOCTETCOUNT_GB)) 1989 stats->txoctetcount_gb += 1990 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO); 1991 1992 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXFRAMECOUNT_GB)) 1993 stats->txframecount_gb += 1994 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO); 1995 1996 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXBROADCASTFRAMES_G)) 1997 stats->txbroadcastframes_g += 1998 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO); 1999 2000 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXMULTICASTFRAMES_G)) 2001 stats->txmulticastframes_g += 2002 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO); 2003 2004 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX64OCTETS_GB)) 2005 stats->tx64octets_gb += 2006 xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO); 2007 2008 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX65TO127OCTETS_GB)) 2009 stats->tx65to127octets_gb += 2010 xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO); 2011 2012 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX128TO255OCTETS_GB)) 2013 stats->tx128to255octets_gb += 2014 xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO); 2015 2016 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX256TO511OCTETS_GB)) 2017 stats->tx256to511octets_gb += 2018 xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO); 2019 2020 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX512TO1023OCTETS_GB)) 2021 stats->tx512to1023octets_gb += 2022 xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO); 2023 2024 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX1024TOMAXOCTETS_GB)) 2025 stats->tx1024tomaxoctets_gb += 2026 xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO); 2027 2028 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXUNICASTFRAMES_GB)) 2029 stats->txunicastframes_gb += 2030 xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO); 2031 2032 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXMULTICASTFRAMES_GB)) 2033 stats->txmulticastframes_gb += 2034 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO); 2035 2036 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXBROADCASTFRAMES_GB)) 2037 stats->txbroadcastframes_g += 2038 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO); 2039 2040 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXUNDERFLOWERROR)) 2041 stats->txunderflowerror += 2042 xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO); 2043 2044 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXOCTETCOUNT_G)) 2045 stats->txoctetcount_g += 2046 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO); 2047 2048 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXFRAMECOUNT_G)) 2049 stats->txframecount_g += 2050 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO); 2051 2052 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXPAUSEFRAMES)) 2053 stats->txpauseframes += 2054 xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO); 2055 2056 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXVLANFRAMES_G)) 2057 stats->txvlanframes_g += 2058 xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO); 2059 } 2060 2061 static void xgbe_rx_mmc_int(struct xgbe_prv_data *pdata) 2062 { 2063 struct xgbe_mmc_stats *stats = &pdata->mmc_stats; 2064 unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_RISR); 2065 2066 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXFRAMECOUNT_GB)) 2067 stats->rxframecount_gb += 2068 xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO); 2069 2070 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOCTETCOUNT_GB)) 2071 stats->rxoctetcount_gb += 2072 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO); 2073 2074 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOCTETCOUNT_G)) 2075 stats->rxoctetcount_g += 2076 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO); 2077 2078 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXBROADCASTFRAMES_G)) 2079 stats->rxbroadcastframes_g += 2080 xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO); 2081 2082 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXMULTICASTFRAMES_G)) 2083 stats->rxmulticastframes_g += 2084 xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO); 2085 2086 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXCRCERROR)) 2087 stats->rxcrcerror += 2088 xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO); 2089 2090 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXRUNTERROR)) 2091 stats->rxrunterror += 2092 xgbe_mmc_read(pdata, MMC_RXRUNTERROR); 2093 2094 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXJABBERERROR)) 2095 stats->rxjabbererror += 2096 xgbe_mmc_read(pdata, MMC_RXJABBERERROR); 2097 2098 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXUNDERSIZE_G)) 2099 stats->rxundersize_g += 2100 xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G); 2101 2102 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOVERSIZE_G)) 2103 stats->rxoversize_g += 2104 xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G); 2105 2106 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX64OCTETS_GB)) 2107 stats->rx64octets_gb += 2108 xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO); 2109 2110 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX65TO127OCTETS_GB)) 2111 stats->rx65to127octets_gb += 2112 xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO); 2113 2114 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX128TO255OCTETS_GB)) 2115 stats->rx128to255octets_gb += 2116 xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO); 2117 2118 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX256TO511OCTETS_GB)) 2119 stats->rx256to511octets_gb += 2120 xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO); 2121 2122 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX512TO1023OCTETS_GB)) 2123 stats->rx512to1023octets_gb += 2124 xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO); 2125 2126 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX1024TOMAXOCTETS_GB)) 2127 stats->rx1024tomaxoctets_gb += 2128 xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO); 2129 2130 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXUNICASTFRAMES_G)) 2131 stats->rxunicastframes_g += 2132 xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO); 2133 2134 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXLENGTHERROR)) 2135 stats->rxlengtherror += 2136 xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO); 2137 2138 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOUTOFRANGETYPE)) 2139 stats->rxoutofrangetype += 2140 xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO); 2141 2142 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXPAUSEFRAMES)) 2143 stats->rxpauseframes += 2144 xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO); 2145 2146 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXFIFOOVERFLOW)) 2147 stats->rxfifooverflow += 2148 xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO); 2149 2150 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXVLANFRAMES_GB)) 2151 stats->rxvlanframes_gb += 2152 xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO); 2153 2154 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXWATCHDOGERROR)) 2155 stats->rxwatchdogerror += 2156 xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR); 2157 } 2158 2159 static void xgbe_read_mmc_stats(struct xgbe_prv_data *pdata) 2160 { 2161 struct xgbe_mmc_stats *stats = &pdata->mmc_stats; 2162 2163 /* Freeze counters */ 2164 XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 1); 2165 2166 stats->txoctetcount_gb += 2167 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO); 2168 2169 stats->txframecount_gb += 2170 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO); 2171 2172 stats->txbroadcastframes_g += 2173 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO); 2174 2175 stats->txmulticastframes_g += 2176 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO); 2177 2178 stats->tx64octets_gb += 2179 xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO); 2180 2181 stats->tx65to127octets_gb += 2182 xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO); 2183 2184 stats->tx128to255octets_gb += 2185 xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO); 2186 2187 stats->tx256to511octets_gb += 2188 xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO); 2189 2190 stats->tx512to1023octets_gb += 2191 xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO); 2192 2193 stats->tx1024tomaxoctets_gb += 2194 xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO); 2195 2196 stats->txunicastframes_gb += 2197 xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO); 2198 2199 stats->txmulticastframes_gb += 2200 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO); 2201 2202 stats->txbroadcastframes_g += 2203 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO); 2204 2205 stats->txunderflowerror += 2206 xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO); 2207 2208 stats->txoctetcount_g += 2209 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO); 2210 2211 stats->txframecount_g += 2212 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO); 2213 2214 stats->txpauseframes += 2215 xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO); 2216 2217 stats->txvlanframes_g += 2218 xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO); 2219 2220 stats->rxframecount_gb += 2221 xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO); 2222 2223 stats->rxoctetcount_gb += 2224 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO); 2225 2226 stats->rxoctetcount_g += 2227 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO); 2228 2229 stats->rxbroadcastframes_g += 2230 xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO); 2231 2232 stats->rxmulticastframes_g += 2233 xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO); 2234 2235 stats->rxcrcerror += 2236 xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO); 2237 2238 stats->rxrunterror += 2239 xgbe_mmc_read(pdata, MMC_RXRUNTERROR); 2240 2241 stats->rxjabbererror += 2242 xgbe_mmc_read(pdata, MMC_RXJABBERERROR); 2243 2244 stats->rxundersize_g += 2245 xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G); 2246 2247 stats->rxoversize_g += 2248 xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G); 2249 2250 stats->rx64octets_gb += 2251 xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO); 2252 2253 stats->rx65to127octets_gb += 2254 xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO); 2255 2256 stats->rx128to255octets_gb += 2257 xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO); 2258 2259 stats->rx256to511octets_gb += 2260 xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO); 2261 2262 stats->rx512to1023octets_gb += 2263 xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO); 2264 2265 stats->rx1024tomaxoctets_gb += 2266 xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO); 2267 2268 stats->rxunicastframes_g += 2269 xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO); 2270 2271 stats->rxlengtherror += 2272 xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO); 2273 2274 stats->rxoutofrangetype += 2275 xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO); 2276 2277 stats->rxpauseframes += 2278 xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO); 2279 2280 stats->rxfifooverflow += 2281 xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO); 2282 2283 stats->rxvlanframes_gb += 2284 xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO); 2285 2286 stats->rxwatchdogerror += 2287 xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR); 2288 2289 /* Un-freeze counters */ 2290 XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 0); 2291 } 2292 2293 static void xgbe_config_mmc(struct xgbe_prv_data *pdata) 2294 { 2295 /* Set counters to reset on read */ 2296 XGMAC_IOWRITE_BITS(pdata, MMC_CR, ROR, 1); 2297 2298 /* Reset the counters */ 2299 XGMAC_IOWRITE_BITS(pdata, MMC_CR, CR, 1); 2300 } 2301 2302 static void xgbe_enable_tx(struct xgbe_prv_data *pdata) 2303 { 2304 struct xgbe_channel *channel; 2305 unsigned int i; 2306 2307 /* Enable each Tx DMA channel */ 2308 channel = pdata->channel; 2309 for (i = 0; i < pdata->channel_count; i++, channel++) { 2310 if (!channel->tx_ring) 2311 break; 2312 2313 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 1); 2314 } 2315 2316 /* Enable each Tx queue */ 2317 for (i = 0; i < pdata->tx_q_count; i++) 2318 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN, 2319 MTL_Q_ENABLED); 2320 2321 /* Enable MAC Tx */ 2322 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1); 2323 } 2324 2325 static void xgbe_disable_tx(struct xgbe_prv_data *pdata) 2326 { 2327 struct xgbe_channel *channel; 2328 unsigned int i; 2329 2330 /* Disable MAC Tx */ 2331 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0); 2332 2333 /* Disable each Tx queue */ 2334 for (i = 0; i < pdata->tx_q_count; i++) 2335 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN, 0); 2336 2337 /* Disable each Tx DMA channel */ 2338 channel = pdata->channel; 2339 for (i = 0; i < pdata->channel_count; i++, channel++) { 2340 if (!channel->tx_ring) 2341 break; 2342 2343 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 0); 2344 } 2345 } 2346 2347 static void xgbe_enable_rx(struct xgbe_prv_data *pdata) 2348 { 2349 struct xgbe_channel *channel; 2350 unsigned int reg_val, i; 2351 2352 /* Enable each Rx DMA channel */ 2353 channel = pdata->channel; 2354 for (i = 0; i < pdata->channel_count; i++, channel++) { 2355 if (!channel->rx_ring) 2356 break; 2357 2358 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 1); 2359 } 2360 2361 /* Enable each Rx queue */ 2362 reg_val = 0; 2363 for (i = 0; i < pdata->rx_q_count; i++) 2364 reg_val |= (0x02 << (i << 1)); 2365 XGMAC_IOWRITE(pdata, MAC_RQC0R, reg_val); 2366 2367 /* Enable MAC Rx */ 2368 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 1); 2369 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 1); 2370 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 1); 2371 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 1); 2372 } 2373 2374 static void xgbe_disable_rx(struct xgbe_prv_data *pdata) 2375 { 2376 struct xgbe_channel *channel; 2377 unsigned int i; 2378 2379 /* Disable MAC Rx */ 2380 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 0); 2381 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 0); 2382 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 0); 2383 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 0); 2384 2385 /* Disable each Rx queue */ 2386 XGMAC_IOWRITE(pdata, MAC_RQC0R, 0); 2387 2388 /* Disable each Rx DMA channel */ 2389 channel = pdata->channel; 2390 for (i = 0; i < pdata->channel_count; i++, channel++) { 2391 if (!channel->rx_ring) 2392 break; 2393 2394 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 0); 2395 } 2396 } 2397 2398 static void xgbe_powerup_tx(struct xgbe_prv_data *pdata) 2399 { 2400 struct xgbe_channel *channel; 2401 unsigned int i; 2402 2403 /* Enable each Tx DMA channel */ 2404 channel = pdata->channel; 2405 for (i = 0; i < pdata->channel_count; i++, channel++) { 2406 if (!channel->tx_ring) 2407 break; 2408 2409 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 1); 2410 } 2411 2412 /* Enable MAC Tx */ 2413 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1); 2414 } 2415 2416 static void xgbe_powerdown_tx(struct xgbe_prv_data *pdata) 2417 { 2418 struct xgbe_channel *channel; 2419 unsigned int i; 2420 2421 /* Disable MAC Tx */ 2422 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0); 2423 2424 /* Disable each Tx DMA channel */ 2425 channel = pdata->channel; 2426 for (i = 0; i < pdata->channel_count; i++, channel++) { 2427 if (!channel->tx_ring) 2428 break; 2429 2430 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 0); 2431 } 2432 } 2433 2434 static void xgbe_powerup_rx(struct xgbe_prv_data *pdata) 2435 { 2436 struct xgbe_channel *channel; 2437 unsigned int i; 2438 2439 /* Enable each Rx DMA channel */ 2440 channel = pdata->channel; 2441 for (i = 0; i < pdata->channel_count; i++, channel++) { 2442 if (!channel->rx_ring) 2443 break; 2444 2445 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 1); 2446 } 2447 } 2448 2449 static void xgbe_powerdown_rx(struct xgbe_prv_data *pdata) 2450 { 2451 struct xgbe_channel *channel; 2452 unsigned int i; 2453 2454 /* Disable each Rx DMA channel */ 2455 channel = pdata->channel; 2456 for (i = 0; i < pdata->channel_count; i++, channel++) { 2457 if (!channel->rx_ring) 2458 break; 2459 2460 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 0); 2461 } 2462 } 2463 2464 static int xgbe_init(struct xgbe_prv_data *pdata) 2465 { 2466 struct xgbe_desc_if *desc_if = &pdata->desc_if; 2467 int ret; 2468 2469 DBGPR("-->xgbe_init\n"); 2470 2471 /* Flush Tx queues */ 2472 ret = xgbe_flush_tx_queues(pdata); 2473 if (ret) 2474 return ret; 2475 2476 /* 2477 * Initialize DMA related features 2478 */ 2479 xgbe_config_dma_bus(pdata); 2480 xgbe_config_dma_cache(pdata); 2481 xgbe_config_osp_mode(pdata); 2482 xgbe_config_pblx8(pdata); 2483 xgbe_config_tx_pbl_val(pdata); 2484 xgbe_config_rx_pbl_val(pdata); 2485 xgbe_config_rx_coalesce(pdata); 2486 xgbe_config_tx_coalesce(pdata); 2487 xgbe_config_rx_buffer_size(pdata); 2488 xgbe_config_tso_mode(pdata); 2489 desc_if->wrapper_tx_desc_init(pdata); 2490 desc_if->wrapper_rx_desc_init(pdata); 2491 xgbe_enable_dma_interrupts(pdata); 2492 2493 /* 2494 * Initialize MTL related features 2495 */ 2496 xgbe_config_mtl_mode(pdata); 2497 xgbe_config_queue_mapping(pdata); 2498 xgbe_config_tsf_mode(pdata, pdata->tx_sf_mode); 2499 xgbe_config_rsf_mode(pdata, pdata->rx_sf_mode); 2500 xgbe_config_tx_threshold(pdata, pdata->tx_threshold); 2501 xgbe_config_rx_threshold(pdata, pdata->rx_threshold); 2502 xgbe_config_tx_fifo_size(pdata); 2503 xgbe_config_rx_fifo_size(pdata); 2504 xgbe_config_flow_control_threshold(pdata); 2505 /*TODO: Error Packet and undersized good Packet forwarding enable 2506 (FEP and FUP) 2507 */ 2508 xgbe_config_dcb_tc(pdata); 2509 xgbe_config_dcb_pfc(pdata); 2510 xgbe_enable_mtl_interrupts(pdata); 2511 2512 /* 2513 * Initialize MAC related features 2514 */ 2515 xgbe_config_mac_address(pdata); 2516 xgbe_config_jumbo_enable(pdata); 2517 xgbe_config_flow_control(pdata); 2518 xgbe_config_checksum_offload(pdata); 2519 xgbe_config_vlan_support(pdata); 2520 xgbe_config_mmc(pdata); 2521 xgbe_enable_mac_interrupts(pdata); 2522 2523 DBGPR("<--xgbe_init\n"); 2524 2525 return 0; 2526 } 2527 2528 void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *hw_if) 2529 { 2530 DBGPR("-->xgbe_init_function_ptrs\n"); 2531 2532 hw_if->tx_complete = xgbe_tx_complete; 2533 2534 hw_if->set_promiscuous_mode = xgbe_set_promiscuous_mode; 2535 hw_if->set_all_multicast_mode = xgbe_set_all_multicast_mode; 2536 hw_if->add_mac_addresses = xgbe_add_mac_addresses; 2537 hw_if->set_mac_address = xgbe_set_mac_address; 2538 2539 hw_if->enable_rx_csum = xgbe_enable_rx_csum; 2540 hw_if->disable_rx_csum = xgbe_disable_rx_csum; 2541 2542 hw_if->enable_rx_vlan_stripping = xgbe_enable_rx_vlan_stripping; 2543 hw_if->disable_rx_vlan_stripping = xgbe_disable_rx_vlan_stripping; 2544 hw_if->enable_rx_vlan_filtering = xgbe_enable_rx_vlan_filtering; 2545 hw_if->disable_rx_vlan_filtering = xgbe_disable_rx_vlan_filtering; 2546 hw_if->update_vlan_hash_table = xgbe_update_vlan_hash_table; 2547 2548 hw_if->read_mmd_regs = xgbe_read_mmd_regs; 2549 hw_if->write_mmd_regs = xgbe_write_mmd_regs; 2550 2551 hw_if->set_gmii_speed = xgbe_set_gmii_speed; 2552 hw_if->set_gmii_2500_speed = xgbe_set_gmii_2500_speed; 2553 hw_if->set_xgmii_speed = xgbe_set_xgmii_speed; 2554 2555 hw_if->enable_tx = xgbe_enable_tx; 2556 hw_if->disable_tx = xgbe_disable_tx; 2557 hw_if->enable_rx = xgbe_enable_rx; 2558 hw_if->disable_rx = xgbe_disable_rx; 2559 2560 hw_if->powerup_tx = xgbe_powerup_tx; 2561 hw_if->powerdown_tx = xgbe_powerdown_tx; 2562 hw_if->powerup_rx = xgbe_powerup_rx; 2563 hw_if->powerdown_rx = xgbe_powerdown_rx; 2564 2565 hw_if->pre_xmit = xgbe_pre_xmit; 2566 hw_if->dev_read = xgbe_dev_read; 2567 hw_if->enable_int = xgbe_enable_int; 2568 hw_if->disable_int = xgbe_disable_int; 2569 hw_if->init = xgbe_init; 2570 hw_if->exit = xgbe_exit; 2571 2572 /* Descriptor related Sequences have to be initialized here */ 2573 hw_if->tx_desc_init = xgbe_tx_desc_init; 2574 hw_if->rx_desc_init = xgbe_rx_desc_init; 2575 hw_if->tx_desc_reset = xgbe_tx_desc_reset; 2576 hw_if->rx_desc_reset = xgbe_rx_desc_reset; 2577 hw_if->is_last_desc = xgbe_is_last_desc; 2578 hw_if->is_context_desc = xgbe_is_context_desc; 2579 2580 /* For FLOW ctrl */ 2581 hw_if->config_tx_flow_control = xgbe_config_tx_flow_control; 2582 hw_if->config_rx_flow_control = xgbe_config_rx_flow_control; 2583 2584 /* For RX coalescing */ 2585 hw_if->config_rx_coalesce = xgbe_config_rx_coalesce; 2586 hw_if->config_tx_coalesce = xgbe_config_tx_coalesce; 2587 hw_if->usec_to_riwt = xgbe_usec_to_riwt; 2588 hw_if->riwt_to_usec = xgbe_riwt_to_usec; 2589 2590 /* For RX and TX threshold config */ 2591 hw_if->config_rx_threshold = xgbe_config_rx_threshold; 2592 hw_if->config_tx_threshold = xgbe_config_tx_threshold; 2593 2594 /* For RX and TX Store and Forward Mode config */ 2595 hw_if->config_rsf_mode = xgbe_config_rsf_mode; 2596 hw_if->config_tsf_mode = xgbe_config_tsf_mode; 2597 2598 /* For TX DMA Operating on Second Frame config */ 2599 hw_if->config_osp_mode = xgbe_config_osp_mode; 2600 2601 /* For RX and TX PBL config */ 2602 hw_if->config_rx_pbl_val = xgbe_config_rx_pbl_val; 2603 hw_if->get_rx_pbl_val = xgbe_get_rx_pbl_val; 2604 hw_if->config_tx_pbl_val = xgbe_config_tx_pbl_val; 2605 hw_if->get_tx_pbl_val = xgbe_get_tx_pbl_val; 2606 hw_if->config_pblx8 = xgbe_config_pblx8; 2607 2608 /* For MMC statistics support */ 2609 hw_if->tx_mmc_int = xgbe_tx_mmc_int; 2610 hw_if->rx_mmc_int = xgbe_rx_mmc_int; 2611 hw_if->read_mmc_stats = xgbe_read_mmc_stats; 2612 2613 /* For PTP config */ 2614 hw_if->config_tstamp = xgbe_config_tstamp; 2615 hw_if->update_tstamp_addend = xgbe_update_tstamp_addend; 2616 hw_if->set_tstamp_time = xgbe_set_tstamp_time; 2617 hw_if->get_tstamp_time = xgbe_get_tstamp_time; 2618 hw_if->get_tx_tstamp = xgbe_get_tx_tstamp; 2619 2620 /* For Data Center Bridging config */ 2621 hw_if->config_dcb_tc = xgbe_config_dcb_tc; 2622 hw_if->config_dcb_pfc = xgbe_config_dcb_pfc; 2623 2624 DBGPR("<--xgbe_init_function_ptrs\n"); 2625 } 2626