1 /* 2 * AMD 10Gb Ethernet driver 3 * 4 * This file is available to you under your choice of the following two 5 * licenses: 6 * 7 * License 1: GPLv2 8 * 9 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc. 10 * 11 * This file is free software; you may copy, redistribute and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation, either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program. If not, see <http://www.gnu.org/licenses/>. 23 * 24 * This file incorporates work covered by the following copyright and 25 * permission notice: 26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 28 * Inc. unless otherwise expressly agreed to in writing between Synopsys 29 * and you. 30 * 31 * The Software IS NOT an item of Licensed Software or Licensed Product 32 * under any End User Software License Agreement or Agreement for Licensed 33 * Product with Synopsys or any supplement thereto. Permission is hereby 34 * granted, free of charge, to any person obtaining a copy of this software 35 * annotated with this license and the Software, to deal in the Software 36 * without restriction, including without limitation the rights to use, 37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 38 * of the Software, and to permit persons to whom the Software is furnished 39 * to do so, subject to the following conditions: 40 * 41 * The above copyright notice and this permission notice shall be included 42 * in all copies or substantial portions of the Software. 43 * 44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 54 * THE POSSIBILITY OF SUCH DAMAGE. 55 * 56 * 57 * License 2: Modified BSD 58 * 59 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc. 60 * All rights reserved. 61 * 62 * Redistribution and use in source and binary forms, with or without 63 * modification, are permitted provided that the following conditions are met: 64 * * Redistributions of source code must retain the above copyright 65 * notice, this list of conditions and the following disclaimer. 66 * * Redistributions in binary form must reproduce the above copyright 67 * notice, this list of conditions and the following disclaimer in the 68 * documentation and/or other materials provided with the distribution. 69 * * Neither the name of Advanced Micro Devices, Inc. nor the 70 * names of its contributors may be used to endorse or promote products 71 * derived from this software without specific prior written permission. 72 * 73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY 77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 83 * 84 * This file incorporates work covered by the following copyright and 85 * permission notice: 86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 88 * Inc. unless otherwise expressly agreed to in writing between Synopsys 89 * and you. 90 * 91 * The Software IS NOT an item of Licensed Software or Licensed Product 92 * under any End User Software License Agreement or Agreement for Licensed 93 * Product with Synopsys or any supplement thereto. Permission is hereby 94 * granted, free of charge, to any person obtaining a copy of this software 95 * annotated with this license and the Software, to deal in the Software 96 * without restriction, including without limitation the rights to use, 97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 98 * of the Software, and to permit persons to whom the Software is furnished 99 * to do so, subject to the following conditions: 100 * 101 * The above copyright notice and this permission notice shall be included 102 * in all copies or substantial portions of the Software. 103 * 104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 114 * THE POSSIBILITY OF SUCH DAMAGE. 115 */ 116 117 #include <linux/phy.h> 118 #include <linux/mdio.h> 119 #include <linux/clk.h> 120 #include <linux/bitrev.h> 121 #include <linux/crc32.h> 122 123 #include "xgbe.h" 124 #include "xgbe-common.h" 125 126 static inline unsigned int xgbe_get_max_frame(struct xgbe_prv_data *pdata) 127 { 128 return pdata->netdev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 129 } 130 131 static unsigned int xgbe_usec_to_riwt(struct xgbe_prv_data *pdata, 132 unsigned int usec) 133 { 134 unsigned long rate; 135 unsigned int ret; 136 137 DBGPR("-->xgbe_usec_to_riwt\n"); 138 139 rate = pdata->sysclk_rate; 140 141 /* 142 * Convert the input usec value to the watchdog timer value. Each 143 * watchdog timer value is equivalent to 256 clock cycles. 144 * Calculate the required value as: 145 * ( usec * ( system_clock_mhz / 10^6 ) / 256 146 */ 147 ret = (usec * (rate / 1000000)) / 256; 148 149 DBGPR("<--xgbe_usec_to_riwt\n"); 150 151 return ret; 152 } 153 154 static unsigned int xgbe_riwt_to_usec(struct xgbe_prv_data *pdata, 155 unsigned int riwt) 156 { 157 unsigned long rate; 158 unsigned int ret; 159 160 DBGPR("-->xgbe_riwt_to_usec\n"); 161 162 rate = pdata->sysclk_rate; 163 164 /* 165 * Convert the input watchdog timer value to the usec value. Each 166 * watchdog timer value is equivalent to 256 clock cycles. 167 * Calculate the required value as: 168 * ( riwt * 256 ) / ( system_clock_mhz / 10^6 ) 169 */ 170 ret = (riwt * 256) / (rate / 1000000); 171 172 DBGPR("<--xgbe_riwt_to_usec\n"); 173 174 return ret; 175 } 176 177 static int xgbe_config_pblx8(struct xgbe_prv_data *pdata) 178 { 179 struct xgbe_channel *channel; 180 unsigned int i; 181 182 channel = pdata->channel; 183 for (i = 0; i < pdata->channel_count; i++, channel++) 184 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_CR, PBLX8, 185 pdata->pblx8); 186 187 return 0; 188 } 189 190 static int xgbe_get_tx_pbl_val(struct xgbe_prv_data *pdata) 191 { 192 return XGMAC_DMA_IOREAD_BITS(pdata->channel, DMA_CH_TCR, PBL); 193 } 194 195 static int xgbe_config_tx_pbl_val(struct xgbe_prv_data *pdata) 196 { 197 struct xgbe_channel *channel; 198 unsigned int i; 199 200 channel = pdata->channel; 201 for (i = 0; i < pdata->channel_count; i++, channel++) { 202 if (!channel->tx_ring) 203 break; 204 205 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, PBL, 206 pdata->tx_pbl); 207 } 208 209 return 0; 210 } 211 212 static int xgbe_get_rx_pbl_val(struct xgbe_prv_data *pdata) 213 { 214 return XGMAC_DMA_IOREAD_BITS(pdata->channel, DMA_CH_RCR, PBL); 215 } 216 217 static int xgbe_config_rx_pbl_val(struct xgbe_prv_data *pdata) 218 { 219 struct xgbe_channel *channel; 220 unsigned int i; 221 222 channel = pdata->channel; 223 for (i = 0; i < pdata->channel_count; i++, channel++) { 224 if (!channel->rx_ring) 225 break; 226 227 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, PBL, 228 pdata->rx_pbl); 229 } 230 231 return 0; 232 } 233 234 static int xgbe_config_osp_mode(struct xgbe_prv_data *pdata) 235 { 236 struct xgbe_channel *channel; 237 unsigned int i; 238 239 channel = pdata->channel; 240 for (i = 0; i < pdata->channel_count; i++, channel++) { 241 if (!channel->tx_ring) 242 break; 243 244 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, OSP, 245 pdata->tx_osp_mode); 246 } 247 248 return 0; 249 } 250 251 static int xgbe_config_rsf_mode(struct xgbe_prv_data *pdata, unsigned int val) 252 { 253 unsigned int i; 254 255 for (i = 0; i < pdata->rx_q_count; i++) 256 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RSF, val); 257 258 return 0; 259 } 260 261 static int xgbe_config_tsf_mode(struct xgbe_prv_data *pdata, unsigned int val) 262 { 263 unsigned int i; 264 265 for (i = 0; i < pdata->tx_q_count; i++) 266 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TSF, val); 267 268 return 0; 269 } 270 271 static int xgbe_config_rx_threshold(struct xgbe_prv_data *pdata, 272 unsigned int val) 273 { 274 unsigned int i; 275 276 for (i = 0; i < pdata->rx_q_count; i++) 277 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RTC, val); 278 279 return 0; 280 } 281 282 static int xgbe_config_tx_threshold(struct xgbe_prv_data *pdata, 283 unsigned int val) 284 { 285 unsigned int i; 286 287 for (i = 0; i < pdata->tx_q_count; i++) 288 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TTC, val); 289 290 return 0; 291 } 292 293 static int xgbe_config_rx_coalesce(struct xgbe_prv_data *pdata) 294 { 295 struct xgbe_channel *channel; 296 unsigned int i; 297 298 channel = pdata->channel; 299 for (i = 0; i < pdata->channel_count; i++, channel++) { 300 if (!channel->rx_ring) 301 break; 302 303 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RIWT, RWT, 304 pdata->rx_riwt); 305 } 306 307 return 0; 308 } 309 310 static int xgbe_config_tx_coalesce(struct xgbe_prv_data *pdata) 311 { 312 return 0; 313 } 314 315 static void xgbe_config_rx_buffer_size(struct xgbe_prv_data *pdata) 316 { 317 struct xgbe_channel *channel; 318 unsigned int i; 319 320 channel = pdata->channel; 321 for (i = 0; i < pdata->channel_count; i++, channel++) { 322 if (!channel->rx_ring) 323 break; 324 325 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, RBSZ, 326 pdata->rx_buf_size); 327 } 328 } 329 330 static void xgbe_config_tso_mode(struct xgbe_prv_data *pdata) 331 { 332 struct xgbe_channel *channel; 333 unsigned int i; 334 335 channel = pdata->channel; 336 for (i = 0; i < pdata->channel_count; i++, channel++) { 337 if (!channel->tx_ring) 338 break; 339 340 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, TSE, 1); 341 } 342 } 343 344 static void xgbe_config_sph_mode(struct xgbe_prv_data *pdata) 345 { 346 struct xgbe_channel *channel; 347 unsigned int i; 348 349 channel = pdata->channel; 350 for (i = 0; i < pdata->channel_count; i++, channel++) { 351 if (!channel->rx_ring) 352 break; 353 354 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_CR, SPH, 1); 355 } 356 357 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, HDSMS, XGBE_SPH_HDSMS_SIZE); 358 } 359 360 static int xgbe_write_rss_reg(struct xgbe_prv_data *pdata, unsigned int type, 361 unsigned int index, unsigned int val) 362 { 363 unsigned int wait; 364 int ret = 0; 365 366 mutex_lock(&pdata->rss_mutex); 367 368 if (XGMAC_IOREAD_BITS(pdata, MAC_RSSAR, OB)) { 369 ret = -EBUSY; 370 goto unlock; 371 } 372 373 XGMAC_IOWRITE(pdata, MAC_RSSDR, val); 374 375 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, RSSIA, index); 376 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, ADDRT, type); 377 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, CT, 0); 378 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, OB, 1); 379 380 wait = 1000; 381 while (wait--) { 382 if (!XGMAC_IOREAD_BITS(pdata, MAC_RSSAR, OB)) 383 goto unlock; 384 385 usleep_range(1000, 1500); 386 } 387 388 ret = -EBUSY; 389 390 unlock: 391 mutex_unlock(&pdata->rss_mutex); 392 393 return ret; 394 } 395 396 static int xgbe_write_rss_hash_key(struct xgbe_prv_data *pdata) 397 { 398 unsigned int key_regs = sizeof(pdata->rss_key) / sizeof(u32); 399 unsigned int *key = (unsigned int *)&pdata->rss_key; 400 int ret; 401 402 while (key_regs--) { 403 ret = xgbe_write_rss_reg(pdata, XGBE_RSS_HASH_KEY_TYPE, 404 key_regs, *key++); 405 if (ret) 406 return ret; 407 } 408 409 return 0; 410 } 411 412 static int xgbe_write_rss_lookup_table(struct xgbe_prv_data *pdata) 413 { 414 unsigned int i; 415 int ret; 416 417 for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++) { 418 ret = xgbe_write_rss_reg(pdata, 419 XGBE_RSS_LOOKUP_TABLE_TYPE, i, 420 pdata->rss_table[i]); 421 if (ret) 422 return ret; 423 } 424 425 return 0; 426 } 427 428 static int xgbe_set_rss_hash_key(struct xgbe_prv_data *pdata, const u8 *key) 429 { 430 memcpy(pdata->rss_key, key, sizeof(pdata->rss_key)); 431 432 return xgbe_write_rss_hash_key(pdata); 433 } 434 435 static int xgbe_set_rss_lookup_table(struct xgbe_prv_data *pdata, 436 const u32 *table) 437 { 438 unsigned int i; 439 440 for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++) 441 XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH, table[i]); 442 443 return xgbe_write_rss_lookup_table(pdata); 444 } 445 446 static int xgbe_enable_rss(struct xgbe_prv_data *pdata) 447 { 448 int ret; 449 450 if (!pdata->hw_feat.rss) 451 return -EOPNOTSUPP; 452 453 /* Program the hash key */ 454 ret = xgbe_write_rss_hash_key(pdata); 455 if (ret) 456 return ret; 457 458 /* Program the lookup table */ 459 ret = xgbe_write_rss_lookup_table(pdata); 460 if (ret) 461 return ret; 462 463 /* Set the RSS options */ 464 XGMAC_IOWRITE(pdata, MAC_RSSCR, pdata->rss_options); 465 466 /* Enable RSS */ 467 XGMAC_IOWRITE_BITS(pdata, MAC_RSSCR, RSSE, 1); 468 469 return 0; 470 } 471 472 static int xgbe_disable_rss(struct xgbe_prv_data *pdata) 473 { 474 if (!pdata->hw_feat.rss) 475 return -EOPNOTSUPP; 476 477 XGMAC_IOWRITE_BITS(pdata, MAC_RSSCR, RSSE, 0); 478 479 return 0; 480 } 481 482 static void xgbe_config_rss(struct xgbe_prv_data *pdata) 483 { 484 int ret; 485 486 if (!pdata->hw_feat.rss) 487 return; 488 489 if (pdata->netdev->features & NETIF_F_RXHASH) 490 ret = xgbe_enable_rss(pdata); 491 else 492 ret = xgbe_disable_rss(pdata); 493 494 if (ret) 495 netdev_err(pdata->netdev, 496 "error configuring RSS, RSS disabled\n"); 497 } 498 499 static bool xgbe_is_pfc_queue(struct xgbe_prv_data *pdata, 500 unsigned int queue) 501 { 502 unsigned int prio, tc; 503 504 for (prio = 0; prio < IEEE_8021QAZ_MAX_TCS; prio++) { 505 /* Does this queue handle the priority? */ 506 if (pdata->prio2q_map[prio] != queue) 507 continue; 508 509 /* Get the Traffic Class for this priority */ 510 tc = pdata->ets->prio_tc[prio]; 511 512 /* Check if PFC is enabled for this traffic class */ 513 if (pdata->pfc->pfc_en & (1 << tc)) 514 return true; 515 } 516 517 return false; 518 } 519 520 static int xgbe_disable_tx_flow_control(struct xgbe_prv_data *pdata) 521 { 522 unsigned int max_q_count, q_count; 523 unsigned int reg, reg_val; 524 unsigned int i; 525 526 /* Clear MTL flow control */ 527 for (i = 0; i < pdata->rx_q_count; i++) 528 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, 0); 529 530 /* Clear MAC flow control */ 531 max_q_count = XGMAC_MAX_FLOW_CONTROL_QUEUES; 532 q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count); 533 reg = MAC_Q0TFCR; 534 for (i = 0; i < q_count; i++) { 535 reg_val = XGMAC_IOREAD(pdata, reg); 536 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 0); 537 XGMAC_IOWRITE(pdata, reg, reg_val); 538 539 reg += MAC_QTFCR_INC; 540 } 541 542 return 0; 543 } 544 545 static int xgbe_enable_tx_flow_control(struct xgbe_prv_data *pdata) 546 { 547 struct ieee_pfc *pfc = pdata->pfc; 548 struct ieee_ets *ets = pdata->ets; 549 unsigned int max_q_count, q_count; 550 unsigned int reg, reg_val; 551 unsigned int i; 552 553 /* Set MTL flow control */ 554 for (i = 0; i < pdata->rx_q_count; i++) { 555 unsigned int ehfc = 0; 556 557 if (pdata->rx_rfd[i]) { 558 /* Flow control thresholds are established */ 559 if (pfc && ets) { 560 if (xgbe_is_pfc_queue(pdata, i)) 561 ehfc = 1; 562 } else { 563 ehfc = 1; 564 } 565 } 566 567 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, ehfc); 568 569 netif_dbg(pdata, drv, pdata->netdev, 570 "flow control %s for RXq%u\n", 571 ehfc ? "enabled" : "disabled", i); 572 } 573 574 /* Set MAC flow control */ 575 max_q_count = XGMAC_MAX_FLOW_CONTROL_QUEUES; 576 q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count); 577 reg = MAC_Q0TFCR; 578 for (i = 0; i < q_count; i++) { 579 reg_val = XGMAC_IOREAD(pdata, reg); 580 581 /* Enable transmit flow control */ 582 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 1); 583 /* Set pause time */ 584 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, PT, 0xffff); 585 586 XGMAC_IOWRITE(pdata, reg, reg_val); 587 588 reg += MAC_QTFCR_INC; 589 } 590 591 return 0; 592 } 593 594 static int xgbe_disable_rx_flow_control(struct xgbe_prv_data *pdata) 595 { 596 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 0); 597 598 return 0; 599 } 600 601 static int xgbe_enable_rx_flow_control(struct xgbe_prv_data *pdata) 602 { 603 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 1); 604 605 return 0; 606 } 607 608 static int xgbe_config_tx_flow_control(struct xgbe_prv_data *pdata) 609 { 610 struct ieee_pfc *pfc = pdata->pfc; 611 612 if (pdata->tx_pause || (pfc && pfc->pfc_en)) 613 xgbe_enable_tx_flow_control(pdata); 614 else 615 xgbe_disable_tx_flow_control(pdata); 616 617 return 0; 618 } 619 620 static int xgbe_config_rx_flow_control(struct xgbe_prv_data *pdata) 621 { 622 struct ieee_pfc *pfc = pdata->pfc; 623 624 if (pdata->rx_pause || (pfc && pfc->pfc_en)) 625 xgbe_enable_rx_flow_control(pdata); 626 else 627 xgbe_disable_rx_flow_control(pdata); 628 629 return 0; 630 } 631 632 static void xgbe_config_flow_control(struct xgbe_prv_data *pdata) 633 { 634 struct ieee_pfc *pfc = pdata->pfc; 635 636 xgbe_config_tx_flow_control(pdata); 637 xgbe_config_rx_flow_control(pdata); 638 639 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 640 (pfc && pfc->pfc_en) ? 1 : 0); 641 } 642 643 static void xgbe_enable_dma_interrupts(struct xgbe_prv_data *pdata) 644 { 645 struct xgbe_channel *channel; 646 unsigned int dma_ch_isr, dma_ch_ier; 647 unsigned int i; 648 649 /* Set the interrupt mode if supported */ 650 if (pdata->channel_irq_mode) 651 XGMAC_IOWRITE_BITS(pdata, DMA_MR, INTM, 652 pdata->channel_irq_mode); 653 654 channel = pdata->channel; 655 for (i = 0; i < pdata->channel_count; i++, channel++) { 656 /* Clear all the interrupts which are set */ 657 dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR); 658 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr); 659 660 /* Clear all interrupt enable bits */ 661 dma_ch_ier = 0; 662 663 /* Enable following interrupts 664 * NIE - Normal Interrupt Summary Enable 665 * AIE - Abnormal Interrupt Summary Enable 666 * FBEE - Fatal Bus Error Enable 667 */ 668 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, NIE, 1); 669 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, AIE, 1); 670 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, FBEE, 1); 671 672 if (channel->tx_ring) { 673 /* Enable the following Tx interrupts 674 * TIE - Transmit Interrupt Enable (unless using 675 * per channel interrupts in edge triggered 676 * mode) 677 */ 678 if (!pdata->per_channel_irq || pdata->channel_irq_mode) 679 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 1); 680 } 681 if (channel->rx_ring) { 682 /* Enable following Rx interrupts 683 * RBUE - Receive Buffer Unavailable Enable 684 * RIE - Receive Interrupt Enable (unless using 685 * per channel interrupts in edge triggered 686 * mode) 687 */ 688 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RBUE, 1); 689 if (!pdata->per_channel_irq || pdata->channel_irq_mode) 690 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 1); 691 } 692 693 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, dma_ch_ier); 694 } 695 } 696 697 static void xgbe_enable_mtl_interrupts(struct xgbe_prv_data *pdata) 698 { 699 unsigned int mtl_q_isr; 700 unsigned int q_count, i; 701 702 q_count = max(pdata->hw_feat.tx_q_cnt, pdata->hw_feat.rx_q_cnt); 703 for (i = 0; i < q_count; i++) { 704 /* Clear all the interrupts which are set */ 705 mtl_q_isr = XGMAC_MTL_IOREAD(pdata, i, MTL_Q_ISR); 706 XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_ISR, mtl_q_isr); 707 708 /* No MTL interrupts to be enabled */ 709 XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_IER, 0); 710 } 711 } 712 713 static void xgbe_enable_mac_interrupts(struct xgbe_prv_data *pdata) 714 { 715 unsigned int mac_ier = 0; 716 717 /* Enable Timestamp interrupt */ 718 XGMAC_SET_BITS(mac_ier, MAC_IER, TSIE, 1); 719 720 XGMAC_IOWRITE(pdata, MAC_IER, mac_ier); 721 722 /* Enable all counter interrupts */ 723 XGMAC_IOWRITE_BITS(pdata, MMC_RIER, ALL_INTERRUPTS, 0xffffffff); 724 XGMAC_IOWRITE_BITS(pdata, MMC_TIER, ALL_INTERRUPTS, 0xffffffff); 725 726 /* Enable MDIO single command completion interrupt */ 727 XGMAC_IOWRITE_BITS(pdata, MAC_MDIOIER, SNGLCOMPIE, 1); 728 } 729 730 static void xgbe_enable_ecc_interrupts(struct xgbe_prv_data *pdata) 731 { 732 unsigned int ecc_isr, ecc_ier = 0; 733 734 if (!pdata->vdata->ecc_support) 735 return; 736 737 /* Clear all the interrupts which are set */ 738 ecc_isr = XP_IOREAD(pdata, XP_ECC_ISR); 739 XP_IOWRITE(pdata, XP_ECC_ISR, ecc_isr); 740 741 /* Enable ECC interrupts */ 742 XP_SET_BITS(ecc_ier, XP_ECC_IER, TX_DED, 1); 743 XP_SET_BITS(ecc_ier, XP_ECC_IER, TX_SEC, 1); 744 XP_SET_BITS(ecc_ier, XP_ECC_IER, RX_DED, 1); 745 XP_SET_BITS(ecc_ier, XP_ECC_IER, RX_SEC, 1); 746 XP_SET_BITS(ecc_ier, XP_ECC_IER, DESC_DED, 1); 747 XP_SET_BITS(ecc_ier, XP_ECC_IER, DESC_SEC, 1); 748 749 XP_IOWRITE(pdata, XP_ECC_IER, ecc_ier); 750 } 751 752 static void xgbe_disable_ecc_ded(struct xgbe_prv_data *pdata) 753 { 754 unsigned int ecc_ier; 755 756 ecc_ier = XP_IOREAD(pdata, XP_ECC_IER); 757 758 /* Disable ECC DED interrupts */ 759 XP_SET_BITS(ecc_ier, XP_ECC_IER, TX_DED, 0); 760 XP_SET_BITS(ecc_ier, XP_ECC_IER, RX_DED, 0); 761 XP_SET_BITS(ecc_ier, XP_ECC_IER, DESC_DED, 0); 762 763 XP_IOWRITE(pdata, XP_ECC_IER, ecc_ier); 764 } 765 766 static void xgbe_disable_ecc_sec(struct xgbe_prv_data *pdata, 767 enum xgbe_ecc_sec sec) 768 { 769 unsigned int ecc_ier; 770 771 ecc_ier = XP_IOREAD(pdata, XP_ECC_IER); 772 773 /* Disable ECC SEC interrupt */ 774 switch (sec) { 775 case XGBE_ECC_SEC_TX: 776 XP_SET_BITS(ecc_ier, XP_ECC_IER, TX_SEC, 0); 777 break; 778 case XGBE_ECC_SEC_RX: 779 XP_SET_BITS(ecc_ier, XP_ECC_IER, RX_SEC, 0); 780 break; 781 case XGBE_ECC_SEC_DESC: 782 XP_SET_BITS(ecc_ier, XP_ECC_IER, DESC_SEC, 0); 783 break; 784 } 785 786 XP_IOWRITE(pdata, XP_ECC_IER, ecc_ier); 787 } 788 789 static int xgbe_set_speed(struct xgbe_prv_data *pdata, int speed) 790 { 791 unsigned int ss; 792 793 switch (speed) { 794 case SPEED_1000: 795 ss = 0x03; 796 break; 797 case SPEED_2500: 798 ss = 0x02; 799 break; 800 case SPEED_10000: 801 ss = 0x00; 802 break; 803 default: 804 return -EINVAL; 805 } 806 807 if (XGMAC_IOREAD_BITS(pdata, MAC_TCR, SS) != ss) 808 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, ss); 809 810 return 0; 811 } 812 813 static int xgbe_enable_rx_vlan_stripping(struct xgbe_prv_data *pdata) 814 { 815 /* Put the VLAN tag in the Rx descriptor */ 816 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLRXS, 1); 817 818 /* Don't check the VLAN type */ 819 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, DOVLTC, 1); 820 821 /* Check only C-TAG (0x8100) packets */ 822 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ERSVLM, 0); 823 824 /* Don't consider an S-TAG (0x88A8) packet as a VLAN packet */ 825 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ESVL, 0); 826 827 /* Enable VLAN tag stripping */ 828 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0x3); 829 830 return 0; 831 } 832 833 static int xgbe_disable_rx_vlan_stripping(struct xgbe_prv_data *pdata) 834 { 835 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0); 836 837 return 0; 838 } 839 840 static int xgbe_enable_rx_vlan_filtering(struct xgbe_prv_data *pdata) 841 { 842 /* Enable VLAN filtering */ 843 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 1); 844 845 /* Enable VLAN Hash Table filtering */ 846 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTHM, 1); 847 848 /* Disable VLAN tag inverse matching */ 849 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTIM, 0); 850 851 /* Only filter on the lower 12-bits of the VLAN tag */ 852 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ETV, 1); 853 854 /* In order for the VLAN Hash Table filtering to be effective, 855 * the VLAN tag identifier in the VLAN Tag Register must not 856 * be zero. Set the VLAN tag identifier to "1" to enable the 857 * VLAN Hash Table filtering. This implies that a VLAN tag of 858 * 1 will always pass filtering. 859 */ 860 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VL, 1); 861 862 return 0; 863 } 864 865 static int xgbe_disable_rx_vlan_filtering(struct xgbe_prv_data *pdata) 866 { 867 /* Disable VLAN filtering */ 868 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 0); 869 870 return 0; 871 } 872 873 static u32 xgbe_vid_crc32_le(__le16 vid_le) 874 { 875 u32 poly = 0xedb88320; /* CRCPOLY_LE */ 876 u32 crc = ~0; 877 u32 temp = 0; 878 unsigned char *data = (unsigned char *)&vid_le; 879 unsigned char data_byte = 0; 880 int i, bits; 881 882 bits = get_bitmask_order(VLAN_VID_MASK); 883 for (i = 0; i < bits; i++) { 884 if ((i % 8) == 0) 885 data_byte = data[i / 8]; 886 887 temp = ((crc & 1) ^ data_byte) & 1; 888 crc >>= 1; 889 data_byte >>= 1; 890 891 if (temp) 892 crc ^= poly; 893 } 894 895 return crc; 896 } 897 898 static int xgbe_update_vlan_hash_table(struct xgbe_prv_data *pdata) 899 { 900 u32 crc; 901 u16 vid; 902 __le16 vid_le; 903 u16 vlan_hash_table = 0; 904 905 /* Generate the VLAN Hash Table value */ 906 for_each_set_bit(vid, pdata->active_vlans, VLAN_N_VID) { 907 /* Get the CRC32 value of the VLAN ID */ 908 vid_le = cpu_to_le16(vid); 909 crc = bitrev32(~xgbe_vid_crc32_le(vid_le)) >> 28; 910 911 vlan_hash_table |= (1 << crc); 912 } 913 914 /* Set the VLAN Hash Table filtering register */ 915 XGMAC_IOWRITE_BITS(pdata, MAC_VLANHTR, VLHT, vlan_hash_table); 916 917 return 0; 918 } 919 920 static int xgbe_set_promiscuous_mode(struct xgbe_prv_data *pdata, 921 unsigned int enable) 922 { 923 unsigned int val = enable ? 1 : 0; 924 925 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PR) == val) 926 return 0; 927 928 netif_dbg(pdata, drv, pdata->netdev, "%s promiscuous mode\n", 929 enable ? "entering" : "leaving"); 930 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, val); 931 932 /* Hardware will still perform VLAN filtering in promiscuous mode */ 933 if (enable) { 934 xgbe_disable_rx_vlan_filtering(pdata); 935 } else { 936 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER) 937 xgbe_enable_rx_vlan_filtering(pdata); 938 } 939 940 return 0; 941 } 942 943 static int xgbe_set_all_multicast_mode(struct xgbe_prv_data *pdata, 944 unsigned int enable) 945 { 946 unsigned int val = enable ? 1 : 0; 947 948 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PM) == val) 949 return 0; 950 951 netif_dbg(pdata, drv, pdata->netdev, "%s allmulti mode\n", 952 enable ? "entering" : "leaving"); 953 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, val); 954 955 return 0; 956 } 957 958 static void xgbe_set_mac_reg(struct xgbe_prv_data *pdata, 959 struct netdev_hw_addr *ha, unsigned int *mac_reg) 960 { 961 unsigned int mac_addr_hi, mac_addr_lo; 962 u8 *mac_addr; 963 964 mac_addr_lo = 0; 965 mac_addr_hi = 0; 966 967 if (ha) { 968 mac_addr = (u8 *)&mac_addr_lo; 969 mac_addr[0] = ha->addr[0]; 970 mac_addr[1] = ha->addr[1]; 971 mac_addr[2] = ha->addr[2]; 972 mac_addr[3] = ha->addr[3]; 973 mac_addr = (u8 *)&mac_addr_hi; 974 mac_addr[0] = ha->addr[4]; 975 mac_addr[1] = ha->addr[5]; 976 977 netif_dbg(pdata, drv, pdata->netdev, 978 "adding mac address %pM at %#x\n", 979 ha->addr, *mac_reg); 980 981 XGMAC_SET_BITS(mac_addr_hi, MAC_MACA1HR, AE, 1); 982 } 983 984 XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_hi); 985 *mac_reg += MAC_MACA_INC; 986 XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_lo); 987 *mac_reg += MAC_MACA_INC; 988 } 989 990 static void xgbe_set_mac_addn_addrs(struct xgbe_prv_data *pdata) 991 { 992 struct net_device *netdev = pdata->netdev; 993 struct netdev_hw_addr *ha; 994 unsigned int mac_reg; 995 unsigned int addn_macs; 996 997 mac_reg = MAC_MACA1HR; 998 addn_macs = pdata->hw_feat.addn_mac; 999 1000 if (netdev_uc_count(netdev) > addn_macs) { 1001 xgbe_set_promiscuous_mode(pdata, 1); 1002 } else { 1003 netdev_for_each_uc_addr(ha, netdev) { 1004 xgbe_set_mac_reg(pdata, ha, &mac_reg); 1005 addn_macs--; 1006 } 1007 1008 if (netdev_mc_count(netdev) > addn_macs) { 1009 xgbe_set_all_multicast_mode(pdata, 1); 1010 } else { 1011 netdev_for_each_mc_addr(ha, netdev) { 1012 xgbe_set_mac_reg(pdata, ha, &mac_reg); 1013 addn_macs--; 1014 } 1015 } 1016 } 1017 1018 /* Clear remaining additional MAC address entries */ 1019 while (addn_macs--) 1020 xgbe_set_mac_reg(pdata, NULL, &mac_reg); 1021 } 1022 1023 static void xgbe_set_mac_hash_table(struct xgbe_prv_data *pdata) 1024 { 1025 struct net_device *netdev = pdata->netdev; 1026 struct netdev_hw_addr *ha; 1027 unsigned int hash_reg; 1028 unsigned int hash_table_shift, hash_table_count; 1029 u32 hash_table[XGBE_MAC_HASH_TABLE_SIZE]; 1030 u32 crc; 1031 unsigned int i; 1032 1033 hash_table_shift = 26 - (pdata->hw_feat.hash_table_size >> 7); 1034 hash_table_count = pdata->hw_feat.hash_table_size / 32; 1035 memset(hash_table, 0, sizeof(hash_table)); 1036 1037 /* Build the MAC Hash Table register values */ 1038 netdev_for_each_uc_addr(ha, netdev) { 1039 crc = bitrev32(~crc32_le(~0, ha->addr, ETH_ALEN)); 1040 crc >>= hash_table_shift; 1041 hash_table[crc >> 5] |= (1 << (crc & 0x1f)); 1042 } 1043 1044 netdev_for_each_mc_addr(ha, netdev) { 1045 crc = bitrev32(~crc32_le(~0, ha->addr, ETH_ALEN)); 1046 crc >>= hash_table_shift; 1047 hash_table[crc >> 5] |= (1 << (crc & 0x1f)); 1048 } 1049 1050 /* Set the MAC Hash Table registers */ 1051 hash_reg = MAC_HTR0; 1052 for (i = 0; i < hash_table_count; i++) { 1053 XGMAC_IOWRITE(pdata, hash_reg, hash_table[i]); 1054 hash_reg += MAC_HTR_INC; 1055 } 1056 } 1057 1058 static int xgbe_add_mac_addresses(struct xgbe_prv_data *pdata) 1059 { 1060 if (pdata->hw_feat.hash_table_size) 1061 xgbe_set_mac_hash_table(pdata); 1062 else 1063 xgbe_set_mac_addn_addrs(pdata); 1064 1065 return 0; 1066 } 1067 1068 static int xgbe_set_mac_address(struct xgbe_prv_data *pdata, u8 *addr) 1069 { 1070 unsigned int mac_addr_hi, mac_addr_lo; 1071 1072 mac_addr_hi = (addr[5] << 8) | (addr[4] << 0); 1073 mac_addr_lo = (addr[3] << 24) | (addr[2] << 16) | 1074 (addr[1] << 8) | (addr[0] << 0); 1075 1076 XGMAC_IOWRITE(pdata, MAC_MACA0HR, mac_addr_hi); 1077 XGMAC_IOWRITE(pdata, MAC_MACA0LR, mac_addr_lo); 1078 1079 return 0; 1080 } 1081 1082 static int xgbe_config_rx_mode(struct xgbe_prv_data *pdata) 1083 { 1084 struct net_device *netdev = pdata->netdev; 1085 unsigned int pr_mode, am_mode; 1086 1087 pr_mode = ((netdev->flags & IFF_PROMISC) != 0); 1088 am_mode = ((netdev->flags & IFF_ALLMULTI) != 0); 1089 1090 xgbe_set_promiscuous_mode(pdata, pr_mode); 1091 xgbe_set_all_multicast_mode(pdata, am_mode); 1092 1093 xgbe_add_mac_addresses(pdata); 1094 1095 return 0; 1096 } 1097 1098 static int xgbe_clr_gpio(struct xgbe_prv_data *pdata, unsigned int gpio) 1099 { 1100 unsigned int reg; 1101 1102 if (gpio > 15) 1103 return -EINVAL; 1104 1105 reg = XGMAC_IOREAD(pdata, MAC_GPIOSR); 1106 1107 reg &= ~(1 << (gpio + 16)); 1108 XGMAC_IOWRITE(pdata, MAC_GPIOSR, reg); 1109 1110 return 0; 1111 } 1112 1113 static int xgbe_set_gpio(struct xgbe_prv_data *pdata, unsigned int gpio) 1114 { 1115 unsigned int reg; 1116 1117 if (gpio > 15) 1118 return -EINVAL; 1119 1120 reg = XGMAC_IOREAD(pdata, MAC_GPIOSR); 1121 1122 reg |= (1 << (gpio + 16)); 1123 XGMAC_IOWRITE(pdata, MAC_GPIOSR, reg); 1124 1125 return 0; 1126 } 1127 1128 static int xgbe_read_mmd_regs_v2(struct xgbe_prv_data *pdata, int prtad, 1129 int mmd_reg) 1130 { 1131 unsigned long flags; 1132 unsigned int mmd_address, index, offset; 1133 int mmd_data; 1134 1135 if (mmd_reg & MII_ADDR_C45) 1136 mmd_address = mmd_reg & ~MII_ADDR_C45; 1137 else 1138 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); 1139 1140 /* The PCS registers are accessed using mmio. The underlying 1141 * management interface uses indirect addressing to access the MMD 1142 * register sets. This requires accessing of the PCS register in two 1143 * phases, an address phase and a data phase. 1144 * 1145 * The mmio interface is based on 16-bit offsets and values. All 1146 * register offsets must therefore be adjusted by left shifting the 1147 * offset 1 bit and reading 16 bits of data. 1148 */ 1149 mmd_address <<= 1; 1150 index = mmd_address & ~pdata->xpcs_window_mask; 1151 offset = pdata->xpcs_window + (mmd_address & pdata->xpcs_window_mask); 1152 1153 spin_lock_irqsave(&pdata->xpcs_lock, flags); 1154 XPCS32_IOWRITE(pdata, PCS_V2_WINDOW_SELECT, index); 1155 mmd_data = XPCS16_IOREAD(pdata, offset); 1156 spin_unlock_irqrestore(&pdata->xpcs_lock, flags); 1157 1158 return mmd_data; 1159 } 1160 1161 static void xgbe_write_mmd_regs_v2(struct xgbe_prv_data *pdata, int prtad, 1162 int mmd_reg, int mmd_data) 1163 { 1164 unsigned long flags; 1165 unsigned int mmd_address, index, offset; 1166 1167 if (mmd_reg & MII_ADDR_C45) 1168 mmd_address = mmd_reg & ~MII_ADDR_C45; 1169 else 1170 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); 1171 1172 /* The PCS registers are accessed using mmio. The underlying 1173 * management interface uses indirect addressing to access the MMD 1174 * register sets. This requires accessing of the PCS register in two 1175 * phases, an address phase and a data phase. 1176 * 1177 * The mmio interface is based on 16-bit offsets and values. All 1178 * register offsets must therefore be adjusted by left shifting the 1179 * offset 1 bit and writing 16 bits of data. 1180 */ 1181 mmd_address <<= 1; 1182 index = mmd_address & ~pdata->xpcs_window_mask; 1183 offset = pdata->xpcs_window + (mmd_address & pdata->xpcs_window_mask); 1184 1185 spin_lock_irqsave(&pdata->xpcs_lock, flags); 1186 XPCS32_IOWRITE(pdata, PCS_V2_WINDOW_SELECT, index); 1187 XPCS16_IOWRITE(pdata, offset, mmd_data); 1188 spin_unlock_irqrestore(&pdata->xpcs_lock, flags); 1189 } 1190 1191 static int xgbe_read_mmd_regs_v1(struct xgbe_prv_data *pdata, int prtad, 1192 int mmd_reg) 1193 { 1194 unsigned long flags; 1195 unsigned int mmd_address; 1196 int mmd_data; 1197 1198 if (mmd_reg & MII_ADDR_C45) 1199 mmd_address = mmd_reg & ~MII_ADDR_C45; 1200 else 1201 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); 1202 1203 /* The PCS registers are accessed using mmio. The underlying APB3 1204 * management interface uses indirect addressing to access the MMD 1205 * register sets. This requires accessing of the PCS register in two 1206 * phases, an address phase and a data phase. 1207 * 1208 * The mmio interface is based on 32-bit offsets and values. All 1209 * register offsets must therefore be adjusted by left shifting the 1210 * offset 2 bits and reading 32 bits of data. 1211 */ 1212 spin_lock_irqsave(&pdata->xpcs_lock, flags); 1213 XPCS32_IOWRITE(pdata, PCS_V1_WINDOW_SELECT, mmd_address >> 8); 1214 mmd_data = XPCS32_IOREAD(pdata, (mmd_address & 0xff) << 2); 1215 spin_unlock_irqrestore(&pdata->xpcs_lock, flags); 1216 1217 return mmd_data; 1218 } 1219 1220 static void xgbe_write_mmd_regs_v1(struct xgbe_prv_data *pdata, int prtad, 1221 int mmd_reg, int mmd_data) 1222 { 1223 unsigned int mmd_address; 1224 unsigned long flags; 1225 1226 if (mmd_reg & MII_ADDR_C45) 1227 mmd_address = mmd_reg & ~MII_ADDR_C45; 1228 else 1229 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); 1230 1231 /* The PCS registers are accessed using mmio. The underlying APB3 1232 * management interface uses indirect addressing to access the MMD 1233 * register sets. This requires accessing of the PCS register in two 1234 * phases, an address phase and a data phase. 1235 * 1236 * The mmio interface is based on 32-bit offsets and values. All 1237 * register offsets must therefore be adjusted by left shifting the 1238 * offset 2 bits and writing 32 bits of data. 1239 */ 1240 spin_lock_irqsave(&pdata->xpcs_lock, flags); 1241 XPCS32_IOWRITE(pdata, PCS_V1_WINDOW_SELECT, mmd_address >> 8); 1242 XPCS32_IOWRITE(pdata, (mmd_address & 0xff) << 2, mmd_data); 1243 spin_unlock_irqrestore(&pdata->xpcs_lock, flags); 1244 } 1245 1246 static int xgbe_read_mmd_regs(struct xgbe_prv_data *pdata, int prtad, 1247 int mmd_reg) 1248 { 1249 switch (pdata->vdata->xpcs_access) { 1250 case XGBE_XPCS_ACCESS_V1: 1251 return xgbe_read_mmd_regs_v1(pdata, prtad, mmd_reg); 1252 1253 case XGBE_XPCS_ACCESS_V2: 1254 default: 1255 return xgbe_read_mmd_regs_v2(pdata, prtad, mmd_reg); 1256 } 1257 } 1258 1259 static void xgbe_write_mmd_regs(struct xgbe_prv_data *pdata, int prtad, 1260 int mmd_reg, int mmd_data) 1261 { 1262 switch (pdata->vdata->xpcs_access) { 1263 case XGBE_XPCS_ACCESS_V1: 1264 return xgbe_write_mmd_regs_v1(pdata, prtad, mmd_reg, mmd_data); 1265 1266 case XGBE_XPCS_ACCESS_V2: 1267 default: 1268 return xgbe_write_mmd_regs_v2(pdata, prtad, mmd_reg, mmd_data); 1269 } 1270 } 1271 1272 static int xgbe_write_ext_mii_regs(struct xgbe_prv_data *pdata, int addr, 1273 int reg, u16 val) 1274 { 1275 unsigned int mdio_sca, mdio_sccd; 1276 1277 reinit_completion(&pdata->mdio_complete); 1278 1279 mdio_sca = 0; 1280 XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, REG, reg); 1281 XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, DA, addr); 1282 XGMAC_IOWRITE(pdata, MAC_MDIOSCAR, mdio_sca); 1283 1284 mdio_sccd = 0; 1285 XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, DATA, val); 1286 XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, CMD, 1); 1287 XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, BUSY, 1); 1288 XGMAC_IOWRITE(pdata, MAC_MDIOSCCDR, mdio_sccd); 1289 1290 if (!wait_for_completion_timeout(&pdata->mdio_complete, HZ)) { 1291 netdev_err(pdata->netdev, "mdio write operation timed out\n"); 1292 return -ETIMEDOUT; 1293 } 1294 1295 return 0; 1296 } 1297 1298 static int xgbe_read_ext_mii_regs(struct xgbe_prv_data *pdata, int addr, 1299 int reg) 1300 { 1301 unsigned int mdio_sca, mdio_sccd; 1302 1303 reinit_completion(&pdata->mdio_complete); 1304 1305 mdio_sca = 0; 1306 XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, REG, reg); 1307 XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, DA, addr); 1308 XGMAC_IOWRITE(pdata, MAC_MDIOSCAR, mdio_sca); 1309 1310 mdio_sccd = 0; 1311 XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, CMD, 3); 1312 XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, BUSY, 1); 1313 XGMAC_IOWRITE(pdata, MAC_MDIOSCCDR, mdio_sccd); 1314 1315 if (!wait_for_completion_timeout(&pdata->mdio_complete, HZ)) { 1316 netdev_err(pdata->netdev, "mdio read operation timed out\n"); 1317 return -ETIMEDOUT; 1318 } 1319 1320 return XGMAC_IOREAD_BITS(pdata, MAC_MDIOSCCDR, DATA); 1321 } 1322 1323 static int xgbe_set_ext_mii_mode(struct xgbe_prv_data *pdata, unsigned int port, 1324 enum xgbe_mdio_mode mode) 1325 { 1326 unsigned int reg_val = 0; 1327 1328 switch (mode) { 1329 case XGBE_MDIO_MODE_CL22: 1330 if (port > XGMAC_MAX_C22_PORT) 1331 return -EINVAL; 1332 reg_val |= (1 << port); 1333 break; 1334 case XGBE_MDIO_MODE_CL45: 1335 break; 1336 default: 1337 return -EINVAL; 1338 } 1339 1340 XGMAC_IOWRITE(pdata, MAC_MDIOCL22R, reg_val); 1341 1342 return 0; 1343 } 1344 1345 static int xgbe_tx_complete(struct xgbe_ring_desc *rdesc) 1346 { 1347 return !XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN); 1348 } 1349 1350 static int xgbe_disable_rx_csum(struct xgbe_prv_data *pdata) 1351 { 1352 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 0); 1353 1354 return 0; 1355 } 1356 1357 static int xgbe_enable_rx_csum(struct xgbe_prv_data *pdata) 1358 { 1359 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 1); 1360 1361 return 0; 1362 } 1363 1364 static void xgbe_tx_desc_reset(struct xgbe_ring_data *rdata) 1365 { 1366 struct xgbe_ring_desc *rdesc = rdata->rdesc; 1367 1368 /* Reset the Tx descriptor 1369 * Set buffer 1 (lo) address to zero 1370 * Set buffer 1 (hi) address to zero 1371 * Reset all other control bits (IC, TTSE, B2L & B1L) 1372 * Reset all other control bits (OWN, CTXT, FD, LD, CPC, CIC, etc) 1373 */ 1374 rdesc->desc0 = 0; 1375 rdesc->desc1 = 0; 1376 rdesc->desc2 = 0; 1377 rdesc->desc3 = 0; 1378 1379 /* Make sure ownership is written to the descriptor */ 1380 dma_wmb(); 1381 } 1382 1383 static void xgbe_tx_desc_init(struct xgbe_channel *channel) 1384 { 1385 struct xgbe_ring *ring = channel->tx_ring; 1386 struct xgbe_ring_data *rdata; 1387 int i; 1388 int start_index = ring->cur; 1389 1390 DBGPR("-->tx_desc_init\n"); 1391 1392 /* Initialze all descriptors */ 1393 for (i = 0; i < ring->rdesc_count; i++) { 1394 rdata = XGBE_GET_DESC_DATA(ring, i); 1395 1396 /* Initialize Tx descriptor */ 1397 xgbe_tx_desc_reset(rdata); 1398 } 1399 1400 /* Update the total number of Tx descriptors */ 1401 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDRLR, ring->rdesc_count - 1); 1402 1403 /* Update the starting address of descriptor ring */ 1404 rdata = XGBE_GET_DESC_DATA(ring, start_index); 1405 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDLR_HI, 1406 upper_32_bits(rdata->rdesc_dma)); 1407 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDLR_LO, 1408 lower_32_bits(rdata->rdesc_dma)); 1409 1410 DBGPR("<--tx_desc_init\n"); 1411 } 1412 1413 static void xgbe_rx_desc_reset(struct xgbe_prv_data *pdata, 1414 struct xgbe_ring_data *rdata, unsigned int index) 1415 { 1416 struct xgbe_ring_desc *rdesc = rdata->rdesc; 1417 unsigned int rx_usecs = pdata->rx_usecs; 1418 unsigned int rx_frames = pdata->rx_frames; 1419 unsigned int inte; 1420 dma_addr_t hdr_dma, buf_dma; 1421 1422 if (!rx_usecs && !rx_frames) { 1423 /* No coalescing, interrupt for every descriptor */ 1424 inte = 1; 1425 } else { 1426 /* Set interrupt based on Rx frame coalescing setting */ 1427 if (rx_frames && !((index + 1) % rx_frames)) 1428 inte = 1; 1429 else 1430 inte = 0; 1431 } 1432 1433 /* Reset the Rx descriptor 1434 * Set buffer 1 (lo) address to header dma address (lo) 1435 * Set buffer 1 (hi) address to header dma address (hi) 1436 * Set buffer 2 (lo) address to buffer dma address (lo) 1437 * Set buffer 2 (hi) address to buffer dma address (hi) and 1438 * set control bits OWN and INTE 1439 */ 1440 hdr_dma = rdata->rx.hdr.dma_base + rdata->rx.hdr.dma_off; 1441 buf_dma = rdata->rx.buf.dma_base + rdata->rx.buf.dma_off; 1442 rdesc->desc0 = cpu_to_le32(lower_32_bits(hdr_dma)); 1443 rdesc->desc1 = cpu_to_le32(upper_32_bits(hdr_dma)); 1444 rdesc->desc2 = cpu_to_le32(lower_32_bits(buf_dma)); 1445 rdesc->desc3 = cpu_to_le32(upper_32_bits(buf_dma)); 1446 1447 XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, INTE, inte); 1448 1449 /* Since the Rx DMA engine is likely running, make sure everything 1450 * is written to the descriptor(s) before setting the OWN bit 1451 * for the descriptor 1452 */ 1453 dma_wmb(); 1454 1455 XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN, 1); 1456 1457 /* Make sure ownership is written to the descriptor */ 1458 dma_wmb(); 1459 } 1460 1461 static void xgbe_rx_desc_init(struct xgbe_channel *channel) 1462 { 1463 struct xgbe_prv_data *pdata = channel->pdata; 1464 struct xgbe_ring *ring = channel->rx_ring; 1465 struct xgbe_ring_data *rdata; 1466 unsigned int start_index = ring->cur; 1467 unsigned int i; 1468 1469 DBGPR("-->rx_desc_init\n"); 1470 1471 /* Initialize all descriptors */ 1472 for (i = 0; i < ring->rdesc_count; i++) { 1473 rdata = XGBE_GET_DESC_DATA(ring, i); 1474 1475 /* Initialize Rx descriptor */ 1476 xgbe_rx_desc_reset(pdata, rdata, i); 1477 } 1478 1479 /* Update the total number of Rx descriptors */ 1480 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDRLR, ring->rdesc_count - 1); 1481 1482 /* Update the starting address of descriptor ring */ 1483 rdata = XGBE_GET_DESC_DATA(ring, start_index); 1484 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDLR_HI, 1485 upper_32_bits(rdata->rdesc_dma)); 1486 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDLR_LO, 1487 lower_32_bits(rdata->rdesc_dma)); 1488 1489 /* Update the Rx Descriptor Tail Pointer */ 1490 rdata = XGBE_GET_DESC_DATA(ring, start_index + ring->rdesc_count - 1); 1491 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO, 1492 lower_32_bits(rdata->rdesc_dma)); 1493 1494 DBGPR("<--rx_desc_init\n"); 1495 } 1496 1497 static void xgbe_update_tstamp_addend(struct xgbe_prv_data *pdata, 1498 unsigned int addend) 1499 { 1500 /* Set the addend register value and tell the device */ 1501 XGMAC_IOWRITE(pdata, MAC_TSAR, addend); 1502 XGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSADDREG, 1); 1503 1504 /* Wait for addend update to complete */ 1505 while (XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSADDREG)) 1506 udelay(5); 1507 } 1508 1509 static void xgbe_set_tstamp_time(struct xgbe_prv_data *pdata, unsigned int sec, 1510 unsigned int nsec) 1511 { 1512 /* Set the time values and tell the device */ 1513 XGMAC_IOWRITE(pdata, MAC_STSUR, sec); 1514 XGMAC_IOWRITE(pdata, MAC_STNUR, nsec); 1515 XGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSINIT, 1); 1516 1517 /* Wait for time update to complete */ 1518 while (XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSINIT)) 1519 udelay(5); 1520 } 1521 1522 static u64 xgbe_get_tstamp_time(struct xgbe_prv_data *pdata) 1523 { 1524 u64 nsec; 1525 1526 nsec = XGMAC_IOREAD(pdata, MAC_STSR); 1527 nsec *= NSEC_PER_SEC; 1528 nsec += XGMAC_IOREAD(pdata, MAC_STNR); 1529 1530 return nsec; 1531 } 1532 1533 static u64 xgbe_get_tx_tstamp(struct xgbe_prv_data *pdata) 1534 { 1535 unsigned int tx_snr, tx_ssr; 1536 u64 nsec; 1537 1538 if (pdata->vdata->tx_tstamp_workaround) { 1539 tx_snr = XGMAC_IOREAD(pdata, MAC_TXSNR); 1540 tx_ssr = XGMAC_IOREAD(pdata, MAC_TXSSR); 1541 } else { 1542 tx_ssr = XGMAC_IOREAD(pdata, MAC_TXSSR); 1543 tx_snr = XGMAC_IOREAD(pdata, MAC_TXSNR); 1544 } 1545 1546 if (XGMAC_GET_BITS(tx_snr, MAC_TXSNR, TXTSSTSMIS)) 1547 return 0; 1548 1549 nsec = tx_ssr; 1550 nsec *= NSEC_PER_SEC; 1551 nsec += tx_snr; 1552 1553 return nsec; 1554 } 1555 1556 static void xgbe_get_rx_tstamp(struct xgbe_packet_data *packet, 1557 struct xgbe_ring_desc *rdesc) 1558 { 1559 u64 nsec; 1560 1561 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_CONTEXT_DESC3, TSA) && 1562 !XGMAC_GET_BITS_LE(rdesc->desc3, RX_CONTEXT_DESC3, TSD)) { 1563 nsec = le32_to_cpu(rdesc->desc1); 1564 nsec <<= 32; 1565 nsec |= le32_to_cpu(rdesc->desc0); 1566 if (nsec != 0xffffffffffffffffULL) { 1567 packet->rx_tstamp = nsec; 1568 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1569 RX_TSTAMP, 1); 1570 } 1571 } 1572 } 1573 1574 static int xgbe_config_tstamp(struct xgbe_prv_data *pdata, 1575 unsigned int mac_tscr) 1576 { 1577 /* Set one nano-second accuracy */ 1578 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCTRLSSR, 1); 1579 1580 /* Set fine timestamp update */ 1581 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCFUPDT, 1); 1582 1583 /* Overwrite earlier timestamps */ 1584 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TXTSSTSM, 1); 1585 1586 XGMAC_IOWRITE(pdata, MAC_TSCR, mac_tscr); 1587 1588 /* Exit if timestamping is not enabled */ 1589 if (!XGMAC_GET_BITS(mac_tscr, MAC_TSCR, TSENA)) 1590 return 0; 1591 1592 /* Initialize time registers */ 1593 XGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SSINC, XGBE_TSTAMP_SSINC); 1594 XGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SNSINC, XGBE_TSTAMP_SNSINC); 1595 xgbe_update_tstamp_addend(pdata, pdata->tstamp_addend); 1596 xgbe_set_tstamp_time(pdata, 0, 0); 1597 1598 /* Initialize the timecounter */ 1599 timecounter_init(&pdata->tstamp_tc, &pdata->tstamp_cc, 1600 ktime_to_ns(ktime_get_real())); 1601 1602 return 0; 1603 } 1604 1605 static void xgbe_tx_start_xmit(struct xgbe_channel *channel, 1606 struct xgbe_ring *ring) 1607 { 1608 struct xgbe_prv_data *pdata = channel->pdata; 1609 struct xgbe_ring_data *rdata; 1610 1611 /* Make sure everything is written before the register write */ 1612 wmb(); 1613 1614 /* Issue a poll command to Tx DMA by writing address 1615 * of next immediate free descriptor */ 1616 rdata = XGBE_GET_DESC_DATA(ring, ring->cur); 1617 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDTR_LO, 1618 lower_32_bits(rdata->rdesc_dma)); 1619 1620 /* Start the Tx timer */ 1621 if (pdata->tx_usecs && !channel->tx_timer_active) { 1622 channel->tx_timer_active = 1; 1623 mod_timer(&channel->tx_timer, 1624 jiffies + usecs_to_jiffies(pdata->tx_usecs)); 1625 } 1626 1627 ring->tx.xmit_more = 0; 1628 } 1629 1630 static void xgbe_dev_xmit(struct xgbe_channel *channel) 1631 { 1632 struct xgbe_prv_data *pdata = channel->pdata; 1633 struct xgbe_ring *ring = channel->tx_ring; 1634 struct xgbe_ring_data *rdata; 1635 struct xgbe_ring_desc *rdesc; 1636 struct xgbe_packet_data *packet = &ring->packet_data; 1637 unsigned int csum, tso, vlan; 1638 unsigned int tso_context, vlan_context; 1639 unsigned int tx_set_ic; 1640 int start_index = ring->cur; 1641 int cur_index = ring->cur; 1642 int i; 1643 1644 DBGPR("-->xgbe_dev_xmit\n"); 1645 1646 csum = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, 1647 CSUM_ENABLE); 1648 tso = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, 1649 TSO_ENABLE); 1650 vlan = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, 1651 VLAN_CTAG); 1652 1653 if (tso && (packet->mss != ring->tx.cur_mss)) 1654 tso_context = 1; 1655 else 1656 tso_context = 0; 1657 1658 if (vlan && (packet->vlan_ctag != ring->tx.cur_vlan_ctag)) 1659 vlan_context = 1; 1660 else 1661 vlan_context = 0; 1662 1663 /* Determine if an interrupt should be generated for this Tx: 1664 * Interrupt: 1665 * - Tx frame count exceeds the frame count setting 1666 * - Addition of Tx frame count to the frame count since the 1667 * last interrupt was set exceeds the frame count setting 1668 * No interrupt: 1669 * - No frame count setting specified (ethtool -C ethX tx-frames 0) 1670 * - Addition of Tx frame count to the frame count since the 1671 * last interrupt was set does not exceed the frame count setting 1672 */ 1673 ring->coalesce_count += packet->tx_packets; 1674 if (!pdata->tx_frames) 1675 tx_set_ic = 0; 1676 else if (packet->tx_packets > pdata->tx_frames) 1677 tx_set_ic = 1; 1678 else if ((ring->coalesce_count % pdata->tx_frames) < 1679 packet->tx_packets) 1680 tx_set_ic = 1; 1681 else 1682 tx_set_ic = 0; 1683 1684 rdata = XGBE_GET_DESC_DATA(ring, cur_index); 1685 rdesc = rdata->rdesc; 1686 1687 /* Create a context descriptor if this is a TSO packet */ 1688 if (tso_context || vlan_context) { 1689 if (tso_context) { 1690 netif_dbg(pdata, tx_queued, pdata->netdev, 1691 "TSO context descriptor, mss=%u\n", 1692 packet->mss); 1693 1694 /* Set the MSS size */ 1695 XGMAC_SET_BITS_LE(rdesc->desc2, TX_CONTEXT_DESC2, 1696 MSS, packet->mss); 1697 1698 /* Mark it as a CONTEXT descriptor */ 1699 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, 1700 CTXT, 1); 1701 1702 /* Indicate this descriptor contains the MSS */ 1703 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, 1704 TCMSSV, 1); 1705 1706 ring->tx.cur_mss = packet->mss; 1707 } 1708 1709 if (vlan_context) { 1710 netif_dbg(pdata, tx_queued, pdata->netdev, 1711 "VLAN context descriptor, ctag=%u\n", 1712 packet->vlan_ctag); 1713 1714 /* Mark it as a CONTEXT descriptor */ 1715 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, 1716 CTXT, 1); 1717 1718 /* Set the VLAN tag */ 1719 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, 1720 VT, packet->vlan_ctag); 1721 1722 /* Indicate this descriptor contains the VLAN tag */ 1723 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, 1724 VLTV, 1); 1725 1726 ring->tx.cur_vlan_ctag = packet->vlan_ctag; 1727 } 1728 1729 cur_index++; 1730 rdata = XGBE_GET_DESC_DATA(ring, cur_index); 1731 rdesc = rdata->rdesc; 1732 } 1733 1734 /* Update buffer address (for TSO this is the header) */ 1735 rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->skb_dma)); 1736 rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->skb_dma)); 1737 1738 /* Update the buffer length */ 1739 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, HL_B1L, 1740 rdata->skb_dma_len); 1741 1742 /* VLAN tag insertion check */ 1743 if (vlan) 1744 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, VTIR, 1745 TX_NORMAL_DESC2_VLAN_INSERT); 1746 1747 /* Timestamp enablement check */ 1748 if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP)) 1749 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, TTSE, 1); 1750 1751 /* Mark it as First Descriptor */ 1752 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, FD, 1); 1753 1754 /* Mark it as a NORMAL descriptor */ 1755 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT, 0); 1756 1757 /* Set OWN bit if not the first descriptor */ 1758 if (cur_index != start_index) 1759 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1); 1760 1761 if (tso) { 1762 /* Enable TSO */ 1763 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TSE, 1); 1764 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TCPPL, 1765 packet->tcp_payload_len); 1766 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TCPHDRLEN, 1767 packet->tcp_header_len / 4); 1768 1769 pdata->ext_stats.tx_tso_packets++; 1770 } else { 1771 /* Enable CRC and Pad Insertion */ 1772 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CPC, 0); 1773 1774 /* Enable HW CSUM */ 1775 if (csum) 1776 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, 1777 CIC, 0x3); 1778 1779 /* Set the total length to be transmitted */ 1780 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, FL, 1781 packet->length); 1782 } 1783 1784 for (i = cur_index - start_index + 1; i < packet->rdesc_count; i++) { 1785 cur_index++; 1786 rdata = XGBE_GET_DESC_DATA(ring, cur_index); 1787 rdesc = rdata->rdesc; 1788 1789 /* Update buffer address */ 1790 rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->skb_dma)); 1791 rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->skb_dma)); 1792 1793 /* Update the buffer length */ 1794 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, HL_B1L, 1795 rdata->skb_dma_len); 1796 1797 /* Set OWN bit */ 1798 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1); 1799 1800 /* Mark it as NORMAL descriptor */ 1801 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT, 0); 1802 1803 /* Enable HW CSUM */ 1804 if (csum) 1805 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, 1806 CIC, 0x3); 1807 } 1808 1809 /* Set LAST bit for the last descriptor */ 1810 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, LD, 1); 1811 1812 /* Set IC bit based on Tx coalescing settings */ 1813 if (tx_set_ic) 1814 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, IC, 1); 1815 1816 /* Save the Tx info to report back during cleanup */ 1817 rdata->tx.packets = packet->tx_packets; 1818 rdata->tx.bytes = packet->tx_bytes; 1819 1820 /* In case the Tx DMA engine is running, make sure everything 1821 * is written to the descriptor(s) before setting the OWN bit 1822 * for the first descriptor 1823 */ 1824 dma_wmb(); 1825 1826 /* Set OWN bit for the first descriptor */ 1827 rdata = XGBE_GET_DESC_DATA(ring, start_index); 1828 rdesc = rdata->rdesc; 1829 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1); 1830 1831 if (netif_msg_tx_queued(pdata)) 1832 xgbe_dump_tx_desc(pdata, ring, start_index, 1833 packet->rdesc_count, 1); 1834 1835 /* Make sure ownership is written to the descriptor */ 1836 smp_wmb(); 1837 1838 ring->cur = cur_index + 1; 1839 if (!packet->skb->xmit_more || 1840 netif_xmit_stopped(netdev_get_tx_queue(pdata->netdev, 1841 channel->queue_index))) 1842 xgbe_tx_start_xmit(channel, ring); 1843 else 1844 ring->tx.xmit_more = 1; 1845 1846 DBGPR(" %s: descriptors %u to %u written\n", 1847 channel->name, start_index & (ring->rdesc_count - 1), 1848 (ring->cur - 1) & (ring->rdesc_count - 1)); 1849 1850 DBGPR("<--xgbe_dev_xmit\n"); 1851 } 1852 1853 static int xgbe_dev_read(struct xgbe_channel *channel) 1854 { 1855 struct xgbe_prv_data *pdata = channel->pdata; 1856 struct xgbe_ring *ring = channel->rx_ring; 1857 struct xgbe_ring_data *rdata; 1858 struct xgbe_ring_desc *rdesc; 1859 struct xgbe_packet_data *packet = &ring->packet_data; 1860 struct net_device *netdev = pdata->netdev; 1861 unsigned int err, etlt, l34t; 1862 1863 DBGPR("-->xgbe_dev_read: cur = %d\n", ring->cur); 1864 1865 rdata = XGBE_GET_DESC_DATA(ring, ring->cur); 1866 rdesc = rdata->rdesc; 1867 1868 /* Check for data availability */ 1869 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN)) 1870 return 1; 1871 1872 /* Make sure descriptor fields are read after reading the OWN bit */ 1873 dma_rmb(); 1874 1875 if (netif_msg_rx_status(pdata)) 1876 xgbe_dump_rx_desc(pdata, ring, ring->cur); 1877 1878 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CTXT)) { 1879 /* Timestamp Context Descriptor */ 1880 xgbe_get_rx_tstamp(packet, rdesc); 1881 1882 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1883 CONTEXT, 1); 1884 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1885 CONTEXT_NEXT, 0); 1886 return 0; 1887 } 1888 1889 /* Normal Descriptor, be sure Context Descriptor bit is off */ 1890 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, CONTEXT, 0); 1891 1892 /* Indicate if a Context Descriptor is next */ 1893 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CDA)) 1894 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1895 CONTEXT_NEXT, 1); 1896 1897 /* Get the header length */ 1898 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, FD)) { 1899 rdata->rx.hdr_len = XGMAC_GET_BITS_LE(rdesc->desc2, 1900 RX_NORMAL_DESC2, HL); 1901 if (rdata->rx.hdr_len) 1902 pdata->ext_stats.rx_split_header_packets++; 1903 } 1904 1905 /* Get the RSS hash */ 1906 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, RSV)) { 1907 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1908 RSS_HASH, 1); 1909 1910 packet->rss_hash = le32_to_cpu(rdesc->desc1); 1911 1912 l34t = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, L34T); 1913 switch (l34t) { 1914 case RX_DESC3_L34T_IPV4_TCP: 1915 case RX_DESC3_L34T_IPV4_UDP: 1916 case RX_DESC3_L34T_IPV6_TCP: 1917 case RX_DESC3_L34T_IPV6_UDP: 1918 packet->rss_hash_type = PKT_HASH_TYPE_L4; 1919 break; 1920 default: 1921 packet->rss_hash_type = PKT_HASH_TYPE_L3; 1922 } 1923 } 1924 1925 /* Get the packet length */ 1926 rdata->rx.len = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, PL); 1927 1928 if (!XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, LD)) { 1929 /* Not all the data has been transferred for this packet */ 1930 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1931 INCOMPLETE, 1); 1932 return 0; 1933 } 1934 1935 /* This is the last of the data for this packet */ 1936 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1937 INCOMPLETE, 0); 1938 1939 /* Set checksum done indicator as appropriate */ 1940 if (netdev->features & NETIF_F_RXCSUM) 1941 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1942 CSUM_DONE, 1); 1943 1944 /* Check for errors (only valid in last descriptor) */ 1945 err = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ES); 1946 etlt = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ETLT); 1947 netif_dbg(pdata, rx_status, netdev, "err=%u, etlt=%#x\n", err, etlt); 1948 1949 if (!err || !etlt) { 1950 /* No error if err is 0 or etlt is 0 */ 1951 if ((etlt == 0x09) && 1952 (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)) { 1953 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1954 VLAN_CTAG, 1); 1955 packet->vlan_ctag = XGMAC_GET_BITS_LE(rdesc->desc0, 1956 RX_NORMAL_DESC0, 1957 OVT); 1958 netif_dbg(pdata, rx_status, netdev, "vlan-ctag=%#06x\n", 1959 packet->vlan_ctag); 1960 } 1961 } else { 1962 if ((etlt == 0x05) || (etlt == 0x06)) 1963 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1964 CSUM_DONE, 0); 1965 else 1966 XGMAC_SET_BITS(packet->errors, RX_PACKET_ERRORS, 1967 FRAME, 1); 1968 } 1969 1970 DBGPR("<--xgbe_dev_read: %s - descriptor=%u (cur=%d)\n", channel->name, 1971 ring->cur & (ring->rdesc_count - 1), ring->cur); 1972 1973 return 0; 1974 } 1975 1976 static int xgbe_is_context_desc(struct xgbe_ring_desc *rdesc) 1977 { 1978 /* Rx and Tx share CTXT bit, so check TDES3.CTXT bit */ 1979 return XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT); 1980 } 1981 1982 static int xgbe_is_last_desc(struct xgbe_ring_desc *rdesc) 1983 { 1984 /* Rx and Tx share LD bit, so check TDES3.LD bit */ 1985 return XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, LD); 1986 } 1987 1988 static int xgbe_enable_int(struct xgbe_channel *channel, 1989 enum xgbe_int int_id) 1990 { 1991 unsigned int dma_ch_ier; 1992 1993 dma_ch_ier = XGMAC_DMA_IOREAD(channel, DMA_CH_IER); 1994 1995 switch (int_id) { 1996 case XGMAC_INT_DMA_CH_SR_TI: 1997 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 1); 1998 break; 1999 case XGMAC_INT_DMA_CH_SR_TPS: 2000 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TXSE, 1); 2001 break; 2002 case XGMAC_INT_DMA_CH_SR_TBU: 2003 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TBUE, 1); 2004 break; 2005 case XGMAC_INT_DMA_CH_SR_RI: 2006 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 1); 2007 break; 2008 case XGMAC_INT_DMA_CH_SR_RBU: 2009 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RBUE, 1); 2010 break; 2011 case XGMAC_INT_DMA_CH_SR_RPS: 2012 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RSE, 1); 2013 break; 2014 case XGMAC_INT_DMA_CH_SR_TI_RI: 2015 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 1); 2016 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 1); 2017 break; 2018 case XGMAC_INT_DMA_CH_SR_FBE: 2019 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, FBEE, 1); 2020 break; 2021 case XGMAC_INT_DMA_ALL: 2022 dma_ch_ier |= channel->saved_ier; 2023 break; 2024 default: 2025 return -1; 2026 } 2027 2028 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, dma_ch_ier); 2029 2030 return 0; 2031 } 2032 2033 static int xgbe_disable_int(struct xgbe_channel *channel, 2034 enum xgbe_int int_id) 2035 { 2036 unsigned int dma_ch_ier; 2037 2038 dma_ch_ier = XGMAC_DMA_IOREAD(channel, DMA_CH_IER); 2039 2040 switch (int_id) { 2041 case XGMAC_INT_DMA_CH_SR_TI: 2042 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 0); 2043 break; 2044 case XGMAC_INT_DMA_CH_SR_TPS: 2045 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TXSE, 0); 2046 break; 2047 case XGMAC_INT_DMA_CH_SR_TBU: 2048 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TBUE, 0); 2049 break; 2050 case XGMAC_INT_DMA_CH_SR_RI: 2051 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 0); 2052 break; 2053 case XGMAC_INT_DMA_CH_SR_RBU: 2054 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RBUE, 0); 2055 break; 2056 case XGMAC_INT_DMA_CH_SR_RPS: 2057 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RSE, 0); 2058 break; 2059 case XGMAC_INT_DMA_CH_SR_TI_RI: 2060 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 0); 2061 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 0); 2062 break; 2063 case XGMAC_INT_DMA_CH_SR_FBE: 2064 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, FBEE, 0); 2065 break; 2066 case XGMAC_INT_DMA_ALL: 2067 channel->saved_ier = dma_ch_ier & XGBE_DMA_INTERRUPT_MASK; 2068 dma_ch_ier &= ~XGBE_DMA_INTERRUPT_MASK; 2069 break; 2070 default: 2071 return -1; 2072 } 2073 2074 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, dma_ch_ier); 2075 2076 return 0; 2077 } 2078 2079 static int __xgbe_exit(struct xgbe_prv_data *pdata) 2080 { 2081 unsigned int count = 2000; 2082 2083 DBGPR("-->xgbe_exit\n"); 2084 2085 /* Issue a software reset */ 2086 XGMAC_IOWRITE_BITS(pdata, DMA_MR, SWR, 1); 2087 usleep_range(10, 15); 2088 2089 /* Poll Until Poll Condition */ 2090 while (--count && XGMAC_IOREAD_BITS(pdata, DMA_MR, SWR)) 2091 usleep_range(500, 600); 2092 2093 if (!count) 2094 return -EBUSY; 2095 2096 DBGPR("<--xgbe_exit\n"); 2097 2098 return 0; 2099 } 2100 2101 static int xgbe_exit(struct xgbe_prv_data *pdata) 2102 { 2103 int ret; 2104 2105 /* To guard against possible incorrectly generated interrupts, 2106 * issue the software reset twice. 2107 */ 2108 ret = __xgbe_exit(pdata); 2109 if (ret) 2110 return ret; 2111 2112 return __xgbe_exit(pdata); 2113 } 2114 2115 static int xgbe_flush_tx_queues(struct xgbe_prv_data *pdata) 2116 { 2117 unsigned int i, count; 2118 2119 if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) < 0x21) 2120 return 0; 2121 2122 for (i = 0; i < pdata->tx_q_count; i++) 2123 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, FTQ, 1); 2124 2125 /* Poll Until Poll Condition */ 2126 for (i = 0; i < pdata->tx_q_count; i++) { 2127 count = 2000; 2128 while (--count && XGMAC_MTL_IOREAD_BITS(pdata, i, 2129 MTL_Q_TQOMR, FTQ)) 2130 usleep_range(500, 600); 2131 2132 if (!count) 2133 return -EBUSY; 2134 } 2135 2136 return 0; 2137 } 2138 2139 static void xgbe_config_dma_bus(struct xgbe_prv_data *pdata) 2140 { 2141 /* Set enhanced addressing mode */ 2142 XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, EAME, 1); 2143 2144 /* Set the System Bus mode */ 2145 XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, UNDEF, 1); 2146 XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, BLEN_256, 1); 2147 } 2148 2149 static void xgbe_config_dma_cache(struct xgbe_prv_data *pdata) 2150 { 2151 unsigned int arcache, awcache; 2152 2153 arcache = 0; 2154 XGMAC_SET_BITS(arcache, DMA_AXIARCR, DRC, pdata->arcache); 2155 XGMAC_SET_BITS(arcache, DMA_AXIARCR, DRD, pdata->axdomain); 2156 XGMAC_SET_BITS(arcache, DMA_AXIARCR, TEC, pdata->arcache); 2157 XGMAC_SET_BITS(arcache, DMA_AXIARCR, TED, pdata->axdomain); 2158 XGMAC_SET_BITS(arcache, DMA_AXIARCR, THC, pdata->arcache); 2159 XGMAC_SET_BITS(arcache, DMA_AXIARCR, THD, pdata->axdomain); 2160 XGMAC_IOWRITE(pdata, DMA_AXIARCR, arcache); 2161 2162 awcache = 0; 2163 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, DWC, pdata->awcache); 2164 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, DWD, pdata->axdomain); 2165 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RPC, pdata->awcache); 2166 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RPD, pdata->axdomain); 2167 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RHC, pdata->awcache); 2168 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RHD, pdata->axdomain); 2169 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, TDC, pdata->awcache); 2170 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, TDD, pdata->axdomain); 2171 XGMAC_IOWRITE(pdata, DMA_AXIAWCR, awcache); 2172 } 2173 2174 static void xgbe_config_mtl_mode(struct xgbe_prv_data *pdata) 2175 { 2176 unsigned int i; 2177 2178 /* Set Tx to weighted round robin scheduling algorithm */ 2179 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_WRR); 2180 2181 /* Set Tx traffic classes to use WRR algorithm with equal weights */ 2182 for (i = 0; i < pdata->hw_feat.tc_cnt; i++) { 2183 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA, 2184 MTL_TSA_ETS); 2185 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW, 1); 2186 } 2187 2188 /* Set Rx to strict priority algorithm */ 2189 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, RAA, MTL_RAA_SP); 2190 } 2191 2192 static void xgbe_queue_flow_control_threshold(struct xgbe_prv_data *pdata, 2193 unsigned int queue, 2194 unsigned int q_fifo_size) 2195 { 2196 unsigned int frame_fifo_size; 2197 unsigned int rfa, rfd; 2198 2199 frame_fifo_size = XGMAC_FLOW_CONTROL_ALIGN(xgbe_get_max_frame(pdata)); 2200 2201 if (pdata->pfcq[queue] && (q_fifo_size > pdata->pfc_rfa)) { 2202 /* PFC is active for this queue */ 2203 rfa = pdata->pfc_rfa; 2204 rfd = rfa + frame_fifo_size; 2205 if (rfd > XGMAC_FLOW_CONTROL_MAX) 2206 rfd = XGMAC_FLOW_CONTROL_MAX; 2207 if (rfa >= XGMAC_FLOW_CONTROL_MAX) 2208 rfa = XGMAC_FLOW_CONTROL_MAX - XGMAC_FLOW_CONTROL_UNIT; 2209 } else { 2210 /* This path deals with just maximum frame sizes which are 2211 * limited to a jumbo frame of 9,000 (plus headers, etc.) 2212 * so we can never exceed the maximum allowable RFA/RFD 2213 * values. 2214 */ 2215 if (q_fifo_size <= 2048) { 2216 /* rx_rfd to zero to signal no flow control */ 2217 pdata->rx_rfa[queue] = 0; 2218 pdata->rx_rfd[queue] = 0; 2219 return; 2220 } 2221 2222 if (q_fifo_size <= 4096) { 2223 /* Between 2048 and 4096 */ 2224 pdata->rx_rfa[queue] = 0; /* Full - 1024 bytes */ 2225 pdata->rx_rfd[queue] = 1; /* Full - 1536 bytes */ 2226 return; 2227 } 2228 2229 if (q_fifo_size <= frame_fifo_size) { 2230 /* Between 4096 and max-frame */ 2231 pdata->rx_rfa[queue] = 2; /* Full - 2048 bytes */ 2232 pdata->rx_rfd[queue] = 5; /* Full - 3584 bytes */ 2233 return; 2234 } 2235 2236 if (q_fifo_size <= (frame_fifo_size * 3)) { 2237 /* Between max-frame and 3 max-frames, 2238 * trigger if we get just over a frame of data and 2239 * resume when we have just under half a frame left. 2240 */ 2241 rfa = q_fifo_size - frame_fifo_size; 2242 rfd = rfa + (frame_fifo_size / 2); 2243 } else { 2244 /* Above 3 max-frames - trigger when just over 2245 * 2 frames of space available 2246 */ 2247 rfa = frame_fifo_size * 2; 2248 rfa += XGMAC_FLOW_CONTROL_UNIT; 2249 rfd = rfa + frame_fifo_size; 2250 } 2251 } 2252 2253 pdata->rx_rfa[queue] = XGMAC_FLOW_CONTROL_VALUE(rfa); 2254 pdata->rx_rfd[queue] = XGMAC_FLOW_CONTROL_VALUE(rfd); 2255 } 2256 2257 static void xgbe_calculate_flow_control_threshold(struct xgbe_prv_data *pdata, 2258 unsigned int *fifo) 2259 { 2260 unsigned int q_fifo_size; 2261 unsigned int i; 2262 2263 for (i = 0; i < pdata->rx_q_count; i++) { 2264 q_fifo_size = (fifo[i] + 1) * XGMAC_FIFO_UNIT; 2265 2266 xgbe_queue_flow_control_threshold(pdata, i, q_fifo_size); 2267 } 2268 } 2269 2270 static void xgbe_config_flow_control_threshold(struct xgbe_prv_data *pdata) 2271 { 2272 unsigned int i; 2273 2274 for (i = 0; i < pdata->rx_q_count; i++) { 2275 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQFCR, RFA, 2276 pdata->rx_rfa[i]); 2277 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQFCR, RFD, 2278 pdata->rx_rfd[i]); 2279 } 2280 } 2281 2282 static unsigned int xgbe_get_tx_fifo_size(struct xgbe_prv_data *pdata) 2283 { 2284 /* The configured value may not be the actual amount of fifo RAM */ 2285 return min_t(unsigned int, pdata->tx_max_fifo_size, 2286 pdata->hw_feat.tx_fifo_size); 2287 } 2288 2289 static unsigned int xgbe_get_rx_fifo_size(struct xgbe_prv_data *pdata) 2290 { 2291 /* The configured value may not be the actual amount of fifo RAM */ 2292 return min_t(unsigned int, pdata->rx_max_fifo_size, 2293 pdata->hw_feat.rx_fifo_size); 2294 } 2295 2296 static void xgbe_calculate_equal_fifo(unsigned int fifo_size, 2297 unsigned int queue_count, 2298 unsigned int *fifo) 2299 { 2300 unsigned int q_fifo_size; 2301 unsigned int p_fifo; 2302 unsigned int i; 2303 2304 q_fifo_size = fifo_size / queue_count; 2305 2306 /* Calculate the fifo setting by dividing the queue's fifo size 2307 * by the fifo allocation increment (with 0 representing the 2308 * base allocation increment so decrement the result by 1). 2309 */ 2310 p_fifo = q_fifo_size / XGMAC_FIFO_UNIT; 2311 if (p_fifo) 2312 p_fifo--; 2313 2314 /* Distribute the fifo equally amongst the queues */ 2315 for (i = 0; i < queue_count; i++) 2316 fifo[i] = p_fifo; 2317 } 2318 2319 static unsigned int xgbe_set_nonprio_fifos(unsigned int fifo_size, 2320 unsigned int queue_count, 2321 unsigned int *fifo) 2322 { 2323 unsigned int i; 2324 2325 BUILD_BUG_ON_NOT_POWER_OF_2(XGMAC_FIFO_MIN_ALLOC); 2326 2327 if (queue_count <= IEEE_8021QAZ_MAX_TCS) 2328 return fifo_size; 2329 2330 /* Rx queues 9 and up are for specialized packets, 2331 * such as PTP or DCB control packets, etc. and 2332 * don't require a large fifo 2333 */ 2334 for (i = IEEE_8021QAZ_MAX_TCS; i < queue_count; i++) { 2335 fifo[i] = (XGMAC_FIFO_MIN_ALLOC / XGMAC_FIFO_UNIT) - 1; 2336 fifo_size -= XGMAC_FIFO_MIN_ALLOC; 2337 } 2338 2339 return fifo_size; 2340 } 2341 2342 static unsigned int xgbe_get_pfc_delay(struct xgbe_prv_data *pdata) 2343 { 2344 unsigned int delay; 2345 2346 /* If a delay has been provided, use that */ 2347 if (pdata->pfc->delay) 2348 return pdata->pfc->delay / 8; 2349 2350 /* Allow for two maximum size frames */ 2351 delay = xgbe_get_max_frame(pdata); 2352 delay += XGMAC_ETH_PREAMBLE; 2353 delay *= 2; 2354 2355 /* Allow for PFC frame */ 2356 delay += XGMAC_PFC_DATA_LEN; 2357 delay += ETH_HLEN + ETH_FCS_LEN; 2358 delay += XGMAC_ETH_PREAMBLE; 2359 2360 /* Allow for miscellaneous delays (LPI exit, cable, etc.) */ 2361 delay += XGMAC_PFC_DELAYS; 2362 2363 return delay; 2364 } 2365 2366 static unsigned int xgbe_get_pfc_queues(struct xgbe_prv_data *pdata) 2367 { 2368 unsigned int count, prio_queues; 2369 unsigned int i; 2370 2371 if (!pdata->pfc->pfc_en) 2372 return 0; 2373 2374 count = 0; 2375 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count); 2376 for (i = 0; i < prio_queues; i++) { 2377 if (!xgbe_is_pfc_queue(pdata, i)) 2378 continue; 2379 2380 pdata->pfcq[i] = 1; 2381 count++; 2382 } 2383 2384 return count; 2385 } 2386 2387 static void xgbe_calculate_dcb_fifo(struct xgbe_prv_data *pdata, 2388 unsigned int fifo_size, 2389 unsigned int *fifo) 2390 { 2391 unsigned int q_fifo_size, rem_fifo, addn_fifo; 2392 unsigned int prio_queues; 2393 unsigned int pfc_count; 2394 unsigned int i; 2395 2396 q_fifo_size = XGMAC_FIFO_ALIGN(xgbe_get_max_frame(pdata)); 2397 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count); 2398 pfc_count = xgbe_get_pfc_queues(pdata); 2399 2400 if (!pfc_count || ((q_fifo_size * prio_queues) > fifo_size)) { 2401 /* No traffic classes with PFC enabled or can't do lossless */ 2402 xgbe_calculate_equal_fifo(fifo_size, prio_queues, fifo); 2403 return; 2404 } 2405 2406 /* Calculate how much fifo we have to play with */ 2407 rem_fifo = fifo_size - (q_fifo_size * prio_queues); 2408 2409 /* Calculate how much more than base fifo PFC needs, which also 2410 * becomes the threshold activation point (RFA) 2411 */ 2412 pdata->pfc_rfa = xgbe_get_pfc_delay(pdata); 2413 pdata->pfc_rfa = XGMAC_FLOW_CONTROL_ALIGN(pdata->pfc_rfa); 2414 2415 if (pdata->pfc_rfa > q_fifo_size) { 2416 addn_fifo = pdata->pfc_rfa - q_fifo_size; 2417 addn_fifo = XGMAC_FIFO_ALIGN(addn_fifo); 2418 } else { 2419 addn_fifo = 0; 2420 } 2421 2422 /* Calculate DCB fifo settings: 2423 * - distribute remaining fifo between the VLAN priority 2424 * queues based on traffic class PFC enablement and overall 2425 * priority (0 is lowest priority, so start at highest) 2426 */ 2427 i = prio_queues; 2428 while (i > 0) { 2429 i--; 2430 2431 fifo[i] = (q_fifo_size / XGMAC_FIFO_UNIT) - 1; 2432 2433 if (!pdata->pfcq[i] || !addn_fifo) 2434 continue; 2435 2436 if (addn_fifo > rem_fifo) { 2437 netdev_warn(pdata->netdev, 2438 "RXq%u cannot set needed fifo size\n", i); 2439 if (!rem_fifo) 2440 continue; 2441 2442 addn_fifo = rem_fifo; 2443 } 2444 2445 fifo[i] += (addn_fifo / XGMAC_FIFO_UNIT); 2446 rem_fifo -= addn_fifo; 2447 } 2448 2449 if (rem_fifo) { 2450 unsigned int inc_fifo = rem_fifo / prio_queues; 2451 2452 /* Distribute remaining fifo across queues */ 2453 for (i = 0; i < prio_queues; i++) 2454 fifo[i] += (inc_fifo / XGMAC_FIFO_UNIT); 2455 } 2456 } 2457 2458 static void xgbe_config_tx_fifo_size(struct xgbe_prv_data *pdata) 2459 { 2460 unsigned int fifo_size; 2461 unsigned int fifo[XGBE_MAX_QUEUES]; 2462 unsigned int i; 2463 2464 fifo_size = xgbe_get_tx_fifo_size(pdata); 2465 2466 xgbe_calculate_equal_fifo(fifo_size, pdata->tx_q_count, fifo); 2467 2468 for (i = 0; i < pdata->tx_q_count; i++) 2469 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TQS, fifo[i]); 2470 2471 netif_info(pdata, drv, pdata->netdev, 2472 "%d Tx hardware queues, %d byte fifo per queue\n", 2473 pdata->tx_q_count, ((fifo[0] + 1) * XGMAC_FIFO_UNIT)); 2474 } 2475 2476 static void xgbe_config_rx_fifo_size(struct xgbe_prv_data *pdata) 2477 { 2478 unsigned int fifo_size; 2479 unsigned int fifo[XGBE_MAX_QUEUES]; 2480 unsigned int prio_queues; 2481 unsigned int i; 2482 2483 /* Clear any DCB related fifo/queue information */ 2484 memset(pdata->pfcq, 0, sizeof(pdata->pfcq)); 2485 pdata->pfc_rfa = 0; 2486 2487 fifo_size = xgbe_get_rx_fifo_size(pdata); 2488 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count); 2489 2490 /* Assign a minimum fifo to the non-VLAN priority queues */ 2491 fifo_size = xgbe_set_nonprio_fifos(fifo_size, pdata->rx_q_count, fifo); 2492 2493 if (pdata->pfc && pdata->ets) 2494 xgbe_calculate_dcb_fifo(pdata, fifo_size, fifo); 2495 else 2496 xgbe_calculate_equal_fifo(fifo_size, prio_queues, fifo); 2497 2498 for (i = 0; i < pdata->rx_q_count; i++) 2499 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RQS, fifo[i]); 2500 2501 xgbe_calculate_flow_control_threshold(pdata, fifo); 2502 xgbe_config_flow_control_threshold(pdata); 2503 2504 if (pdata->pfc && pdata->ets && pdata->pfc->pfc_en) { 2505 netif_info(pdata, drv, pdata->netdev, 2506 "%u Rx hardware queues\n", pdata->rx_q_count); 2507 for (i = 0; i < pdata->rx_q_count; i++) 2508 netif_info(pdata, drv, pdata->netdev, 2509 "RxQ%u, %u byte fifo queue\n", i, 2510 ((fifo[i] + 1) * XGMAC_FIFO_UNIT)); 2511 } else { 2512 netif_info(pdata, drv, pdata->netdev, 2513 "%u Rx hardware queues, %u byte fifo per queue\n", 2514 pdata->rx_q_count, 2515 ((fifo[0] + 1) * XGMAC_FIFO_UNIT)); 2516 } 2517 } 2518 2519 static void xgbe_config_queue_mapping(struct xgbe_prv_data *pdata) 2520 { 2521 unsigned int qptc, qptc_extra, queue; 2522 unsigned int prio_queues; 2523 unsigned int ppq, ppq_extra, prio; 2524 unsigned int mask; 2525 unsigned int i, j, reg, reg_val; 2526 2527 /* Map the MTL Tx Queues to Traffic Classes 2528 * Note: Tx Queues >= Traffic Classes 2529 */ 2530 qptc = pdata->tx_q_count / pdata->hw_feat.tc_cnt; 2531 qptc_extra = pdata->tx_q_count % pdata->hw_feat.tc_cnt; 2532 2533 for (i = 0, queue = 0; i < pdata->hw_feat.tc_cnt; i++) { 2534 for (j = 0; j < qptc; j++) { 2535 netif_dbg(pdata, drv, pdata->netdev, 2536 "TXq%u mapped to TC%u\n", queue, i); 2537 XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR, 2538 Q2TCMAP, i); 2539 pdata->q2tc_map[queue++] = i; 2540 } 2541 2542 if (i < qptc_extra) { 2543 netif_dbg(pdata, drv, pdata->netdev, 2544 "TXq%u mapped to TC%u\n", queue, i); 2545 XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR, 2546 Q2TCMAP, i); 2547 pdata->q2tc_map[queue++] = i; 2548 } 2549 } 2550 2551 /* Map the 8 VLAN priority values to available MTL Rx queues */ 2552 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count); 2553 ppq = IEEE_8021QAZ_MAX_TCS / prio_queues; 2554 ppq_extra = IEEE_8021QAZ_MAX_TCS % prio_queues; 2555 2556 reg = MAC_RQC2R; 2557 reg_val = 0; 2558 for (i = 0, prio = 0; i < prio_queues;) { 2559 mask = 0; 2560 for (j = 0; j < ppq; j++) { 2561 netif_dbg(pdata, drv, pdata->netdev, 2562 "PRIO%u mapped to RXq%u\n", prio, i); 2563 mask |= (1 << prio); 2564 pdata->prio2q_map[prio++] = i; 2565 } 2566 2567 if (i < ppq_extra) { 2568 netif_dbg(pdata, drv, pdata->netdev, 2569 "PRIO%u mapped to RXq%u\n", prio, i); 2570 mask |= (1 << prio); 2571 pdata->prio2q_map[prio++] = i; 2572 } 2573 2574 reg_val |= (mask << ((i++ % MAC_RQC2_Q_PER_REG) << 3)); 2575 2576 if ((i % MAC_RQC2_Q_PER_REG) && (i != prio_queues)) 2577 continue; 2578 2579 XGMAC_IOWRITE(pdata, reg, reg_val); 2580 reg += MAC_RQC2_INC; 2581 reg_val = 0; 2582 } 2583 2584 /* Select dynamic mapping of MTL Rx queue to DMA Rx channel */ 2585 reg = MTL_RQDCM0R; 2586 reg_val = 0; 2587 for (i = 0; i < pdata->rx_q_count;) { 2588 reg_val |= (0x80 << ((i++ % MTL_RQDCM_Q_PER_REG) << 3)); 2589 2590 if ((i % MTL_RQDCM_Q_PER_REG) && (i != pdata->rx_q_count)) 2591 continue; 2592 2593 XGMAC_IOWRITE(pdata, reg, reg_val); 2594 2595 reg += MTL_RQDCM_INC; 2596 reg_val = 0; 2597 } 2598 } 2599 2600 static void xgbe_config_tc(struct xgbe_prv_data *pdata) 2601 { 2602 unsigned int offset, queue, prio; 2603 u8 i; 2604 2605 netdev_reset_tc(pdata->netdev); 2606 if (!pdata->num_tcs) 2607 return; 2608 2609 netdev_set_num_tc(pdata->netdev, pdata->num_tcs); 2610 2611 for (i = 0, queue = 0, offset = 0; i < pdata->num_tcs; i++) { 2612 while ((queue < pdata->tx_q_count) && 2613 (pdata->q2tc_map[queue] == i)) 2614 queue++; 2615 2616 netif_dbg(pdata, drv, pdata->netdev, "TC%u using TXq%u-%u\n", 2617 i, offset, queue - 1); 2618 netdev_set_tc_queue(pdata->netdev, i, queue - offset, offset); 2619 offset = queue; 2620 } 2621 2622 if (!pdata->ets) 2623 return; 2624 2625 for (prio = 0; prio < IEEE_8021QAZ_MAX_TCS; prio++) 2626 netdev_set_prio_tc_map(pdata->netdev, prio, 2627 pdata->ets->prio_tc[prio]); 2628 } 2629 2630 static void xgbe_config_dcb_tc(struct xgbe_prv_data *pdata) 2631 { 2632 struct ieee_ets *ets = pdata->ets; 2633 unsigned int total_weight, min_weight, weight; 2634 unsigned int mask, reg, reg_val; 2635 unsigned int i, prio; 2636 2637 if (!ets) 2638 return; 2639 2640 /* Set Tx to deficit weighted round robin scheduling algorithm (when 2641 * traffic class is using ETS algorithm) 2642 */ 2643 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_DWRR); 2644 2645 /* Set Traffic Class algorithms */ 2646 total_weight = pdata->netdev->mtu * pdata->hw_feat.tc_cnt; 2647 min_weight = total_weight / 100; 2648 if (!min_weight) 2649 min_weight = 1; 2650 2651 for (i = 0; i < pdata->hw_feat.tc_cnt; i++) { 2652 /* Map the priorities to the traffic class */ 2653 mask = 0; 2654 for (prio = 0; prio < IEEE_8021QAZ_MAX_TCS; prio++) { 2655 if (ets->prio_tc[prio] == i) 2656 mask |= (1 << prio); 2657 } 2658 mask &= 0xff; 2659 2660 netif_dbg(pdata, drv, pdata->netdev, "TC%u PRIO mask=%#x\n", 2661 i, mask); 2662 reg = MTL_TCPM0R + (MTL_TCPM_INC * (i / MTL_TCPM_TC_PER_REG)); 2663 reg_val = XGMAC_IOREAD(pdata, reg); 2664 2665 reg_val &= ~(0xff << ((i % MTL_TCPM_TC_PER_REG) << 3)); 2666 reg_val |= (mask << ((i % MTL_TCPM_TC_PER_REG) << 3)); 2667 2668 XGMAC_IOWRITE(pdata, reg, reg_val); 2669 2670 /* Set the traffic class algorithm */ 2671 switch (ets->tc_tsa[i]) { 2672 case IEEE_8021QAZ_TSA_STRICT: 2673 netif_dbg(pdata, drv, pdata->netdev, 2674 "TC%u using SP\n", i); 2675 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA, 2676 MTL_TSA_SP); 2677 break; 2678 case IEEE_8021QAZ_TSA_ETS: 2679 weight = total_weight * ets->tc_tx_bw[i] / 100; 2680 weight = clamp(weight, min_weight, total_weight); 2681 2682 netif_dbg(pdata, drv, pdata->netdev, 2683 "TC%u using DWRR (weight %u)\n", i, weight); 2684 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA, 2685 MTL_TSA_ETS); 2686 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW, 2687 weight); 2688 break; 2689 } 2690 } 2691 2692 xgbe_config_tc(pdata); 2693 } 2694 2695 static void xgbe_config_dcb_pfc(struct xgbe_prv_data *pdata) 2696 { 2697 if (!test_bit(XGBE_DOWN, &pdata->dev_state)) { 2698 /* Just stop the Tx queues while Rx fifo is changed */ 2699 netif_tx_stop_all_queues(pdata->netdev); 2700 2701 /* Suspend Rx so that fifo's can be adjusted */ 2702 pdata->hw_if.disable_rx(pdata); 2703 } 2704 2705 xgbe_config_rx_fifo_size(pdata); 2706 xgbe_config_flow_control(pdata); 2707 2708 if (!test_bit(XGBE_DOWN, &pdata->dev_state)) { 2709 /* Resume Rx */ 2710 pdata->hw_if.enable_rx(pdata); 2711 2712 /* Resume Tx queues */ 2713 netif_tx_start_all_queues(pdata->netdev); 2714 } 2715 } 2716 2717 static void xgbe_config_mac_address(struct xgbe_prv_data *pdata) 2718 { 2719 xgbe_set_mac_address(pdata, pdata->netdev->dev_addr); 2720 2721 /* Filtering is done using perfect filtering and hash filtering */ 2722 if (pdata->hw_feat.hash_table_size) { 2723 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 1); 2724 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 1); 2725 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HMC, 1); 2726 } 2727 } 2728 2729 static void xgbe_config_jumbo_enable(struct xgbe_prv_data *pdata) 2730 { 2731 unsigned int val; 2732 2733 val = (pdata->netdev->mtu > XGMAC_STD_PACKET_MTU) ? 1 : 0; 2734 2735 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, JE, val); 2736 } 2737 2738 static void xgbe_config_mac_speed(struct xgbe_prv_data *pdata) 2739 { 2740 xgbe_set_speed(pdata, pdata->phy_speed); 2741 } 2742 2743 static void xgbe_config_checksum_offload(struct xgbe_prv_data *pdata) 2744 { 2745 if (pdata->netdev->features & NETIF_F_RXCSUM) 2746 xgbe_enable_rx_csum(pdata); 2747 else 2748 xgbe_disable_rx_csum(pdata); 2749 } 2750 2751 static void xgbe_config_vlan_support(struct xgbe_prv_data *pdata) 2752 { 2753 /* Indicate that VLAN Tx CTAGs come from context descriptors */ 2754 XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, CSVL, 0); 2755 XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, VLTI, 1); 2756 2757 /* Set the current VLAN Hash Table register value */ 2758 xgbe_update_vlan_hash_table(pdata); 2759 2760 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER) 2761 xgbe_enable_rx_vlan_filtering(pdata); 2762 else 2763 xgbe_disable_rx_vlan_filtering(pdata); 2764 2765 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) 2766 xgbe_enable_rx_vlan_stripping(pdata); 2767 else 2768 xgbe_disable_rx_vlan_stripping(pdata); 2769 } 2770 2771 static u64 xgbe_mmc_read(struct xgbe_prv_data *pdata, unsigned int reg_lo) 2772 { 2773 bool read_hi; 2774 u64 val; 2775 2776 if (pdata->vdata->mmc_64bit) { 2777 switch (reg_lo) { 2778 /* These registers are always 32 bit */ 2779 case MMC_RXRUNTERROR: 2780 case MMC_RXJABBERERROR: 2781 case MMC_RXUNDERSIZE_G: 2782 case MMC_RXOVERSIZE_G: 2783 case MMC_RXWATCHDOGERROR: 2784 read_hi = false; 2785 break; 2786 2787 default: 2788 read_hi = true; 2789 } 2790 } else { 2791 switch (reg_lo) { 2792 /* These registers are always 64 bit */ 2793 case MMC_TXOCTETCOUNT_GB_LO: 2794 case MMC_TXOCTETCOUNT_G_LO: 2795 case MMC_RXOCTETCOUNT_GB_LO: 2796 case MMC_RXOCTETCOUNT_G_LO: 2797 read_hi = true; 2798 break; 2799 2800 default: 2801 read_hi = false; 2802 } 2803 } 2804 2805 val = XGMAC_IOREAD(pdata, reg_lo); 2806 2807 if (read_hi) 2808 val |= ((u64)XGMAC_IOREAD(pdata, reg_lo + 4) << 32); 2809 2810 return val; 2811 } 2812 2813 static void xgbe_tx_mmc_int(struct xgbe_prv_data *pdata) 2814 { 2815 struct xgbe_mmc_stats *stats = &pdata->mmc_stats; 2816 unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_TISR); 2817 2818 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXOCTETCOUNT_GB)) 2819 stats->txoctetcount_gb += 2820 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO); 2821 2822 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXFRAMECOUNT_GB)) 2823 stats->txframecount_gb += 2824 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO); 2825 2826 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXBROADCASTFRAMES_G)) 2827 stats->txbroadcastframes_g += 2828 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO); 2829 2830 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXMULTICASTFRAMES_G)) 2831 stats->txmulticastframes_g += 2832 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO); 2833 2834 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX64OCTETS_GB)) 2835 stats->tx64octets_gb += 2836 xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO); 2837 2838 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX65TO127OCTETS_GB)) 2839 stats->tx65to127octets_gb += 2840 xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO); 2841 2842 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX128TO255OCTETS_GB)) 2843 stats->tx128to255octets_gb += 2844 xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO); 2845 2846 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX256TO511OCTETS_GB)) 2847 stats->tx256to511octets_gb += 2848 xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO); 2849 2850 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX512TO1023OCTETS_GB)) 2851 stats->tx512to1023octets_gb += 2852 xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO); 2853 2854 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX1024TOMAXOCTETS_GB)) 2855 stats->tx1024tomaxoctets_gb += 2856 xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO); 2857 2858 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXUNICASTFRAMES_GB)) 2859 stats->txunicastframes_gb += 2860 xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO); 2861 2862 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXMULTICASTFRAMES_GB)) 2863 stats->txmulticastframes_gb += 2864 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO); 2865 2866 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXBROADCASTFRAMES_GB)) 2867 stats->txbroadcastframes_g += 2868 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO); 2869 2870 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXUNDERFLOWERROR)) 2871 stats->txunderflowerror += 2872 xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO); 2873 2874 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXOCTETCOUNT_G)) 2875 stats->txoctetcount_g += 2876 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO); 2877 2878 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXFRAMECOUNT_G)) 2879 stats->txframecount_g += 2880 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO); 2881 2882 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXPAUSEFRAMES)) 2883 stats->txpauseframes += 2884 xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO); 2885 2886 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXVLANFRAMES_G)) 2887 stats->txvlanframes_g += 2888 xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO); 2889 } 2890 2891 static void xgbe_rx_mmc_int(struct xgbe_prv_data *pdata) 2892 { 2893 struct xgbe_mmc_stats *stats = &pdata->mmc_stats; 2894 unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_RISR); 2895 2896 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXFRAMECOUNT_GB)) 2897 stats->rxframecount_gb += 2898 xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO); 2899 2900 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOCTETCOUNT_GB)) 2901 stats->rxoctetcount_gb += 2902 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO); 2903 2904 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOCTETCOUNT_G)) 2905 stats->rxoctetcount_g += 2906 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO); 2907 2908 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXBROADCASTFRAMES_G)) 2909 stats->rxbroadcastframes_g += 2910 xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO); 2911 2912 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXMULTICASTFRAMES_G)) 2913 stats->rxmulticastframes_g += 2914 xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO); 2915 2916 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXCRCERROR)) 2917 stats->rxcrcerror += 2918 xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO); 2919 2920 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXRUNTERROR)) 2921 stats->rxrunterror += 2922 xgbe_mmc_read(pdata, MMC_RXRUNTERROR); 2923 2924 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXJABBERERROR)) 2925 stats->rxjabbererror += 2926 xgbe_mmc_read(pdata, MMC_RXJABBERERROR); 2927 2928 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXUNDERSIZE_G)) 2929 stats->rxundersize_g += 2930 xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G); 2931 2932 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOVERSIZE_G)) 2933 stats->rxoversize_g += 2934 xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G); 2935 2936 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX64OCTETS_GB)) 2937 stats->rx64octets_gb += 2938 xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO); 2939 2940 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX65TO127OCTETS_GB)) 2941 stats->rx65to127octets_gb += 2942 xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO); 2943 2944 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX128TO255OCTETS_GB)) 2945 stats->rx128to255octets_gb += 2946 xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO); 2947 2948 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX256TO511OCTETS_GB)) 2949 stats->rx256to511octets_gb += 2950 xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO); 2951 2952 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX512TO1023OCTETS_GB)) 2953 stats->rx512to1023octets_gb += 2954 xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO); 2955 2956 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX1024TOMAXOCTETS_GB)) 2957 stats->rx1024tomaxoctets_gb += 2958 xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO); 2959 2960 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXUNICASTFRAMES_G)) 2961 stats->rxunicastframes_g += 2962 xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO); 2963 2964 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXLENGTHERROR)) 2965 stats->rxlengtherror += 2966 xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO); 2967 2968 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOUTOFRANGETYPE)) 2969 stats->rxoutofrangetype += 2970 xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO); 2971 2972 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXPAUSEFRAMES)) 2973 stats->rxpauseframes += 2974 xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO); 2975 2976 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXFIFOOVERFLOW)) 2977 stats->rxfifooverflow += 2978 xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO); 2979 2980 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXVLANFRAMES_GB)) 2981 stats->rxvlanframes_gb += 2982 xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO); 2983 2984 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXWATCHDOGERROR)) 2985 stats->rxwatchdogerror += 2986 xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR); 2987 } 2988 2989 static void xgbe_read_mmc_stats(struct xgbe_prv_data *pdata) 2990 { 2991 struct xgbe_mmc_stats *stats = &pdata->mmc_stats; 2992 2993 /* Freeze counters */ 2994 XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 1); 2995 2996 stats->txoctetcount_gb += 2997 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO); 2998 2999 stats->txframecount_gb += 3000 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO); 3001 3002 stats->txbroadcastframes_g += 3003 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO); 3004 3005 stats->txmulticastframes_g += 3006 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO); 3007 3008 stats->tx64octets_gb += 3009 xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO); 3010 3011 stats->tx65to127octets_gb += 3012 xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO); 3013 3014 stats->tx128to255octets_gb += 3015 xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO); 3016 3017 stats->tx256to511octets_gb += 3018 xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO); 3019 3020 stats->tx512to1023octets_gb += 3021 xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO); 3022 3023 stats->tx1024tomaxoctets_gb += 3024 xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO); 3025 3026 stats->txunicastframes_gb += 3027 xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO); 3028 3029 stats->txmulticastframes_gb += 3030 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO); 3031 3032 stats->txbroadcastframes_g += 3033 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO); 3034 3035 stats->txunderflowerror += 3036 xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO); 3037 3038 stats->txoctetcount_g += 3039 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO); 3040 3041 stats->txframecount_g += 3042 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO); 3043 3044 stats->txpauseframes += 3045 xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO); 3046 3047 stats->txvlanframes_g += 3048 xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO); 3049 3050 stats->rxframecount_gb += 3051 xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO); 3052 3053 stats->rxoctetcount_gb += 3054 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO); 3055 3056 stats->rxoctetcount_g += 3057 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO); 3058 3059 stats->rxbroadcastframes_g += 3060 xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO); 3061 3062 stats->rxmulticastframes_g += 3063 xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO); 3064 3065 stats->rxcrcerror += 3066 xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO); 3067 3068 stats->rxrunterror += 3069 xgbe_mmc_read(pdata, MMC_RXRUNTERROR); 3070 3071 stats->rxjabbererror += 3072 xgbe_mmc_read(pdata, MMC_RXJABBERERROR); 3073 3074 stats->rxundersize_g += 3075 xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G); 3076 3077 stats->rxoversize_g += 3078 xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G); 3079 3080 stats->rx64octets_gb += 3081 xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO); 3082 3083 stats->rx65to127octets_gb += 3084 xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO); 3085 3086 stats->rx128to255octets_gb += 3087 xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO); 3088 3089 stats->rx256to511octets_gb += 3090 xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO); 3091 3092 stats->rx512to1023octets_gb += 3093 xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO); 3094 3095 stats->rx1024tomaxoctets_gb += 3096 xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO); 3097 3098 stats->rxunicastframes_g += 3099 xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO); 3100 3101 stats->rxlengtherror += 3102 xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO); 3103 3104 stats->rxoutofrangetype += 3105 xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO); 3106 3107 stats->rxpauseframes += 3108 xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO); 3109 3110 stats->rxfifooverflow += 3111 xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO); 3112 3113 stats->rxvlanframes_gb += 3114 xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO); 3115 3116 stats->rxwatchdogerror += 3117 xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR); 3118 3119 /* Un-freeze counters */ 3120 XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 0); 3121 } 3122 3123 static void xgbe_config_mmc(struct xgbe_prv_data *pdata) 3124 { 3125 /* Set counters to reset on read */ 3126 XGMAC_IOWRITE_BITS(pdata, MMC_CR, ROR, 1); 3127 3128 /* Reset the counters */ 3129 XGMAC_IOWRITE_BITS(pdata, MMC_CR, CR, 1); 3130 } 3131 3132 static void xgbe_txq_prepare_tx_stop(struct xgbe_prv_data *pdata, 3133 unsigned int queue) 3134 { 3135 unsigned int tx_status; 3136 unsigned long tx_timeout; 3137 3138 /* The Tx engine cannot be stopped if it is actively processing 3139 * packets. Wait for the Tx queue to empty the Tx fifo. Don't 3140 * wait forever though... 3141 */ 3142 tx_timeout = jiffies + (XGBE_DMA_STOP_TIMEOUT * HZ); 3143 while (time_before(jiffies, tx_timeout)) { 3144 tx_status = XGMAC_MTL_IOREAD(pdata, queue, MTL_Q_TQDR); 3145 if ((XGMAC_GET_BITS(tx_status, MTL_Q_TQDR, TRCSTS) != 1) && 3146 (XGMAC_GET_BITS(tx_status, MTL_Q_TQDR, TXQSTS) == 0)) 3147 break; 3148 3149 usleep_range(500, 1000); 3150 } 3151 3152 if (!time_before(jiffies, tx_timeout)) 3153 netdev_info(pdata->netdev, 3154 "timed out waiting for Tx queue %u to empty\n", 3155 queue); 3156 } 3157 3158 static void xgbe_prepare_tx_stop(struct xgbe_prv_data *pdata, 3159 unsigned int queue) 3160 { 3161 unsigned int tx_dsr, tx_pos, tx_qidx; 3162 unsigned int tx_status; 3163 unsigned long tx_timeout; 3164 3165 if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) > 0x20) 3166 return xgbe_txq_prepare_tx_stop(pdata, queue); 3167 3168 /* Calculate the status register to read and the position within */ 3169 if (queue < DMA_DSRX_FIRST_QUEUE) { 3170 tx_dsr = DMA_DSR0; 3171 tx_pos = (queue * DMA_DSR_Q_WIDTH) + DMA_DSR0_TPS_START; 3172 } else { 3173 tx_qidx = queue - DMA_DSRX_FIRST_QUEUE; 3174 3175 tx_dsr = DMA_DSR1 + ((tx_qidx / DMA_DSRX_QPR) * DMA_DSRX_INC); 3176 tx_pos = ((tx_qidx % DMA_DSRX_QPR) * DMA_DSR_Q_WIDTH) + 3177 DMA_DSRX_TPS_START; 3178 } 3179 3180 /* The Tx engine cannot be stopped if it is actively processing 3181 * descriptors. Wait for the Tx engine to enter the stopped or 3182 * suspended state. Don't wait forever though... 3183 */ 3184 tx_timeout = jiffies + (XGBE_DMA_STOP_TIMEOUT * HZ); 3185 while (time_before(jiffies, tx_timeout)) { 3186 tx_status = XGMAC_IOREAD(pdata, tx_dsr); 3187 tx_status = GET_BITS(tx_status, tx_pos, DMA_DSR_TPS_WIDTH); 3188 if ((tx_status == DMA_TPS_STOPPED) || 3189 (tx_status == DMA_TPS_SUSPENDED)) 3190 break; 3191 3192 usleep_range(500, 1000); 3193 } 3194 3195 if (!time_before(jiffies, tx_timeout)) 3196 netdev_info(pdata->netdev, 3197 "timed out waiting for Tx DMA channel %u to stop\n", 3198 queue); 3199 } 3200 3201 static void xgbe_enable_tx(struct xgbe_prv_data *pdata) 3202 { 3203 struct xgbe_channel *channel; 3204 unsigned int i; 3205 3206 /* Enable each Tx DMA channel */ 3207 channel = pdata->channel; 3208 for (i = 0; i < pdata->channel_count; i++, channel++) { 3209 if (!channel->tx_ring) 3210 break; 3211 3212 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 1); 3213 } 3214 3215 /* Enable each Tx queue */ 3216 for (i = 0; i < pdata->tx_q_count; i++) 3217 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN, 3218 MTL_Q_ENABLED); 3219 3220 /* Enable MAC Tx */ 3221 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1); 3222 } 3223 3224 static void xgbe_disable_tx(struct xgbe_prv_data *pdata) 3225 { 3226 struct xgbe_channel *channel; 3227 unsigned int i; 3228 3229 /* Prepare for Tx DMA channel stop */ 3230 for (i = 0; i < pdata->tx_q_count; i++) 3231 xgbe_prepare_tx_stop(pdata, i); 3232 3233 /* Disable MAC Tx */ 3234 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0); 3235 3236 /* Disable each Tx queue */ 3237 for (i = 0; i < pdata->tx_q_count; i++) 3238 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN, 0); 3239 3240 /* Disable each Tx DMA channel */ 3241 channel = pdata->channel; 3242 for (i = 0; i < pdata->channel_count; i++, channel++) { 3243 if (!channel->tx_ring) 3244 break; 3245 3246 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 0); 3247 } 3248 } 3249 3250 static void xgbe_prepare_rx_stop(struct xgbe_prv_data *pdata, 3251 unsigned int queue) 3252 { 3253 unsigned int rx_status; 3254 unsigned long rx_timeout; 3255 3256 /* The Rx engine cannot be stopped if it is actively processing 3257 * packets. Wait for the Rx queue to empty the Rx fifo. Don't 3258 * wait forever though... 3259 */ 3260 rx_timeout = jiffies + (XGBE_DMA_STOP_TIMEOUT * HZ); 3261 while (time_before(jiffies, rx_timeout)) { 3262 rx_status = XGMAC_MTL_IOREAD(pdata, queue, MTL_Q_RQDR); 3263 if ((XGMAC_GET_BITS(rx_status, MTL_Q_RQDR, PRXQ) == 0) && 3264 (XGMAC_GET_BITS(rx_status, MTL_Q_RQDR, RXQSTS) == 0)) 3265 break; 3266 3267 usleep_range(500, 1000); 3268 } 3269 3270 if (!time_before(jiffies, rx_timeout)) 3271 netdev_info(pdata->netdev, 3272 "timed out waiting for Rx queue %u to empty\n", 3273 queue); 3274 } 3275 3276 static void xgbe_enable_rx(struct xgbe_prv_data *pdata) 3277 { 3278 struct xgbe_channel *channel; 3279 unsigned int reg_val, i; 3280 3281 /* Enable each Rx DMA channel */ 3282 channel = pdata->channel; 3283 for (i = 0; i < pdata->channel_count; i++, channel++) { 3284 if (!channel->rx_ring) 3285 break; 3286 3287 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 1); 3288 } 3289 3290 /* Enable each Rx queue */ 3291 reg_val = 0; 3292 for (i = 0; i < pdata->rx_q_count; i++) 3293 reg_val |= (0x02 << (i << 1)); 3294 XGMAC_IOWRITE(pdata, MAC_RQC0R, reg_val); 3295 3296 /* Enable MAC Rx */ 3297 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 1); 3298 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 1); 3299 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 1); 3300 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 1); 3301 } 3302 3303 static void xgbe_disable_rx(struct xgbe_prv_data *pdata) 3304 { 3305 struct xgbe_channel *channel; 3306 unsigned int i; 3307 3308 /* Disable MAC Rx */ 3309 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 0); 3310 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 0); 3311 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 0); 3312 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 0); 3313 3314 /* Prepare for Rx DMA channel stop */ 3315 for (i = 0; i < pdata->rx_q_count; i++) 3316 xgbe_prepare_rx_stop(pdata, i); 3317 3318 /* Disable each Rx queue */ 3319 XGMAC_IOWRITE(pdata, MAC_RQC0R, 0); 3320 3321 /* Disable each Rx DMA channel */ 3322 channel = pdata->channel; 3323 for (i = 0; i < pdata->channel_count; i++, channel++) { 3324 if (!channel->rx_ring) 3325 break; 3326 3327 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 0); 3328 } 3329 } 3330 3331 static void xgbe_powerup_tx(struct xgbe_prv_data *pdata) 3332 { 3333 struct xgbe_channel *channel; 3334 unsigned int i; 3335 3336 /* Enable each Tx DMA channel */ 3337 channel = pdata->channel; 3338 for (i = 0; i < pdata->channel_count; i++, channel++) { 3339 if (!channel->tx_ring) 3340 break; 3341 3342 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 1); 3343 } 3344 3345 /* Enable MAC Tx */ 3346 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1); 3347 } 3348 3349 static void xgbe_powerdown_tx(struct xgbe_prv_data *pdata) 3350 { 3351 struct xgbe_channel *channel; 3352 unsigned int i; 3353 3354 /* Prepare for Tx DMA channel stop */ 3355 for (i = 0; i < pdata->tx_q_count; i++) 3356 xgbe_prepare_tx_stop(pdata, i); 3357 3358 /* Disable MAC Tx */ 3359 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0); 3360 3361 /* Disable each Tx DMA channel */ 3362 channel = pdata->channel; 3363 for (i = 0; i < pdata->channel_count; i++, channel++) { 3364 if (!channel->tx_ring) 3365 break; 3366 3367 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 0); 3368 } 3369 } 3370 3371 static void xgbe_powerup_rx(struct xgbe_prv_data *pdata) 3372 { 3373 struct xgbe_channel *channel; 3374 unsigned int i; 3375 3376 /* Enable each Rx DMA channel */ 3377 channel = pdata->channel; 3378 for (i = 0; i < pdata->channel_count; i++, channel++) { 3379 if (!channel->rx_ring) 3380 break; 3381 3382 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 1); 3383 } 3384 } 3385 3386 static void xgbe_powerdown_rx(struct xgbe_prv_data *pdata) 3387 { 3388 struct xgbe_channel *channel; 3389 unsigned int i; 3390 3391 /* Disable each Rx DMA channel */ 3392 channel = pdata->channel; 3393 for (i = 0; i < pdata->channel_count; i++, channel++) { 3394 if (!channel->rx_ring) 3395 break; 3396 3397 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 0); 3398 } 3399 } 3400 3401 static int xgbe_init(struct xgbe_prv_data *pdata) 3402 { 3403 struct xgbe_desc_if *desc_if = &pdata->desc_if; 3404 int ret; 3405 3406 DBGPR("-->xgbe_init\n"); 3407 3408 /* Flush Tx queues */ 3409 ret = xgbe_flush_tx_queues(pdata); 3410 if (ret) 3411 return ret; 3412 3413 /* 3414 * Initialize DMA related features 3415 */ 3416 xgbe_config_dma_bus(pdata); 3417 xgbe_config_dma_cache(pdata); 3418 xgbe_config_osp_mode(pdata); 3419 xgbe_config_pblx8(pdata); 3420 xgbe_config_tx_pbl_val(pdata); 3421 xgbe_config_rx_pbl_val(pdata); 3422 xgbe_config_rx_coalesce(pdata); 3423 xgbe_config_tx_coalesce(pdata); 3424 xgbe_config_rx_buffer_size(pdata); 3425 xgbe_config_tso_mode(pdata); 3426 xgbe_config_sph_mode(pdata); 3427 xgbe_config_rss(pdata); 3428 desc_if->wrapper_tx_desc_init(pdata); 3429 desc_if->wrapper_rx_desc_init(pdata); 3430 xgbe_enable_dma_interrupts(pdata); 3431 3432 /* 3433 * Initialize MTL related features 3434 */ 3435 xgbe_config_mtl_mode(pdata); 3436 xgbe_config_queue_mapping(pdata); 3437 xgbe_config_tsf_mode(pdata, pdata->tx_sf_mode); 3438 xgbe_config_rsf_mode(pdata, pdata->rx_sf_mode); 3439 xgbe_config_tx_threshold(pdata, pdata->tx_threshold); 3440 xgbe_config_rx_threshold(pdata, pdata->rx_threshold); 3441 xgbe_config_tx_fifo_size(pdata); 3442 xgbe_config_rx_fifo_size(pdata); 3443 /*TODO: Error Packet and undersized good Packet forwarding enable 3444 (FEP and FUP) 3445 */ 3446 xgbe_config_dcb_tc(pdata); 3447 xgbe_enable_mtl_interrupts(pdata); 3448 3449 /* 3450 * Initialize MAC related features 3451 */ 3452 xgbe_config_mac_address(pdata); 3453 xgbe_config_rx_mode(pdata); 3454 xgbe_config_jumbo_enable(pdata); 3455 xgbe_config_flow_control(pdata); 3456 xgbe_config_mac_speed(pdata); 3457 xgbe_config_checksum_offload(pdata); 3458 xgbe_config_vlan_support(pdata); 3459 xgbe_config_mmc(pdata); 3460 xgbe_enable_mac_interrupts(pdata); 3461 3462 /* 3463 * Initialize ECC related features 3464 */ 3465 xgbe_enable_ecc_interrupts(pdata); 3466 3467 DBGPR("<--xgbe_init\n"); 3468 3469 return 0; 3470 } 3471 3472 void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *hw_if) 3473 { 3474 DBGPR("-->xgbe_init_function_ptrs\n"); 3475 3476 hw_if->tx_complete = xgbe_tx_complete; 3477 3478 hw_if->set_mac_address = xgbe_set_mac_address; 3479 hw_if->config_rx_mode = xgbe_config_rx_mode; 3480 3481 hw_if->enable_rx_csum = xgbe_enable_rx_csum; 3482 hw_if->disable_rx_csum = xgbe_disable_rx_csum; 3483 3484 hw_if->enable_rx_vlan_stripping = xgbe_enable_rx_vlan_stripping; 3485 hw_if->disable_rx_vlan_stripping = xgbe_disable_rx_vlan_stripping; 3486 hw_if->enable_rx_vlan_filtering = xgbe_enable_rx_vlan_filtering; 3487 hw_if->disable_rx_vlan_filtering = xgbe_disable_rx_vlan_filtering; 3488 hw_if->update_vlan_hash_table = xgbe_update_vlan_hash_table; 3489 3490 hw_if->read_mmd_regs = xgbe_read_mmd_regs; 3491 hw_if->write_mmd_regs = xgbe_write_mmd_regs; 3492 3493 hw_if->set_speed = xgbe_set_speed; 3494 3495 hw_if->set_ext_mii_mode = xgbe_set_ext_mii_mode; 3496 hw_if->read_ext_mii_regs = xgbe_read_ext_mii_regs; 3497 hw_if->write_ext_mii_regs = xgbe_write_ext_mii_regs; 3498 3499 hw_if->set_gpio = xgbe_set_gpio; 3500 hw_if->clr_gpio = xgbe_clr_gpio; 3501 3502 hw_if->enable_tx = xgbe_enable_tx; 3503 hw_if->disable_tx = xgbe_disable_tx; 3504 hw_if->enable_rx = xgbe_enable_rx; 3505 hw_if->disable_rx = xgbe_disable_rx; 3506 3507 hw_if->powerup_tx = xgbe_powerup_tx; 3508 hw_if->powerdown_tx = xgbe_powerdown_tx; 3509 hw_if->powerup_rx = xgbe_powerup_rx; 3510 hw_if->powerdown_rx = xgbe_powerdown_rx; 3511 3512 hw_if->dev_xmit = xgbe_dev_xmit; 3513 hw_if->dev_read = xgbe_dev_read; 3514 hw_if->enable_int = xgbe_enable_int; 3515 hw_if->disable_int = xgbe_disable_int; 3516 hw_if->init = xgbe_init; 3517 hw_if->exit = xgbe_exit; 3518 3519 /* Descriptor related Sequences have to be initialized here */ 3520 hw_if->tx_desc_init = xgbe_tx_desc_init; 3521 hw_if->rx_desc_init = xgbe_rx_desc_init; 3522 hw_if->tx_desc_reset = xgbe_tx_desc_reset; 3523 hw_if->rx_desc_reset = xgbe_rx_desc_reset; 3524 hw_if->is_last_desc = xgbe_is_last_desc; 3525 hw_if->is_context_desc = xgbe_is_context_desc; 3526 hw_if->tx_start_xmit = xgbe_tx_start_xmit; 3527 3528 /* For FLOW ctrl */ 3529 hw_if->config_tx_flow_control = xgbe_config_tx_flow_control; 3530 hw_if->config_rx_flow_control = xgbe_config_rx_flow_control; 3531 3532 /* For RX coalescing */ 3533 hw_if->config_rx_coalesce = xgbe_config_rx_coalesce; 3534 hw_if->config_tx_coalesce = xgbe_config_tx_coalesce; 3535 hw_if->usec_to_riwt = xgbe_usec_to_riwt; 3536 hw_if->riwt_to_usec = xgbe_riwt_to_usec; 3537 3538 /* For RX and TX threshold config */ 3539 hw_if->config_rx_threshold = xgbe_config_rx_threshold; 3540 hw_if->config_tx_threshold = xgbe_config_tx_threshold; 3541 3542 /* For RX and TX Store and Forward Mode config */ 3543 hw_if->config_rsf_mode = xgbe_config_rsf_mode; 3544 hw_if->config_tsf_mode = xgbe_config_tsf_mode; 3545 3546 /* For TX DMA Operating on Second Frame config */ 3547 hw_if->config_osp_mode = xgbe_config_osp_mode; 3548 3549 /* For RX and TX PBL config */ 3550 hw_if->config_rx_pbl_val = xgbe_config_rx_pbl_val; 3551 hw_if->get_rx_pbl_val = xgbe_get_rx_pbl_val; 3552 hw_if->config_tx_pbl_val = xgbe_config_tx_pbl_val; 3553 hw_if->get_tx_pbl_val = xgbe_get_tx_pbl_val; 3554 hw_if->config_pblx8 = xgbe_config_pblx8; 3555 3556 /* For MMC statistics support */ 3557 hw_if->tx_mmc_int = xgbe_tx_mmc_int; 3558 hw_if->rx_mmc_int = xgbe_rx_mmc_int; 3559 hw_if->read_mmc_stats = xgbe_read_mmc_stats; 3560 3561 /* For PTP config */ 3562 hw_if->config_tstamp = xgbe_config_tstamp; 3563 hw_if->update_tstamp_addend = xgbe_update_tstamp_addend; 3564 hw_if->set_tstamp_time = xgbe_set_tstamp_time; 3565 hw_if->get_tstamp_time = xgbe_get_tstamp_time; 3566 hw_if->get_tx_tstamp = xgbe_get_tx_tstamp; 3567 3568 /* For Data Center Bridging config */ 3569 hw_if->config_tc = xgbe_config_tc; 3570 hw_if->config_dcb_tc = xgbe_config_dcb_tc; 3571 hw_if->config_dcb_pfc = xgbe_config_dcb_pfc; 3572 3573 /* For Receive Side Scaling */ 3574 hw_if->enable_rss = xgbe_enable_rss; 3575 hw_if->disable_rss = xgbe_disable_rss; 3576 hw_if->set_rss_hash_key = xgbe_set_rss_hash_key; 3577 hw_if->set_rss_lookup_table = xgbe_set_rss_lookup_table; 3578 3579 /* For ECC */ 3580 hw_if->disable_ecc_ded = xgbe_disable_ecc_ded; 3581 hw_if->disable_ecc_sec = xgbe_disable_ecc_sec; 3582 3583 DBGPR("<--xgbe_init_function_ptrs\n"); 3584 } 3585