1 /*
2  * AMD 10Gb Ethernet driver
3  *
4  * This file is available to you under your choice of the following two
5  * licenses:
6  *
7  * License 1: GPLv2
8  *
9  * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
10  *
11  * This file is free software; you may copy, redistribute and/or modify
12  * it under the terms of the GNU General Public License as published by
13  * the Free Software Foundation, either version 2 of the License, or (at
14  * your option) any later version.
15  *
16  * This file is distributed in the hope that it will be useful, but
17  * WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19  * General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
23  *
24  * This file incorporates work covered by the following copyright and
25  * permission notice:
26  *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
27  *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28  *     Inc. unless otherwise expressly agreed to in writing between Synopsys
29  *     and you.
30  *
31  *     The Software IS NOT an item of Licensed Software or Licensed Product
32  *     under any End User Software License Agreement or Agreement for Licensed
33  *     Product with Synopsys or any supplement thereto.  Permission is hereby
34  *     granted, free of charge, to any person obtaining a copy of this software
35  *     annotated with this license and the Software, to deal in the Software
36  *     without restriction, including without limitation the rights to use,
37  *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38  *     of the Software, and to permit persons to whom the Software is furnished
39  *     to do so, subject to the following conditions:
40  *
41  *     The above copyright notice and this permission notice shall be included
42  *     in all copies or substantial portions of the Software.
43  *
44  *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45  *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46  *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47  *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48  *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49  *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50  *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51  *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52  *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53  *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54  *     THE POSSIBILITY OF SUCH DAMAGE.
55  *
56  *
57  * License 2: Modified BSD
58  *
59  * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
60  * All rights reserved.
61  *
62  * Redistribution and use in source and binary forms, with or without
63  * modification, are permitted provided that the following conditions are met:
64  *     * Redistributions of source code must retain the above copyright
65  *       notice, this list of conditions and the following disclaimer.
66  *     * Redistributions in binary form must reproduce the above copyright
67  *       notice, this list of conditions and the following disclaimer in the
68  *       documentation and/or other materials provided with the distribution.
69  *     * Neither the name of Advanced Micro Devices, Inc. nor the
70  *       names of its contributors may be used to endorse or promote products
71  *       derived from this software without specific prior written permission.
72  *
73  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76  * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
83  *
84  * This file incorporates work covered by the following copyright and
85  * permission notice:
86  *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
87  *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88  *     Inc. unless otherwise expressly agreed to in writing between Synopsys
89  *     and you.
90  *
91  *     The Software IS NOT an item of Licensed Software or Licensed Product
92  *     under any End User Software License Agreement or Agreement for Licensed
93  *     Product with Synopsys or any supplement thereto.  Permission is hereby
94  *     granted, free of charge, to any person obtaining a copy of this software
95  *     annotated with this license and the Software, to deal in the Software
96  *     without restriction, including without limitation the rights to use,
97  *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98  *     of the Software, and to permit persons to whom the Software is furnished
99  *     to do so, subject to the following conditions:
100  *
101  *     The above copyright notice and this permission notice shall be included
102  *     in all copies or substantial portions of the Software.
103  *
104  *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105  *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106  *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107  *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108  *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109  *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110  *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111  *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112  *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113  *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114  *     THE POSSIBILITY OF SUCH DAMAGE.
115  */
116 
117 #include <linux/phy.h>
118 #include <linux/mdio.h>
119 #include <linux/clk.h>
120 #include <linux/bitrev.h>
121 #include <linux/crc32.h>
122 #include <linux/crc32poly.h>
123 
124 #include "xgbe.h"
125 #include "xgbe-common.h"
126 
127 static inline unsigned int xgbe_get_max_frame(struct xgbe_prv_data *pdata)
128 {
129 	return pdata->netdev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
130 }
131 
132 static unsigned int xgbe_usec_to_riwt(struct xgbe_prv_data *pdata,
133 				      unsigned int usec)
134 {
135 	unsigned long rate;
136 	unsigned int ret;
137 
138 	DBGPR("-->xgbe_usec_to_riwt\n");
139 
140 	rate = pdata->sysclk_rate;
141 
142 	/*
143 	 * Convert the input usec value to the watchdog timer value. Each
144 	 * watchdog timer value is equivalent to 256 clock cycles.
145 	 * Calculate the required value as:
146 	 *   ( usec * ( system_clock_mhz / 10^6 ) / 256
147 	 */
148 	ret = (usec * (rate / 1000000)) / 256;
149 
150 	DBGPR("<--xgbe_usec_to_riwt\n");
151 
152 	return ret;
153 }
154 
155 static unsigned int xgbe_riwt_to_usec(struct xgbe_prv_data *pdata,
156 				      unsigned int riwt)
157 {
158 	unsigned long rate;
159 	unsigned int ret;
160 
161 	DBGPR("-->xgbe_riwt_to_usec\n");
162 
163 	rate = pdata->sysclk_rate;
164 
165 	/*
166 	 * Convert the input watchdog timer value to the usec value. Each
167 	 * watchdog timer value is equivalent to 256 clock cycles.
168 	 * Calculate the required value as:
169 	 *   ( riwt * 256 ) / ( system_clock_mhz / 10^6 )
170 	 */
171 	ret = (riwt * 256) / (rate / 1000000);
172 
173 	DBGPR("<--xgbe_riwt_to_usec\n");
174 
175 	return ret;
176 }
177 
178 static int xgbe_config_pbl_val(struct xgbe_prv_data *pdata)
179 {
180 	unsigned int pblx8, pbl;
181 	unsigned int i;
182 
183 	pblx8 = DMA_PBL_X8_DISABLE;
184 	pbl = pdata->pbl;
185 
186 	if (pdata->pbl > 32) {
187 		pblx8 = DMA_PBL_X8_ENABLE;
188 		pbl >>= 3;
189 	}
190 
191 	for (i = 0; i < pdata->channel_count; i++) {
192 		XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_CR, PBLX8,
193 				       pblx8);
194 
195 		if (pdata->channel[i]->tx_ring)
196 			XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR,
197 					       PBL, pbl);
198 
199 		if (pdata->channel[i]->rx_ring)
200 			XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR,
201 					       PBL, pbl);
202 	}
203 
204 	return 0;
205 }
206 
207 static int xgbe_config_osp_mode(struct xgbe_prv_data *pdata)
208 {
209 	unsigned int i;
210 
211 	for (i = 0; i < pdata->channel_count; i++) {
212 		if (!pdata->channel[i]->tx_ring)
213 			break;
214 
215 		XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, OSP,
216 				       pdata->tx_osp_mode);
217 	}
218 
219 	return 0;
220 }
221 
222 static int xgbe_config_rsf_mode(struct xgbe_prv_data *pdata, unsigned int val)
223 {
224 	unsigned int i;
225 
226 	for (i = 0; i < pdata->rx_q_count; i++)
227 		XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RSF, val);
228 
229 	return 0;
230 }
231 
232 static int xgbe_config_tsf_mode(struct xgbe_prv_data *pdata, unsigned int val)
233 {
234 	unsigned int i;
235 
236 	for (i = 0; i < pdata->tx_q_count; i++)
237 		XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TSF, val);
238 
239 	return 0;
240 }
241 
242 static int xgbe_config_rx_threshold(struct xgbe_prv_data *pdata,
243 				    unsigned int val)
244 {
245 	unsigned int i;
246 
247 	for (i = 0; i < pdata->rx_q_count; i++)
248 		XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RTC, val);
249 
250 	return 0;
251 }
252 
253 static int xgbe_config_tx_threshold(struct xgbe_prv_data *pdata,
254 				    unsigned int val)
255 {
256 	unsigned int i;
257 
258 	for (i = 0; i < pdata->tx_q_count; i++)
259 		XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TTC, val);
260 
261 	return 0;
262 }
263 
264 static int xgbe_config_rx_coalesce(struct xgbe_prv_data *pdata)
265 {
266 	unsigned int i;
267 
268 	for (i = 0; i < pdata->channel_count; i++) {
269 		if (!pdata->channel[i]->rx_ring)
270 			break;
271 
272 		XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RIWT, RWT,
273 				       pdata->rx_riwt);
274 	}
275 
276 	return 0;
277 }
278 
279 static int xgbe_config_tx_coalesce(struct xgbe_prv_data *pdata)
280 {
281 	return 0;
282 }
283 
284 static void xgbe_config_rx_buffer_size(struct xgbe_prv_data *pdata)
285 {
286 	unsigned int i;
287 
288 	for (i = 0; i < pdata->channel_count; i++) {
289 		if (!pdata->channel[i]->rx_ring)
290 			break;
291 
292 		XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, RBSZ,
293 				       pdata->rx_buf_size);
294 	}
295 }
296 
297 static void xgbe_config_tso_mode(struct xgbe_prv_data *pdata)
298 {
299 	unsigned int i;
300 
301 	for (i = 0; i < pdata->channel_count; i++) {
302 		if (!pdata->channel[i]->tx_ring)
303 			break;
304 
305 		XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, TSE, 1);
306 	}
307 }
308 
309 static void xgbe_config_sph_mode(struct xgbe_prv_data *pdata)
310 {
311 	unsigned int i;
312 
313 	for (i = 0; i < pdata->channel_count; i++) {
314 		if (!pdata->channel[i]->rx_ring)
315 			break;
316 
317 		XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_CR, SPH, 1);
318 	}
319 
320 	XGMAC_IOWRITE_BITS(pdata, MAC_RCR, HDSMS, XGBE_SPH_HDSMS_SIZE);
321 }
322 
323 static int xgbe_write_rss_reg(struct xgbe_prv_data *pdata, unsigned int type,
324 			      unsigned int index, unsigned int val)
325 {
326 	unsigned int wait;
327 	int ret = 0;
328 
329 	mutex_lock(&pdata->rss_mutex);
330 
331 	if (XGMAC_IOREAD_BITS(pdata, MAC_RSSAR, OB)) {
332 		ret = -EBUSY;
333 		goto unlock;
334 	}
335 
336 	XGMAC_IOWRITE(pdata, MAC_RSSDR, val);
337 
338 	XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, RSSIA, index);
339 	XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, ADDRT, type);
340 	XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, CT, 0);
341 	XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, OB, 1);
342 
343 	wait = 1000;
344 	while (wait--) {
345 		if (!XGMAC_IOREAD_BITS(pdata, MAC_RSSAR, OB))
346 			goto unlock;
347 
348 		usleep_range(1000, 1500);
349 	}
350 
351 	ret = -EBUSY;
352 
353 unlock:
354 	mutex_unlock(&pdata->rss_mutex);
355 
356 	return ret;
357 }
358 
359 static int xgbe_write_rss_hash_key(struct xgbe_prv_data *pdata)
360 {
361 	unsigned int key_regs = sizeof(pdata->rss_key) / sizeof(u32);
362 	unsigned int *key = (unsigned int *)&pdata->rss_key;
363 	int ret;
364 
365 	while (key_regs--) {
366 		ret = xgbe_write_rss_reg(pdata, XGBE_RSS_HASH_KEY_TYPE,
367 					 key_regs, *key++);
368 		if (ret)
369 			return ret;
370 	}
371 
372 	return 0;
373 }
374 
375 static int xgbe_write_rss_lookup_table(struct xgbe_prv_data *pdata)
376 {
377 	unsigned int i;
378 	int ret;
379 
380 	for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++) {
381 		ret = xgbe_write_rss_reg(pdata,
382 					 XGBE_RSS_LOOKUP_TABLE_TYPE, i,
383 					 pdata->rss_table[i]);
384 		if (ret)
385 			return ret;
386 	}
387 
388 	return 0;
389 }
390 
391 static int xgbe_set_rss_hash_key(struct xgbe_prv_data *pdata, const u8 *key)
392 {
393 	memcpy(pdata->rss_key, key, sizeof(pdata->rss_key));
394 
395 	return xgbe_write_rss_hash_key(pdata);
396 }
397 
398 static int xgbe_set_rss_lookup_table(struct xgbe_prv_data *pdata,
399 				     const u32 *table)
400 {
401 	unsigned int i;
402 
403 	for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++)
404 		XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH, table[i]);
405 
406 	return xgbe_write_rss_lookup_table(pdata);
407 }
408 
409 static int xgbe_enable_rss(struct xgbe_prv_data *pdata)
410 {
411 	int ret;
412 
413 	if (!pdata->hw_feat.rss)
414 		return -EOPNOTSUPP;
415 
416 	/* Program the hash key */
417 	ret = xgbe_write_rss_hash_key(pdata);
418 	if (ret)
419 		return ret;
420 
421 	/* Program the lookup table */
422 	ret = xgbe_write_rss_lookup_table(pdata);
423 	if (ret)
424 		return ret;
425 
426 	/* Set the RSS options */
427 	XGMAC_IOWRITE(pdata, MAC_RSSCR, pdata->rss_options);
428 
429 	/* Enable RSS */
430 	XGMAC_IOWRITE_BITS(pdata, MAC_RSSCR, RSSE, 1);
431 
432 	return 0;
433 }
434 
435 static int xgbe_disable_rss(struct xgbe_prv_data *pdata)
436 {
437 	if (!pdata->hw_feat.rss)
438 		return -EOPNOTSUPP;
439 
440 	XGMAC_IOWRITE_BITS(pdata, MAC_RSSCR, RSSE, 0);
441 
442 	return 0;
443 }
444 
445 static void xgbe_config_rss(struct xgbe_prv_data *pdata)
446 {
447 	int ret;
448 
449 	if (!pdata->hw_feat.rss)
450 		return;
451 
452 	if (pdata->netdev->features & NETIF_F_RXHASH)
453 		ret = xgbe_enable_rss(pdata);
454 	else
455 		ret = xgbe_disable_rss(pdata);
456 
457 	if (ret)
458 		netdev_err(pdata->netdev,
459 			   "error configuring RSS, RSS disabled\n");
460 }
461 
462 static bool xgbe_is_pfc_queue(struct xgbe_prv_data *pdata,
463 			      unsigned int queue)
464 {
465 	unsigned int prio, tc;
466 
467 	for (prio = 0; prio < IEEE_8021QAZ_MAX_TCS; prio++) {
468 		/* Does this queue handle the priority? */
469 		if (pdata->prio2q_map[prio] != queue)
470 			continue;
471 
472 		/* Get the Traffic Class for this priority */
473 		tc = pdata->ets->prio_tc[prio];
474 
475 		/* Check if PFC is enabled for this traffic class */
476 		if (pdata->pfc->pfc_en & (1 << tc))
477 			return true;
478 	}
479 
480 	return false;
481 }
482 
483 static void xgbe_set_vxlan_id(struct xgbe_prv_data *pdata)
484 {
485 	/* Program the VXLAN port */
486 	XGMAC_IOWRITE_BITS(pdata, MAC_TIR, TNID, pdata->vxlan_port);
487 
488 	netif_dbg(pdata, drv, pdata->netdev, "VXLAN tunnel id set to %hx\n",
489 		  pdata->vxlan_port);
490 }
491 
492 static void xgbe_enable_vxlan(struct xgbe_prv_data *pdata)
493 {
494 	if (!pdata->hw_feat.vxn)
495 		return;
496 
497 	/* Program the VXLAN port */
498 	xgbe_set_vxlan_id(pdata);
499 
500 	/* Allow for IPv6/UDP zero-checksum VXLAN packets */
501 	XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VUCC, 1);
502 
503 	/* Enable VXLAN tunneling mode */
504 	XGMAC_IOWRITE_BITS(pdata, MAC_TCR, VNM, 0);
505 	XGMAC_IOWRITE_BITS(pdata, MAC_TCR, VNE, 1);
506 
507 	netif_dbg(pdata, drv, pdata->netdev, "VXLAN acceleration enabled\n");
508 }
509 
510 static void xgbe_disable_vxlan(struct xgbe_prv_data *pdata)
511 {
512 	if (!pdata->hw_feat.vxn)
513 		return;
514 
515 	/* Disable tunneling mode */
516 	XGMAC_IOWRITE_BITS(pdata, MAC_TCR, VNE, 0);
517 
518 	/* Clear IPv6/UDP zero-checksum VXLAN packets setting */
519 	XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VUCC, 0);
520 
521 	/* Clear the VXLAN port */
522 	XGMAC_IOWRITE_BITS(pdata, MAC_TIR, TNID, 0);
523 
524 	netif_dbg(pdata, drv, pdata->netdev, "VXLAN acceleration disabled\n");
525 }
526 
527 static int xgbe_disable_tx_flow_control(struct xgbe_prv_data *pdata)
528 {
529 	unsigned int max_q_count, q_count;
530 	unsigned int reg, reg_val;
531 	unsigned int i;
532 
533 	/* Clear MTL flow control */
534 	for (i = 0; i < pdata->rx_q_count; i++)
535 		XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, 0);
536 
537 	/* Clear MAC flow control */
538 	max_q_count = XGMAC_MAX_FLOW_CONTROL_QUEUES;
539 	q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count);
540 	reg = MAC_Q0TFCR;
541 	for (i = 0; i < q_count; i++) {
542 		reg_val = XGMAC_IOREAD(pdata, reg);
543 		XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 0);
544 		XGMAC_IOWRITE(pdata, reg, reg_val);
545 
546 		reg += MAC_QTFCR_INC;
547 	}
548 
549 	return 0;
550 }
551 
552 static int xgbe_enable_tx_flow_control(struct xgbe_prv_data *pdata)
553 {
554 	struct ieee_pfc *pfc = pdata->pfc;
555 	struct ieee_ets *ets = pdata->ets;
556 	unsigned int max_q_count, q_count;
557 	unsigned int reg, reg_val;
558 	unsigned int i;
559 
560 	/* Set MTL flow control */
561 	for (i = 0; i < pdata->rx_q_count; i++) {
562 		unsigned int ehfc = 0;
563 
564 		if (pdata->rx_rfd[i]) {
565 			/* Flow control thresholds are established */
566 			if (pfc && ets) {
567 				if (xgbe_is_pfc_queue(pdata, i))
568 					ehfc = 1;
569 			} else {
570 				ehfc = 1;
571 			}
572 		}
573 
574 		XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, ehfc);
575 
576 		netif_dbg(pdata, drv, pdata->netdev,
577 			  "flow control %s for RXq%u\n",
578 			  ehfc ? "enabled" : "disabled", i);
579 	}
580 
581 	/* Set MAC flow control */
582 	max_q_count = XGMAC_MAX_FLOW_CONTROL_QUEUES;
583 	q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count);
584 	reg = MAC_Q0TFCR;
585 	for (i = 0; i < q_count; i++) {
586 		reg_val = XGMAC_IOREAD(pdata, reg);
587 
588 		/* Enable transmit flow control */
589 		XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 1);
590 		/* Set pause time */
591 		XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, PT, 0xffff);
592 
593 		XGMAC_IOWRITE(pdata, reg, reg_val);
594 
595 		reg += MAC_QTFCR_INC;
596 	}
597 
598 	return 0;
599 }
600 
601 static int xgbe_disable_rx_flow_control(struct xgbe_prv_data *pdata)
602 {
603 	XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 0);
604 
605 	return 0;
606 }
607 
608 static int xgbe_enable_rx_flow_control(struct xgbe_prv_data *pdata)
609 {
610 	XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 1);
611 
612 	return 0;
613 }
614 
615 static int xgbe_config_tx_flow_control(struct xgbe_prv_data *pdata)
616 {
617 	struct ieee_pfc *pfc = pdata->pfc;
618 
619 	if (pdata->tx_pause || (pfc && pfc->pfc_en))
620 		xgbe_enable_tx_flow_control(pdata);
621 	else
622 		xgbe_disable_tx_flow_control(pdata);
623 
624 	return 0;
625 }
626 
627 static int xgbe_config_rx_flow_control(struct xgbe_prv_data *pdata)
628 {
629 	struct ieee_pfc *pfc = pdata->pfc;
630 
631 	if (pdata->rx_pause || (pfc && pfc->pfc_en))
632 		xgbe_enable_rx_flow_control(pdata);
633 	else
634 		xgbe_disable_rx_flow_control(pdata);
635 
636 	return 0;
637 }
638 
639 static void xgbe_config_flow_control(struct xgbe_prv_data *pdata)
640 {
641 	struct ieee_pfc *pfc = pdata->pfc;
642 
643 	xgbe_config_tx_flow_control(pdata);
644 	xgbe_config_rx_flow_control(pdata);
645 
646 	XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE,
647 			   (pfc && pfc->pfc_en) ? 1 : 0);
648 }
649 
650 static void xgbe_enable_dma_interrupts(struct xgbe_prv_data *pdata)
651 {
652 	struct xgbe_channel *channel;
653 	unsigned int i, ver;
654 
655 	/* Set the interrupt mode if supported */
656 	if (pdata->channel_irq_mode)
657 		XGMAC_IOWRITE_BITS(pdata, DMA_MR, INTM,
658 				   pdata->channel_irq_mode);
659 
660 	ver = XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER);
661 
662 	for (i = 0; i < pdata->channel_count; i++) {
663 		channel = pdata->channel[i];
664 
665 		/* Clear all the interrupts which are set */
666 		XGMAC_DMA_IOWRITE(channel, DMA_CH_SR,
667 				  XGMAC_DMA_IOREAD(channel, DMA_CH_SR));
668 
669 		/* Clear all interrupt enable bits */
670 		channel->curr_ier = 0;
671 
672 		/* Enable following interrupts
673 		 *   NIE  - Normal Interrupt Summary Enable
674 		 *   AIE  - Abnormal Interrupt Summary Enable
675 		 *   FBEE - Fatal Bus Error Enable
676 		 */
677 		if (ver < 0x21) {
678 			XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, NIE20, 1);
679 			XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, AIE20, 1);
680 		} else {
681 			XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, NIE, 1);
682 			XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, AIE, 1);
683 		}
684 		XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, FBEE, 1);
685 
686 		if (channel->tx_ring) {
687 			/* Enable the following Tx interrupts
688 			 *   TIE  - Transmit Interrupt Enable (unless using
689 			 *          per channel interrupts in edge triggered
690 			 *          mode)
691 			 */
692 			if (!pdata->per_channel_irq || pdata->channel_irq_mode)
693 				XGMAC_SET_BITS(channel->curr_ier,
694 					       DMA_CH_IER, TIE, 1);
695 		}
696 		if (channel->rx_ring) {
697 			/* Enable following Rx interrupts
698 			 *   RBUE - Receive Buffer Unavailable Enable
699 			 *   RIE  - Receive Interrupt Enable (unless using
700 			 *          per channel interrupts in edge triggered
701 			 *          mode)
702 			 */
703 			XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RBUE, 1);
704 			if (!pdata->per_channel_irq || pdata->channel_irq_mode)
705 				XGMAC_SET_BITS(channel->curr_ier,
706 					       DMA_CH_IER, RIE, 1);
707 		}
708 
709 		XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, channel->curr_ier);
710 	}
711 }
712 
713 static void xgbe_enable_mtl_interrupts(struct xgbe_prv_data *pdata)
714 {
715 	unsigned int mtl_q_isr;
716 	unsigned int q_count, i;
717 
718 	q_count = max(pdata->hw_feat.tx_q_cnt, pdata->hw_feat.rx_q_cnt);
719 	for (i = 0; i < q_count; i++) {
720 		/* Clear all the interrupts which are set */
721 		mtl_q_isr = XGMAC_MTL_IOREAD(pdata, i, MTL_Q_ISR);
722 		XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_ISR, mtl_q_isr);
723 
724 		/* No MTL interrupts to be enabled */
725 		XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_IER, 0);
726 	}
727 }
728 
729 static void xgbe_enable_mac_interrupts(struct xgbe_prv_data *pdata)
730 {
731 	unsigned int mac_ier = 0;
732 
733 	/* Enable Timestamp interrupt */
734 	XGMAC_SET_BITS(mac_ier, MAC_IER, TSIE, 1);
735 
736 	XGMAC_IOWRITE(pdata, MAC_IER, mac_ier);
737 
738 	/* Enable all counter interrupts */
739 	XGMAC_IOWRITE_BITS(pdata, MMC_RIER, ALL_INTERRUPTS, 0xffffffff);
740 	XGMAC_IOWRITE_BITS(pdata, MMC_TIER, ALL_INTERRUPTS, 0xffffffff);
741 
742 	/* Enable MDIO single command completion interrupt */
743 	XGMAC_IOWRITE_BITS(pdata, MAC_MDIOIER, SNGLCOMPIE, 1);
744 }
745 
746 static void xgbe_enable_ecc_interrupts(struct xgbe_prv_data *pdata)
747 {
748 	unsigned int ecc_isr, ecc_ier = 0;
749 
750 	if (!pdata->vdata->ecc_support)
751 		return;
752 
753 	/* Clear all the interrupts which are set */
754 	ecc_isr = XP_IOREAD(pdata, XP_ECC_ISR);
755 	XP_IOWRITE(pdata, XP_ECC_ISR, ecc_isr);
756 
757 	/* Enable ECC interrupts */
758 	XP_SET_BITS(ecc_ier, XP_ECC_IER, TX_DED, 1);
759 	XP_SET_BITS(ecc_ier, XP_ECC_IER, TX_SEC, 1);
760 	XP_SET_BITS(ecc_ier, XP_ECC_IER, RX_DED, 1);
761 	XP_SET_BITS(ecc_ier, XP_ECC_IER, RX_SEC, 1);
762 	XP_SET_BITS(ecc_ier, XP_ECC_IER, DESC_DED, 1);
763 	XP_SET_BITS(ecc_ier, XP_ECC_IER, DESC_SEC, 1);
764 
765 	XP_IOWRITE(pdata, XP_ECC_IER, ecc_ier);
766 }
767 
768 static void xgbe_disable_ecc_ded(struct xgbe_prv_data *pdata)
769 {
770 	unsigned int ecc_ier;
771 
772 	ecc_ier = XP_IOREAD(pdata, XP_ECC_IER);
773 
774 	/* Disable ECC DED interrupts */
775 	XP_SET_BITS(ecc_ier, XP_ECC_IER, TX_DED, 0);
776 	XP_SET_BITS(ecc_ier, XP_ECC_IER, RX_DED, 0);
777 	XP_SET_BITS(ecc_ier, XP_ECC_IER, DESC_DED, 0);
778 
779 	XP_IOWRITE(pdata, XP_ECC_IER, ecc_ier);
780 }
781 
782 static void xgbe_disable_ecc_sec(struct xgbe_prv_data *pdata,
783 				 enum xgbe_ecc_sec sec)
784 {
785 	unsigned int ecc_ier;
786 
787 	ecc_ier = XP_IOREAD(pdata, XP_ECC_IER);
788 
789 	/* Disable ECC SEC interrupt */
790 	switch (sec) {
791 	case XGBE_ECC_SEC_TX:
792 	XP_SET_BITS(ecc_ier, XP_ECC_IER, TX_SEC, 0);
793 		break;
794 	case XGBE_ECC_SEC_RX:
795 	XP_SET_BITS(ecc_ier, XP_ECC_IER, RX_SEC, 0);
796 		break;
797 	case XGBE_ECC_SEC_DESC:
798 	XP_SET_BITS(ecc_ier, XP_ECC_IER, DESC_SEC, 0);
799 		break;
800 	}
801 
802 	XP_IOWRITE(pdata, XP_ECC_IER, ecc_ier);
803 }
804 
805 static int xgbe_set_speed(struct xgbe_prv_data *pdata, int speed)
806 {
807 	unsigned int ss;
808 
809 	switch (speed) {
810 	case SPEED_1000:
811 		ss = 0x03;
812 		break;
813 	case SPEED_2500:
814 		ss = 0x02;
815 		break;
816 	case SPEED_10000:
817 		ss = 0x00;
818 		break;
819 	default:
820 		return -EINVAL;
821 	}
822 
823 	if (XGMAC_IOREAD_BITS(pdata, MAC_TCR, SS) != ss)
824 		XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, ss);
825 
826 	return 0;
827 }
828 
829 static int xgbe_enable_rx_vlan_stripping(struct xgbe_prv_data *pdata)
830 {
831 	/* Put the VLAN tag in the Rx descriptor */
832 	XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLRXS, 1);
833 
834 	/* Don't check the VLAN type */
835 	XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, DOVLTC, 1);
836 
837 	/* Check only C-TAG (0x8100) packets */
838 	XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ERSVLM, 0);
839 
840 	/* Don't consider an S-TAG (0x88A8) packet as a VLAN packet */
841 	XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ESVL, 0);
842 
843 	/* Enable VLAN tag stripping */
844 	XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0x3);
845 
846 	return 0;
847 }
848 
849 static int xgbe_disable_rx_vlan_stripping(struct xgbe_prv_data *pdata)
850 {
851 	XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0);
852 
853 	return 0;
854 }
855 
856 static int xgbe_enable_rx_vlan_filtering(struct xgbe_prv_data *pdata)
857 {
858 	/* Enable VLAN filtering */
859 	XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 1);
860 
861 	/* Enable VLAN Hash Table filtering */
862 	XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTHM, 1);
863 
864 	/* Disable VLAN tag inverse matching */
865 	XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTIM, 0);
866 
867 	/* Only filter on the lower 12-bits of the VLAN tag */
868 	XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ETV, 1);
869 
870 	/* In order for the VLAN Hash Table filtering to be effective,
871 	 * the VLAN tag identifier in the VLAN Tag Register must not
872 	 * be zero.  Set the VLAN tag identifier to "1" to enable the
873 	 * VLAN Hash Table filtering.  This implies that a VLAN tag of
874 	 * 1 will always pass filtering.
875 	 */
876 	XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VL, 1);
877 
878 	return 0;
879 }
880 
881 static int xgbe_disable_rx_vlan_filtering(struct xgbe_prv_data *pdata)
882 {
883 	/* Disable VLAN filtering */
884 	XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 0);
885 
886 	return 0;
887 }
888 
889 static u32 xgbe_vid_crc32_le(__le16 vid_le)
890 {
891 	u32 crc = ~0;
892 	u32 temp = 0;
893 	unsigned char *data = (unsigned char *)&vid_le;
894 	unsigned char data_byte = 0;
895 	int i, bits;
896 
897 	bits = get_bitmask_order(VLAN_VID_MASK);
898 	for (i = 0; i < bits; i++) {
899 		if ((i % 8) == 0)
900 			data_byte = data[i / 8];
901 
902 		temp = ((crc & 1) ^ data_byte) & 1;
903 		crc >>= 1;
904 		data_byte >>= 1;
905 
906 		if (temp)
907 			crc ^= CRC32_POLY_LE;
908 	}
909 
910 	return crc;
911 }
912 
913 static int xgbe_update_vlan_hash_table(struct xgbe_prv_data *pdata)
914 {
915 	u32 crc;
916 	u16 vid;
917 	__le16 vid_le;
918 	u16 vlan_hash_table = 0;
919 
920 	/* Generate the VLAN Hash Table value */
921 	for_each_set_bit(vid, pdata->active_vlans, VLAN_N_VID) {
922 		/* Get the CRC32 value of the VLAN ID */
923 		vid_le = cpu_to_le16(vid);
924 		crc = bitrev32(~xgbe_vid_crc32_le(vid_le)) >> 28;
925 
926 		vlan_hash_table |= (1 << crc);
927 	}
928 
929 	/* Set the VLAN Hash Table filtering register */
930 	XGMAC_IOWRITE_BITS(pdata, MAC_VLANHTR, VLHT, vlan_hash_table);
931 
932 	return 0;
933 }
934 
935 static int xgbe_set_promiscuous_mode(struct xgbe_prv_data *pdata,
936 				     unsigned int enable)
937 {
938 	unsigned int val = enable ? 1 : 0;
939 
940 	if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PR) == val)
941 		return 0;
942 
943 	netif_dbg(pdata, drv, pdata->netdev, "%s promiscuous mode\n",
944 		  enable ? "entering" : "leaving");
945 	XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, val);
946 
947 	/* Hardware will still perform VLAN filtering in promiscuous mode */
948 	if (enable) {
949 		xgbe_disable_rx_vlan_filtering(pdata);
950 	} else {
951 		if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER)
952 			xgbe_enable_rx_vlan_filtering(pdata);
953 	}
954 
955 	return 0;
956 }
957 
958 static int xgbe_set_all_multicast_mode(struct xgbe_prv_data *pdata,
959 				       unsigned int enable)
960 {
961 	unsigned int val = enable ? 1 : 0;
962 
963 	if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PM) == val)
964 		return 0;
965 
966 	netif_dbg(pdata, drv, pdata->netdev, "%s allmulti mode\n",
967 		  enable ? "entering" : "leaving");
968 	XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, val);
969 
970 	return 0;
971 }
972 
973 static void xgbe_set_mac_reg(struct xgbe_prv_data *pdata,
974 			     struct netdev_hw_addr *ha, unsigned int *mac_reg)
975 {
976 	unsigned int mac_addr_hi, mac_addr_lo;
977 	u8 *mac_addr;
978 
979 	mac_addr_lo = 0;
980 	mac_addr_hi = 0;
981 
982 	if (ha) {
983 		mac_addr = (u8 *)&mac_addr_lo;
984 		mac_addr[0] = ha->addr[0];
985 		mac_addr[1] = ha->addr[1];
986 		mac_addr[2] = ha->addr[2];
987 		mac_addr[3] = ha->addr[3];
988 		mac_addr = (u8 *)&mac_addr_hi;
989 		mac_addr[0] = ha->addr[4];
990 		mac_addr[1] = ha->addr[5];
991 
992 		netif_dbg(pdata, drv, pdata->netdev,
993 			  "adding mac address %pM at %#x\n",
994 			  ha->addr, *mac_reg);
995 
996 		XGMAC_SET_BITS(mac_addr_hi, MAC_MACA1HR, AE, 1);
997 	}
998 
999 	XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_hi);
1000 	*mac_reg += MAC_MACA_INC;
1001 	XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_lo);
1002 	*mac_reg += MAC_MACA_INC;
1003 }
1004 
1005 static void xgbe_set_mac_addn_addrs(struct xgbe_prv_data *pdata)
1006 {
1007 	struct net_device *netdev = pdata->netdev;
1008 	struct netdev_hw_addr *ha;
1009 	unsigned int mac_reg;
1010 	unsigned int addn_macs;
1011 
1012 	mac_reg = MAC_MACA1HR;
1013 	addn_macs = pdata->hw_feat.addn_mac;
1014 
1015 	if (netdev_uc_count(netdev) > addn_macs) {
1016 		xgbe_set_promiscuous_mode(pdata, 1);
1017 	} else {
1018 		netdev_for_each_uc_addr(ha, netdev) {
1019 			xgbe_set_mac_reg(pdata, ha, &mac_reg);
1020 			addn_macs--;
1021 		}
1022 
1023 		if (netdev_mc_count(netdev) > addn_macs) {
1024 			xgbe_set_all_multicast_mode(pdata, 1);
1025 		} else {
1026 			netdev_for_each_mc_addr(ha, netdev) {
1027 				xgbe_set_mac_reg(pdata, ha, &mac_reg);
1028 				addn_macs--;
1029 			}
1030 		}
1031 	}
1032 
1033 	/* Clear remaining additional MAC address entries */
1034 	while (addn_macs--)
1035 		xgbe_set_mac_reg(pdata, NULL, &mac_reg);
1036 }
1037 
1038 static void xgbe_set_mac_hash_table(struct xgbe_prv_data *pdata)
1039 {
1040 	struct net_device *netdev = pdata->netdev;
1041 	struct netdev_hw_addr *ha;
1042 	unsigned int hash_reg;
1043 	unsigned int hash_table_shift, hash_table_count;
1044 	u32 hash_table[XGBE_MAC_HASH_TABLE_SIZE];
1045 	u32 crc;
1046 	unsigned int i;
1047 
1048 	hash_table_shift = 26 - (pdata->hw_feat.hash_table_size >> 7);
1049 	hash_table_count = pdata->hw_feat.hash_table_size / 32;
1050 	memset(hash_table, 0, sizeof(hash_table));
1051 
1052 	/* Build the MAC Hash Table register values */
1053 	netdev_for_each_uc_addr(ha, netdev) {
1054 		crc = bitrev32(~crc32_le(~0, ha->addr, ETH_ALEN));
1055 		crc >>= hash_table_shift;
1056 		hash_table[crc >> 5] |= (1 << (crc & 0x1f));
1057 	}
1058 
1059 	netdev_for_each_mc_addr(ha, netdev) {
1060 		crc = bitrev32(~crc32_le(~0, ha->addr, ETH_ALEN));
1061 		crc >>= hash_table_shift;
1062 		hash_table[crc >> 5] |= (1 << (crc & 0x1f));
1063 	}
1064 
1065 	/* Set the MAC Hash Table registers */
1066 	hash_reg = MAC_HTR0;
1067 	for (i = 0; i < hash_table_count; i++) {
1068 		XGMAC_IOWRITE(pdata, hash_reg, hash_table[i]);
1069 		hash_reg += MAC_HTR_INC;
1070 	}
1071 }
1072 
1073 static int xgbe_add_mac_addresses(struct xgbe_prv_data *pdata)
1074 {
1075 	if (pdata->hw_feat.hash_table_size)
1076 		xgbe_set_mac_hash_table(pdata);
1077 	else
1078 		xgbe_set_mac_addn_addrs(pdata);
1079 
1080 	return 0;
1081 }
1082 
1083 static int xgbe_set_mac_address(struct xgbe_prv_data *pdata, u8 *addr)
1084 {
1085 	unsigned int mac_addr_hi, mac_addr_lo;
1086 
1087 	mac_addr_hi = (addr[5] <<  8) | (addr[4] <<  0);
1088 	mac_addr_lo = (addr[3] << 24) | (addr[2] << 16) |
1089 		      (addr[1] <<  8) | (addr[0] <<  0);
1090 
1091 	XGMAC_IOWRITE(pdata, MAC_MACA0HR, mac_addr_hi);
1092 	XGMAC_IOWRITE(pdata, MAC_MACA0LR, mac_addr_lo);
1093 
1094 	return 0;
1095 }
1096 
1097 static int xgbe_config_rx_mode(struct xgbe_prv_data *pdata)
1098 {
1099 	struct net_device *netdev = pdata->netdev;
1100 	unsigned int pr_mode, am_mode;
1101 
1102 	pr_mode = ((netdev->flags & IFF_PROMISC) != 0);
1103 	am_mode = ((netdev->flags & IFF_ALLMULTI) != 0);
1104 
1105 	xgbe_set_promiscuous_mode(pdata, pr_mode);
1106 	xgbe_set_all_multicast_mode(pdata, am_mode);
1107 
1108 	xgbe_add_mac_addresses(pdata);
1109 
1110 	return 0;
1111 }
1112 
1113 static int xgbe_clr_gpio(struct xgbe_prv_data *pdata, unsigned int gpio)
1114 {
1115 	unsigned int reg;
1116 
1117 	if (gpio > 15)
1118 		return -EINVAL;
1119 
1120 	reg = XGMAC_IOREAD(pdata, MAC_GPIOSR);
1121 
1122 	reg &= ~(1 << (gpio + 16));
1123 	XGMAC_IOWRITE(pdata, MAC_GPIOSR, reg);
1124 
1125 	return 0;
1126 }
1127 
1128 static int xgbe_set_gpio(struct xgbe_prv_data *pdata, unsigned int gpio)
1129 {
1130 	unsigned int reg;
1131 
1132 	if (gpio > 15)
1133 		return -EINVAL;
1134 
1135 	reg = XGMAC_IOREAD(pdata, MAC_GPIOSR);
1136 
1137 	reg |= (1 << (gpio + 16));
1138 	XGMAC_IOWRITE(pdata, MAC_GPIOSR, reg);
1139 
1140 	return 0;
1141 }
1142 
1143 static int xgbe_read_mmd_regs_v2(struct xgbe_prv_data *pdata, int prtad,
1144 				 int mmd_reg)
1145 {
1146 	unsigned long flags;
1147 	unsigned int mmd_address, index, offset;
1148 	int mmd_data;
1149 
1150 	if (mmd_reg & MII_ADDR_C45)
1151 		mmd_address = mmd_reg & ~MII_ADDR_C45;
1152 	else
1153 		mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff);
1154 
1155 	/* The PCS registers are accessed using mmio. The underlying
1156 	 * management interface uses indirect addressing to access the MMD
1157 	 * register sets. This requires accessing of the PCS register in two
1158 	 * phases, an address phase and a data phase.
1159 	 *
1160 	 * The mmio interface is based on 16-bit offsets and values. All
1161 	 * register offsets must therefore be adjusted by left shifting the
1162 	 * offset 1 bit and reading 16 bits of data.
1163 	 */
1164 	mmd_address <<= 1;
1165 	index = mmd_address & ~pdata->xpcs_window_mask;
1166 	offset = pdata->xpcs_window + (mmd_address & pdata->xpcs_window_mask);
1167 
1168 	spin_lock_irqsave(&pdata->xpcs_lock, flags);
1169 	XPCS32_IOWRITE(pdata, pdata->xpcs_window_sel_reg, index);
1170 	mmd_data = XPCS16_IOREAD(pdata, offset);
1171 	spin_unlock_irqrestore(&pdata->xpcs_lock, flags);
1172 
1173 	return mmd_data;
1174 }
1175 
1176 static void xgbe_write_mmd_regs_v2(struct xgbe_prv_data *pdata, int prtad,
1177 				   int mmd_reg, int mmd_data)
1178 {
1179 	unsigned long flags;
1180 	unsigned int mmd_address, index, offset;
1181 
1182 	if (mmd_reg & MII_ADDR_C45)
1183 		mmd_address = mmd_reg & ~MII_ADDR_C45;
1184 	else
1185 		mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff);
1186 
1187 	/* The PCS registers are accessed using mmio. The underlying
1188 	 * management interface uses indirect addressing to access the MMD
1189 	 * register sets. This requires accessing of the PCS register in two
1190 	 * phases, an address phase and a data phase.
1191 	 *
1192 	 * The mmio interface is based on 16-bit offsets and values. All
1193 	 * register offsets must therefore be adjusted by left shifting the
1194 	 * offset 1 bit and writing 16 bits of data.
1195 	 */
1196 	mmd_address <<= 1;
1197 	index = mmd_address & ~pdata->xpcs_window_mask;
1198 	offset = pdata->xpcs_window + (mmd_address & pdata->xpcs_window_mask);
1199 
1200 	spin_lock_irqsave(&pdata->xpcs_lock, flags);
1201 	XPCS32_IOWRITE(pdata, pdata->xpcs_window_sel_reg, index);
1202 	XPCS16_IOWRITE(pdata, offset, mmd_data);
1203 	spin_unlock_irqrestore(&pdata->xpcs_lock, flags);
1204 }
1205 
1206 static int xgbe_read_mmd_regs_v1(struct xgbe_prv_data *pdata, int prtad,
1207 				 int mmd_reg)
1208 {
1209 	unsigned long flags;
1210 	unsigned int mmd_address;
1211 	int mmd_data;
1212 
1213 	if (mmd_reg & MII_ADDR_C45)
1214 		mmd_address = mmd_reg & ~MII_ADDR_C45;
1215 	else
1216 		mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff);
1217 
1218 	/* The PCS registers are accessed using mmio. The underlying APB3
1219 	 * management interface uses indirect addressing to access the MMD
1220 	 * register sets. This requires accessing of the PCS register in two
1221 	 * phases, an address phase and a data phase.
1222 	 *
1223 	 * The mmio interface is based on 32-bit offsets and values. All
1224 	 * register offsets must therefore be adjusted by left shifting the
1225 	 * offset 2 bits and reading 32 bits of data.
1226 	 */
1227 	spin_lock_irqsave(&pdata->xpcs_lock, flags);
1228 	XPCS32_IOWRITE(pdata, PCS_V1_WINDOW_SELECT, mmd_address >> 8);
1229 	mmd_data = XPCS32_IOREAD(pdata, (mmd_address & 0xff) << 2);
1230 	spin_unlock_irqrestore(&pdata->xpcs_lock, flags);
1231 
1232 	return mmd_data;
1233 }
1234 
1235 static void xgbe_write_mmd_regs_v1(struct xgbe_prv_data *pdata, int prtad,
1236 				   int mmd_reg, int mmd_data)
1237 {
1238 	unsigned int mmd_address;
1239 	unsigned long flags;
1240 
1241 	if (mmd_reg & MII_ADDR_C45)
1242 		mmd_address = mmd_reg & ~MII_ADDR_C45;
1243 	else
1244 		mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff);
1245 
1246 	/* The PCS registers are accessed using mmio. The underlying APB3
1247 	 * management interface uses indirect addressing to access the MMD
1248 	 * register sets. This requires accessing of the PCS register in two
1249 	 * phases, an address phase and a data phase.
1250 	 *
1251 	 * The mmio interface is based on 32-bit offsets and values. All
1252 	 * register offsets must therefore be adjusted by left shifting the
1253 	 * offset 2 bits and writing 32 bits of data.
1254 	 */
1255 	spin_lock_irqsave(&pdata->xpcs_lock, flags);
1256 	XPCS32_IOWRITE(pdata, PCS_V1_WINDOW_SELECT, mmd_address >> 8);
1257 	XPCS32_IOWRITE(pdata, (mmd_address & 0xff) << 2, mmd_data);
1258 	spin_unlock_irqrestore(&pdata->xpcs_lock, flags);
1259 }
1260 
1261 static int xgbe_read_mmd_regs(struct xgbe_prv_data *pdata, int prtad,
1262 			      int mmd_reg)
1263 {
1264 	switch (pdata->vdata->xpcs_access) {
1265 	case XGBE_XPCS_ACCESS_V1:
1266 		return xgbe_read_mmd_regs_v1(pdata, prtad, mmd_reg);
1267 
1268 	case XGBE_XPCS_ACCESS_V2:
1269 	default:
1270 		return xgbe_read_mmd_regs_v2(pdata, prtad, mmd_reg);
1271 	}
1272 }
1273 
1274 static void xgbe_write_mmd_regs(struct xgbe_prv_data *pdata, int prtad,
1275 				int mmd_reg, int mmd_data)
1276 {
1277 	switch (pdata->vdata->xpcs_access) {
1278 	case XGBE_XPCS_ACCESS_V1:
1279 		return xgbe_write_mmd_regs_v1(pdata, prtad, mmd_reg, mmd_data);
1280 
1281 	case XGBE_XPCS_ACCESS_V2:
1282 	default:
1283 		return xgbe_write_mmd_regs_v2(pdata, prtad, mmd_reg, mmd_data);
1284 	}
1285 }
1286 
1287 static int xgbe_write_ext_mii_regs(struct xgbe_prv_data *pdata, int addr,
1288 				   int reg, u16 val)
1289 {
1290 	unsigned int mdio_sca, mdio_sccd;
1291 
1292 	reinit_completion(&pdata->mdio_complete);
1293 
1294 	mdio_sca = 0;
1295 	XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, REG, reg);
1296 	XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, DA, addr);
1297 	XGMAC_IOWRITE(pdata, MAC_MDIOSCAR, mdio_sca);
1298 
1299 	mdio_sccd = 0;
1300 	XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, DATA, val);
1301 	XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, CMD, 1);
1302 	XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, BUSY, 1);
1303 	XGMAC_IOWRITE(pdata, MAC_MDIOSCCDR, mdio_sccd);
1304 
1305 	if (!wait_for_completion_timeout(&pdata->mdio_complete, HZ)) {
1306 		netdev_err(pdata->netdev, "mdio write operation timed out\n");
1307 		return -ETIMEDOUT;
1308 	}
1309 
1310 	return 0;
1311 }
1312 
1313 static int xgbe_read_ext_mii_regs(struct xgbe_prv_data *pdata, int addr,
1314 				  int reg)
1315 {
1316 	unsigned int mdio_sca, mdio_sccd;
1317 
1318 	reinit_completion(&pdata->mdio_complete);
1319 
1320 	mdio_sca = 0;
1321 	XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, REG, reg);
1322 	XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, DA, addr);
1323 	XGMAC_IOWRITE(pdata, MAC_MDIOSCAR, mdio_sca);
1324 
1325 	mdio_sccd = 0;
1326 	XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, CMD, 3);
1327 	XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, BUSY, 1);
1328 	XGMAC_IOWRITE(pdata, MAC_MDIOSCCDR, mdio_sccd);
1329 
1330 	if (!wait_for_completion_timeout(&pdata->mdio_complete, HZ)) {
1331 		netdev_err(pdata->netdev, "mdio read operation timed out\n");
1332 		return -ETIMEDOUT;
1333 	}
1334 
1335 	return XGMAC_IOREAD_BITS(pdata, MAC_MDIOSCCDR, DATA);
1336 }
1337 
1338 static int xgbe_set_ext_mii_mode(struct xgbe_prv_data *pdata, unsigned int port,
1339 				 enum xgbe_mdio_mode mode)
1340 {
1341 	unsigned int reg_val = XGMAC_IOREAD(pdata, MAC_MDIOCL22R);
1342 
1343 	switch (mode) {
1344 	case XGBE_MDIO_MODE_CL22:
1345 		if (port > XGMAC_MAX_C22_PORT)
1346 			return -EINVAL;
1347 		reg_val |= (1 << port);
1348 		break;
1349 	case XGBE_MDIO_MODE_CL45:
1350 		break;
1351 	default:
1352 		return -EINVAL;
1353 	}
1354 
1355 	XGMAC_IOWRITE(pdata, MAC_MDIOCL22R, reg_val);
1356 
1357 	return 0;
1358 }
1359 
1360 static int xgbe_tx_complete(struct xgbe_ring_desc *rdesc)
1361 {
1362 	return !XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN);
1363 }
1364 
1365 static int xgbe_disable_rx_csum(struct xgbe_prv_data *pdata)
1366 {
1367 	XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 0);
1368 
1369 	return 0;
1370 }
1371 
1372 static int xgbe_enable_rx_csum(struct xgbe_prv_data *pdata)
1373 {
1374 	XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 1);
1375 
1376 	return 0;
1377 }
1378 
1379 static void xgbe_tx_desc_reset(struct xgbe_ring_data *rdata)
1380 {
1381 	struct xgbe_ring_desc *rdesc = rdata->rdesc;
1382 
1383 	/* Reset the Tx descriptor
1384 	 *   Set buffer 1 (lo) address to zero
1385 	 *   Set buffer 1 (hi) address to zero
1386 	 *   Reset all other control bits (IC, TTSE, B2L & B1L)
1387 	 *   Reset all other control bits (OWN, CTXT, FD, LD, CPC, CIC, etc)
1388 	 */
1389 	rdesc->desc0 = 0;
1390 	rdesc->desc1 = 0;
1391 	rdesc->desc2 = 0;
1392 	rdesc->desc3 = 0;
1393 
1394 	/* Make sure ownership is written to the descriptor */
1395 	dma_wmb();
1396 }
1397 
1398 static void xgbe_tx_desc_init(struct xgbe_channel *channel)
1399 {
1400 	struct xgbe_ring *ring = channel->tx_ring;
1401 	struct xgbe_ring_data *rdata;
1402 	int i;
1403 	int start_index = ring->cur;
1404 
1405 	DBGPR("-->tx_desc_init\n");
1406 
1407 	/* Initialze all descriptors */
1408 	for (i = 0; i < ring->rdesc_count; i++) {
1409 		rdata = XGBE_GET_DESC_DATA(ring, i);
1410 
1411 		/* Initialize Tx descriptor */
1412 		xgbe_tx_desc_reset(rdata);
1413 	}
1414 
1415 	/* Update the total number of Tx descriptors */
1416 	XGMAC_DMA_IOWRITE(channel, DMA_CH_TDRLR, ring->rdesc_count - 1);
1417 
1418 	/* Update the starting address of descriptor ring */
1419 	rdata = XGBE_GET_DESC_DATA(ring, start_index);
1420 	XGMAC_DMA_IOWRITE(channel, DMA_CH_TDLR_HI,
1421 			  upper_32_bits(rdata->rdesc_dma));
1422 	XGMAC_DMA_IOWRITE(channel, DMA_CH_TDLR_LO,
1423 			  lower_32_bits(rdata->rdesc_dma));
1424 
1425 	DBGPR("<--tx_desc_init\n");
1426 }
1427 
1428 static void xgbe_rx_desc_reset(struct xgbe_prv_data *pdata,
1429 			       struct xgbe_ring_data *rdata, unsigned int index)
1430 {
1431 	struct xgbe_ring_desc *rdesc = rdata->rdesc;
1432 	unsigned int rx_usecs = pdata->rx_usecs;
1433 	unsigned int rx_frames = pdata->rx_frames;
1434 	unsigned int inte;
1435 	dma_addr_t hdr_dma, buf_dma;
1436 
1437 	if (!rx_usecs && !rx_frames) {
1438 		/* No coalescing, interrupt for every descriptor */
1439 		inte = 1;
1440 	} else {
1441 		/* Set interrupt based on Rx frame coalescing setting */
1442 		if (rx_frames && !((index + 1) % rx_frames))
1443 			inte = 1;
1444 		else
1445 			inte = 0;
1446 	}
1447 
1448 	/* Reset the Rx descriptor
1449 	 *   Set buffer 1 (lo) address to header dma address (lo)
1450 	 *   Set buffer 1 (hi) address to header dma address (hi)
1451 	 *   Set buffer 2 (lo) address to buffer dma address (lo)
1452 	 *   Set buffer 2 (hi) address to buffer dma address (hi) and
1453 	 *     set control bits OWN and INTE
1454 	 */
1455 	hdr_dma = rdata->rx.hdr.dma_base + rdata->rx.hdr.dma_off;
1456 	buf_dma = rdata->rx.buf.dma_base + rdata->rx.buf.dma_off;
1457 	rdesc->desc0 = cpu_to_le32(lower_32_bits(hdr_dma));
1458 	rdesc->desc1 = cpu_to_le32(upper_32_bits(hdr_dma));
1459 	rdesc->desc2 = cpu_to_le32(lower_32_bits(buf_dma));
1460 	rdesc->desc3 = cpu_to_le32(upper_32_bits(buf_dma));
1461 
1462 	XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, INTE, inte);
1463 
1464 	/* Since the Rx DMA engine is likely running, make sure everything
1465 	 * is written to the descriptor(s) before setting the OWN bit
1466 	 * for the descriptor
1467 	 */
1468 	dma_wmb();
1469 
1470 	XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN, 1);
1471 
1472 	/* Make sure ownership is written to the descriptor */
1473 	dma_wmb();
1474 }
1475 
1476 static void xgbe_rx_desc_init(struct xgbe_channel *channel)
1477 {
1478 	struct xgbe_prv_data *pdata = channel->pdata;
1479 	struct xgbe_ring *ring = channel->rx_ring;
1480 	struct xgbe_ring_data *rdata;
1481 	unsigned int start_index = ring->cur;
1482 	unsigned int i;
1483 
1484 	DBGPR("-->rx_desc_init\n");
1485 
1486 	/* Initialize all descriptors */
1487 	for (i = 0; i < ring->rdesc_count; i++) {
1488 		rdata = XGBE_GET_DESC_DATA(ring, i);
1489 
1490 		/* Initialize Rx descriptor */
1491 		xgbe_rx_desc_reset(pdata, rdata, i);
1492 	}
1493 
1494 	/* Update the total number of Rx descriptors */
1495 	XGMAC_DMA_IOWRITE(channel, DMA_CH_RDRLR, ring->rdesc_count - 1);
1496 
1497 	/* Update the starting address of descriptor ring */
1498 	rdata = XGBE_GET_DESC_DATA(ring, start_index);
1499 	XGMAC_DMA_IOWRITE(channel, DMA_CH_RDLR_HI,
1500 			  upper_32_bits(rdata->rdesc_dma));
1501 	XGMAC_DMA_IOWRITE(channel, DMA_CH_RDLR_LO,
1502 			  lower_32_bits(rdata->rdesc_dma));
1503 
1504 	/* Update the Rx Descriptor Tail Pointer */
1505 	rdata = XGBE_GET_DESC_DATA(ring, start_index + ring->rdesc_count - 1);
1506 	XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO,
1507 			  lower_32_bits(rdata->rdesc_dma));
1508 
1509 	DBGPR("<--rx_desc_init\n");
1510 }
1511 
1512 static void xgbe_update_tstamp_addend(struct xgbe_prv_data *pdata,
1513 				      unsigned int addend)
1514 {
1515 	unsigned int count = 10000;
1516 
1517 	/* Set the addend register value and tell the device */
1518 	XGMAC_IOWRITE(pdata, MAC_TSAR, addend);
1519 	XGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSADDREG, 1);
1520 
1521 	/* Wait for addend update to complete */
1522 	while (--count && XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSADDREG))
1523 		udelay(5);
1524 
1525 	if (!count)
1526 		netdev_err(pdata->netdev,
1527 			   "timed out updating timestamp addend register\n");
1528 }
1529 
1530 static void xgbe_set_tstamp_time(struct xgbe_prv_data *pdata, unsigned int sec,
1531 				 unsigned int nsec)
1532 {
1533 	unsigned int count = 10000;
1534 
1535 	/* Set the time values and tell the device */
1536 	XGMAC_IOWRITE(pdata, MAC_STSUR, sec);
1537 	XGMAC_IOWRITE(pdata, MAC_STNUR, nsec);
1538 	XGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSINIT, 1);
1539 
1540 	/* Wait for time update to complete */
1541 	while (--count && XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSINIT))
1542 		udelay(5);
1543 
1544 	if (!count)
1545 		netdev_err(pdata->netdev, "timed out initializing timestamp\n");
1546 }
1547 
1548 static u64 xgbe_get_tstamp_time(struct xgbe_prv_data *pdata)
1549 {
1550 	u64 nsec;
1551 
1552 	nsec = XGMAC_IOREAD(pdata, MAC_STSR);
1553 	nsec *= NSEC_PER_SEC;
1554 	nsec += XGMAC_IOREAD(pdata, MAC_STNR);
1555 
1556 	return nsec;
1557 }
1558 
1559 static u64 xgbe_get_tx_tstamp(struct xgbe_prv_data *pdata)
1560 {
1561 	unsigned int tx_snr, tx_ssr;
1562 	u64 nsec;
1563 
1564 	if (pdata->vdata->tx_tstamp_workaround) {
1565 		tx_snr = XGMAC_IOREAD(pdata, MAC_TXSNR);
1566 		tx_ssr = XGMAC_IOREAD(pdata, MAC_TXSSR);
1567 	} else {
1568 		tx_ssr = XGMAC_IOREAD(pdata, MAC_TXSSR);
1569 		tx_snr = XGMAC_IOREAD(pdata, MAC_TXSNR);
1570 	}
1571 
1572 	if (XGMAC_GET_BITS(tx_snr, MAC_TXSNR, TXTSSTSMIS))
1573 		return 0;
1574 
1575 	nsec = tx_ssr;
1576 	nsec *= NSEC_PER_SEC;
1577 	nsec += tx_snr;
1578 
1579 	return nsec;
1580 }
1581 
1582 static void xgbe_get_rx_tstamp(struct xgbe_packet_data *packet,
1583 			       struct xgbe_ring_desc *rdesc)
1584 {
1585 	u64 nsec;
1586 
1587 	if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_CONTEXT_DESC3, TSA) &&
1588 	    !XGMAC_GET_BITS_LE(rdesc->desc3, RX_CONTEXT_DESC3, TSD)) {
1589 		nsec = le32_to_cpu(rdesc->desc1);
1590 		nsec <<= 32;
1591 		nsec |= le32_to_cpu(rdesc->desc0);
1592 		if (nsec != 0xffffffffffffffffULL) {
1593 			packet->rx_tstamp = nsec;
1594 			XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1595 				       RX_TSTAMP, 1);
1596 		}
1597 	}
1598 }
1599 
1600 static int xgbe_config_tstamp(struct xgbe_prv_data *pdata,
1601 			      unsigned int mac_tscr)
1602 {
1603 	/* Set one nano-second accuracy */
1604 	XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCTRLSSR, 1);
1605 
1606 	/* Set fine timestamp update */
1607 	XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCFUPDT, 1);
1608 
1609 	/* Overwrite earlier timestamps */
1610 	XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TXTSSTSM, 1);
1611 
1612 	XGMAC_IOWRITE(pdata, MAC_TSCR, mac_tscr);
1613 
1614 	/* Exit if timestamping is not enabled */
1615 	if (!XGMAC_GET_BITS(mac_tscr, MAC_TSCR, TSENA))
1616 		return 0;
1617 
1618 	/* Initialize time registers */
1619 	XGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SSINC, XGBE_TSTAMP_SSINC);
1620 	XGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SNSINC, XGBE_TSTAMP_SNSINC);
1621 	xgbe_update_tstamp_addend(pdata, pdata->tstamp_addend);
1622 	xgbe_set_tstamp_time(pdata, 0, 0);
1623 
1624 	/* Initialize the timecounter */
1625 	timecounter_init(&pdata->tstamp_tc, &pdata->tstamp_cc,
1626 			 ktime_to_ns(ktime_get_real()));
1627 
1628 	return 0;
1629 }
1630 
1631 static void xgbe_tx_start_xmit(struct xgbe_channel *channel,
1632 			       struct xgbe_ring *ring)
1633 {
1634 	struct xgbe_prv_data *pdata = channel->pdata;
1635 	struct xgbe_ring_data *rdata;
1636 
1637 	/* Make sure everything is written before the register write */
1638 	wmb();
1639 
1640 	/* Issue a poll command to Tx DMA by writing address
1641 	 * of next immediate free descriptor */
1642 	rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
1643 	XGMAC_DMA_IOWRITE(channel, DMA_CH_TDTR_LO,
1644 			  lower_32_bits(rdata->rdesc_dma));
1645 
1646 	/* Start the Tx timer */
1647 	if (pdata->tx_usecs && !channel->tx_timer_active) {
1648 		channel->tx_timer_active = 1;
1649 		mod_timer(&channel->tx_timer,
1650 			  jiffies + usecs_to_jiffies(pdata->tx_usecs));
1651 	}
1652 
1653 	ring->tx.xmit_more = 0;
1654 }
1655 
1656 static void xgbe_dev_xmit(struct xgbe_channel *channel)
1657 {
1658 	struct xgbe_prv_data *pdata = channel->pdata;
1659 	struct xgbe_ring *ring = channel->tx_ring;
1660 	struct xgbe_ring_data *rdata;
1661 	struct xgbe_ring_desc *rdesc;
1662 	struct xgbe_packet_data *packet = &ring->packet_data;
1663 	unsigned int tx_packets, tx_bytes;
1664 	unsigned int csum, tso, vlan, vxlan;
1665 	unsigned int tso_context, vlan_context;
1666 	unsigned int tx_set_ic;
1667 	int start_index = ring->cur;
1668 	int cur_index = ring->cur;
1669 	int i;
1670 
1671 	DBGPR("-->xgbe_dev_xmit\n");
1672 
1673 	tx_packets = packet->tx_packets;
1674 	tx_bytes = packet->tx_bytes;
1675 
1676 	csum = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1677 			      CSUM_ENABLE);
1678 	tso = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1679 			     TSO_ENABLE);
1680 	vlan = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1681 			      VLAN_CTAG);
1682 	vxlan = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1683 			       VXLAN);
1684 
1685 	if (tso && (packet->mss != ring->tx.cur_mss))
1686 		tso_context = 1;
1687 	else
1688 		tso_context = 0;
1689 
1690 	if (vlan && (packet->vlan_ctag != ring->tx.cur_vlan_ctag))
1691 		vlan_context = 1;
1692 	else
1693 		vlan_context = 0;
1694 
1695 	/* Determine if an interrupt should be generated for this Tx:
1696 	 *   Interrupt:
1697 	 *     - Tx frame count exceeds the frame count setting
1698 	 *     - Addition of Tx frame count to the frame count since the
1699 	 *       last interrupt was set exceeds the frame count setting
1700 	 *   No interrupt:
1701 	 *     - No frame count setting specified (ethtool -C ethX tx-frames 0)
1702 	 *     - Addition of Tx frame count to the frame count since the
1703 	 *       last interrupt was set does not exceed the frame count setting
1704 	 */
1705 	ring->coalesce_count += tx_packets;
1706 	if (!pdata->tx_frames)
1707 		tx_set_ic = 0;
1708 	else if (tx_packets > pdata->tx_frames)
1709 		tx_set_ic = 1;
1710 	else if ((ring->coalesce_count % pdata->tx_frames) < tx_packets)
1711 		tx_set_ic = 1;
1712 	else
1713 		tx_set_ic = 0;
1714 
1715 	rdata = XGBE_GET_DESC_DATA(ring, cur_index);
1716 	rdesc = rdata->rdesc;
1717 
1718 	/* Create a context descriptor if this is a TSO packet */
1719 	if (tso_context || vlan_context) {
1720 		if (tso_context) {
1721 			netif_dbg(pdata, tx_queued, pdata->netdev,
1722 				  "TSO context descriptor, mss=%u\n",
1723 				  packet->mss);
1724 
1725 			/* Set the MSS size */
1726 			XGMAC_SET_BITS_LE(rdesc->desc2, TX_CONTEXT_DESC2,
1727 					  MSS, packet->mss);
1728 
1729 			/* Mark it as a CONTEXT descriptor */
1730 			XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
1731 					  CTXT, 1);
1732 
1733 			/* Indicate this descriptor contains the MSS */
1734 			XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
1735 					  TCMSSV, 1);
1736 
1737 			ring->tx.cur_mss = packet->mss;
1738 		}
1739 
1740 		if (vlan_context) {
1741 			netif_dbg(pdata, tx_queued, pdata->netdev,
1742 				  "VLAN context descriptor, ctag=%u\n",
1743 				  packet->vlan_ctag);
1744 
1745 			/* Mark it as a CONTEXT descriptor */
1746 			XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
1747 					  CTXT, 1);
1748 
1749 			/* Set the VLAN tag */
1750 			XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
1751 					  VT, packet->vlan_ctag);
1752 
1753 			/* Indicate this descriptor contains the VLAN tag */
1754 			XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
1755 					  VLTV, 1);
1756 
1757 			ring->tx.cur_vlan_ctag = packet->vlan_ctag;
1758 		}
1759 
1760 		cur_index++;
1761 		rdata = XGBE_GET_DESC_DATA(ring, cur_index);
1762 		rdesc = rdata->rdesc;
1763 	}
1764 
1765 	/* Update buffer address (for TSO this is the header) */
1766 	rdesc->desc0 =  cpu_to_le32(lower_32_bits(rdata->skb_dma));
1767 	rdesc->desc1 =  cpu_to_le32(upper_32_bits(rdata->skb_dma));
1768 
1769 	/* Update the buffer length */
1770 	XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, HL_B1L,
1771 			  rdata->skb_dma_len);
1772 
1773 	/* VLAN tag insertion check */
1774 	if (vlan)
1775 		XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, VTIR,
1776 				  TX_NORMAL_DESC2_VLAN_INSERT);
1777 
1778 	/* Timestamp enablement check */
1779 	if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP))
1780 		XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, TTSE, 1);
1781 
1782 	/* Mark it as First Descriptor */
1783 	XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, FD, 1);
1784 
1785 	/* Mark it as a NORMAL descriptor */
1786 	XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT, 0);
1787 
1788 	/* Set OWN bit if not the first descriptor */
1789 	if (cur_index != start_index)
1790 		XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1);
1791 
1792 	if (tso) {
1793 		/* Enable TSO */
1794 		XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TSE, 1);
1795 		XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TCPPL,
1796 				  packet->tcp_payload_len);
1797 		XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TCPHDRLEN,
1798 				  packet->tcp_header_len / 4);
1799 
1800 		pdata->ext_stats.tx_tso_packets += tx_packets;
1801 	} else {
1802 		/* Enable CRC and Pad Insertion */
1803 		XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CPC, 0);
1804 
1805 		/* Enable HW CSUM */
1806 		if (csum)
1807 			XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3,
1808 					  CIC, 0x3);
1809 
1810 		/* Set the total length to be transmitted */
1811 		XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, FL,
1812 				  packet->length);
1813 	}
1814 
1815 	if (vxlan) {
1816 		XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, VNP,
1817 				  TX_NORMAL_DESC3_VXLAN_PACKET);
1818 
1819 		pdata->ext_stats.tx_vxlan_packets += packet->tx_packets;
1820 	}
1821 
1822 	for (i = cur_index - start_index + 1; i < packet->rdesc_count; i++) {
1823 		cur_index++;
1824 		rdata = XGBE_GET_DESC_DATA(ring, cur_index);
1825 		rdesc = rdata->rdesc;
1826 
1827 		/* Update buffer address */
1828 		rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->skb_dma));
1829 		rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->skb_dma));
1830 
1831 		/* Update the buffer length */
1832 		XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, HL_B1L,
1833 				  rdata->skb_dma_len);
1834 
1835 		/* Set OWN bit */
1836 		XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1);
1837 
1838 		/* Mark it as NORMAL descriptor */
1839 		XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT, 0);
1840 
1841 		/* Enable HW CSUM */
1842 		if (csum)
1843 			XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3,
1844 					  CIC, 0x3);
1845 	}
1846 
1847 	/* Set LAST bit for the last descriptor */
1848 	XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, LD, 1);
1849 
1850 	/* Set IC bit based on Tx coalescing settings */
1851 	if (tx_set_ic)
1852 		XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, IC, 1);
1853 
1854 	/* Save the Tx info to report back during cleanup */
1855 	rdata->tx.packets = tx_packets;
1856 	rdata->tx.bytes = tx_bytes;
1857 
1858 	pdata->ext_stats.txq_packets[channel->queue_index] += tx_packets;
1859 	pdata->ext_stats.txq_bytes[channel->queue_index] += tx_bytes;
1860 
1861 	/* In case the Tx DMA engine is running, make sure everything
1862 	 * is written to the descriptor(s) before setting the OWN bit
1863 	 * for the first descriptor
1864 	 */
1865 	dma_wmb();
1866 
1867 	/* Set OWN bit for the first descriptor */
1868 	rdata = XGBE_GET_DESC_DATA(ring, start_index);
1869 	rdesc = rdata->rdesc;
1870 	XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1);
1871 
1872 	if (netif_msg_tx_queued(pdata))
1873 		xgbe_dump_tx_desc(pdata, ring, start_index,
1874 				  packet->rdesc_count, 1);
1875 
1876 	/* Make sure ownership is written to the descriptor */
1877 	smp_wmb();
1878 
1879 	ring->cur = cur_index + 1;
1880 	if (!packet->skb->xmit_more ||
1881 	    netif_xmit_stopped(netdev_get_tx_queue(pdata->netdev,
1882 						   channel->queue_index)))
1883 		xgbe_tx_start_xmit(channel, ring);
1884 	else
1885 		ring->tx.xmit_more = 1;
1886 
1887 	DBGPR("  %s: descriptors %u to %u written\n",
1888 	      channel->name, start_index & (ring->rdesc_count - 1),
1889 	      (ring->cur - 1) & (ring->rdesc_count - 1));
1890 
1891 	DBGPR("<--xgbe_dev_xmit\n");
1892 }
1893 
1894 static int xgbe_dev_read(struct xgbe_channel *channel)
1895 {
1896 	struct xgbe_prv_data *pdata = channel->pdata;
1897 	struct xgbe_ring *ring = channel->rx_ring;
1898 	struct xgbe_ring_data *rdata;
1899 	struct xgbe_ring_desc *rdesc;
1900 	struct xgbe_packet_data *packet = &ring->packet_data;
1901 	struct net_device *netdev = pdata->netdev;
1902 	unsigned int err, etlt, l34t;
1903 
1904 	DBGPR("-->xgbe_dev_read: cur = %d\n", ring->cur);
1905 
1906 	rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
1907 	rdesc = rdata->rdesc;
1908 
1909 	/* Check for data availability */
1910 	if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN))
1911 		return 1;
1912 
1913 	/* Make sure descriptor fields are read after reading the OWN bit */
1914 	dma_rmb();
1915 
1916 	if (netif_msg_rx_status(pdata))
1917 		xgbe_dump_rx_desc(pdata, ring, ring->cur);
1918 
1919 	if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CTXT)) {
1920 		/* Timestamp Context Descriptor */
1921 		xgbe_get_rx_tstamp(packet, rdesc);
1922 
1923 		XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1924 			       CONTEXT, 1);
1925 		XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1926 			       CONTEXT_NEXT, 0);
1927 		return 0;
1928 	}
1929 
1930 	/* Normal Descriptor, be sure Context Descriptor bit is off */
1931 	XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, CONTEXT, 0);
1932 
1933 	/* Indicate if a Context Descriptor is next */
1934 	if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CDA))
1935 		XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1936 			       CONTEXT_NEXT, 1);
1937 
1938 	/* Get the header length */
1939 	if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, FD)) {
1940 		XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1941 			       FIRST, 1);
1942 		rdata->rx.hdr_len = XGMAC_GET_BITS_LE(rdesc->desc2,
1943 						      RX_NORMAL_DESC2, HL);
1944 		if (rdata->rx.hdr_len)
1945 			pdata->ext_stats.rx_split_header_packets++;
1946 	} else {
1947 		XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1948 			       FIRST, 0);
1949 	}
1950 
1951 	/* Get the RSS hash */
1952 	if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, RSV)) {
1953 		XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1954 			       RSS_HASH, 1);
1955 
1956 		packet->rss_hash = le32_to_cpu(rdesc->desc1);
1957 
1958 		l34t = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, L34T);
1959 		switch (l34t) {
1960 		case RX_DESC3_L34T_IPV4_TCP:
1961 		case RX_DESC3_L34T_IPV4_UDP:
1962 		case RX_DESC3_L34T_IPV6_TCP:
1963 		case RX_DESC3_L34T_IPV6_UDP:
1964 			packet->rss_hash_type = PKT_HASH_TYPE_L4;
1965 			break;
1966 		default:
1967 			packet->rss_hash_type = PKT_HASH_TYPE_L3;
1968 		}
1969 	}
1970 
1971 	/* Not all the data has been transferred for this packet */
1972 	if (!XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, LD))
1973 		return 0;
1974 
1975 	/* This is the last of the data for this packet */
1976 	XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1977 		       LAST, 1);
1978 
1979 	/* Get the packet length */
1980 	rdata->rx.len = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, PL);
1981 
1982 	/* Set checksum done indicator as appropriate */
1983 	if (netdev->features & NETIF_F_RXCSUM) {
1984 		XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1985 			       CSUM_DONE, 1);
1986 		XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1987 			       TNPCSUM_DONE, 1);
1988 	}
1989 
1990 	/* Set the tunneled packet indicator */
1991 	if (XGMAC_GET_BITS_LE(rdesc->desc2, RX_NORMAL_DESC2, TNP)) {
1992 		XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1993 			       TNP, 1);
1994 		pdata->ext_stats.rx_vxlan_packets++;
1995 
1996 		l34t = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, L34T);
1997 		switch (l34t) {
1998 		case RX_DESC3_L34T_IPV4_UNKNOWN:
1999 		case RX_DESC3_L34T_IPV6_UNKNOWN:
2000 			XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
2001 				       TNPCSUM_DONE, 0);
2002 			break;
2003 		}
2004 	}
2005 
2006 	/* Check for errors (only valid in last descriptor) */
2007 	err = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ES);
2008 	etlt = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ETLT);
2009 	netif_dbg(pdata, rx_status, netdev, "err=%u, etlt=%#x\n", err, etlt);
2010 
2011 	if (!err || !etlt) {
2012 		/* No error if err is 0 or etlt is 0 */
2013 		if ((etlt == 0x09) &&
2014 		    (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
2015 			XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
2016 				       VLAN_CTAG, 1);
2017 			packet->vlan_ctag = XGMAC_GET_BITS_LE(rdesc->desc0,
2018 							      RX_NORMAL_DESC0,
2019 							      OVT);
2020 			netif_dbg(pdata, rx_status, netdev, "vlan-ctag=%#06x\n",
2021 				  packet->vlan_ctag);
2022 		}
2023 	} else {
2024 		unsigned int tnp = XGMAC_GET_BITS(packet->attributes,
2025 						  RX_PACKET_ATTRIBUTES, TNP);
2026 
2027 		if ((etlt == 0x05) || (etlt == 0x06)) {
2028 			XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
2029 				       CSUM_DONE, 0);
2030 			XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
2031 				       TNPCSUM_DONE, 0);
2032 			pdata->ext_stats.rx_csum_errors++;
2033 		} else if (tnp && ((etlt == 0x09) || (etlt == 0x0a))) {
2034 			XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
2035 				       CSUM_DONE, 0);
2036 			XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
2037 				       TNPCSUM_DONE, 0);
2038 			pdata->ext_stats.rx_vxlan_csum_errors++;
2039 		} else {
2040 			XGMAC_SET_BITS(packet->errors, RX_PACKET_ERRORS,
2041 				       FRAME, 1);
2042 		}
2043 	}
2044 
2045 	pdata->ext_stats.rxq_packets[channel->queue_index]++;
2046 	pdata->ext_stats.rxq_bytes[channel->queue_index] += rdata->rx.len;
2047 
2048 	DBGPR("<--xgbe_dev_read: %s - descriptor=%u (cur=%d)\n", channel->name,
2049 	      ring->cur & (ring->rdesc_count - 1), ring->cur);
2050 
2051 	return 0;
2052 }
2053 
2054 static int xgbe_is_context_desc(struct xgbe_ring_desc *rdesc)
2055 {
2056 	/* Rx and Tx share CTXT bit, so check TDES3.CTXT bit */
2057 	return XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT);
2058 }
2059 
2060 static int xgbe_is_last_desc(struct xgbe_ring_desc *rdesc)
2061 {
2062 	/* Rx and Tx share LD bit, so check TDES3.LD bit */
2063 	return XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, LD);
2064 }
2065 
2066 static int xgbe_enable_int(struct xgbe_channel *channel,
2067 			   enum xgbe_int int_id)
2068 {
2069 	switch (int_id) {
2070 	case XGMAC_INT_DMA_CH_SR_TI:
2071 		XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TIE, 1);
2072 		break;
2073 	case XGMAC_INT_DMA_CH_SR_TPS:
2074 		XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TXSE, 1);
2075 		break;
2076 	case XGMAC_INT_DMA_CH_SR_TBU:
2077 		XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TBUE, 1);
2078 		break;
2079 	case XGMAC_INT_DMA_CH_SR_RI:
2080 		XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RIE, 1);
2081 		break;
2082 	case XGMAC_INT_DMA_CH_SR_RBU:
2083 		XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RBUE, 1);
2084 		break;
2085 	case XGMAC_INT_DMA_CH_SR_RPS:
2086 		XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RSE, 1);
2087 		break;
2088 	case XGMAC_INT_DMA_CH_SR_TI_RI:
2089 		XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TIE, 1);
2090 		XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RIE, 1);
2091 		break;
2092 	case XGMAC_INT_DMA_CH_SR_FBE:
2093 		XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, FBEE, 1);
2094 		break;
2095 	case XGMAC_INT_DMA_ALL:
2096 		channel->curr_ier |= channel->saved_ier;
2097 		break;
2098 	default:
2099 		return -1;
2100 	}
2101 
2102 	XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, channel->curr_ier);
2103 
2104 	return 0;
2105 }
2106 
2107 static int xgbe_disable_int(struct xgbe_channel *channel,
2108 			    enum xgbe_int int_id)
2109 {
2110 	switch (int_id) {
2111 	case XGMAC_INT_DMA_CH_SR_TI:
2112 		XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TIE, 0);
2113 		break;
2114 	case XGMAC_INT_DMA_CH_SR_TPS:
2115 		XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TXSE, 0);
2116 		break;
2117 	case XGMAC_INT_DMA_CH_SR_TBU:
2118 		XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TBUE, 0);
2119 		break;
2120 	case XGMAC_INT_DMA_CH_SR_RI:
2121 		XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RIE, 0);
2122 		break;
2123 	case XGMAC_INT_DMA_CH_SR_RBU:
2124 		XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RBUE, 0);
2125 		break;
2126 	case XGMAC_INT_DMA_CH_SR_RPS:
2127 		XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RSE, 0);
2128 		break;
2129 	case XGMAC_INT_DMA_CH_SR_TI_RI:
2130 		XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TIE, 0);
2131 		XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RIE, 0);
2132 		break;
2133 	case XGMAC_INT_DMA_CH_SR_FBE:
2134 		XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, FBEE, 0);
2135 		break;
2136 	case XGMAC_INT_DMA_ALL:
2137 		channel->saved_ier = channel->curr_ier;
2138 		channel->curr_ier = 0;
2139 		break;
2140 	default:
2141 		return -1;
2142 	}
2143 
2144 	XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, channel->curr_ier);
2145 
2146 	return 0;
2147 }
2148 
2149 static int __xgbe_exit(struct xgbe_prv_data *pdata)
2150 {
2151 	unsigned int count = 2000;
2152 
2153 	DBGPR("-->xgbe_exit\n");
2154 
2155 	/* Issue a software reset */
2156 	XGMAC_IOWRITE_BITS(pdata, DMA_MR, SWR, 1);
2157 	usleep_range(10, 15);
2158 
2159 	/* Poll Until Poll Condition */
2160 	while (--count && XGMAC_IOREAD_BITS(pdata, DMA_MR, SWR))
2161 		usleep_range(500, 600);
2162 
2163 	if (!count)
2164 		return -EBUSY;
2165 
2166 	DBGPR("<--xgbe_exit\n");
2167 
2168 	return 0;
2169 }
2170 
2171 static int xgbe_exit(struct xgbe_prv_data *pdata)
2172 {
2173 	int ret;
2174 
2175 	/* To guard against possible incorrectly generated interrupts,
2176 	 * issue the software reset twice.
2177 	 */
2178 	ret = __xgbe_exit(pdata);
2179 	if (ret)
2180 		return ret;
2181 
2182 	return __xgbe_exit(pdata);
2183 }
2184 
2185 static int xgbe_flush_tx_queues(struct xgbe_prv_data *pdata)
2186 {
2187 	unsigned int i, count;
2188 
2189 	if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) < 0x21)
2190 		return 0;
2191 
2192 	for (i = 0; i < pdata->tx_q_count; i++)
2193 		XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, FTQ, 1);
2194 
2195 	/* Poll Until Poll Condition */
2196 	for (i = 0; i < pdata->tx_q_count; i++) {
2197 		count = 2000;
2198 		while (--count && XGMAC_MTL_IOREAD_BITS(pdata, i,
2199 							MTL_Q_TQOMR, FTQ))
2200 			usleep_range(500, 600);
2201 
2202 		if (!count)
2203 			return -EBUSY;
2204 	}
2205 
2206 	return 0;
2207 }
2208 
2209 static void xgbe_config_dma_bus(struct xgbe_prv_data *pdata)
2210 {
2211 	unsigned int sbmr;
2212 
2213 	sbmr = XGMAC_IOREAD(pdata, DMA_SBMR);
2214 
2215 	/* Set enhanced addressing mode */
2216 	XGMAC_SET_BITS(sbmr, DMA_SBMR, EAME, 1);
2217 
2218 	/* Set the System Bus mode */
2219 	XGMAC_SET_BITS(sbmr, DMA_SBMR, UNDEF, 1);
2220 	XGMAC_SET_BITS(sbmr, DMA_SBMR, BLEN, pdata->blen >> 2);
2221 	XGMAC_SET_BITS(sbmr, DMA_SBMR, AAL, pdata->aal);
2222 	XGMAC_SET_BITS(sbmr, DMA_SBMR, RD_OSR_LMT, pdata->rd_osr_limit - 1);
2223 	XGMAC_SET_BITS(sbmr, DMA_SBMR, WR_OSR_LMT, pdata->wr_osr_limit - 1);
2224 
2225 	XGMAC_IOWRITE(pdata, DMA_SBMR, sbmr);
2226 
2227 	/* Set descriptor fetching threshold */
2228 	if (pdata->vdata->tx_desc_prefetch)
2229 		XGMAC_IOWRITE_BITS(pdata, DMA_TXEDMACR, TDPS,
2230 				   pdata->vdata->tx_desc_prefetch);
2231 
2232 	if (pdata->vdata->rx_desc_prefetch)
2233 		XGMAC_IOWRITE_BITS(pdata, DMA_RXEDMACR, RDPS,
2234 				   pdata->vdata->rx_desc_prefetch);
2235 }
2236 
2237 static void xgbe_config_dma_cache(struct xgbe_prv_data *pdata)
2238 {
2239 	XGMAC_IOWRITE(pdata, DMA_AXIARCR, pdata->arcr);
2240 	XGMAC_IOWRITE(pdata, DMA_AXIAWCR, pdata->awcr);
2241 	if (pdata->awarcr)
2242 		XGMAC_IOWRITE(pdata, DMA_AXIAWARCR, pdata->awarcr);
2243 }
2244 
2245 static void xgbe_config_mtl_mode(struct xgbe_prv_data *pdata)
2246 {
2247 	unsigned int i;
2248 
2249 	/* Set Tx to weighted round robin scheduling algorithm */
2250 	XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_WRR);
2251 
2252 	/* Set Tx traffic classes to use WRR algorithm with equal weights */
2253 	for (i = 0; i < pdata->hw_feat.tc_cnt; i++) {
2254 		XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA,
2255 				       MTL_TSA_ETS);
2256 		XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW, 1);
2257 	}
2258 
2259 	/* Set Rx to strict priority algorithm */
2260 	XGMAC_IOWRITE_BITS(pdata, MTL_OMR, RAA, MTL_RAA_SP);
2261 }
2262 
2263 static void xgbe_queue_flow_control_threshold(struct xgbe_prv_data *pdata,
2264 					      unsigned int queue,
2265 					      unsigned int q_fifo_size)
2266 {
2267 	unsigned int frame_fifo_size;
2268 	unsigned int rfa, rfd;
2269 
2270 	frame_fifo_size = XGMAC_FLOW_CONTROL_ALIGN(xgbe_get_max_frame(pdata));
2271 
2272 	if (pdata->pfcq[queue] && (q_fifo_size > pdata->pfc_rfa)) {
2273 		/* PFC is active for this queue */
2274 		rfa = pdata->pfc_rfa;
2275 		rfd = rfa + frame_fifo_size;
2276 		if (rfd > XGMAC_FLOW_CONTROL_MAX)
2277 			rfd = XGMAC_FLOW_CONTROL_MAX;
2278 		if (rfa >= XGMAC_FLOW_CONTROL_MAX)
2279 			rfa = XGMAC_FLOW_CONTROL_MAX - XGMAC_FLOW_CONTROL_UNIT;
2280 	} else {
2281 		/* This path deals with just maximum frame sizes which are
2282 		 * limited to a jumbo frame of 9,000 (plus headers, etc.)
2283 		 * so we can never exceed the maximum allowable RFA/RFD
2284 		 * values.
2285 		 */
2286 		if (q_fifo_size <= 2048) {
2287 			/* rx_rfd to zero to signal no flow control */
2288 			pdata->rx_rfa[queue] = 0;
2289 			pdata->rx_rfd[queue] = 0;
2290 			return;
2291 		}
2292 
2293 		if (q_fifo_size <= 4096) {
2294 			/* Between 2048 and 4096 */
2295 			pdata->rx_rfa[queue] = 0;	/* Full - 1024 bytes */
2296 			pdata->rx_rfd[queue] = 1;	/* Full - 1536 bytes */
2297 			return;
2298 		}
2299 
2300 		if (q_fifo_size <= frame_fifo_size) {
2301 			/* Between 4096 and max-frame */
2302 			pdata->rx_rfa[queue] = 2;	/* Full - 2048 bytes */
2303 			pdata->rx_rfd[queue] = 5;	/* Full - 3584 bytes */
2304 			return;
2305 		}
2306 
2307 		if (q_fifo_size <= (frame_fifo_size * 3)) {
2308 			/* Between max-frame and 3 max-frames,
2309 			 * trigger if we get just over a frame of data and
2310 			 * resume when we have just under half a frame left.
2311 			 */
2312 			rfa = q_fifo_size - frame_fifo_size;
2313 			rfd = rfa + (frame_fifo_size / 2);
2314 		} else {
2315 			/* Above 3 max-frames - trigger when just over
2316 			 * 2 frames of space available
2317 			 */
2318 			rfa = frame_fifo_size * 2;
2319 			rfa += XGMAC_FLOW_CONTROL_UNIT;
2320 			rfd = rfa + frame_fifo_size;
2321 		}
2322 	}
2323 
2324 	pdata->rx_rfa[queue] = XGMAC_FLOW_CONTROL_VALUE(rfa);
2325 	pdata->rx_rfd[queue] = XGMAC_FLOW_CONTROL_VALUE(rfd);
2326 }
2327 
2328 static void xgbe_calculate_flow_control_threshold(struct xgbe_prv_data *pdata,
2329 						  unsigned int *fifo)
2330 {
2331 	unsigned int q_fifo_size;
2332 	unsigned int i;
2333 
2334 	for (i = 0; i < pdata->rx_q_count; i++) {
2335 		q_fifo_size = (fifo[i] + 1) * XGMAC_FIFO_UNIT;
2336 
2337 		xgbe_queue_flow_control_threshold(pdata, i, q_fifo_size);
2338 	}
2339 }
2340 
2341 static void xgbe_config_flow_control_threshold(struct xgbe_prv_data *pdata)
2342 {
2343 	unsigned int i;
2344 
2345 	for (i = 0; i < pdata->rx_q_count; i++) {
2346 		XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQFCR, RFA,
2347 				       pdata->rx_rfa[i]);
2348 		XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQFCR, RFD,
2349 				       pdata->rx_rfd[i]);
2350 	}
2351 }
2352 
2353 static unsigned int xgbe_get_tx_fifo_size(struct xgbe_prv_data *pdata)
2354 {
2355 	/* The configured value may not be the actual amount of fifo RAM */
2356 	return min_t(unsigned int, pdata->tx_max_fifo_size,
2357 		     pdata->hw_feat.tx_fifo_size);
2358 }
2359 
2360 static unsigned int xgbe_get_rx_fifo_size(struct xgbe_prv_data *pdata)
2361 {
2362 	/* The configured value may not be the actual amount of fifo RAM */
2363 	return min_t(unsigned int, pdata->rx_max_fifo_size,
2364 		     pdata->hw_feat.rx_fifo_size);
2365 }
2366 
2367 static void xgbe_calculate_equal_fifo(unsigned int fifo_size,
2368 				      unsigned int queue_count,
2369 				      unsigned int *fifo)
2370 {
2371 	unsigned int q_fifo_size;
2372 	unsigned int p_fifo;
2373 	unsigned int i;
2374 
2375 	q_fifo_size = fifo_size / queue_count;
2376 
2377 	/* Calculate the fifo setting by dividing the queue's fifo size
2378 	 * by the fifo allocation increment (with 0 representing the
2379 	 * base allocation increment so decrement the result by 1).
2380 	 */
2381 	p_fifo = q_fifo_size / XGMAC_FIFO_UNIT;
2382 	if (p_fifo)
2383 		p_fifo--;
2384 
2385 	/* Distribute the fifo equally amongst the queues */
2386 	for (i = 0; i < queue_count; i++)
2387 		fifo[i] = p_fifo;
2388 }
2389 
2390 static unsigned int xgbe_set_nonprio_fifos(unsigned int fifo_size,
2391 					   unsigned int queue_count,
2392 					   unsigned int *fifo)
2393 {
2394 	unsigned int i;
2395 
2396 	BUILD_BUG_ON_NOT_POWER_OF_2(XGMAC_FIFO_MIN_ALLOC);
2397 
2398 	if (queue_count <= IEEE_8021QAZ_MAX_TCS)
2399 		return fifo_size;
2400 
2401 	/* Rx queues 9 and up are for specialized packets,
2402 	 * such as PTP or DCB control packets, etc. and
2403 	 * don't require a large fifo
2404 	 */
2405 	for (i = IEEE_8021QAZ_MAX_TCS; i < queue_count; i++) {
2406 		fifo[i] = (XGMAC_FIFO_MIN_ALLOC / XGMAC_FIFO_UNIT) - 1;
2407 		fifo_size -= XGMAC_FIFO_MIN_ALLOC;
2408 	}
2409 
2410 	return fifo_size;
2411 }
2412 
2413 static unsigned int xgbe_get_pfc_delay(struct xgbe_prv_data *pdata)
2414 {
2415 	unsigned int delay;
2416 
2417 	/* If a delay has been provided, use that */
2418 	if (pdata->pfc->delay)
2419 		return pdata->pfc->delay / 8;
2420 
2421 	/* Allow for two maximum size frames */
2422 	delay = xgbe_get_max_frame(pdata);
2423 	delay += XGMAC_ETH_PREAMBLE;
2424 	delay *= 2;
2425 
2426 	/* Allow for PFC frame */
2427 	delay += XGMAC_PFC_DATA_LEN;
2428 	delay += ETH_HLEN + ETH_FCS_LEN;
2429 	delay += XGMAC_ETH_PREAMBLE;
2430 
2431 	/* Allow for miscellaneous delays (LPI exit, cable, etc.) */
2432 	delay += XGMAC_PFC_DELAYS;
2433 
2434 	return delay;
2435 }
2436 
2437 static unsigned int xgbe_get_pfc_queues(struct xgbe_prv_data *pdata)
2438 {
2439 	unsigned int count, prio_queues;
2440 	unsigned int i;
2441 
2442 	if (!pdata->pfc->pfc_en)
2443 		return 0;
2444 
2445 	count = 0;
2446 	prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count);
2447 	for (i = 0; i < prio_queues; i++) {
2448 		if (!xgbe_is_pfc_queue(pdata, i))
2449 			continue;
2450 
2451 		pdata->pfcq[i] = 1;
2452 		count++;
2453 	}
2454 
2455 	return count;
2456 }
2457 
2458 static void xgbe_calculate_dcb_fifo(struct xgbe_prv_data *pdata,
2459 				    unsigned int fifo_size,
2460 				    unsigned int *fifo)
2461 {
2462 	unsigned int q_fifo_size, rem_fifo, addn_fifo;
2463 	unsigned int prio_queues;
2464 	unsigned int pfc_count;
2465 	unsigned int i;
2466 
2467 	q_fifo_size = XGMAC_FIFO_ALIGN(xgbe_get_max_frame(pdata));
2468 	prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count);
2469 	pfc_count = xgbe_get_pfc_queues(pdata);
2470 
2471 	if (!pfc_count || ((q_fifo_size * prio_queues) > fifo_size)) {
2472 		/* No traffic classes with PFC enabled or can't do lossless */
2473 		xgbe_calculate_equal_fifo(fifo_size, prio_queues, fifo);
2474 		return;
2475 	}
2476 
2477 	/* Calculate how much fifo we have to play with */
2478 	rem_fifo = fifo_size - (q_fifo_size * prio_queues);
2479 
2480 	/* Calculate how much more than base fifo PFC needs, which also
2481 	 * becomes the threshold activation point (RFA)
2482 	 */
2483 	pdata->pfc_rfa = xgbe_get_pfc_delay(pdata);
2484 	pdata->pfc_rfa = XGMAC_FLOW_CONTROL_ALIGN(pdata->pfc_rfa);
2485 
2486 	if (pdata->pfc_rfa > q_fifo_size) {
2487 		addn_fifo = pdata->pfc_rfa - q_fifo_size;
2488 		addn_fifo = XGMAC_FIFO_ALIGN(addn_fifo);
2489 	} else {
2490 		addn_fifo = 0;
2491 	}
2492 
2493 	/* Calculate DCB fifo settings:
2494 	 *   - distribute remaining fifo between the VLAN priority
2495 	 *     queues based on traffic class PFC enablement and overall
2496 	 *     priority (0 is lowest priority, so start at highest)
2497 	 */
2498 	i = prio_queues;
2499 	while (i > 0) {
2500 		i--;
2501 
2502 		fifo[i] = (q_fifo_size / XGMAC_FIFO_UNIT) - 1;
2503 
2504 		if (!pdata->pfcq[i] || !addn_fifo)
2505 			continue;
2506 
2507 		if (addn_fifo > rem_fifo) {
2508 			netdev_warn(pdata->netdev,
2509 				    "RXq%u cannot set needed fifo size\n", i);
2510 			if (!rem_fifo)
2511 				continue;
2512 
2513 			addn_fifo = rem_fifo;
2514 		}
2515 
2516 		fifo[i] += (addn_fifo / XGMAC_FIFO_UNIT);
2517 		rem_fifo -= addn_fifo;
2518 	}
2519 
2520 	if (rem_fifo) {
2521 		unsigned int inc_fifo = rem_fifo / prio_queues;
2522 
2523 		/* Distribute remaining fifo across queues */
2524 		for (i = 0; i < prio_queues; i++)
2525 			fifo[i] += (inc_fifo / XGMAC_FIFO_UNIT);
2526 	}
2527 }
2528 
2529 static void xgbe_config_tx_fifo_size(struct xgbe_prv_data *pdata)
2530 {
2531 	unsigned int fifo_size;
2532 	unsigned int fifo[XGBE_MAX_QUEUES];
2533 	unsigned int i;
2534 
2535 	fifo_size = xgbe_get_tx_fifo_size(pdata);
2536 
2537 	xgbe_calculate_equal_fifo(fifo_size, pdata->tx_q_count, fifo);
2538 
2539 	for (i = 0; i < pdata->tx_q_count; i++)
2540 		XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TQS, fifo[i]);
2541 
2542 	netif_info(pdata, drv, pdata->netdev,
2543 		   "%d Tx hardware queues, %d byte fifo per queue\n",
2544 		   pdata->tx_q_count, ((fifo[0] + 1) * XGMAC_FIFO_UNIT));
2545 }
2546 
2547 static void xgbe_config_rx_fifo_size(struct xgbe_prv_data *pdata)
2548 {
2549 	unsigned int fifo_size;
2550 	unsigned int fifo[XGBE_MAX_QUEUES];
2551 	unsigned int prio_queues;
2552 	unsigned int i;
2553 
2554 	/* Clear any DCB related fifo/queue information */
2555 	memset(pdata->pfcq, 0, sizeof(pdata->pfcq));
2556 	pdata->pfc_rfa = 0;
2557 
2558 	fifo_size = xgbe_get_rx_fifo_size(pdata);
2559 	prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count);
2560 
2561 	/* Assign a minimum fifo to the non-VLAN priority queues */
2562 	fifo_size = xgbe_set_nonprio_fifos(fifo_size, pdata->rx_q_count, fifo);
2563 
2564 	if (pdata->pfc && pdata->ets)
2565 		xgbe_calculate_dcb_fifo(pdata, fifo_size, fifo);
2566 	else
2567 		xgbe_calculate_equal_fifo(fifo_size, prio_queues, fifo);
2568 
2569 	for (i = 0; i < pdata->rx_q_count; i++)
2570 		XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RQS, fifo[i]);
2571 
2572 	xgbe_calculate_flow_control_threshold(pdata, fifo);
2573 	xgbe_config_flow_control_threshold(pdata);
2574 
2575 	if (pdata->pfc && pdata->ets && pdata->pfc->pfc_en) {
2576 		netif_info(pdata, drv, pdata->netdev,
2577 			   "%u Rx hardware queues\n", pdata->rx_q_count);
2578 		for (i = 0; i < pdata->rx_q_count; i++)
2579 			netif_info(pdata, drv, pdata->netdev,
2580 				   "RxQ%u, %u byte fifo queue\n", i,
2581 				   ((fifo[i] + 1) * XGMAC_FIFO_UNIT));
2582 	} else {
2583 		netif_info(pdata, drv, pdata->netdev,
2584 			   "%u Rx hardware queues, %u byte fifo per queue\n",
2585 			   pdata->rx_q_count,
2586 			   ((fifo[0] + 1) * XGMAC_FIFO_UNIT));
2587 	}
2588 }
2589 
2590 static void xgbe_config_queue_mapping(struct xgbe_prv_data *pdata)
2591 {
2592 	unsigned int qptc, qptc_extra, queue;
2593 	unsigned int prio_queues;
2594 	unsigned int ppq, ppq_extra, prio;
2595 	unsigned int mask;
2596 	unsigned int i, j, reg, reg_val;
2597 
2598 	/* Map the MTL Tx Queues to Traffic Classes
2599 	 *   Note: Tx Queues >= Traffic Classes
2600 	 */
2601 	qptc = pdata->tx_q_count / pdata->hw_feat.tc_cnt;
2602 	qptc_extra = pdata->tx_q_count % pdata->hw_feat.tc_cnt;
2603 
2604 	for (i = 0, queue = 0; i < pdata->hw_feat.tc_cnt; i++) {
2605 		for (j = 0; j < qptc; j++) {
2606 			netif_dbg(pdata, drv, pdata->netdev,
2607 				  "TXq%u mapped to TC%u\n", queue, i);
2608 			XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR,
2609 					       Q2TCMAP, i);
2610 			pdata->q2tc_map[queue++] = i;
2611 		}
2612 
2613 		if (i < qptc_extra) {
2614 			netif_dbg(pdata, drv, pdata->netdev,
2615 				  "TXq%u mapped to TC%u\n", queue, i);
2616 			XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR,
2617 					       Q2TCMAP, i);
2618 			pdata->q2tc_map[queue++] = i;
2619 		}
2620 	}
2621 
2622 	/* Map the 8 VLAN priority values to available MTL Rx queues */
2623 	prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count);
2624 	ppq = IEEE_8021QAZ_MAX_TCS / prio_queues;
2625 	ppq_extra = IEEE_8021QAZ_MAX_TCS % prio_queues;
2626 
2627 	reg = MAC_RQC2R;
2628 	reg_val = 0;
2629 	for (i = 0, prio = 0; i < prio_queues;) {
2630 		mask = 0;
2631 		for (j = 0; j < ppq; j++) {
2632 			netif_dbg(pdata, drv, pdata->netdev,
2633 				  "PRIO%u mapped to RXq%u\n", prio, i);
2634 			mask |= (1 << prio);
2635 			pdata->prio2q_map[prio++] = i;
2636 		}
2637 
2638 		if (i < ppq_extra) {
2639 			netif_dbg(pdata, drv, pdata->netdev,
2640 				  "PRIO%u mapped to RXq%u\n", prio, i);
2641 			mask |= (1 << prio);
2642 			pdata->prio2q_map[prio++] = i;
2643 		}
2644 
2645 		reg_val |= (mask << ((i++ % MAC_RQC2_Q_PER_REG) << 3));
2646 
2647 		if ((i % MAC_RQC2_Q_PER_REG) && (i != prio_queues))
2648 			continue;
2649 
2650 		XGMAC_IOWRITE(pdata, reg, reg_val);
2651 		reg += MAC_RQC2_INC;
2652 		reg_val = 0;
2653 	}
2654 
2655 	/* Select dynamic mapping of MTL Rx queue to DMA Rx channel */
2656 	reg = MTL_RQDCM0R;
2657 	reg_val = 0;
2658 	for (i = 0; i < pdata->rx_q_count;) {
2659 		reg_val |= (0x80 << ((i++ % MTL_RQDCM_Q_PER_REG) << 3));
2660 
2661 		if ((i % MTL_RQDCM_Q_PER_REG) && (i != pdata->rx_q_count))
2662 			continue;
2663 
2664 		XGMAC_IOWRITE(pdata, reg, reg_val);
2665 
2666 		reg += MTL_RQDCM_INC;
2667 		reg_val = 0;
2668 	}
2669 }
2670 
2671 static void xgbe_config_tc(struct xgbe_prv_data *pdata)
2672 {
2673 	unsigned int offset, queue, prio;
2674 	u8 i;
2675 
2676 	netdev_reset_tc(pdata->netdev);
2677 	if (!pdata->num_tcs)
2678 		return;
2679 
2680 	netdev_set_num_tc(pdata->netdev, pdata->num_tcs);
2681 
2682 	for (i = 0, queue = 0, offset = 0; i < pdata->num_tcs; i++) {
2683 		while ((queue < pdata->tx_q_count) &&
2684 		       (pdata->q2tc_map[queue] == i))
2685 			queue++;
2686 
2687 		netif_dbg(pdata, drv, pdata->netdev, "TC%u using TXq%u-%u\n",
2688 			  i, offset, queue - 1);
2689 		netdev_set_tc_queue(pdata->netdev, i, queue - offset, offset);
2690 		offset = queue;
2691 	}
2692 
2693 	if (!pdata->ets)
2694 		return;
2695 
2696 	for (prio = 0; prio < IEEE_8021QAZ_MAX_TCS; prio++)
2697 		netdev_set_prio_tc_map(pdata->netdev, prio,
2698 				       pdata->ets->prio_tc[prio]);
2699 }
2700 
2701 static void xgbe_config_dcb_tc(struct xgbe_prv_data *pdata)
2702 {
2703 	struct ieee_ets *ets = pdata->ets;
2704 	unsigned int total_weight, min_weight, weight;
2705 	unsigned int mask, reg, reg_val;
2706 	unsigned int i, prio;
2707 
2708 	if (!ets)
2709 		return;
2710 
2711 	/* Set Tx to deficit weighted round robin scheduling algorithm (when
2712 	 * traffic class is using ETS algorithm)
2713 	 */
2714 	XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_DWRR);
2715 
2716 	/* Set Traffic Class algorithms */
2717 	total_weight = pdata->netdev->mtu * pdata->hw_feat.tc_cnt;
2718 	min_weight = total_weight / 100;
2719 	if (!min_weight)
2720 		min_weight = 1;
2721 
2722 	for (i = 0; i < pdata->hw_feat.tc_cnt; i++) {
2723 		/* Map the priorities to the traffic class */
2724 		mask = 0;
2725 		for (prio = 0; prio < IEEE_8021QAZ_MAX_TCS; prio++) {
2726 			if (ets->prio_tc[prio] == i)
2727 				mask |= (1 << prio);
2728 		}
2729 		mask &= 0xff;
2730 
2731 		netif_dbg(pdata, drv, pdata->netdev, "TC%u PRIO mask=%#x\n",
2732 			  i, mask);
2733 		reg = MTL_TCPM0R + (MTL_TCPM_INC * (i / MTL_TCPM_TC_PER_REG));
2734 		reg_val = XGMAC_IOREAD(pdata, reg);
2735 
2736 		reg_val &= ~(0xff << ((i % MTL_TCPM_TC_PER_REG) << 3));
2737 		reg_val |= (mask << ((i % MTL_TCPM_TC_PER_REG) << 3));
2738 
2739 		XGMAC_IOWRITE(pdata, reg, reg_val);
2740 
2741 		/* Set the traffic class algorithm */
2742 		switch (ets->tc_tsa[i]) {
2743 		case IEEE_8021QAZ_TSA_STRICT:
2744 			netif_dbg(pdata, drv, pdata->netdev,
2745 				  "TC%u using SP\n", i);
2746 			XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA,
2747 					       MTL_TSA_SP);
2748 			break;
2749 		case IEEE_8021QAZ_TSA_ETS:
2750 			weight = total_weight * ets->tc_tx_bw[i] / 100;
2751 			weight = clamp(weight, min_weight, total_weight);
2752 
2753 			netif_dbg(pdata, drv, pdata->netdev,
2754 				  "TC%u using DWRR (weight %u)\n", i, weight);
2755 			XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA,
2756 					       MTL_TSA_ETS);
2757 			XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW,
2758 					       weight);
2759 			break;
2760 		}
2761 	}
2762 
2763 	xgbe_config_tc(pdata);
2764 }
2765 
2766 static void xgbe_config_dcb_pfc(struct xgbe_prv_data *pdata)
2767 {
2768 	if (!test_bit(XGBE_DOWN, &pdata->dev_state)) {
2769 		/* Just stop the Tx queues while Rx fifo is changed */
2770 		netif_tx_stop_all_queues(pdata->netdev);
2771 
2772 		/* Suspend Rx so that fifo's can be adjusted */
2773 		pdata->hw_if.disable_rx(pdata);
2774 	}
2775 
2776 	xgbe_config_rx_fifo_size(pdata);
2777 	xgbe_config_flow_control(pdata);
2778 
2779 	if (!test_bit(XGBE_DOWN, &pdata->dev_state)) {
2780 		/* Resume Rx */
2781 		pdata->hw_if.enable_rx(pdata);
2782 
2783 		/* Resume Tx queues */
2784 		netif_tx_start_all_queues(pdata->netdev);
2785 	}
2786 }
2787 
2788 static void xgbe_config_mac_address(struct xgbe_prv_data *pdata)
2789 {
2790 	xgbe_set_mac_address(pdata, pdata->netdev->dev_addr);
2791 
2792 	/* Filtering is done using perfect filtering and hash filtering */
2793 	if (pdata->hw_feat.hash_table_size) {
2794 		XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 1);
2795 		XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 1);
2796 		XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HMC, 1);
2797 	}
2798 }
2799 
2800 static void xgbe_config_jumbo_enable(struct xgbe_prv_data *pdata)
2801 {
2802 	unsigned int val;
2803 
2804 	val = (pdata->netdev->mtu > XGMAC_STD_PACKET_MTU) ? 1 : 0;
2805 
2806 	XGMAC_IOWRITE_BITS(pdata, MAC_RCR, JE, val);
2807 }
2808 
2809 static void xgbe_config_mac_speed(struct xgbe_prv_data *pdata)
2810 {
2811 	xgbe_set_speed(pdata, pdata->phy_speed);
2812 }
2813 
2814 static void xgbe_config_checksum_offload(struct xgbe_prv_data *pdata)
2815 {
2816 	if (pdata->netdev->features & NETIF_F_RXCSUM)
2817 		xgbe_enable_rx_csum(pdata);
2818 	else
2819 		xgbe_disable_rx_csum(pdata);
2820 }
2821 
2822 static void xgbe_config_vlan_support(struct xgbe_prv_data *pdata)
2823 {
2824 	/* Indicate that VLAN Tx CTAGs come from context descriptors */
2825 	XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, CSVL, 0);
2826 	XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, VLTI, 1);
2827 
2828 	/* Set the current VLAN Hash Table register value */
2829 	xgbe_update_vlan_hash_table(pdata);
2830 
2831 	if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER)
2832 		xgbe_enable_rx_vlan_filtering(pdata);
2833 	else
2834 		xgbe_disable_rx_vlan_filtering(pdata);
2835 
2836 	if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
2837 		xgbe_enable_rx_vlan_stripping(pdata);
2838 	else
2839 		xgbe_disable_rx_vlan_stripping(pdata);
2840 }
2841 
2842 static u64 xgbe_mmc_read(struct xgbe_prv_data *pdata, unsigned int reg_lo)
2843 {
2844 	bool read_hi;
2845 	u64 val;
2846 
2847 	if (pdata->vdata->mmc_64bit) {
2848 		switch (reg_lo) {
2849 		/* These registers are always 32 bit */
2850 		case MMC_RXRUNTERROR:
2851 		case MMC_RXJABBERERROR:
2852 		case MMC_RXUNDERSIZE_G:
2853 		case MMC_RXOVERSIZE_G:
2854 		case MMC_RXWATCHDOGERROR:
2855 			read_hi = false;
2856 			break;
2857 
2858 		default:
2859 			read_hi = true;
2860 		}
2861 	} else {
2862 		switch (reg_lo) {
2863 		/* These registers are always 64 bit */
2864 		case MMC_TXOCTETCOUNT_GB_LO:
2865 		case MMC_TXOCTETCOUNT_G_LO:
2866 		case MMC_RXOCTETCOUNT_GB_LO:
2867 		case MMC_RXOCTETCOUNT_G_LO:
2868 			read_hi = true;
2869 			break;
2870 
2871 		default:
2872 			read_hi = false;
2873 		}
2874 	}
2875 
2876 	val = XGMAC_IOREAD(pdata, reg_lo);
2877 
2878 	if (read_hi)
2879 		val |= ((u64)XGMAC_IOREAD(pdata, reg_lo + 4) << 32);
2880 
2881 	return val;
2882 }
2883 
2884 static void xgbe_tx_mmc_int(struct xgbe_prv_data *pdata)
2885 {
2886 	struct xgbe_mmc_stats *stats = &pdata->mmc_stats;
2887 	unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_TISR);
2888 
2889 	if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXOCTETCOUNT_GB))
2890 		stats->txoctetcount_gb +=
2891 			xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO);
2892 
2893 	if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXFRAMECOUNT_GB))
2894 		stats->txframecount_gb +=
2895 			xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO);
2896 
2897 	if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXBROADCASTFRAMES_G))
2898 		stats->txbroadcastframes_g +=
2899 			xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO);
2900 
2901 	if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXMULTICASTFRAMES_G))
2902 		stats->txmulticastframes_g +=
2903 			xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO);
2904 
2905 	if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX64OCTETS_GB))
2906 		stats->tx64octets_gb +=
2907 			xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO);
2908 
2909 	if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX65TO127OCTETS_GB))
2910 		stats->tx65to127octets_gb +=
2911 			xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO);
2912 
2913 	if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX128TO255OCTETS_GB))
2914 		stats->tx128to255octets_gb +=
2915 			xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO);
2916 
2917 	if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX256TO511OCTETS_GB))
2918 		stats->tx256to511octets_gb +=
2919 			xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO);
2920 
2921 	if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX512TO1023OCTETS_GB))
2922 		stats->tx512to1023octets_gb +=
2923 			xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO);
2924 
2925 	if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX1024TOMAXOCTETS_GB))
2926 		stats->tx1024tomaxoctets_gb +=
2927 			xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO);
2928 
2929 	if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXUNICASTFRAMES_GB))
2930 		stats->txunicastframes_gb +=
2931 			xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO);
2932 
2933 	if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXMULTICASTFRAMES_GB))
2934 		stats->txmulticastframes_gb +=
2935 			xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO);
2936 
2937 	if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXBROADCASTFRAMES_GB))
2938 		stats->txbroadcastframes_g +=
2939 			xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO);
2940 
2941 	if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXUNDERFLOWERROR))
2942 		stats->txunderflowerror +=
2943 			xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO);
2944 
2945 	if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXOCTETCOUNT_G))
2946 		stats->txoctetcount_g +=
2947 			xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO);
2948 
2949 	if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXFRAMECOUNT_G))
2950 		stats->txframecount_g +=
2951 			xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO);
2952 
2953 	if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXPAUSEFRAMES))
2954 		stats->txpauseframes +=
2955 			xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO);
2956 
2957 	if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXVLANFRAMES_G))
2958 		stats->txvlanframes_g +=
2959 			xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO);
2960 }
2961 
2962 static void xgbe_rx_mmc_int(struct xgbe_prv_data *pdata)
2963 {
2964 	struct xgbe_mmc_stats *stats = &pdata->mmc_stats;
2965 	unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_RISR);
2966 
2967 	if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXFRAMECOUNT_GB))
2968 		stats->rxframecount_gb +=
2969 			xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO);
2970 
2971 	if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOCTETCOUNT_GB))
2972 		stats->rxoctetcount_gb +=
2973 			xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO);
2974 
2975 	if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOCTETCOUNT_G))
2976 		stats->rxoctetcount_g +=
2977 			xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO);
2978 
2979 	if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXBROADCASTFRAMES_G))
2980 		stats->rxbroadcastframes_g +=
2981 			xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO);
2982 
2983 	if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXMULTICASTFRAMES_G))
2984 		stats->rxmulticastframes_g +=
2985 			xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO);
2986 
2987 	if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXCRCERROR))
2988 		stats->rxcrcerror +=
2989 			xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO);
2990 
2991 	if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXRUNTERROR))
2992 		stats->rxrunterror +=
2993 			xgbe_mmc_read(pdata, MMC_RXRUNTERROR);
2994 
2995 	if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXJABBERERROR))
2996 		stats->rxjabbererror +=
2997 			xgbe_mmc_read(pdata, MMC_RXJABBERERROR);
2998 
2999 	if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXUNDERSIZE_G))
3000 		stats->rxundersize_g +=
3001 			xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G);
3002 
3003 	if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOVERSIZE_G))
3004 		stats->rxoversize_g +=
3005 			xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G);
3006 
3007 	if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX64OCTETS_GB))
3008 		stats->rx64octets_gb +=
3009 			xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO);
3010 
3011 	if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX65TO127OCTETS_GB))
3012 		stats->rx65to127octets_gb +=
3013 			xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO);
3014 
3015 	if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX128TO255OCTETS_GB))
3016 		stats->rx128to255octets_gb +=
3017 			xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO);
3018 
3019 	if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX256TO511OCTETS_GB))
3020 		stats->rx256to511octets_gb +=
3021 			xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO);
3022 
3023 	if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX512TO1023OCTETS_GB))
3024 		stats->rx512to1023octets_gb +=
3025 			xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO);
3026 
3027 	if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX1024TOMAXOCTETS_GB))
3028 		stats->rx1024tomaxoctets_gb +=
3029 			xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO);
3030 
3031 	if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXUNICASTFRAMES_G))
3032 		stats->rxunicastframes_g +=
3033 			xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO);
3034 
3035 	if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXLENGTHERROR))
3036 		stats->rxlengtherror +=
3037 			xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO);
3038 
3039 	if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOUTOFRANGETYPE))
3040 		stats->rxoutofrangetype +=
3041 			xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO);
3042 
3043 	if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXPAUSEFRAMES))
3044 		stats->rxpauseframes +=
3045 			xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO);
3046 
3047 	if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXFIFOOVERFLOW))
3048 		stats->rxfifooverflow +=
3049 			xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO);
3050 
3051 	if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXVLANFRAMES_GB))
3052 		stats->rxvlanframes_gb +=
3053 			xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO);
3054 
3055 	if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXWATCHDOGERROR))
3056 		stats->rxwatchdogerror +=
3057 			xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR);
3058 }
3059 
3060 static void xgbe_read_mmc_stats(struct xgbe_prv_data *pdata)
3061 {
3062 	struct xgbe_mmc_stats *stats = &pdata->mmc_stats;
3063 
3064 	/* Freeze counters */
3065 	XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 1);
3066 
3067 	stats->txoctetcount_gb +=
3068 		xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO);
3069 
3070 	stats->txframecount_gb +=
3071 		xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO);
3072 
3073 	stats->txbroadcastframes_g +=
3074 		xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO);
3075 
3076 	stats->txmulticastframes_g +=
3077 		xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO);
3078 
3079 	stats->tx64octets_gb +=
3080 		xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO);
3081 
3082 	stats->tx65to127octets_gb +=
3083 		xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO);
3084 
3085 	stats->tx128to255octets_gb +=
3086 		xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO);
3087 
3088 	stats->tx256to511octets_gb +=
3089 		xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO);
3090 
3091 	stats->tx512to1023octets_gb +=
3092 		xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO);
3093 
3094 	stats->tx1024tomaxoctets_gb +=
3095 		xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO);
3096 
3097 	stats->txunicastframes_gb +=
3098 		xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO);
3099 
3100 	stats->txmulticastframes_gb +=
3101 		xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO);
3102 
3103 	stats->txbroadcastframes_g +=
3104 		xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO);
3105 
3106 	stats->txunderflowerror +=
3107 		xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO);
3108 
3109 	stats->txoctetcount_g +=
3110 		xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO);
3111 
3112 	stats->txframecount_g +=
3113 		xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO);
3114 
3115 	stats->txpauseframes +=
3116 		xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO);
3117 
3118 	stats->txvlanframes_g +=
3119 		xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO);
3120 
3121 	stats->rxframecount_gb +=
3122 		xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO);
3123 
3124 	stats->rxoctetcount_gb +=
3125 		xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO);
3126 
3127 	stats->rxoctetcount_g +=
3128 		xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO);
3129 
3130 	stats->rxbroadcastframes_g +=
3131 		xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO);
3132 
3133 	stats->rxmulticastframes_g +=
3134 		xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO);
3135 
3136 	stats->rxcrcerror +=
3137 		xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO);
3138 
3139 	stats->rxrunterror +=
3140 		xgbe_mmc_read(pdata, MMC_RXRUNTERROR);
3141 
3142 	stats->rxjabbererror +=
3143 		xgbe_mmc_read(pdata, MMC_RXJABBERERROR);
3144 
3145 	stats->rxundersize_g +=
3146 		xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G);
3147 
3148 	stats->rxoversize_g +=
3149 		xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G);
3150 
3151 	stats->rx64octets_gb +=
3152 		xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO);
3153 
3154 	stats->rx65to127octets_gb +=
3155 		xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO);
3156 
3157 	stats->rx128to255octets_gb +=
3158 		xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO);
3159 
3160 	stats->rx256to511octets_gb +=
3161 		xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO);
3162 
3163 	stats->rx512to1023octets_gb +=
3164 		xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO);
3165 
3166 	stats->rx1024tomaxoctets_gb +=
3167 		xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO);
3168 
3169 	stats->rxunicastframes_g +=
3170 		xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO);
3171 
3172 	stats->rxlengtherror +=
3173 		xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO);
3174 
3175 	stats->rxoutofrangetype +=
3176 		xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO);
3177 
3178 	stats->rxpauseframes +=
3179 		xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO);
3180 
3181 	stats->rxfifooverflow +=
3182 		xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO);
3183 
3184 	stats->rxvlanframes_gb +=
3185 		xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO);
3186 
3187 	stats->rxwatchdogerror +=
3188 		xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR);
3189 
3190 	/* Un-freeze counters */
3191 	XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 0);
3192 }
3193 
3194 static void xgbe_config_mmc(struct xgbe_prv_data *pdata)
3195 {
3196 	/* Set counters to reset on read */
3197 	XGMAC_IOWRITE_BITS(pdata, MMC_CR, ROR, 1);
3198 
3199 	/* Reset the counters */
3200 	XGMAC_IOWRITE_BITS(pdata, MMC_CR, CR, 1);
3201 }
3202 
3203 static void xgbe_txq_prepare_tx_stop(struct xgbe_prv_data *pdata,
3204 				     unsigned int queue)
3205 {
3206 	unsigned int tx_status;
3207 	unsigned long tx_timeout;
3208 
3209 	/* The Tx engine cannot be stopped if it is actively processing
3210 	 * packets. Wait for the Tx queue to empty the Tx fifo.  Don't
3211 	 * wait forever though...
3212 	 */
3213 	tx_timeout = jiffies + (XGBE_DMA_STOP_TIMEOUT * HZ);
3214 	while (time_before(jiffies, tx_timeout)) {
3215 		tx_status = XGMAC_MTL_IOREAD(pdata, queue, MTL_Q_TQDR);
3216 		if ((XGMAC_GET_BITS(tx_status, MTL_Q_TQDR, TRCSTS) != 1) &&
3217 		    (XGMAC_GET_BITS(tx_status, MTL_Q_TQDR, TXQSTS) == 0))
3218 			break;
3219 
3220 		usleep_range(500, 1000);
3221 	}
3222 
3223 	if (!time_before(jiffies, tx_timeout))
3224 		netdev_info(pdata->netdev,
3225 			    "timed out waiting for Tx queue %u to empty\n",
3226 			    queue);
3227 }
3228 
3229 static void xgbe_prepare_tx_stop(struct xgbe_prv_data *pdata,
3230 				 unsigned int queue)
3231 {
3232 	unsigned int tx_dsr, tx_pos, tx_qidx;
3233 	unsigned int tx_status;
3234 	unsigned long tx_timeout;
3235 
3236 	if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) > 0x20)
3237 		return xgbe_txq_prepare_tx_stop(pdata, queue);
3238 
3239 	/* Calculate the status register to read and the position within */
3240 	if (queue < DMA_DSRX_FIRST_QUEUE) {
3241 		tx_dsr = DMA_DSR0;
3242 		tx_pos = (queue * DMA_DSR_Q_WIDTH) + DMA_DSR0_TPS_START;
3243 	} else {
3244 		tx_qidx = queue - DMA_DSRX_FIRST_QUEUE;
3245 
3246 		tx_dsr = DMA_DSR1 + ((tx_qidx / DMA_DSRX_QPR) * DMA_DSRX_INC);
3247 		tx_pos = ((tx_qidx % DMA_DSRX_QPR) * DMA_DSR_Q_WIDTH) +
3248 			 DMA_DSRX_TPS_START;
3249 	}
3250 
3251 	/* The Tx engine cannot be stopped if it is actively processing
3252 	 * descriptors. Wait for the Tx engine to enter the stopped or
3253 	 * suspended state.  Don't wait forever though...
3254 	 */
3255 	tx_timeout = jiffies + (XGBE_DMA_STOP_TIMEOUT * HZ);
3256 	while (time_before(jiffies, tx_timeout)) {
3257 		tx_status = XGMAC_IOREAD(pdata, tx_dsr);
3258 		tx_status = GET_BITS(tx_status, tx_pos, DMA_DSR_TPS_WIDTH);
3259 		if ((tx_status == DMA_TPS_STOPPED) ||
3260 		    (tx_status == DMA_TPS_SUSPENDED))
3261 			break;
3262 
3263 		usleep_range(500, 1000);
3264 	}
3265 
3266 	if (!time_before(jiffies, tx_timeout))
3267 		netdev_info(pdata->netdev,
3268 			    "timed out waiting for Tx DMA channel %u to stop\n",
3269 			    queue);
3270 }
3271 
3272 static void xgbe_enable_tx(struct xgbe_prv_data *pdata)
3273 {
3274 	unsigned int i;
3275 
3276 	/* Enable each Tx DMA channel */
3277 	for (i = 0; i < pdata->channel_count; i++) {
3278 		if (!pdata->channel[i]->tx_ring)
3279 			break;
3280 
3281 		XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 1);
3282 	}
3283 
3284 	/* Enable each Tx queue */
3285 	for (i = 0; i < pdata->tx_q_count; i++)
3286 		XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN,
3287 				       MTL_Q_ENABLED);
3288 
3289 	/* Enable MAC Tx */
3290 	XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1);
3291 }
3292 
3293 static void xgbe_disable_tx(struct xgbe_prv_data *pdata)
3294 {
3295 	unsigned int i;
3296 
3297 	/* Prepare for Tx DMA channel stop */
3298 	for (i = 0; i < pdata->tx_q_count; i++)
3299 		xgbe_prepare_tx_stop(pdata, i);
3300 
3301 	/* Disable MAC Tx */
3302 	XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0);
3303 
3304 	/* Disable each Tx queue */
3305 	for (i = 0; i < pdata->tx_q_count; i++)
3306 		XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN, 0);
3307 
3308 	/* Disable each Tx DMA channel */
3309 	for (i = 0; i < pdata->channel_count; i++) {
3310 		if (!pdata->channel[i]->tx_ring)
3311 			break;
3312 
3313 		XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 0);
3314 	}
3315 }
3316 
3317 static void xgbe_prepare_rx_stop(struct xgbe_prv_data *pdata,
3318 				 unsigned int queue)
3319 {
3320 	unsigned int rx_status;
3321 	unsigned long rx_timeout;
3322 
3323 	/* The Rx engine cannot be stopped if it is actively processing
3324 	 * packets. Wait for the Rx queue to empty the Rx fifo.  Don't
3325 	 * wait forever though...
3326 	 */
3327 	rx_timeout = jiffies + (XGBE_DMA_STOP_TIMEOUT * HZ);
3328 	while (time_before(jiffies, rx_timeout)) {
3329 		rx_status = XGMAC_MTL_IOREAD(pdata, queue, MTL_Q_RQDR);
3330 		if ((XGMAC_GET_BITS(rx_status, MTL_Q_RQDR, PRXQ) == 0) &&
3331 		    (XGMAC_GET_BITS(rx_status, MTL_Q_RQDR, RXQSTS) == 0))
3332 			break;
3333 
3334 		usleep_range(500, 1000);
3335 	}
3336 
3337 	if (!time_before(jiffies, rx_timeout))
3338 		netdev_info(pdata->netdev,
3339 			    "timed out waiting for Rx queue %u to empty\n",
3340 			    queue);
3341 }
3342 
3343 static void xgbe_enable_rx(struct xgbe_prv_data *pdata)
3344 {
3345 	unsigned int reg_val, i;
3346 
3347 	/* Enable each Rx DMA channel */
3348 	for (i = 0; i < pdata->channel_count; i++) {
3349 		if (!pdata->channel[i]->rx_ring)
3350 			break;
3351 
3352 		XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 1);
3353 	}
3354 
3355 	/* Enable each Rx queue */
3356 	reg_val = 0;
3357 	for (i = 0; i < pdata->rx_q_count; i++)
3358 		reg_val |= (0x02 << (i << 1));
3359 	XGMAC_IOWRITE(pdata, MAC_RQC0R, reg_val);
3360 
3361 	/* Enable MAC Rx */
3362 	XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 1);
3363 	XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 1);
3364 	XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 1);
3365 	XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 1);
3366 }
3367 
3368 static void xgbe_disable_rx(struct xgbe_prv_data *pdata)
3369 {
3370 	unsigned int i;
3371 
3372 	/* Disable MAC Rx */
3373 	XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 0);
3374 	XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 0);
3375 	XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 0);
3376 	XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 0);
3377 
3378 	/* Prepare for Rx DMA channel stop */
3379 	for (i = 0; i < pdata->rx_q_count; i++)
3380 		xgbe_prepare_rx_stop(pdata, i);
3381 
3382 	/* Disable each Rx queue */
3383 	XGMAC_IOWRITE(pdata, MAC_RQC0R, 0);
3384 
3385 	/* Disable each Rx DMA channel */
3386 	for (i = 0; i < pdata->channel_count; i++) {
3387 		if (!pdata->channel[i]->rx_ring)
3388 			break;
3389 
3390 		XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 0);
3391 	}
3392 }
3393 
3394 static void xgbe_powerup_tx(struct xgbe_prv_data *pdata)
3395 {
3396 	unsigned int i;
3397 
3398 	/* Enable each Tx DMA channel */
3399 	for (i = 0; i < pdata->channel_count; i++) {
3400 		if (!pdata->channel[i]->tx_ring)
3401 			break;
3402 
3403 		XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 1);
3404 	}
3405 
3406 	/* Enable MAC Tx */
3407 	XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1);
3408 }
3409 
3410 static void xgbe_powerdown_tx(struct xgbe_prv_data *pdata)
3411 {
3412 	unsigned int i;
3413 
3414 	/* Prepare for Tx DMA channel stop */
3415 	for (i = 0; i < pdata->tx_q_count; i++)
3416 		xgbe_prepare_tx_stop(pdata, i);
3417 
3418 	/* Disable MAC Tx */
3419 	XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0);
3420 
3421 	/* Disable each Tx DMA channel */
3422 	for (i = 0; i < pdata->channel_count; i++) {
3423 		if (!pdata->channel[i]->tx_ring)
3424 			break;
3425 
3426 		XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 0);
3427 	}
3428 }
3429 
3430 static void xgbe_powerup_rx(struct xgbe_prv_data *pdata)
3431 {
3432 	unsigned int i;
3433 
3434 	/* Enable each Rx DMA channel */
3435 	for (i = 0; i < pdata->channel_count; i++) {
3436 		if (!pdata->channel[i]->rx_ring)
3437 			break;
3438 
3439 		XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 1);
3440 	}
3441 }
3442 
3443 static void xgbe_powerdown_rx(struct xgbe_prv_data *pdata)
3444 {
3445 	unsigned int i;
3446 
3447 	/* Disable each Rx DMA channel */
3448 	for (i = 0; i < pdata->channel_count; i++) {
3449 		if (!pdata->channel[i]->rx_ring)
3450 			break;
3451 
3452 		XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 0);
3453 	}
3454 }
3455 
3456 static int xgbe_init(struct xgbe_prv_data *pdata)
3457 {
3458 	struct xgbe_desc_if *desc_if = &pdata->desc_if;
3459 	int ret;
3460 
3461 	DBGPR("-->xgbe_init\n");
3462 
3463 	/* Flush Tx queues */
3464 	ret = xgbe_flush_tx_queues(pdata);
3465 	if (ret) {
3466 		netdev_err(pdata->netdev, "error flushing TX queues\n");
3467 		return ret;
3468 	}
3469 
3470 	/*
3471 	 * Initialize DMA related features
3472 	 */
3473 	xgbe_config_dma_bus(pdata);
3474 	xgbe_config_dma_cache(pdata);
3475 	xgbe_config_osp_mode(pdata);
3476 	xgbe_config_pbl_val(pdata);
3477 	xgbe_config_rx_coalesce(pdata);
3478 	xgbe_config_tx_coalesce(pdata);
3479 	xgbe_config_rx_buffer_size(pdata);
3480 	xgbe_config_tso_mode(pdata);
3481 	xgbe_config_sph_mode(pdata);
3482 	xgbe_config_rss(pdata);
3483 	desc_if->wrapper_tx_desc_init(pdata);
3484 	desc_if->wrapper_rx_desc_init(pdata);
3485 	xgbe_enable_dma_interrupts(pdata);
3486 
3487 	/*
3488 	 * Initialize MTL related features
3489 	 */
3490 	xgbe_config_mtl_mode(pdata);
3491 	xgbe_config_queue_mapping(pdata);
3492 	xgbe_config_tsf_mode(pdata, pdata->tx_sf_mode);
3493 	xgbe_config_rsf_mode(pdata, pdata->rx_sf_mode);
3494 	xgbe_config_tx_threshold(pdata, pdata->tx_threshold);
3495 	xgbe_config_rx_threshold(pdata, pdata->rx_threshold);
3496 	xgbe_config_tx_fifo_size(pdata);
3497 	xgbe_config_rx_fifo_size(pdata);
3498 	/*TODO: Error Packet and undersized good Packet forwarding enable
3499 		(FEP and FUP)
3500 	 */
3501 	xgbe_config_dcb_tc(pdata);
3502 	xgbe_enable_mtl_interrupts(pdata);
3503 
3504 	/*
3505 	 * Initialize MAC related features
3506 	 */
3507 	xgbe_config_mac_address(pdata);
3508 	xgbe_config_rx_mode(pdata);
3509 	xgbe_config_jumbo_enable(pdata);
3510 	xgbe_config_flow_control(pdata);
3511 	xgbe_config_mac_speed(pdata);
3512 	xgbe_config_checksum_offload(pdata);
3513 	xgbe_config_vlan_support(pdata);
3514 	xgbe_config_mmc(pdata);
3515 	xgbe_enable_mac_interrupts(pdata);
3516 
3517 	/*
3518 	 * Initialize ECC related features
3519 	 */
3520 	xgbe_enable_ecc_interrupts(pdata);
3521 
3522 	DBGPR("<--xgbe_init\n");
3523 
3524 	return 0;
3525 }
3526 
3527 void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *hw_if)
3528 {
3529 	DBGPR("-->xgbe_init_function_ptrs\n");
3530 
3531 	hw_if->tx_complete = xgbe_tx_complete;
3532 
3533 	hw_if->set_mac_address = xgbe_set_mac_address;
3534 	hw_if->config_rx_mode = xgbe_config_rx_mode;
3535 
3536 	hw_if->enable_rx_csum = xgbe_enable_rx_csum;
3537 	hw_if->disable_rx_csum = xgbe_disable_rx_csum;
3538 
3539 	hw_if->enable_rx_vlan_stripping = xgbe_enable_rx_vlan_stripping;
3540 	hw_if->disable_rx_vlan_stripping = xgbe_disable_rx_vlan_stripping;
3541 	hw_if->enable_rx_vlan_filtering = xgbe_enable_rx_vlan_filtering;
3542 	hw_if->disable_rx_vlan_filtering = xgbe_disable_rx_vlan_filtering;
3543 	hw_if->update_vlan_hash_table = xgbe_update_vlan_hash_table;
3544 
3545 	hw_if->read_mmd_regs = xgbe_read_mmd_regs;
3546 	hw_if->write_mmd_regs = xgbe_write_mmd_regs;
3547 
3548 	hw_if->set_speed = xgbe_set_speed;
3549 
3550 	hw_if->set_ext_mii_mode = xgbe_set_ext_mii_mode;
3551 	hw_if->read_ext_mii_regs = xgbe_read_ext_mii_regs;
3552 	hw_if->write_ext_mii_regs = xgbe_write_ext_mii_regs;
3553 
3554 	hw_if->set_gpio = xgbe_set_gpio;
3555 	hw_if->clr_gpio = xgbe_clr_gpio;
3556 
3557 	hw_if->enable_tx = xgbe_enable_tx;
3558 	hw_if->disable_tx = xgbe_disable_tx;
3559 	hw_if->enable_rx = xgbe_enable_rx;
3560 	hw_if->disable_rx = xgbe_disable_rx;
3561 
3562 	hw_if->powerup_tx = xgbe_powerup_tx;
3563 	hw_if->powerdown_tx = xgbe_powerdown_tx;
3564 	hw_if->powerup_rx = xgbe_powerup_rx;
3565 	hw_if->powerdown_rx = xgbe_powerdown_rx;
3566 
3567 	hw_if->dev_xmit = xgbe_dev_xmit;
3568 	hw_if->dev_read = xgbe_dev_read;
3569 	hw_if->enable_int = xgbe_enable_int;
3570 	hw_if->disable_int = xgbe_disable_int;
3571 	hw_if->init = xgbe_init;
3572 	hw_if->exit = xgbe_exit;
3573 
3574 	/* Descriptor related Sequences have to be initialized here */
3575 	hw_if->tx_desc_init = xgbe_tx_desc_init;
3576 	hw_if->rx_desc_init = xgbe_rx_desc_init;
3577 	hw_if->tx_desc_reset = xgbe_tx_desc_reset;
3578 	hw_if->rx_desc_reset = xgbe_rx_desc_reset;
3579 	hw_if->is_last_desc = xgbe_is_last_desc;
3580 	hw_if->is_context_desc = xgbe_is_context_desc;
3581 	hw_if->tx_start_xmit = xgbe_tx_start_xmit;
3582 
3583 	/* For FLOW ctrl */
3584 	hw_if->config_tx_flow_control = xgbe_config_tx_flow_control;
3585 	hw_if->config_rx_flow_control = xgbe_config_rx_flow_control;
3586 
3587 	/* For RX coalescing */
3588 	hw_if->config_rx_coalesce = xgbe_config_rx_coalesce;
3589 	hw_if->config_tx_coalesce = xgbe_config_tx_coalesce;
3590 	hw_if->usec_to_riwt = xgbe_usec_to_riwt;
3591 	hw_if->riwt_to_usec = xgbe_riwt_to_usec;
3592 
3593 	/* For RX and TX threshold config */
3594 	hw_if->config_rx_threshold = xgbe_config_rx_threshold;
3595 	hw_if->config_tx_threshold = xgbe_config_tx_threshold;
3596 
3597 	/* For RX and TX Store and Forward Mode config */
3598 	hw_if->config_rsf_mode = xgbe_config_rsf_mode;
3599 	hw_if->config_tsf_mode = xgbe_config_tsf_mode;
3600 
3601 	/* For TX DMA Operating on Second Frame config */
3602 	hw_if->config_osp_mode = xgbe_config_osp_mode;
3603 
3604 	/* For MMC statistics support */
3605 	hw_if->tx_mmc_int = xgbe_tx_mmc_int;
3606 	hw_if->rx_mmc_int = xgbe_rx_mmc_int;
3607 	hw_if->read_mmc_stats = xgbe_read_mmc_stats;
3608 
3609 	/* For PTP config */
3610 	hw_if->config_tstamp = xgbe_config_tstamp;
3611 	hw_if->update_tstamp_addend = xgbe_update_tstamp_addend;
3612 	hw_if->set_tstamp_time = xgbe_set_tstamp_time;
3613 	hw_if->get_tstamp_time = xgbe_get_tstamp_time;
3614 	hw_if->get_tx_tstamp = xgbe_get_tx_tstamp;
3615 
3616 	/* For Data Center Bridging config */
3617 	hw_if->config_tc = xgbe_config_tc;
3618 	hw_if->config_dcb_tc = xgbe_config_dcb_tc;
3619 	hw_if->config_dcb_pfc = xgbe_config_dcb_pfc;
3620 
3621 	/* For Receive Side Scaling */
3622 	hw_if->enable_rss = xgbe_enable_rss;
3623 	hw_if->disable_rss = xgbe_disable_rss;
3624 	hw_if->set_rss_hash_key = xgbe_set_rss_hash_key;
3625 	hw_if->set_rss_lookup_table = xgbe_set_rss_lookup_table;
3626 
3627 	/* For ECC */
3628 	hw_if->disable_ecc_ded = xgbe_disable_ecc_ded;
3629 	hw_if->disable_ecc_sec = xgbe_disable_ecc_sec;
3630 
3631 	/* For VXLAN */
3632 	hw_if->enable_vxlan = xgbe_enable_vxlan;
3633 	hw_if->disable_vxlan = xgbe_disable_vxlan;
3634 	hw_if->set_vxlan_id = xgbe_set_vxlan_id;
3635 
3636 	DBGPR("<--xgbe_init_function_ptrs\n");
3637 }
3638