1 /* 2 * AMD 10Gb Ethernet driver 3 * 4 * This file is available to you under your choice of the following two 5 * licenses: 6 * 7 * License 1: GPLv2 8 * 9 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc. 10 * 11 * This file is free software; you may copy, redistribute and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation, either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program. If not, see <http://www.gnu.org/licenses/>. 23 * 24 * This file incorporates work covered by the following copyright and 25 * permission notice: 26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 28 * Inc. unless otherwise expressly agreed to in writing between Synopsys 29 * and you. 30 * 31 * The Software IS NOT an item of Licensed Software or Licensed Product 32 * under any End User Software License Agreement or Agreement for Licensed 33 * Product with Synopsys or any supplement thereto. Permission is hereby 34 * granted, free of charge, to any person obtaining a copy of this software 35 * annotated with this license and the Software, to deal in the Software 36 * without restriction, including without limitation the rights to use, 37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 38 * of the Software, and to permit persons to whom the Software is furnished 39 * to do so, subject to the following conditions: 40 * 41 * The above copyright notice and this permission notice shall be included 42 * in all copies or substantial portions of the Software. 43 * 44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 54 * THE POSSIBILITY OF SUCH DAMAGE. 55 * 56 * 57 * License 2: Modified BSD 58 * 59 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc. 60 * All rights reserved. 61 * 62 * Redistribution and use in source and binary forms, with or without 63 * modification, are permitted provided that the following conditions are met: 64 * * Redistributions of source code must retain the above copyright 65 * notice, this list of conditions and the following disclaimer. 66 * * Redistributions in binary form must reproduce the above copyright 67 * notice, this list of conditions and the following disclaimer in the 68 * documentation and/or other materials provided with the distribution. 69 * * Neither the name of Advanced Micro Devices, Inc. nor the 70 * names of its contributors may be used to endorse or promote products 71 * derived from this software without specific prior written permission. 72 * 73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY 77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 83 * 84 * This file incorporates work covered by the following copyright and 85 * permission notice: 86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 88 * Inc. unless otherwise expressly agreed to in writing between Synopsys 89 * and you. 90 * 91 * The Software IS NOT an item of Licensed Software or Licensed Product 92 * under any End User Software License Agreement or Agreement for Licensed 93 * Product with Synopsys or any supplement thereto. Permission is hereby 94 * granted, free of charge, to any person obtaining a copy of this software 95 * annotated with this license and the Software, to deal in the Software 96 * without restriction, including without limitation the rights to use, 97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 98 * of the Software, and to permit persons to whom the Software is furnished 99 * to do so, subject to the following conditions: 100 * 101 * The above copyright notice and this permission notice shall be included 102 * in all copies or substantial portions of the Software. 103 * 104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 114 * THE POSSIBILITY OF SUCH DAMAGE. 115 */ 116 117 #include <linux/phy.h> 118 #include <linux/mdio.h> 119 #include <linux/clk.h> 120 #include <linux/bitrev.h> 121 #include <linux/crc32.h> 122 #include <linux/crc32poly.h> 123 124 #include "xgbe.h" 125 #include "xgbe-common.h" 126 127 static inline unsigned int xgbe_get_max_frame(struct xgbe_prv_data *pdata) 128 { 129 return pdata->netdev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 130 } 131 132 static unsigned int xgbe_usec_to_riwt(struct xgbe_prv_data *pdata, 133 unsigned int usec) 134 { 135 unsigned long rate; 136 unsigned int ret; 137 138 DBGPR("-->xgbe_usec_to_riwt\n"); 139 140 rate = pdata->sysclk_rate; 141 142 /* 143 * Convert the input usec value to the watchdog timer value. Each 144 * watchdog timer value is equivalent to 256 clock cycles. 145 * Calculate the required value as: 146 * ( usec * ( system_clock_mhz / 10^6 ) / 256 147 */ 148 ret = (usec * (rate / 1000000)) / 256; 149 150 DBGPR("<--xgbe_usec_to_riwt\n"); 151 152 return ret; 153 } 154 155 static unsigned int xgbe_riwt_to_usec(struct xgbe_prv_data *pdata, 156 unsigned int riwt) 157 { 158 unsigned long rate; 159 unsigned int ret; 160 161 DBGPR("-->xgbe_riwt_to_usec\n"); 162 163 rate = pdata->sysclk_rate; 164 165 /* 166 * Convert the input watchdog timer value to the usec value. Each 167 * watchdog timer value is equivalent to 256 clock cycles. 168 * Calculate the required value as: 169 * ( riwt * 256 ) / ( system_clock_mhz / 10^6 ) 170 */ 171 ret = (riwt * 256) / (rate / 1000000); 172 173 DBGPR("<--xgbe_riwt_to_usec\n"); 174 175 return ret; 176 } 177 178 static int xgbe_config_pbl_val(struct xgbe_prv_data *pdata) 179 { 180 unsigned int pblx8, pbl; 181 unsigned int i; 182 183 pblx8 = DMA_PBL_X8_DISABLE; 184 pbl = pdata->pbl; 185 186 if (pdata->pbl > 32) { 187 pblx8 = DMA_PBL_X8_ENABLE; 188 pbl >>= 3; 189 } 190 191 for (i = 0; i < pdata->channel_count; i++) { 192 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_CR, PBLX8, 193 pblx8); 194 195 if (pdata->channel[i]->tx_ring) 196 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, 197 PBL, pbl); 198 199 if (pdata->channel[i]->rx_ring) 200 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, 201 PBL, pbl); 202 } 203 204 return 0; 205 } 206 207 static int xgbe_config_osp_mode(struct xgbe_prv_data *pdata) 208 { 209 unsigned int i; 210 211 for (i = 0; i < pdata->channel_count; i++) { 212 if (!pdata->channel[i]->tx_ring) 213 break; 214 215 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, OSP, 216 pdata->tx_osp_mode); 217 } 218 219 return 0; 220 } 221 222 static int xgbe_config_rsf_mode(struct xgbe_prv_data *pdata, unsigned int val) 223 { 224 unsigned int i; 225 226 for (i = 0; i < pdata->rx_q_count; i++) 227 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RSF, val); 228 229 return 0; 230 } 231 232 static int xgbe_config_tsf_mode(struct xgbe_prv_data *pdata, unsigned int val) 233 { 234 unsigned int i; 235 236 for (i = 0; i < pdata->tx_q_count; i++) 237 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TSF, val); 238 239 return 0; 240 } 241 242 static int xgbe_config_rx_threshold(struct xgbe_prv_data *pdata, 243 unsigned int val) 244 { 245 unsigned int i; 246 247 for (i = 0; i < pdata->rx_q_count; i++) 248 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RTC, val); 249 250 return 0; 251 } 252 253 static int xgbe_config_tx_threshold(struct xgbe_prv_data *pdata, 254 unsigned int val) 255 { 256 unsigned int i; 257 258 for (i = 0; i < pdata->tx_q_count; i++) 259 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TTC, val); 260 261 return 0; 262 } 263 264 static int xgbe_config_rx_coalesce(struct xgbe_prv_data *pdata) 265 { 266 unsigned int i; 267 268 for (i = 0; i < pdata->channel_count; i++) { 269 if (!pdata->channel[i]->rx_ring) 270 break; 271 272 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RIWT, RWT, 273 pdata->rx_riwt); 274 } 275 276 return 0; 277 } 278 279 static int xgbe_config_tx_coalesce(struct xgbe_prv_data *pdata) 280 { 281 return 0; 282 } 283 284 static void xgbe_config_rx_buffer_size(struct xgbe_prv_data *pdata) 285 { 286 unsigned int i; 287 288 for (i = 0; i < pdata->channel_count; i++) { 289 if (!pdata->channel[i]->rx_ring) 290 break; 291 292 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, RBSZ, 293 pdata->rx_buf_size); 294 } 295 } 296 297 static void xgbe_config_tso_mode(struct xgbe_prv_data *pdata) 298 { 299 unsigned int i; 300 301 for (i = 0; i < pdata->channel_count; i++) { 302 if (!pdata->channel[i]->tx_ring) 303 break; 304 305 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, TSE, 1); 306 } 307 } 308 309 static void xgbe_config_sph_mode(struct xgbe_prv_data *pdata) 310 { 311 unsigned int i; 312 313 for (i = 0; i < pdata->channel_count; i++) { 314 if (!pdata->channel[i]->rx_ring) 315 break; 316 317 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_CR, SPH, 1); 318 } 319 320 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, HDSMS, XGBE_SPH_HDSMS_SIZE); 321 } 322 323 static int xgbe_write_rss_reg(struct xgbe_prv_data *pdata, unsigned int type, 324 unsigned int index, unsigned int val) 325 { 326 unsigned int wait; 327 int ret = 0; 328 329 mutex_lock(&pdata->rss_mutex); 330 331 if (XGMAC_IOREAD_BITS(pdata, MAC_RSSAR, OB)) { 332 ret = -EBUSY; 333 goto unlock; 334 } 335 336 XGMAC_IOWRITE(pdata, MAC_RSSDR, val); 337 338 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, RSSIA, index); 339 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, ADDRT, type); 340 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, CT, 0); 341 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, OB, 1); 342 343 wait = 1000; 344 while (wait--) { 345 if (!XGMAC_IOREAD_BITS(pdata, MAC_RSSAR, OB)) 346 goto unlock; 347 348 usleep_range(1000, 1500); 349 } 350 351 ret = -EBUSY; 352 353 unlock: 354 mutex_unlock(&pdata->rss_mutex); 355 356 return ret; 357 } 358 359 static int xgbe_write_rss_hash_key(struct xgbe_prv_data *pdata) 360 { 361 unsigned int key_regs = sizeof(pdata->rss_key) / sizeof(u32); 362 unsigned int *key = (unsigned int *)&pdata->rss_key; 363 int ret; 364 365 while (key_regs--) { 366 ret = xgbe_write_rss_reg(pdata, XGBE_RSS_HASH_KEY_TYPE, 367 key_regs, *key++); 368 if (ret) 369 return ret; 370 } 371 372 return 0; 373 } 374 375 static int xgbe_write_rss_lookup_table(struct xgbe_prv_data *pdata) 376 { 377 unsigned int i; 378 int ret; 379 380 for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++) { 381 ret = xgbe_write_rss_reg(pdata, 382 XGBE_RSS_LOOKUP_TABLE_TYPE, i, 383 pdata->rss_table[i]); 384 if (ret) 385 return ret; 386 } 387 388 return 0; 389 } 390 391 static int xgbe_set_rss_hash_key(struct xgbe_prv_data *pdata, const u8 *key) 392 { 393 memcpy(pdata->rss_key, key, sizeof(pdata->rss_key)); 394 395 return xgbe_write_rss_hash_key(pdata); 396 } 397 398 static int xgbe_set_rss_lookup_table(struct xgbe_prv_data *pdata, 399 const u32 *table) 400 { 401 unsigned int i; 402 403 for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++) 404 XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH, table[i]); 405 406 return xgbe_write_rss_lookup_table(pdata); 407 } 408 409 static int xgbe_enable_rss(struct xgbe_prv_data *pdata) 410 { 411 int ret; 412 413 if (!pdata->hw_feat.rss) 414 return -EOPNOTSUPP; 415 416 /* Program the hash key */ 417 ret = xgbe_write_rss_hash_key(pdata); 418 if (ret) 419 return ret; 420 421 /* Program the lookup table */ 422 ret = xgbe_write_rss_lookup_table(pdata); 423 if (ret) 424 return ret; 425 426 /* Set the RSS options */ 427 XGMAC_IOWRITE(pdata, MAC_RSSCR, pdata->rss_options); 428 429 /* Enable RSS */ 430 XGMAC_IOWRITE_BITS(pdata, MAC_RSSCR, RSSE, 1); 431 432 return 0; 433 } 434 435 static int xgbe_disable_rss(struct xgbe_prv_data *pdata) 436 { 437 if (!pdata->hw_feat.rss) 438 return -EOPNOTSUPP; 439 440 XGMAC_IOWRITE_BITS(pdata, MAC_RSSCR, RSSE, 0); 441 442 return 0; 443 } 444 445 static void xgbe_config_rss(struct xgbe_prv_data *pdata) 446 { 447 int ret; 448 449 if (!pdata->hw_feat.rss) 450 return; 451 452 if (pdata->netdev->features & NETIF_F_RXHASH) 453 ret = xgbe_enable_rss(pdata); 454 else 455 ret = xgbe_disable_rss(pdata); 456 457 if (ret) 458 netdev_err(pdata->netdev, 459 "error configuring RSS, RSS disabled\n"); 460 } 461 462 static bool xgbe_is_pfc_queue(struct xgbe_prv_data *pdata, 463 unsigned int queue) 464 { 465 unsigned int prio, tc; 466 467 for (prio = 0; prio < IEEE_8021QAZ_MAX_TCS; prio++) { 468 /* Does this queue handle the priority? */ 469 if (pdata->prio2q_map[prio] != queue) 470 continue; 471 472 /* Get the Traffic Class for this priority */ 473 tc = pdata->ets->prio_tc[prio]; 474 475 /* Check if PFC is enabled for this traffic class */ 476 if (pdata->pfc->pfc_en & (1 << tc)) 477 return true; 478 } 479 480 return false; 481 } 482 483 static void xgbe_set_vxlan_id(struct xgbe_prv_data *pdata) 484 { 485 /* Program the VXLAN port */ 486 XGMAC_IOWRITE_BITS(pdata, MAC_TIR, TNID, pdata->vxlan_port); 487 488 netif_dbg(pdata, drv, pdata->netdev, "VXLAN tunnel id set to %hx\n", 489 pdata->vxlan_port); 490 } 491 492 static void xgbe_enable_vxlan(struct xgbe_prv_data *pdata) 493 { 494 if (!pdata->hw_feat.vxn) 495 return; 496 497 /* Program the VXLAN port */ 498 xgbe_set_vxlan_id(pdata); 499 500 /* Allow for IPv6/UDP zero-checksum VXLAN packets */ 501 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VUCC, 1); 502 503 /* Enable VXLAN tunneling mode */ 504 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, VNM, 0); 505 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, VNE, 1); 506 507 netif_dbg(pdata, drv, pdata->netdev, "VXLAN acceleration enabled\n"); 508 } 509 510 static void xgbe_disable_vxlan(struct xgbe_prv_data *pdata) 511 { 512 if (!pdata->hw_feat.vxn) 513 return; 514 515 /* Disable tunneling mode */ 516 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, VNE, 0); 517 518 /* Clear IPv6/UDP zero-checksum VXLAN packets setting */ 519 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VUCC, 0); 520 521 /* Clear the VXLAN port */ 522 XGMAC_IOWRITE_BITS(pdata, MAC_TIR, TNID, 0); 523 524 netif_dbg(pdata, drv, pdata->netdev, "VXLAN acceleration disabled\n"); 525 } 526 527 static int xgbe_disable_tx_flow_control(struct xgbe_prv_data *pdata) 528 { 529 unsigned int max_q_count, q_count; 530 unsigned int reg, reg_val; 531 unsigned int i; 532 533 /* Clear MTL flow control */ 534 for (i = 0; i < pdata->rx_q_count; i++) 535 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, 0); 536 537 /* Clear MAC flow control */ 538 max_q_count = XGMAC_MAX_FLOW_CONTROL_QUEUES; 539 q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count); 540 reg = MAC_Q0TFCR; 541 for (i = 0; i < q_count; i++) { 542 reg_val = XGMAC_IOREAD(pdata, reg); 543 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 0); 544 XGMAC_IOWRITE(pdata, reg, reg_val); 545 546 reg += MAC_QTFCR_INC; 547 } 548 549 return 0; 550 } 551 552 static int xgbe_enable_tx_flow_control(struct xgbe_prv_data *pdata) 553 { 554 struct ieee_pfc *pfc = pdata->pfc; 555 struct ieee_ets *ets = pdata->ets; 556 unsigned int max_q_count, q_count; 557 unsigned int reg, reg_val; 558 unsigned int i; 559 560 /* Set MTL flow control */ 561 for (i = 0; i < pdata->rx_q_count; i++) { 562 unsigned int ehfc = 0; 563 564 if (pdata->rx_rfd[i]) { 565 /* Flow control thresholds are established */ 566 if (pfc && ets) { 567 if (xgbe_is_pfc_queue(pdata, i)) 568 ehfc = 1; 569 } else { 570 ehfc = 1; 571 } 572 } 573 574 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, ehfc); 575 576 netif_dbg(pdata, drv, pdata->netdev, 577 "flow control %s for RXq%u\n", 578 ehfc ? "enabled" : "disabled", i); 579 } 580 581 /* Set MAC flow control */ 582 max_q_count = XGMAC_MAX_FLOW_CONTROL_QUEUES; 583 q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count); 584 reg = MAC_Q0TFCR; 585 for (i = 0; i < q_count; i++) { 586 reg_val = XGMAC_IOREAD(pdata, reg); 587 588 /* Enable transmit flow control */ 589 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 1); 590 /* Set pause time */ 591 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, PT, 0xffff); 592 593 XGMAC_IOWRITE(pdata, reg, reg_val); 594 595 reg += MAC_QTFCR_INC; 596 } 597 598 return 0; 599 } 600 601 static int xgbe_disable_rx_flow_control(struct xgbe_prv_data *pdata) 602 { 603 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 0); 604 605 return 0; 606 } 607 608 static int xgbe_enable_rx_flow_control(struct xgbe_prv_data *pdata) 609 { 610 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 1); 611 612 return 0; 613 } 614 615 static int xgbe_config_tx_flow_control(struct xgbe_prv_data *pdata) 616 { 617 struct ieee_pfc *pfc = pdata->pfc; 618 619 if (pdata->tx_pause || (pfc && pfc->pfc_en)) 620 xgbe_enable_tx_flow_control(pdata); 621 else 622 xgbe_disable_tx_flow_control(pdata); 623 624 return 0; 625 } 626 627 static int xgbe_config_rx_flow_control(struct xgbe_prv_data *pdata) 628 { 629 struct ieee_pfc *pfc = pdata->pfc; 630 631 if (pdata->rx_pause || (pfc && pfc->pfc_en)) 632 xgbe_enable_rx_flow_control(pdata); 633 else 634 xgbe_disable_rx_flow_control(pdata); 635 636 return 0; 637 } 638 639 static void xgbe_config_flow_control(struct xgbe_prv_data *pdata) 640 { 641 struct ieee_pfc *pfc = pdata->pfc; 642 643 xgbe_config_tx_flow_control(pdata); 644 xgbe_config_rx_flow_control(pdata); 645 646 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 647 (pfc && pfc->pfc_en) ? 1 : 0); 648 } 649 650 static void xgbe_enable_dma_interrupts(struct xgbe_prv_data *pdata) 651 { 652 struct xgbe_channel *channel; 653 unsigned int i, ver; 654 655 /* Set the interrupt mode if supported */ 656 if (pdata->channel_irq_mode) 657 XGMAC_IOWRITE_BITS(pdata, DMA_MR, INTM, 658 pdata->channel_irq_mode); 659 660 ver = XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER); 661 662 for (i = 0; i < pdata->channel_count; i++) { 663 channel = pdata->channel[i]; 664 665 /* Clear all the interrupts which are set */ 666 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, 667 XGMAC_DMA_IOREAD(channel, DMA_CH_SR)); 668 669 /* Clear all interrupt enable bits */ 670 channel->curr_ier = 0; 671 672 /* Enable following interrupts 673 * NIE - Normal Interrupt Summary Enable 674 * AIE - Abnormal Interrupt Summary Enable 675 * FBEE - Fatal Bus Error Enable 676 */ 677 if (ver < 0x21) { 678 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, NIE20, 1); 679 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, AIE20, 1); 680 } else { 681 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, NIE, 1); 682 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, AIE, 1); 683 } 684 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, FBEE, 1); 685 686 if (channel->tx_ring) { 687 /* Enable the following Tx interrupts 688 * TIE - Transmit Interrupt Enable (unless using 689 * per channel interrupts in edge triggered 690 * mode) 691 */ 692 if (!pdata->per_channel_irq || pdata->channel_irq_mode) 693 XGMAC_SET_BITS(channel->curr_ier, 694 DMA_CH_IER, TIE, 1); 695 } 696 if (channel->rx_ring) { 697 /* Enable following Rx interrupts 698 * RBUE - Receive Buffer Unavailable Enable 699 * RIE - Receive Interrupt Enable (unless using 700 * per channel interrupts in edge triggered 701 * mode) 702 */ 703 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RBUE, 1); 704 if (!pdata->per_channel_irq || pdata->channel_irq_mode) 705 XGMAC_SET_BITS(channel->curr_ier, 706 DMA_CH_IER, RIE, 1); 707 } 708 709 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, channel->curr_ier); 710 } 711 } 712 713 static void xgbe_enable_mtl_interrupts(struct xgbe_prv_data *pdata) 714 { 715 unsigned int mtl_q_isr; 716 unsigned int q_count, i; 717 718 q_count = max(pdata->hw_feat.tx_q_cnt, pdata->hw_feat.rx_q_cnt); 719 for (i = 0; i < q_count; i++) { 720 /* Clear all the interrupts which are set */ 721 mtl_q_isr = XGMAC_MTL_IOREAD(pdata, i, MTL_Q_ISR); 722 XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_ISR, mtl_q_isr); 723 724 /* No MTL interrupts to be enabled */ 725 XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_IER, 0); 726 } 727 } 728 729 static void xgbe_enable_mac_interrupts(struct xgbe_prv_data *pdata) 730 { 731 unsigned int mac_ier = 0; 732 733 /* Enable Timestamp interrupt */ 734 XGMAC_SET_BITS(mac_ier, MAC_IER, TSIE, 1); 735 736 XGMAC_IOWRITE(pdata, MAC_IER, mac_ier); 737 738 /* Enable all counter interrupts */ 739 XGMAC_IOWRITE_BITS(pdata, MMC_RIER, ALL_INTERRUPTS, 0xffffffff); 740 XGMAC_IOWRITE_BITS(pdata, MMC_TIER, ALL_INTERRUPTS, 0xffffffff); 741 742 /* Enable MDIO single command completion interrupt */ 743 XGMAC_IOWRITE_BITS(pdata, MAC_MDIOIER, SNGLCOMPIE, 1); 744 } 745 746 static void xgbe_enable_ecc_interrupts(struct xgbe_prv_data *pdata) 747 { 748 unsigned int ecc_isr, ecc_ier = 0; 749 750 if (!pdata->vdata->ecc_support) 751 return; 752 753 /* Clear all the interrupts which are set */ 754 ecc_isr = XP_IOREAD(pdata, XP_ECC_ISR); 755 XP_IOWRITE(pdata, XP_ECC_ISR, ecc_isr); 756 757 /* Enable ECC interrupts */ 758 XP_SET_BITS(ecc_ier, XP_ECC_IER, TX_DED, 1); 759 XP_SET_BITS(ecc_ier, XP_ECC_IER, TX_SEC, 1); 760 XP_SET_BITS(ecc_ier, XP_ECC_IER, RX_DED, 1); 761 XP_SET_BITS(ecc_ier, XP_ECC_IER, RX_SEC, 1); 762 XP_SET_BITS(ecc_ier, XP_ECC_IER, DESC_DED, 1); 763 XP_SET_BITS(ecc_ier, XP_ECC_IER, DESC_SEC, 1); 764 765 XP_IOWRITE(pdata, XP_ECC_IER, ecc_ier); 766 } 767 768 static void xgbe_disable_ecc_ded(struct xgbe_prv_data *pdata) 769 { 770 unsigned int ecc_ier; 771 772 ecc_ier = XP_IOREAD(pdata, XP_ECC_IER); 773 774 /* Disable ECC DED interrupts */ 775 XP_SET_BITS(ecc_ier, XP_ECC_IER, TX_DED, 0); 776 XP_SET_BITS(ecc_ier, XP_ECC_IER, RX_DED, 0); 777 XP_SET_BITS(ecc_ier, XP_ECC_IER, DESC_DED, 0); 778 779 XP_IOWRITE(pdata, XP_ECC_IER, ecc_ier); 780 } 781 782 static void xgbe_disable_ecc_sec(struct xgbe_prv_data *pdata, 783 enum xgbe_ecc_sec sec) 784 { 785 unsigned int ecc_ier; 786 787 ecc_ier = XP_IOREAD(pdata, XP_ECC_IER); 788 789 /* Disable ECC SEC interrupt */ 790 switch (sec) { 791 case XGBE_ECC_SEC_TX: 792 XP_SET_BITS(ecc_ier, XP_ECC_IER, TX_SEC, 0); 793 break; 794 case XGBE_ECC_SEC_RX: 795 XP_SET_BITS(ecc_ier, XP_ECC_IER, RX_SEC, 0); 796 break; 797 case XGBE_ECC_SEC_DESC: 798 XP_SET_BITS(ecc_ier, XP_ECC_IER, DESC_SEC, 0); 799 break; 800 } 801 802 XP_IOWRITE(pdata, XP_ECC_IER, ecc_ier); 803 } 804 805 static int xgbe_set_speed(struct xgbe_prv_data *pdata, int speed) 806 { 807 unsigned int ss; 808 809 switch (speed) { 810 case SPEED_10: 811 ss = 0x07; 812 break; 813 case SPEED_1000: 814 ss = 0x03; 815 break; 816 case SPEED_2500: 817 ss = 0x02; 818 break; 819 case SPEED_10000: 820 ss = 0x00; 821 break; 822 default: 823 return -EINVAL; 824 } 825 826 if (XGMAC_IOREAD_BITS(pdata, MAC_TCR, SS) != ss) 827 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, ss); 828 829 return 0; 830 } 831 832 static int xgbe_enable_rx_vlan_stripping(struct xgbe_prv_data *pdata) 833 { 834 /* Put the VLAN tag in the Rx descriptor */ 835 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLRXS, 1); 836 837 /* Don't check the VLAN type */ 838 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, DOVLTC, 1); 839 840 /* Check only C-TAG (0x8100) packets */ 841 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ERSVLM, 0); 842 843 /* Don't consider an S-TAG (0x88A8) packet as a VLAN packet */ 844 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ESVL, 0); 845 846 /* Enable VLAN tag stripping */ 847 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0x3); 848 849 return 0; 850 } 851 852 static int xgbe_disable_rx_vlan_stripping(struct xgbe_prv_data *pdata) 853 { 854 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0); 855 856 return 0; 857 } 858 859 static int xgbe_enable_rx_vlan_filtering(struct xgbe_prv_data *pdata) 860 { 861 /* Enable VLAN filtering */ 862 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 1); 863 864 /* Enable VLAN Hash Table filtering */ 865 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTHM, 1); 866 867 /* Disable VLAN tag inverse matching */ 868 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTIM, 0); 869 870 /* Only filter on the lower 12-bits of the VLAN tag */ 871 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ETV, 1); 872 873 /* In order for the VLAN Hash Table filtering to be effective, 874 * the VLAN tag identifier in the VLAN Tag Register must not 875 * be zero. Set the VLAN tag identifier to "1" to enable the 876 * VLAN Hash Table filtering. This implies that a VLAN tag of 877 * 1 will always pass filtering. 878 */ 879 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VL, 1); 880 881 return 0; 882 } 883 884 static int xgbe_disable_rx_vlan_filtering(struct xgbe_prv_data *pdata) 885 { 886 /* Disable VLAN filtering */ 887 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 0); 888 889 return 0; 890 } 891 892 static u32 xgbe_vid_crc32_le(__le16 vid_le) 893 { 894 u32 crc = ~0; 895 u32 temp = 0; 896 unsigned char *data = (unsigned char *)&vid_le; 897 unsigned char data_byte = 0; 898 int i, bits; 899 900 bits = get_bitmask_order(VLAN_VID_MASK); 901 for (i = 0; i < bits; i++) { 902 if ((i % 8) == 0) 903 data_byte = data[i / 8]; 904 905 temp = ((crc & 1) ^ data_byte) & 1; 906 crc >>= 1; 907 data_byte >>= 1; 908 909 if (temp) 910 crc ^= CRC32_POLY_LE; 911 } 912 913 return crc; 914 } 915 916 static int xgbe_update_vlan_hash_table(struct xgbe_prv_data *pdata) 917 { 918 u32 crc; 919 u16 vid; 920 __le16 vid_le; 921 u16 vlan_hash_table = 0; 922 923 /* Generate the VLAN Hash Table value */ 924 for_each_set_bit(vid, pdata->active_vlans, VLAN_N_VID) { 925 /* Get the CRC32 value of the VLAN ID */ 926 vid_le = cpu_to_le16(vid); 927 crc = bitrev32(~xgbe_vid_crc32_le(vid_le)) >> 28; 928 929 vlan_hash_table |= (1 << crc); 930 } 931 932 /* Set the VLAN Hash Table filtering register */ 933 XGMAC_IOWRITE_BITS(pdata, MAC_VLANHTR, VLHT, vlan_hash_table); 934 935 return 0; 936 } 937 938 static int xgbe_set_promiscuous_mode(struct xgbe_prv_data *pdata, 939 unsigned int enable) 940 { 941 unsigned int val = enable ? 1 : 0; 942 943 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PR) == val) 944 return 0; 945 946 netif_dbg(pdata, drv, pdata->netdev, "%s promiscuous mode\n", 947 enable ? "entering" : "leaving"); 948 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, val); 949 950 /* Hardware will still perform VLAN filtering in promiscuous mode */ 951 if (enable) { 952 xgbe_disable_rx_vlan_filtering(pdata); 953 } else { 954 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER) 955 xgbe_enable_rx_vlan_filtering(pdata); 956 } 957 958 return 0; 959 } 960 961 static int xgbe_set_all_multicast_mode(struct xgbe_prv_data *pdata, 962 unsigned int enable) 963 { 964 unsigned int val = enable ? 1 : 0; 965 966 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PM) == val) 967 return 0; 968 969 netif_dbg(pdata, drv, pdata->netdev, "%s allmulti mode\n", 970 enable ? "entering" : "leaving"); 971 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, val); 972 973 return 0; 974 } 975 976 static void xgbe_set_mac_reg(struct xgbe_prv_data *pdata, 977 struct netdev_hw_addr *ha, unsigned int *mac_reg) 978 { 979 unsigned int mac_addr_hi, mac_addr_lo; 980 u8 *mac_addr; 981 982 mac_addr_lo = 0; 983 mac_addr_hi = 0; 984 985 if (ha) { 986 mac_addr = (u8 *)&mac_addr_lo; 987 mac_addr[0] = ha->addr[0]; 988 mac_addr[1] = ha->addr[1]; 989 mac_addr[2] = ha->addr[2]; 990 mac_addr[3] = ha->addr[3]; 991 mac_addr = (u8 *)&mac_addr_hi; 992 mac_addr[0] = ha->addr[4]; 993 mac_addr[1] = ha->addr[5]; 994 995 netif_dbg(pdata, drv, pdata->netdev, 996 "adding mac address %pM at %#x\n", 997 ha->addr, *mac_reg); 998 999 XGMAC_SET_BITS(mac_addr_hi, MAC_MACA1HR, AE, 1); 1000 } 1001 1002 XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_hi); 1003 *mac_reg += MAC_MACA_INC; 1004 XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_lo); 1005 *mac_reg += MAC_MACA_INC; 1006 } 1007 1008 static void xgbe_set_mac_addn_addrs(struct xgbe_prv_data *pdata) 1009 { 1010 struct net_device *netdev = pdata->netdev; 1011 struct netdev_hw_addr *ha; 1012 unsigned int mac_reg; 1013 unsigned int addn_macs; 1014 1015 mac_reg = MAC_MACA1HR; 1016 addn_macs = pdata->hw_feat.addn_mac; 1017 1018 if (netdev_uc_count(netdev) > addn_macs) { 1019 xgbe_set_promiscuous_mode(pdata, 1); 1020 } else { 1021 netdev_for_each_uc_addr(ha, netdev) { 1022 xgbe_set_mac_reg(pdata, ha, &mac_reg); 1023 addn_macs--; 1024 } 1025 1026 if (netdev_mc_count(netdev) > addn_macs) { 1027 xgbe_set_all_multicast_mode(pdata, 1); 1028 } else { 1029 netdev_for_each_mc_addr(ha, netdev) { 1030 xgbe_set_mac_reg(pdata, ha, &mac_reg); 1031 addn_macs--; 1032 } 1033 } 1034 } 1035 1036 /* Clear remaining additional MAC address entries */ 1037 while (addn_macs--) 1038 xgbe_set_mac_reg(pdata, NULL, &mac_reg); 1039 } 1040 1041 static void xgbe_set_mac_hash_table(struct xgbe_prv_data *pdata) 1042 { 1043 struct net_device *netdev = pdata->netdev; 1044 struct netdev_hw_addr *ha; 1045 unsigned int hash_reg; 1046 unsigned int hash_table_shift, hash_table_count; 1047 u32 hash_table[XGBE_MAC_HASH_TABLE_SIZE]; 1048 u32 crc; 1049 unsigned int i; 1050 1051 hash_table_shift = 26 - (pdata->hw_feat.hash_table_size >> 7); 1052 hash_table_count = pdata->hw_feat.hash_table_size / 32; 1053 memset(hash_table, 0, sizeof(hash_table)); 1054 1055 /* Build the MAC Hash Table register values */ 1056 netdev_for_each_uc_addr(ha, netdev) { 1057 crc = bitrev32(~crc32_le(~0, ha->addr, ETH_ALEN)); 1058 crc >>= hash_table_shift; 1059 hash_table[crc >> 5] |= (1 << (crc & 0x1f)); 1060 } 1061 1062 netdev_for_each_mc_addr(ha, netdev) { 1063 crc = bitrev32(~crc32_le(~0, ha->addr, ETH_ALEN)); 1064 crc >>= hash_table_shift; 1065 hash_table[crc >> 5] |= (1 << (crc & 0x1f)); 1066 } 1067 1068 /* Set the MAC Hash Table registers */ 1069 hash_reg = MAC_HTR0; 1070 for (i = 0; i < hash_table_count; i++) { 1071 XGMAC_IOWRITE(pdata, hash_reg, hash_table[i]); 1072 hash_reg += MAC_HTR_INC; 1073 } 1074 } 1075 1076 static int xgbe_add_mac_addresses(struct xgbe_prv_data *pdata) 1077 { 1078 if (pdata->hw_feat.hash_table_size) 1079 xgbe_set_mac_hash_table(pdata); 1080 else 1081 xgbe_set_mac_addn_addrs(pdata); 1082 1083 return 0; 1084 } 1085 1086 static int xgbe_set_mac_address(struct xgbe_prv_data *pdata, const u8 *addr) 1087 { 1088 unsigned int mac_addr_hi, mac_addr_lo; 1089 1090 mac_addr_hi = (addr[5] << 8) | (addr[4] << 0); 1091 mac_addr_lo = (addr[3] << 24) | (addr[2] << 16) | 1092 (addr[1] << 8) | (addr[0] << 0); 1093 1094 XGMAC_IOWRITE(pdata, MAC_MACA0HR, mac_addr_hi); 1095 XGMAC_IOWRITE(pdata, MAC_MACA0LR, mac_addr_lo); 1096 1097 return 0; 1098 } 1099 1100 static int xgbe_config_rx_mode(struct xgbe_prv_data *pdata) 1101 { 1102 struct net_device *netdev = pdata->netdev; 1103 unsigned int pr_mode, am_mode; 1104 1105 pr_mode = ((netdev->flags & IFF_PROMISC) != 0); 1106 am_mode = ((netdev->flags & IFF_ALLMULTI) != 0); 1107 1108 xgbe_set_promiscuous_mode(pdata, pr_mode); 1109 xgbe_set_all_multicast_mode(pdata, am_mode); 1110 1111 xgbe_add_mac_addresses(pdata); 1112 1113 return 0; 1114 } 1115 1116 static int xgbe_clr_gpio(struct xgbe_prv_data *pdata, unsigned int gpio) 1117 { 1118 unsigned int reg; 1119 1120 if (gpio > 15) 1121 return -EINVAL; 1122 1123 reg = XGMAC_IOREAD(pdata, MAC_GPIOSR); 1124 1125 reg &= ~(1 << (gpio + 16)); 1126 XGMAC_IOWRITE(pdata, MAC_GPIOSR, reg); 1127 1128 return 0; 1129 } 1130 1131 static int xgbe_set_gpio(struct xgbe_prv_data *pdata, unsigned int gpio) 1132 { 1133 unsigned int reg; 1134 1135 if (gpio > 15) 1136 return -EINVAL; 1137 1138 reg = XGMAC_IOREAD(pdata, MAC_GPIOSR); 1139 1140 reg |= (1 << (gpio + 16)); 1141 XGMAC_IOWRITE(pdata, MAC_GPIOSR, reg); 1142 1143 return 0; 1144 } 1145 1146 static int xgbe_read_mmd_regs_v2(struct xgbe_prv_data *pdata, int prtad, 1147 int mmd_reg) 1148 { 1149 unsigned long flags; 1150 unsigned int mmd_address, index, offset; 1151 int mmd_data; 1152 1153 if (mmd_reg & XGBE_ADDR_C45) 1154 mmd_address = mmd_reg & ~XGBE_ADDR_C45; 1155 else 1156 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); 1157 1158 /* The PCS registers are accessed using mmio. The underlying 1159 * management interface uses indirect addressing to access the MMD 1160 * register sets. This requires accessing of the PCS register in two 1161 * phases, an address phase and a data phase. 1162 * 1163 * The mmio interface is based on 16-bit offsets and values. All 1164 * register offsets must therefore be adjusted by left shifting the 1165 * offset 1 bit and reading 16 bits of data. 1166 */ 1167 mmd_address <<= 1; 1168 index = mmd_address & ~pdata->xpcs_window_mask; 1169 offset = pdata->xpcs_window + (mmd_address & pdata->xpcs_window_mask); 1170 1171 spin_lock_irqsave(&pdata->xpcs_lock, flags); 1172 XPCS32_IOWRITE(pdata, pdata->xpcs_window_sel_reg, index); 1173 mmd_data = XPCS16_IOREAD(pdata, offset); 1174 spin_unlock_irqrestore(&pdata->xpcs_lock, flags); 1175 1176 return mmd_data; 1177 } 1178 1179 static void xgbe_write_mmd_regs_v2(struct xgbe_prv_data *pdata, int prtad, 1180 int mmd_reg, int mmd_data) 1181 { 1182 unsigned long flags; 1183 unsigned int mmd_address, index, offset; 1184 1185 if (mmd_reg & XGBE_ADDR_C45) 1186 mmd_address = mmd_reg & ~XGBE_ADDR_C45; 1187 else 1188 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); 1189 1190 /* The PCS registers are accessed using mmio. The underlying 1191 * management interface uses indirect addressing to access the MMD 1192 * register sets. This requires accessing of the PCS register in two 1193 * phases, an address phase and a data phase. 1194 * 1195 * The mmio interface is based on 16-bit offsets and values. All 1196 * register offsets must therefore be adjusted by left shifting the 1197 * offset 1 bit and writing 16 bits of data. 1198 */ 1199 mmd_address <<= 1; 1200 index = mmd_address & ~pdata->xpcs_window_mask; 1201 offset = pdata->xpcs_window + (mmd_address & pdata->xpcs_window_mask); 1202 1203 spin_lock_irqsave(&pdata->xpcs_lock, flags); 1204 XPCS32_IOWRITE(pdata, pdata->xpcs_window_sel_reg, index); 1205 XPCS16_IOWRITE(pdata, offset, mmd_data); 1206 spin_unlock_irqrestore(&pdata->xpcs_lock, flags); 1207 } 1208 1209 static int xgbe_read_mmd_regs_v1(struct xgbe_prv_data *pdata, int prtad, 1210 int mmd_reg) 1211 { 1212 unsigned long flags; 1213 unsigned int mmd_address; 1214 int mmd_data; 1215 1216 if (mmd_reg & XGBE_ADDR_C45) 1217 mmd_address = mmd_reg & ~XGBE_ADDR_C45; 1218 else 1219 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); 1220 1221 /* The PCS registers are accessed using mmio. The underlying APB3 1222 * management interface uses indirect addressing to access the MMD 1223 * register sets. This requires accessing of the PCS register in two 1224 * phases, an address phase and a data phase. 1225 * 1226 * The mmio interface is based on 32-bit offsets and values. All 1227 * register offsets must therefore be adjusted by left shifting the 1228 * offset 2 bits and reading 32 bits of data. 1229 */ 1230 spin_lock_irqsave(&pdata->xpcs_lock, flags); 1231 XPCS32_IOWRITE(pdata, PCS_V1_WINDOW_SELECT, mmd_address >> 8); 1232 mmd_data = XPCS32_IOREAD(pdata, (mmd_address & 0xff) << 2); 1233 spin_unlock_irqrestore(&pdata->xpcs_lock, flags); 1234 1235 return mmd_data; 1236 } 1237 1238 static void xgbe_write_mmd_regs_v1(struct xgbe_prv_data *pdata, int prtad, 1239 int mmd_reg, int mmd_data) 1240 { 1241 unsigned int mmd_address; 1242 unsigned long flags; 1243 1244 if (mmd_reg & XGBE_ADDR_C45) 1245 mmd_address = mmd_reg & ~XGBE_ADDR_C45; 1246 else 1247 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); 1248 1249 /* The PCS registers are accessed using mmio. The underlying APB3 1250 * management interface uses indirect addressing to access the MMD 1251 * register sets. This requires accessing of the PCS register in two 1252 * phases, an address phase and a data phase. 1253 * 1254 * The mmio interface is based on 32-bit offsets and values. All 1255 * register offsets must therefore be adjusted by left shifting the 1256 * offset 2 bits and writing 32 bits of data. 1257 */ 1258 spin_lock_irqsave(&pdata->xpcs_lock, flags); 1259 XPCS32_IOWRITE(pdata, PCS_V1_WINDOW_SELECT, mmd_address >> 8); 1260 XPCS32_IOWRITE(pdata, (mmd_address & 0xff) << 2, mmd_data); 1261 spin_unlock_irqrestore(&pdata->xpcs_lock, flags); 1262 } 1263 1264 static int xgbe_read_mmd_regs(struct xgbe_prv_data *pdata, int prtad, 1265 int mmd_reg) 1266 { 1267 switch (pdata->vdata->xpcs_access) { 1268 case XGBE_XPCS_ACCESS_V1: 1269 return xgbe_read_mmd_regs_v1(pdata, prtad, mmd_reg); 1270 1271 case XGBE_XPCS_ACCESS_V2: 1272 default: 1273 return xgbe_read_mmd_regs_v2(pdata, prtad, mmd_reg); 1274 } 1275 } 1276 1277 static void xgbe_write_mmd_regs(struct xgbe_prv_data *pdata, int prtad, 1278 int mmd_reg, int mmd_data) 1279 { 1280 switch (pdata->vdata->xpcs_access) { 1281 case XGBE_XPCS_ACCESS_V1: 1282 return xgbe_write_mmd_regs_v1(pdata, prtad, mmd_reg, mmd_data); 1283 1284 case XGBE_XPCS_ACCESS_V2: 1285 default: 1286 return xgbe_write_mmd_regs_v2(pdata, prtad, mmd_reg, mmd_data); 1287 } 1288 } 1289 1290 static unsigned int xgbe_create_mdio_sca_c22(int port, int reg) 1291 { 1292 unsigned int mdio_sca; 1293 1294 mdio_sca = 0; 1295 XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, RA, reg); 1296 XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, PA, port); 1297 1298 return mdio_sca; 1299 } 1300 1301 static unsigned int xgbe_create_mdio_sca_c45(int port, unsigned int da, int reg) 1302 { 1303 unsigned int mdio_sca; 1304 1305 mdio_sca = 0; 1306 XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, RA, reg); 1307 XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, PA, port); 1308 XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, DA, da); 1309 1310 return mdio_sca; 1311 } 1312 1313 static int xgbe_write_ext_mii_regs(struct xgbe_prv_data *pdata, 1314 unsigned int mdio_sca, u16 val) 1315 { 1316 unsigned int mdio_sccd; 1317 1318 reinit_completion(&pdata->mdio_complete); 1319 1320 XGMAC_IOWRITE(pdata, MAC_MDIOSCAR, mdio_sca); 1321 1322 mdio_sccd = 0; 1323 XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, DATA, val); 1324 XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, CMD, 1); 1325 XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, BUSY, 1); 1326 XGMAC_IOWRITE(pdata, MAC_MDIOSCCDR, mdio_sccd); 1327 1328 if (!wait_for_completion_timeout(&pdata->mdio_complete, HZ)) { 1329 netdev_err(pdata->netdev, "mdio write operation timed out\n"); 1330 return -ETIMEDOUT; 1331 } 1332 1333 return 0; 1334 } 1335 1336 static int xgbe_write_ext_mii_regs_c22(struct xgbe_prv_data *pdata, int addr, 1337 int reg, u16 val) 1338 { 1339 unsigned int mdio_sca; 1340 1341 mdio_sca = xgbe_create_mdio_sca_c22(addr, reg); 1342 1343 return xgbe_write_ext_mii_regs(pdata, mdio_sca, val); 1344 } 1345 1346 static int xgbe_write_ext_mii_regs_c45(struct xgbe_prv_data *pdata, int addr, 1347 int devad, int reg, u16 val) 1348 { 1349 unsigned int mdio_sca; 1350 1351 mdio_sca = xgbe_create_mdio_sca_c45(addr, devad, reg); 1352 1353 return xgbe_write_ext_mii_regs(pdata, mdio_sca, val); 1354 } 1355 1356 static int xgbe_read_ext_mii_regs(struct xgbe_prv_data *pdata, 1357 unsigned int mdio_sca) 1358 { 1359 unsigned int mdio_sccd; 1360 1361 reinit_completion(&pdata->mdio_complete); 1362 1363 XGMAC_IOWRITE(pdata, MAC_MDIOSCAR, mdio_sca); 1364 1365 mdio_sccd = 0; 1366 XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, CMD, 3); 1367 XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, BUSY, 1); 1368 XGMAC_IOWRITE(pdata, MAC_MDIOSCCDR, mdio_sccd); 1369 1370 if (!wait_for_completion_timeout(&pdata->mdio_complete, HZ)) { 1371 netdev_err(pdata->netdev, "mdio read operation timed out\n"); 1372 return -ETIMEDOUT; 1373 } 1374 1375 return XGMAC_IOREAD_BITS(pdata, MAC_MDIOSCCDR, DATA); 1376 } 1377 1378 static int xgbe_read_ext_mii_regs_c22(struct xgbe_prv_data *pdata, int addr, 1379 int reg) 1380 { 1381 unsigned int mdio_sca; 1382 1383 mdio_sca = xgbe_create_mdio_sca_c22(addr, reg); 1384 1385 return xgbe_read_ext_mii_regs(pdata, mdio_sca); 1386 } 1387 1388 static int xgbe_read_ext_mii_regs_c45(struct xgbe_prv_data *pdata, int addr, 1389 int devad, int reg) 1390 { 1391 unsigned int mdio_sca; 1392 1393 mdio_sca = xgbe_create_mdio_sca_c45(addr, devad, reg); 1394 1395 return xgbe_read_ext_mii_regs(pdata, mdio_sca); 1396 } 1397 1398 static int xgbe_set_ext_mii_mode(struct xgbe_prv_data *pdata, unsigned int port, 1399 enum xgbe_mdio_mode mode) 1400 { 1401 unsigned int reg_val = XGMAC_IOREAD(pdata, MAC_MDIOCL22R); 1402 1403 switch (mode) { 1404 case XGBE_MDIO_MODE_CL22: 1405 if (port > XGMAC_MAX_C22_PORT) 1406 return -EINVAL; 1407 reg_val |= (1 << port); 1408 break; 1409 case XGBE_MDIO_MODE_CL45: 1410 break; 1411 default: 1412 return -EINVAL; 1413 } 1414 1415 XGMAC_IOWRITE(pdata, MAC_MDIOCL22R, reg_val); 1416 1417 return 0; 1418 } 1419 1420 static int xgbe_tx_complete(struct xgbe_ring_desc *rdesc) 1421 { 1422 return !XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN); 1423 } 1424 1425 static int xgbe_disable_rx_csum(struct xgbe_prv_data *pdata) 1426 { 1427 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 0); 1428 1429 return 0; 1430 } 1431 1432 static int xgbe_enable_rx_csum(struct xgbe_prv_data *pdata) 1433 { 1434 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 1); 1435 1436 return 0; 1437 } 1438 1439 static void xgbe_tx_desc_reset(struct xgbe_ring_data *rdata) 1440 { 1441 struct xgbe_ring_desc *rdesc = rdata->rdesc; 1442 1443 /* Reset the Tx descriptor 1444 * Set buffer 1 (lo) address to zero 1445 * Set buffer 1 (hi) address to zero 1446 * Reset all other control bits (IC, TTSE, B2L & B1L) 1447 * Reset all other control bits (OWN, CTXT, FD, LD, CPC, CIC, etc) 1448 */ 1449 rdesc->desc0 = 0; 1450 rdesc->desc1 = 0; 1451 rdesc->desc2 = 0; 1452 rdesc->desc3 = 0; 1453 1454 /* Make sure ownership is written to the descriptor */ 1455 dma_wmb(); 1456 } 1457 1458 static void xgbe_tx_desc_init(struct xgbe_channel *channel) 1459 { 1460 struct xgbe_ring *ring = channel->tx_ring; 1461 struct xgbe_ring_data *rdata; 1462 int i; 1463 int start_index = ring->cur; 1464 1465 DBGPR("-->tx_desc_init\n"); 1466 1467 /* Initialze all descriptors */ 1468 for (i = 0; i < ring->rdesc_count; i++) { 1469 rdata = XGBE_GET_DESC_DATA(ring, i); 1470 1471 /* Initialize Tx descriptor */ 1472 xgbe_tx_desc_reset(rdata); 1473 } 1474 1475 /* Update the total number of Tx descriptors */ 1476 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDRLR, ring->rdesc_count - 1); 1477 1478 /* Update the starting address of descriptor ring */ 1479 rdata = XGBE_GET_DESC_DATA(ring, start_index); 1480 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDLR_HI, 1481 upper_32_bits(rdata->rdesc_dma)); 1482 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDLR_LO, 1483 lower_32_bits(rdata->rdesc_dma)); 1484 1485 DBGPR("<--tx_desc_init\n"); 1486 } 1487 1488 static void xgbe_rx_desc_reset(struct xgbe_prv_data *pdata, 1489 struct xgbe_ring_data *rdata, unsigned int index) 1490 { 1491 struct xgbe_ring_desc *rdesc = rdata->rdesc; 1492 unsigned int rx_usecs = pdata->rx_usecs; 1493 unsigned int rx_frames = pdata->rx_frames; 1494 unsigned int inte; 1495 dma_addr_t hdr_dma, buf_dma; 1496 1497 if (!rx_usecs && !rx_frames) { 1498 /* No coalescing, interrupt for every descriptor */ 1499 inte = 1; 1500 } else { 1501 /* Set interrupt based on Rx frame coalescing setting */ 1502 if (rx_frames && !((index + 1) % rx_frames)) 1503 inte = 1; 1504 else 1505 inte = 0; 1506 } 1507 1508 /* Reset the Rx descriptor 1509 * Set buffer 1 (lo) address to header dma address (lo) 1510 * Set buffer 1 (hi) address to header dma address (hi) 1511 * Set buffer 2 (lo) address to buffer dma address (lo) 1512 * Set buffer 2 (hi) address to buffer dma address (hi) and 1513 * set control bits OWN and INTE 1514 */ 1515 hdr_dma = rdata->rx.hdr.dma_base + rdata->rx.hdr.dma_off; 1516 buf_dma = rdata->rx.buf.dma_base + rdata->rx.buf.dma_off; 1517 rdesc->desc0 = cpu_to_le32(lower_32_bits(hdr_dma)); 1518 rdesc->desc1 = cpu_to_le32(upper_32_bits(hdr_dma)); 1519 rdesc->desc2 = cpu_to_le32(lower_32_bits(buf_dma)); 1520 rdesc->desc3 = cpu_to_le32(upper_32_bits(buf_dma)); 1521 1522 XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, INTE, inte); 1523 1524 /* Since the Rx DMA engine is likely running, make sure everything 1525 * is written to the descriptor(s) before setting the OWN bit 1526 * for the descriptor 1527 */ 1528 dma_wmb(); 1529 1530 XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN, 1); 1531 1532 /* Make sure ownership is written to the descriptor */ 1533 dma_wmb(); 1534 } 1535 1536 static void xgbe_rx_desc_init(struct xgbe_channel *channel) 1537 { 1538 struct xgbe_prv_data *pdata = channel->pdata; 1539 struct xgbe_ring *ring = channel->rx_ring; 1540 struct xgbe_ring_data *rdata; 1541 unsigned int start_index = ring->cur; 1542 unsigned int i; 1543 1544 DBGPR("-->rx_desc_init\n"); 1545 1546 /* Initialize all descriptors */ 1547 for (i = 0; i < ring->rdesc_count; i++) { 1548 rdata = XGBE_GET_DESC_DATA(ring, i); 1549 1550 /* Initialize Rx descriptor */ 1551 xgbe_rx_desc_reset(pdata, rdata, i); 1552 } 1553 1554 /* Update the total number of Rx descriptors */ 1555 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDRLR, ring->rdesc_count - 1); 1556 1557 /* Update the starting address of descriptor ring */ 1558 rdata = XGBE_GET_DESC_DATA(ring, start_index); 1559 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDLR_HI, 1560 upper_32_bits(rdata->rdesc_dma)); 1561 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDLR_LO, 1562 lower_32_bits(rdata->rdesc_dma)); 1563 1564 /* Update the Rx Descriptor Tail Pointer */ 1565 rdata = XGBE_GET_DESC_DATA(ring, start_index + ring->rdesc_count - 1); 1566 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO, 1567 lower_32_bits(rdata->rdesc_dma)); 1568 1569 DBGPR("<--rx_desc_init\n"); 1570 } 1571 1572 static void xgbe_update_tstamp_addend(struct xgbe_prv_data *pdata, 1573 unsigned int addend) 1574 { 1575 unsigned int count = 10000; 1576 1577 /* Set the addend register value and tell the device */ 1578 XGMAC_IOWRITE(pdata, MAC_TSAR, addend); 1579 XGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSADDREG, 1); 1580 1581 /* Wait for addend update to complete */ 1582 while (--count && XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSADDREG)) 1583 udelay(5); 1584 1585 if (!count) 1586 netdev_err(pdata->netdev, 1587 "timed out updating timestamp addend register\n"); 1588 } 1589 1590 static void xgbe_set_tstamp_time(struct xgbe_prv_data *pdata, unsigned int sec, 1591 unsigned int nsec) 1592 { 1593 unsigned int count = 10000; 1594 1595 /* Set the time values and tell the device */ 1596 XGMAC_IOWRITE(pdata, MAC_STSUR, sec); 1597 XGMAC_IOWRITE(pdata, MAC_STNUR, nsec); 1598 XGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSINIT, 1); 1599 1600 /* Wait for time update to complete */ 1601 while (--count && XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSINIT)) 1602 udelay(5); 1603 1604 if (!count) 1605 netdev_err(pdata->netdev, "timed out initializing timestamp\n"); 1606 } 1607 1608 static u64 xgbe_get_tstamp_time(struct xgbe_prv_data *pdata) 1609 { 1610 u64 nsec; 1611 1612 nsec = XGMAC_IOREAD(pdata, MAC_STSR); 1613 nsec *= NSEC_PER_SEC; 1614 nsec += XGMAC_IOREAD(pdata, MAC_STNR); 1615 1616 return nsec; 1617 } 1618 1619 static u64 xgbe_get_tx_tstamp(struct xgbe_prv_data *pdata) 1620 { 1621 unsigned int tx_snr, tx_ssr; 1622 u64 nsec; 1623 1624 if (pdata->vdata->tx_tstamp_workaround) { 1625 tx_snr = XGMAC_IOREAD(pdata, MAC_TXSNR); 1626 tx_ssr = XGMAC_IOREAD(pdata, MAC_TXSSR); 1627 } else { 1628 tx_ssr = XGMAC_IOREAD(pdata, MAC_TXSSR); 1629 tx_snr = XGMAC_IOREAD(pdata, MAC_TXSNR); 1630 } 1631 1632 if (XGMAC_GET_BITS(tx_snr, MAC_TXSNR, TXTSSTSMIS)) 1633 return 0; 1634 1635 nsec = tx_ssr; 1636 nsec *= NSEC_PER_SEC; 1637 nsec += tx_snr; 1638 1639 return nsec; 1640 } 1641 1642 static void xgbe_get_rx_tstamp(struct xgbe_packet_data *packet, 1643 struct xgbe_ring_desc *rdesc) 1644 { 1645 u64 nsec; 1646 1647 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_CONTEXT_DESC3, TSA) && 1648 !XGMAC_GET_BITS_LE(rdesc->desc3, RX_CONTEXT_DESC3, TSD)) { 1649 nsec = le32_to_cpu(rdesc->desc1); 1650 nsec <<= 32; 1651 nsec |= le32_to_cpu(rdesc->desc0); 1652 if (nsec != 0xffffffffffffffffULL) { 1653 packet->rx_tstamp = nsec; 1654 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1655 RX_TSTAMP, 1); 1656 } 1657 } 1658 } 1659 1660 static int xgbe_config_tstamp(struct xgbe_prv_data *pdata, 1661 unsigned int mac_tscr) 1662 { 1663 /* Set one nano-second accuracy */ 1664 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCTRLSSR, 1); 1665 1666 /* Set fine timestamp update */ 1667 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCFUPDT, 1); 1668 1669 /* Overwrite earlier timestamps */ 1670 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TXTSSTSM, 1); 1671 1672 XGMAC_IOWRITE(pdata, MAC_TSCR, mac_tscr); 1673 1674 /* Exit if timestamping is not enabled */ 1675 if (!XGMAC_GET_BITS(mac_tscr, MAC_TSCR, TSENA)) 1676 return 0; 1677 1678 /* Initialize time registers */ 1679 XGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SSINC, XGBE_TSTAMP_SSINC); 1680 XGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SNSINC, XGBE_TSTAMP_SNSINC); 1681 xgbe_update_tstamp_addend(pdata, pdata->tstamp_addend); 1682 xgbe_set_tstamp_time(pdata, 0, 0); 1683 1684 /* Initialize the timecounter */ 1685 timecounter_init(&pdata->tstamp_tc, &pdata->tstamp_cc, 1686 ktime_to_ns(ktime_get_real())); 1687 1688 return 0; 1689 } 1690 1691 static void xgbe_tx_start_xmit(struct xgbe_channel *channel, 1692 struct xgbe_ring *ring) 1693 { 1694 struct xgbe_prv_data *pdata = channel->pdata; 1695 struct xgbe_ring_data *rdata; 1696 1697 /* Make sure everything is written before the register write */ 1698 wmb(); 1699 1700 /* Issue a poll command to Tx DMA by writing address 1701 * of next immediate free descriptor */ 1702 rdata = XGBE_GET_DESC_DATA(ring, ring->cur); 1703 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDTR_LO, 1704 lower_32_bits(rdata->rdesc_dma)); 1705 1706 /* Start the Tx timer */ 1707 if (pdata->tx_usecs && !channel->tx_timer_active) { 1708 channel->tx_timer_active = 1; 1709 mod_timer(&channel->tx_timer, 1710 jiffies + usecs_to_jiffies(pdata->tx_usecs)); 1711 } 1712 1713 ring->tx.xmit_more = 0; 1714 } 1715 1716 static void xgbe_dev_xmit(struct xgbe_channel *channel) 1717 { 1718 struct xgbe_prv_data *pdata = channel->pdata; 1719 struct xgbe_ring *ring = channel->tx_ring; 1720 struct xgbe_ring_data *rdata; 1721 struct xgbe_ring_desc *rdesc; 1722 struct xgbe_packet_data *packet = &ring->packet_data; 1723 unsigned int tx_packets, tx_bytes; 1724 unsigned int csum, tso, vlan, vxlan; 1725 unsigned int tso_context, vlan_context; 1726 unsigned int tx_set_ic; 1727 int start_index = ring->cur; 1728 int cur_index = ring->cur; 1729 int i; 1730 1731 DBGPR("-->xgbe_dev_xmit\n"); 1732 1733 tx_packets = packet->tx_packets; 1734 tx_bytes = packet->tx_bytes; 1735 1736 csum = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, 1737 CSUM_ENABLE); 1738 tso = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, 1739 TSO_ENABLE); 1740 vlan = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, 1741 VLAN_CTAG); 1742 vxlan = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, 1743 VXLAN); 1744 1745 if (tso && (packet->mss != ring->tx.cur_mss)) 1746 tso_context = 1; 1747 else 1748 tso_context = 0; 1749 1750 if (vlan && (packet->vlan_ctag != ring->tx.cur_vlan_ctag)) 1751 vlan_context = 1; 1752 else 1753 vlan_context = 0; 1754 1755 /* Determine if an interrupt should be generated for this Tx: 1756 * Interrupt: 1757 * - Tx frame count exceeds the frame count setting 1758 * - Addition of Tx frame count to the frame count since the 1759 * last interrupt was set exceeds the frame count setting 1760 * No interrupt: 1761 * - No frame count setting specified (ethtool -C ethX tx-frames 0) 1762 * - Addition of Tx frame count to the frame count since the 1763 * last interrupt was set does not exceed the frame count setting 1764 */ 1765 ring->coalesce_count += tx_packets; 1766 if (!pdata->tx_frames) 1767 tx_set_ic = 0; 1768 else if (tx_packets > pdata->tx_frames) 1769 tx_set_ic = 1; 1770 else if ((ring->coalesce_count % pdata->tx_frames) < tx_packets) 1771 tx_set_ic = 1; 1772 else 1773 tx_set_ic = 0; 1774 1775 rdata = XGBE_GET_DESC_DATA(ring, cur_index); 1776 rdesc = rdata->rdesc; 1777 1778 /* Create a context descriptor if this is a TSO packet */ 1779 if (tso_context || vlan_context) { 1780 if (tso_context) { 1781 netif_dbg(pdata, tx_queued, pdata->netdev, 1782 "TSO context descriptor, mss=%u\n", 1783 packet->mss); 1784 1785 /* Set the MSS size */ 1786 XGMAC_SET_BITS_LE(rdesc->desc2, TX_CONTEXT_DESC2, 1787 MSS, packet->mss); 1788 1789 /* Mark it as a CONTEXT descriptor */ 1790 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, 1791 CTXT, 1); 1792 1793 /* Indicate this descriptor contains the MSS */ 1794 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, 1795 TCMSSV, 1); 1796 1797 ring->tx.cur_mss = packet->mss; 1798 } 1799 1800 if (vlan_context) { 1801 netif_dbg(pdata, tx_queued, pdata->netdev, 1802 "VLAN context descriptor, ctag=%u\n", 1803 packet->vlan_ctag); 1804 1805 /* Mark it as a CONTEXT descriptor */ 1806 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, 1807 CTXT, 1); 1808 1809 /* Set the VLAN tag */ 1810 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, 1811 VT, packet->vlan_ctag); 1812 1813 /* Indicate this descriptor contains the VLAN tag */ 1814 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, 1815 VLTV, 1); 1816 1817 ring->tx.cur_vlan_ctag = packet->vlan_ctag; 1818 } 1819 1820 cur_index++; 1821 rdata = XGBE_GET_DESC_DATA(ring, cur_index); 1822 rdesc = rdata->rdesc; 1823 } 1824 1825 /* Update buffer address (for TSO this is the header) */ 1826 rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->skb_dma)); 1827 rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->skb_dma)); 1828 1829 /* Update the buffer length */ 1830 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, HL_B1L, 1831 rdata->skb_dma_len); 1832 1833 /* VLAN tag insertion check */ 1834 if (vlan) 1835 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, VTIR, 1836 TX_NORMAL_DESC2_VLAN_INSERT); 1837 1838 /* Timestamp enablement check */ 1839 if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP)) 1840 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, TTSE, 1); 1841 1842 /* Mark it as First Descriptor */ 1843 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, FD, 1); 1844 1845 /* Mark it as a NORMAL descriptor */ 1846 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT, 0); 1847 1848 /* Set OWN bit if not the first descriptor */ 1849 if (cur_index != start_index) 1850 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1); 1851 1852 if (tso) { 1853 /* Enable TSO */ 1854 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TSE, 1); 1855 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TCPPL, 1856 packet->tcp_payload_len); 1857 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TCPHDRLEN, 1858 packet->tcp_header_len / 4); 1859 1860 pdata->ext_stats.tx_tso_packets += tx_packets; 1861 } else { 1862 /* Enable CRC and Pad Insertion */ 1863 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CPC, 0); 1864 1865 /* Enable HW CSUM */ 1866 if (csum) 1867 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, 1868 CIC, 0x3); 1869 1870 /* Set the total length to be transmitted */ 1871 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, FL, 1872 packet->length); 1873 } 1874 1875 if (vxlan) { 1876 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, VNP, 1877 TX_NORMAL_DESC3_VXLAN_PACKET); 1878 1879 pdata->ext_stats.tx_vxlan_packets += packet->tx_packets; 1880 } 1881 1882 for (i = cur_index - start_index + 1; i < packet->rdesc_count; i++) { 1883 cur_index++; 1884 rdata = XGBE_GET_DESC_DATA(ring, cur_index); 1885 rdesc = rdata->rdesc; 1886 1887 /* Update buffer address */ 1888 rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->skb_dma)); 1889 rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->skb_dma)); 1890 1891 /* Update the buffer length */ 1892 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, HL_B1L, 1893 rdata->skb_dma_len); 1894 1895 /* Set OWN bit */ 1896 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1); 1897 1898 /* Mark it as NORMAL descriptor */ 1899 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT, 0); 1900 1901 /* Enable HW CSUM */ 1902 if (csum) 1903 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, 1904 CIC, 0x3); 1905 } 1906 1907 /* Set LAST bit for the last descriptor */ 1908 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, LD, 1); 1909 1910 /* Set IC bit based on Tx coalescing settings */ 1911 if (tx_set_ic) 1912 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, IC, 1); 1913 1914 /* Save the Tx info to report back during cleanup */ 1915 rdata->tx.packets = tx_packets; 1916 rdata->tx.bytes = tx_bytes; 1917 1918 pdata->ext_stats.txq_packets[channel->queue_index] += tx_packets; 1919 pdata->ext_stats.txq_bytes[channel->queue_index] += tx_bytes; 1920 1921 /* In case the Tx DMA engine is running, make sure everything 1922 * is written to the descriptor(s) before setting the OWN bit 1923 * for the first descriptor 1924 */ 1925 dma_wmb(); 1926 1927 /* Set OWN bit for the first descriptor */ 1928 rdata = XGBE_GET_DESC_DATA(ring, start_index); 1929 rdesc = rdata->rdesc; 1930 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1); 1931 1932 if (netif_msg_tx_queued(pdata)) 1933 xgbe_dump_tx_desc(pdata, ring, start_index, 1934 packet->rdesc_count, 1); 1935 1936 /* Make sure ownership is written to the descriptor */ 1937 smp_wmb(); 1938 1939 ring->cur = cur_index + 1; 1940 if (!netdev_xmit_more() || 1941 netif_xmit_stopped(netdev_get_tx_queue(pdata->netdev, 1942 channel->queue_index))) 1943 xgbe_tx_start_xmit(channel, ring); 1944 else 1945 ring->tx.xmit_more = 1; 1946 1947 DBGPR(" %s: descriptors %u to %u written\n", 1948 channel->name, start_index & (ring->rdesc_count - 1), 1949 (ring->cur - 1) & (ring->rdesc_count - 1)); 1950 1951 DBGPR("<--xgbe_dev_xmit\n"); 1952 } 1953 1954 static int xgbe_dev_read(struct xgbe_channel *channel) 1955 { 1956 struct xgbe_prv_data *pdata = channel->pdata; 1957 struct xgbe_ring *ring = channel->rx_ring; 1958 struct xgbe_ring_data *rdata; 1959 struct xgbe_ring_desc *rdesc; 1960 struct xgbe_packet_data *packet = &ring->packet_data; 1961 struct net_device *netdev = pdata->netdev; 1962 unsigned int err, etlt, l34t; 1963 1964 DBGPR("-->xgbe_dev_read: cur = %d\n", ring->cur); 1965 1966 rdata = XGBE_GET_DESC_DATA(ring, ring->cur); 1967 rdesc = rdata->rdesc; 1968 1969 /* Check for data availability */ 1970 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN)) 1971 return 1; 1972 1973 /* Make sure descriptor fields are read after reading the OWN bit */ 1974 dma_rmb(); 1975 1976 if (netif_msg_rx_status(pdata)) 1977 xgbe_dump_rx_desc(pdata, ring, ring->cur); 1978 1979 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CTXT)) { 1980 /* Timestamp Context Descriptor */ 1981 xgbe_get_rx_tstamp(packet, rdesc); 1982 1983 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1984 CONTEXT, 1); 1985 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1986 CONTEXT_NEXT, 0); 1987 return 0; 1988 } 1989 1990 /* Normal Descriptor, be sure Context Descriptor bit is off */ 1991 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, CONTEXT, 0); 1992 1993 /* Indicate if a Context Descriptor is next */ 1994 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CDA)) 1995 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1996 CONTEXT_NEXT, 1); 1997 1998 /* Get the header length */ 1999 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, FD)) { 2000 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 2001 FIRST, 1); 2002 rdata->rx.hdr_len = XGMAC_GET_BITS_LE(rdesc->desc2, 2003 RX_NORMAL_DESC2, HL); 2004 if (rdata->rx.hdr_len) 2005 pdata->ext_stats.rx_split_header_packets++; 2006 } else { 2007 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 2008 FIRST, 0); 2009 } 2010 2011 /* Get the RSS hash */ 2012 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, RSV)) { 2013 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 2014 RSS_HASH, 1); 2015 2016 packet->rss_hash = le32_to_cpu(rdesc->desc1); 2017 2018 l34t = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, L34T); 2019 switch (l34t) { 2020 case RX_DESC3_L34T_IPV4_TCP: 2021 case RX_DESC3_L34T_IPV4_UDP: 2022 case RX_DESC3_L34T_IPV6_TCP: 2023 case RX_DESC3_L34T_IPV6_UDP: 2024 packet->rss_hash_type = PKT_HASH_TYPE_L4; 2025 break; 2026 default: 2027 packet->rss_hash_type = PKT_HASH_TYPE_L3; 2028 } 2029 } 2030 2031 /* Not all the data has been transferred for this packet */ 2032 if (!XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, LD)) 2033 return 0; 2034 2035 /* This is the last of the data for this packet */ 2036 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 2037 LAST, 1); 2038 2039 /* Get the packet length */ 2040 rdata->rx.len = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, PL); 2041 2042 /* Set checksum done indicator as appropriate */ 2043 if (netdev->features & NETIF_F_RXCSUM) { 2044 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 2045 CSUM_DONE, 1); 2046 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 2047 TNPCSUM_DONE, 1); 2048 } 2049 2050 /* Set the tunneled packet indicator */ 2051 if (XGMAC_GET_BITS_LE(rdesc->desc2, RX_NORMAL_DESC2, TNP)) { 2052 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 2053 TNP, 1); 2054 pdata->ext_stats.rx_vxlan_packets++; 2055 2056 l34t = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, L34T); 2057 switch (l34t) { 2058 case RX_DESC3_L34T_IPV4_UNKNOWN: 2059 case RX_DESC3_L34T_IPV6_UNKNOWN: 2060 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 2061 TNPCSUM_DONE, 0); 2062 break; 2063 } 2064 } 2065 2066 /* Check for errors (only valid in last descriptor) */ 2067 err = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ES); 2068 etlt = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ETLT); 2069 netif_dbg(pdata, rx_status, netdev, "err=%u, etlt=%#x\n", err, etlt); 2070 2071 if (!err || !etlt) { 2072 /* No error if err is 0 or etlt is 0 */ 2073 if ((etlt == 0x09) && 2074 (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)) { 2075 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 2076 VLAN_CTAG, 1); 2077 packet->vlan_ctag = XGMAC_GET_BITS_LE(rdesc->desc0, 2078 RX_NORMAL_DESC0, 2079 OVT); 2080 netif_dbg(pdata, rx_status, netdev, "vlan-ctag=%#06x\n", 2081 packet->vlan_ctag); 2082 } 2083 } else { 2084 unsigned int tnp = XGMAC_GET_BITS(packet->attributes, 2085 RX_PACKET_ATTRIBUTES, TNP); 2086 2087 if ((etlt == 0x05) || (etlt == 0x06)) { 2088 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 2089 CSUM_DONE, 0); 2090 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 2091 TNPCSUM_DONE, 0); 2092 pdata->ext_stats.rx_csum_errors++; 2093 } else if (tnp && ((etlt == 0x09) || (etlt == 0x0a))) { 2094 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 2095 CSUM_DONE, 0); 2096 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 2097 TNPCSUM_DONE, 0); 2098 pdata->ext_stats.rx_vxlan_csum_errors++; 2099 } else { 2100 XGMAC_SET_BITS(packet->errors, RX_PACKET_ERRORS, 2101 FRAME, 1); 2102 } 2103 } 2104 2105 pdata->ext_stats.rxq_packets[channel->queue_index]++; 2106 pdata->ext_stats.rxq_bytes[channel->queue_index] += rdata->rx.len; 2107 2108 DBGPR("<--xgbe_dev_read: %s - descriptor=%u (cur=%d)\n", channel->name, 2109 ring->cur & (ring->rdesc_count - 1), ring->cur); 2110 2111 return 0; 2112 } 2113 2114 static int xgbe_is_context_desc(struct xgbe_ring_desc *rdesc) 2115 { 2116 /* Rx and Tx share CTXT bit, so check TDES3.CTXT bit */ 2117 return XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT); 2118 } 2119 2120 static int xgbe_is_last_desc(struct xgbe_ring_desc *rdesc) 2121 { 2122 /* Rx and Tx share LD bit, so check TDES3.LD bit */ 2123 return XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, LD); 2124 } 2125 2126 static int xgbe_enable_int(struct xgbe_channel *channel, 2127 enum xgbe_int int_id) 2128 { 2129 switch (int_id) { 2130 case XGMAC_INT_DMA_CH_SR_TI: 2131 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TIE, 1); 2132 break; 2133 case XGMAC_INT_DMA_CH_SR_TPS: 2134 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TXSE, 1); 2135 break; 2136 case XGMAC_INT_DMA_CH_SR_TBU: 2137 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TBUE, 1); 2138 break; 2139 case XGMAC_INT_DMA_CH_SR_RI: 2140 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RIE, 1); 2141 break; 2142 case XGMAC_INT_DMA_CH_SR_RBU: 2143 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RBUE, 1); 2144 break; 2145 case XGMAC_INT_DMA_CH_SR_RPS: 2146 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RSE, 1); 2147 break; 2148 case XGMAC_INT_DMA_CH_SR_TI_RI: 2149 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TIE, 1); 2150 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RIE, 1); 2151 break; 2152 case XGMAC_INT_DMA_CH_SR_FBE: 2153 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, FBEE, 1); 2154 break; 2155 case XGMAC_INT_DMA_ALL: 2156 channel->curr_ier |= channel->saved_ier; 2157 break; 2158 default: 2159 return -1; 2160 } 2161 2162 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, channel->curr_ier); 2163 2164 return 0; 2165 } 2166 2167 static int xgbe_disable_int(struct xgbe_channel *channel, 2168 enum xgbe_int int_id) 2169 { 2170 switch (int_id) { 2171 case XGMAC_INT_DMA_CH_SR_TI: 2172 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TIE, 0); 2173 break; 2174 case XGMAC_INT_DMA_CH_SR_TPS: 2175 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TXSE, 0); 2176 break; 2177 case XGMAC_INT_DMA_CH_SR_TBU: 2178 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TBUE, 0); 2179 break; 2180 case XGMAC_INT_DMA_CH_SR_RI: 2181 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RIE, 0); 2182 break; 2183 case XGMAC_INT_DMA_CH_SR_RBU: 2184 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RBUE, 0); 2185 break; 2186 case XGMAC_INT_DMA_CH_SR_RPS: 2187 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RSE, 0); 2188 break; 2189 case XGMAC_INT_DMA_CH_SR_TI_RI: 2190 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TIE, 0); 2191 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RIE, 0); 2192 break; 2193 case XGMAC_INT_DMA_CH_SR_FBE: 2194 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, FBEE, 0); 2195 break; 2196 case XGMAC_INT_DMA_ALL: 2197 channel->saved_ier = channel->curr_ier; 2198 channel->curr_ier = 0; 2199 break; 2200 default: 2201 return -1; 2202 } 2203 2204 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, channel->curr_ier); 2205 2206 return 0; 2207 } 2208 2209 static int __xgbe_exit(struct xgbe_prv_data *pdata) 2210 { 2211 unsigned int count = 2000; 2212 2213 DBGPR("-->xgbe_exit\n"); 2214 2215 /* Issue a software reset */ 2216 XGMAC_IOWRITE_BITS(pdata, DMA_MR, SWR, 1); 2217 usleep_range(10, 15); 2218 2219 /* Poll Until Poll Condition */ 2220 while (--count && XGMAC_IOREAD_BITS(pdata, DMA_MR, SWR)) 2221 usleep_range(500, 600); 2222 2223 if (!count) 2224 return -EBUSY; 2225 2226 DBGPR("<--xgbe_exit\n"); 2227 2228 return 0; 2229 } 2230 2231 static int xgbe_exit(struct xgbe_prv_data *pdata) 2232 { 2233 int ret; 2234 2235 /* To guard against possible incorrectly generated interrupts, 2236 * issue the software reset twice. 2237 */ 2238 ret = __xgbe_exit(pdata); 2239 if (ret) 2240 return ret; 2241 2242 return __xgbe_exit(pdata); 2243 } 2244 2245 static int xgbe_flush_tx_queues(struct xgbe_prv_data *pdata) 2246 { 2247 unsigned int i, count; 2248 2249 if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) < 0x21) 2250 return 0; 2251 2252 for (i = 0; i < pdata->tx_q_count; i++) 2253 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, FTQ, 1); 2254 2255 /* Poll Until Poll Condition */ 2256 for (i = 0; i < pdata->tx_q_count; i++) { 2257 count = 2000; 2258 while (--count && XGMAC_MTL_IOREAD_BITS(pdata, i, 2259 MTL_Q_TQOMR, FTQ)) 2260 usleep_range(500, 600); 2261 2262 if (!count) 2263 return -EBUSY; 2264 } 2265 2266 return 0; 2267 } 2268 2269 static void xgbe_config_dma_bus(struct xgbe_prv_data *pdata) 2270 { 2271 unsigned int sbmr; 2272 2273 sbmr = XGMAC_IOREAD(pdata, DMA_SBMR); 2274 2275 /* Set enhanced addressing mode */ 2276 XGMAC_SET_BITS(sbmr, DMA_SBMR, EAME, 1); 2277 2278 /* Set the System Bus mode */ 2279 XGMAC_SET_BITS(sbmr, DMA_SBMR, UNDEF, 1); 2280 XGMAC_SET_BITS(sbmr, DMA_SBMR, BLEN, pdata->blen >> 2); 2281 XGMAC_SET_BITS(sbmr, DMA_SBMR, AAL, pdata->aal); 2282 XGMAC_SET_BITS(sbmr, DMA_SBMR, RD_OSR_LMT, pdata->rd_osr_limit - 1); 2283 XGMAC_SET_BITS(sbmr, DMA_SBMR, WR_OSR_LMT, pdata->wr_osr_limit - 1); 2284 2285 XGMAC_IOWRITE(pdata, DMA_SBMR, sbmr); 2286 2287 /* Set descriptor fetching threshold */ 2288 if (pdata->vdata->tx_desc_prefetch) 2289 XGMAC_IOWRITE_BITS(pdata, DMA_TXEDMACR, TDPS, 2290 pdata->vdata->tx_desc_prefetch); 2291 2292 if (pdata->vdata->rx_desc_prefetch) 2293 XGMAC_IOWRITE_BITS(pdata, DMA_RXEDMACR, RDPS, 2294 pdata->vdata->rx_desc_prefetch); 2295 } 2296 2297 static void xgbe_config_dma_cache(struct xgbe_prv_data *pdata) 2298 { 2299 XGMAC_IOWRITE(pdata, DMA_AXIARCR, pdata->arcr); 2300 XGMAC_IOWRITE(pdata, DMA_AXIAWCR, pdata->awcr); 2301 if (pdata->awarcr) 2302 XGMAC_IOWRITE(pdata, DMA_AXIAWARCR, pdata->awarcr); 2303 } 2304 2305 static void xgbe_config_mtl_mode(struct xgbe_prv_data *pdata) 2306 { 2307 unsigned int i; 2308 2309 /* Set Tx to weighted round robin scheduling algorithm */ 2310 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_WRR); 2311 2312 /* Set Tx traffic classes to use WRR algorithm with equal weights */ 2313 for (i = 0; i < pdata->hw_feat.tc_cnt; i++) { 2314 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA, 2315 MTL_TSA_ETS); 2316 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW, 1); 2317 } 2318 2319 /* Set Rx to strict priority algorithm */ 2320 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, RAA, MTL_RAA_SP); 2321 } 2322 2323 static void xgbe_queue_flow_control_threshold(struct xgbe_prv_data *pdata, 2324 unsigned int queue, 2325 unsigned int q_fifo_size) 2326 { 2327 unsigned int frame_fifo_size; 2328 unsigned int rfa, rfd; 2329 2330 frame_fifo_size = XGMAC_FLOW_CONTROL_ALIGN(xgbe_get_max_frame(pdata)); 2331 2332 if (pdata->pfcq[queue] && (q_fifo_size > pdata->pfc_rfa)) { 2333 /* PFC is active for this queue */ 2334 rfa = pdata->pfc_rfa; 2335 rfd = rfa + frame_fifo_size; 2336 if (rfd > XGMAC_FLOW_CONTROL_MAX) 2337 rfd = XGMAC_FLOW_CONTROL_MAX; 2338 if (rfa >= XGMAC_FLOW_CONTROL_MAX) 2339 rfa = XGMAC_FLOW_CONTROL_MAX - XGMAC_FLOW_CONTROL_UNIT; 2340 } else { 2341 /* This path deals with just maximum frame sizes which are 2342 * limited to a jumbo frame of 9,000 (plus headers, etc.) 2343 * so we can never exceed the maximum allowable RFA/RFD 2344 * values. 2345 */ 2346 if (q_fifo_size <= 2048) { 2347 /* rx_rfd to zero to signal no flow control */ 2348 pdata->rx_rfa[queue] = 0; 2349 pdata->rx_rfd[queue] = 0; 2350 return; 2351 } 2352 2353 if (q_fifo_size <= 4096) { 2354 /* Between 2048 and 4096 */ 2355 pdata->rx_rfa[queue] = 0; /* Full - 1024 bytes */ 2356 pdata->rx_rfd[queue] = 1; /* Full - 1536 bytes */ 2357 return; 2358 } 2359 2360 if (q_fifo_size <= frame_fifo_size) { 2361 /* Between 4096 and max-frame */ 2362 pdata->rx_rfa[queue] = 2; /* Full - 2048 bytes */ 2363 pdata->rx_rfd[queue] = 5; /* Full - 3584 bytes */ 2364 return; 2365 } 2366 2367 if (q_fifo_size <= (frame_fifo_size * 3)) { 2368 /* Between max-frame and 3 max-frames, 2369 * trigger if we get just over a frame of data and 2370 * resume when we have just under half a frame left. 2371 */ 2372 rfa = q_fifo_size - frame_fifo_size; 2373 rfd = rfa + (frame_fifo_size / 2); 2374 } else { 2375 /* Above 3 max-frames - trigger when just over 2376 * 2 frames of space available 2377 */ 2378 rfa = frame_fifo_size * 2; 2379 rfa += XGMAC_FLOW_CONTROL_UNIT; 2380 rfd = rfa + frame_fifo_size; 2381 } 2382 } 2383 2384 pdata->rx_rfa[queue] = XGMAC_FLOW_CONTROL_VALUE(rfa); 2385 pdata->rx_rfd[queue] = XGMAC_FLOW_CONTROL_VALUE(rfd); 2386 } 2387 2388 static void xgbe_calculate_flow_control_threshold(struct xgbe_prv_data *pdata, 2389 unsigned int *fifo) 2390 { 2391 unsigned int q_fifo_size; 2392 unsigned int i; 2393 2394 for (i = 0; i < pdata->rx_q_count; i++) { 2395 q_fifo_size = (fifo[i] + 1) * XGMAC_FIFO_UNIT; 2396 2397 xgbe_queue_flow_control_threshold(pdata, i, q_fifo_size); 2398 } 2399 } 2400 2401 static void xgbe_config_flow_control_threshold(struct xgbe_prv_data *pdata) 2402 { 2403 unsigned int i; 2404 2405 for (i = 0; i < pdata->rx_q_count; i++) { 2406 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQFCR, RFA, 2407 pdata->rx_rfa[i]); 2408 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQFCR, RFD, 2409 pdata->rx_rfd[i]); 2410 } 2411 } 2412 2413 static unsigned int xgbe_get_tx_fifo_size(struct xgbe_prv_data *pdata) 2414 { 2415 /* The configured value may not be the actual amount of fifo RAM */ 2416 return min_t(unsigned int, pdata->tx_max_fifo_size, 2417 pdata->hw_feat.tx_fifo_size); 2418 } 2419 2420 static unsigned int xgbe_get_rx_fifo_size(struct xgbe_prv_data *pdata) 2421 { 2422 /* The configured value may not be the actual amount of fifo RAM */ 2423 return min_t(unsigned int, pdata->rx_max_fifo_size, 2424 pdata->hw_feat.rx_fifo_size); 2425 } 2426 2427 static void xgbe_calculate_equal_fifo(unsigned int fifo_size, 2428 unsigned int queue_count, 2429 unsigned int *fifo) 2430 { 2431 unsigned int q_fifo_size; 2432 unsigned int p_fifo; 2433 unsigned int i; 2434 2435 q_fifo_size = fifo_size / queue_count; 2436 2437 /* Calculate the fifo setting by dividing the queue's fifo size 2438 * by the fifo allocation increment (with 0 representing the 2439 * base allocation increment so decrement the result by 1). 2440 */ 2441 p_fifo = q_fifo_size / XGMAC_FIFO_UNIT; 2442 if (p_fifo) 2443 p_fifo--; 2444 2445 /* Distribute the fifo equally amongst the queues */ 2446 for (i = 0; i < queue_count; i++) 2447 fifo[i] = p_fifo; 2448 } 2449 2450 static unsigned int xgbe_set_nonprio_fifos(unsigned int fifo_size, 2451 unsigned int queue_count, 2452 unsigned int *fifo) 2453 { 2454 unsigned int i; 2455 2456 BUILD_BUG_ON_NOT_POWER_OF_2(XGMAC_FIFO_MIN_ALLOC); 2457 2458 if (queue_count <= IEEE_8021QAZ_MAX_TCS) 2459 return fifo_size; 2460 2461 /* Rx queues 9 and up are for specialized packets, 2462 * such as PTP or DCB control packets, etc. and 2463 * don't require a large fifo 2464 */ 2465 for (i = IEEE_8021QAZ_MAX_TCS; i < queue_count; i++) { 2466 fifo[i] = (XGMAC_FIFO_MIN_ALLOC / XGMAC_FIFO_UNIT) - 1; 2467 fifo_size -= XGMAC_FIFO_MIN_ALLOC; 2468 } 2469 2470 return fifo_size; 2471 } 2472 2473 static unsigned int xgbe_get_pfc_delay(struct xgbe_prv_data *pdata) 2474 { 2475 unsigned int delay; 2476 2477 /* If a delay has been provided, use that */ 2478 if (pdata->pfc->delay) 2479 return pdata->pfc->delay / 8; 2480 2481 /* Allow for two maximum size frames */ 2482 delay = xgbe_get_max_frame(pdata); 2483 delay += XGMAC_ETH_PREAMBLE; 2484 delay *= 2; 2485 2486 /* Allow for PFC frame */ 2487 delay += XGMAC_PFC_DATA_LEN; 2488 delay += ETH_HLEN + ETH_FCS_LEN; 2489 delay += XGMAC_ETH_PREAMBLE; 2490 2491 /* Allow for miscellaneous delays (LPI exit, cable, etc.) */ 2492 delay += XGMAC_PFC_DELAYS; 2493 2494 return delay; 2495 } 2496 2497 static unsigned int xgbe_get_pfc_queues(struct xgbe_prv_data *pdata) 2498 { 2499 unsigned int count, prio_queues; 2500 unsigned int i; 2501 2502 if (!pdata->pfc->pfc_en) 2503 return 0; 2504 2505 count = 0; 2506 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count); 2507 for (i = 0; i < prio_queues; i++) { 2508 if (!xgbe_is_pfc_queue(pdata, i)) 2509 continue; 2510 2511 pdata->pfcq[i] = 1; 2512 count++; 2513 } 2514 2515 return count; 2516 } 2517 2518 static void xgbe_calculate_dcb_fifo(struct xgbe_prv_data *pdata, 2519 unsigned int fifo_size, 2520 unsigned int *fifo) 2521 { 2522 unsigned int q_fifo_size, rem_fifo, addn_fifo; 2523 unsigned int prio_queues; 2524 unsigned int pfc_count; 2525 unsigned int i; 2526 2527 q_fifo_size = XGMAC_FIFO_ALIGN(xgbe_get_max_frame(pdata)); 2528 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count); 2529 pfc_count = xgbe_get_pfc_queues(pdata); 2530 2531 if (!pfc_count || ((q_fifo_size * prio_queues) > fifo_size)) { 2532 /* No traffic classes with PFC enabled or can't do lossless */ 2533 xgbe_calculate_equal_fifo(fifo_size, prio_queues, fifo); 2534 return; 2535 } 2536 2537 /* Calculate how much fifo we have to play with */ 2538 rem_fifo = fifo_size - (q_fifo_size * prio_queues); 2539 2540 /* Calculate how much more than base fifo PFC needs, which also 2541 * becomes the threshold activation point (RFA) 2542 */ 2543 pdata->pfc_rfa = xgbe_get_pfc_delay(pdata); 2544 pdata->pfc_rfa = XGMAC_FLOW_CONTROL_ALIGN(pdata->pfc_rfa); 2545 2546 if (pdata->pfc_rfa > q_fifo_size) { 2547 addn_fifo = pdata->pfc_rfa - q_fifo_size; 2548 addn_fifo = XGMAC_FIFO_ALIGN(addn_fifo); 2549 } else { 2550 addn_fifo = 0; 2551 } 2552 2553 /* Calculate DCB fifo settings: 2554 * - distribute remaining fifo between the VLAN priority 2555 * queues based on traffic class PFC enablement and overall 2556 * priority (0 is lowest priority, so start at highest) 2557 */ 2558 i = prio_queues; 2559 while (i > 0) { 2560 i--; 2561 2562 fifo[i] = (q_fifo_size / XGMAC_FIFO_UNIT) - 1; 2563 2564 if (!pdata->pfcq[i] || !addn_fifo) 2565 continue; 2566 2567 if (addn_fifo > rem_fifo) { 2568 netdev_warn(pdata->netdev, 2569 "RXq%u cannot set needed fifo size\n", i); 2570 if (!rem_fifo) 2571 continue; 2572 2573 addn_fifo = rem_fifo; 2574 } 2575 2576 fifo[i] += (addn_fifo / XGMAC_FIFO_UNIT); 2577 rem_fifo -= addn_fifo; 2578 } 2579 2580 if (rem_fifo) { 2581 unsigned int inc_fifo = rem_fifo / prio_queues; 2582 2583 /* Distribute remaining fifo across queues */ 2584 for (i = 0; i < prio_queues; i++) 2585 fifo[i] += (inc_fifo / XGMAC_FIFO_UNIT); 2586 } 2587 } 2588 2589 static void xgbe_config_tx_fifo_size(struct xgbe_prv_data *pdata) 2590 { 2591 unsigned int fifo_size; 2592 unsigned int fifo[XGBE_MAX_QUEUES]; 2593 unsigned int i; 2594 2595 fifo_size = xgbe_get_tx_fifo_size(pdata); 2596 2597 xgbe_calculate_equal_fifo(fifo_size, pdata->tx_q_count, fifo); 2598 2599 for (i = 0; i < pdata->tx_q_count; i++) 2600 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TQS, fifo[i]); 2601 2602 netif_info(pdata, drv, pdata->netdev, 2603 "%d Tx hardware queues, %d byte fifo per queue\n", 2604 pdata->tx_q_count, ((fifo[0] + 1) * XGMAC_FIFO_UNIT)); 2605 } 2606 2607 static void xgbe_config_rx_fifo_size(struct xgbe_prv_data *pdata) 2608 { 2609 unsigned int fifo_size; 2610 unsigned int fifo[XGBE_MAX_QUEUES]; 2611 unsigned int prio_queues; 2612 unsigned int i; 2613 2614 /* Clear any DCB related fifo/queue information */ 2615 memset(pdata->pfcq, 0, sizeof(pdata->pfcq)); 2616 pdata->pfc_rfa = 0; 2617 2618 fifo_size = xgbe_get_rx_fifo_size(pdata); 2619 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count); 2620 2621 /* Assign a minimum fifo to the non-VLAN priority queues */ 2622 fifo_size = xgbe_set_nonprio_fifos(fifo_size, pdata->rx_q_count, fifo); 2623 2624 if (pdata->pfc && pdata->ets) 2625 xgbe_calculate_dcb_fifo(pdata, fifo_size, fifo); 2626 else 2627 xgbe_calculate_equal_fifo(fifo_size, prio_queues, fifo); 2628 2629 for (i = 0; i < pdata->rx_q_count; i++) 2630 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RQS, fifo[i]); 2631 2632 xgbe_calculate_flow_control_threshold(pdata, fifo); 2633 xgbe_config_flow_control_threshold(pdata); 2634 2635 if (pdata->pfc && pdata->ets && pdata->pfc->pfc_en) { 2636 netif_info(pdata, drv, pdata->netdev, 2637 "%u Rx hardware queues\n", pdata->rx_q_count); 2638 for (i = 0; i < pdata->rx_q_count; i++) 2639 netif_info(pdata, drv, pdata->netdev, 2640 "RxQ%u, %u byte fifo queue\n", i, 2641 ((fifo[i] + 1) * XGMAC_FIFO_UNIT)); 2642 } else { 2643 netif_info(pdata, drv, pdata->netdev, 2644 "%u Rx hardware queues, %u byte fifo per queue\n", 2645 pdata->rx_q_count, 2646 ((fifo[0] + 1) * XGMAC_FIFO_UNIT)); 2647 } 2648 } 2649 2650 static void xgbe_config_queue_mapping(struct xgbe_prv_data *pdata) 2651 { 2652 unsigned int qptc, qptc_extra, queue; 2653 unsigned int prio_queues; 2654 unsigned int ppq, ppq_extra, prio; 2655 unsigned int mask; 2656 unsigned int i, j, reg, reg_val; 2657 2658 /* Map the MTL Tx Queues to Traffic Classes 2659 * Note: Tx Queues >= Traffic Classes 2660 */ 2661 qptc = pdata->tx_q_count / pdata->hw_feat.tc_cnt; 2662 qptc_extra = pdata->tx_q_count % pdata->hw_feat.tc_cnt; 2663 2664 for (i = 0, queue = 0; i < pdata->hw_feat.tc_cnt; i++) { 2665 for (j = 0; j < qptc; j++) { 2666 netif_dbg(pdata, drv, pdata->netdev, 2667 "TXq%u mapped to TC%u\n", queue, i); 2668 XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR, 2669 Q2TCMAP, i); 2670 pdata->q2tc_map[queue++] = i; 2671 } 2672 2673 if (i < qptc_extra) { 2674 netif_dbg(pdata, drv, pdata->netdev, 2675 "TXq%u mapped to TC%u\n", queue, i); 2676 XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR, 2677 Q2TCMAP, i); 2678 pdata->q2tc_map[queue++] = i; 2679 } 2680 } 2681 2682 /* Map the 8 VLAN priority values to available MTL Rx queues */ 2683 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count); 2684 ppq = IEEE_8021QAZ_MAX_TCS / prio_queues; 2685 ppq_extra = IEEE_8021QAZ_MAX_TCS % prio_queues; 2686 2687 reg = MAC_RQC2R; 2688 reg_val = 0; 2689 for (i = 0, prio = 0; i < prio_queues;) { 2690 mask = 0; 2691 for (j = 0; j < ppq; j++) { 2692 netif_dbg(pdata, drv, pdata->netdev, 2693 "PRIO%u mapped to RXq%u\n", prio, i); 2694 mask |= (1 << prio); 2695 pdata->prio2q_map[prio++] = i; 2696 } 2697 2698 if (i < ppq_extra) { 2699 netif_dbg(pdata, drv, pdata->netdev, 2700 "PRIO%u mapped to RXq%u\n", prio, i); 2701 mask |= (1 << prio); 2702 pdata->prio2q_map[prio++] = i; 2703 } 2704 2705 reg_val |= (mask << ((i++ % MAC_RQC2_Q_PER_REG) << 3)); 2706 2707 if ((i % MAC_RQC2_Q_PER_REG) && (i != prio_queues)) 2708 continue; 2709 2710 XGMAC_IOWRITE(pdata, reg, reg_val); 2711 reg += MAC_RQC2_INC; 2712 reg_val = 0; 2713 } 2714 2715 /* Select dynamic mapping of MTL Rx queue to DMA Rx channel */ 2716 reg = MTL_RQDCM0R; 2717 reg_val = 0; 2718 for (i = 0; i < pdata->rx_q_count;) { 2719 reg_val |= (0x80 << ((i++ % MTL_RQDCM_Q_PER_REG) << 3)); 2720 2721 if ((i % MTL_RQDCM_Q_PER_REG) && (i != pdata->rx_q_count)) 2722 continue; 2723 2724 XGMAC_IOWRITE(pdata, reg, reg_val); 2725 2726 reg += MTL_RQDCM_INC; 2727 reg_val = 0; 2728 } 2729 } 2730 2731 static void xgbe_config_tc(struct xgbe_prv_data *pdata) 2732 { 2733 unsigned int offset, queue, prio; 2734 u8 i; 2735 2736 netdev_reset_tc(pdata->netdev); 2737 if (!pdata->num_tcs) 2738 return; 2739 2740 netdev_set_num_tc(pdata->netdev, pdata->num_tcs); 2741 2742 for (i = 0, queue = 0, offset = 0; i < pdata->num_tcs; i++) { 2743 while ((queue < pdata->tx_q_count) && 2744 (pdata->q2tc_map[queue] == i)) 2745 queue++; 2746 2747 netif_dbg(pdata, drv, pdata->netdev, "TC%u using TXq%u-%u\n", 2748 i, offset, queue - 1); 2749 netdev_set_tc_queue(pdata->netdev, i, queue - offset, offset); 2750 offset = queue; 2751 } 2752 2753 if (!pdata->ets) 2754 return; 2755 2756 for (prio = 0; prio < IEEE_8021QAZ_MAX_TCS; prio++) 2757 netdev_set_prio_tc_map(pdata->netdev, prio, 2758 pdata->ets->prio_tc[prio]); 2759 } 2760 2761 static void xgbe_config_dcb_tc(struct xgbe_prv_data *pdata) 2762 { 2763 struct ieee_ets *ets = pdata->ets; 2764 unsigned int total_weight, min_weight, weight; 2765 unsigned int mask, reg, reg_val; 2766 unsigned int i, prio; 2767 2768 if (!ets) 2769 return; 2770 2771 /* Set Tx to deficit weighted round robin scheduling algorithm (when 2772 * traffic class is using ETS algorithm) 2773 */ 2774 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_DWRR); 2775 2776 /* Set Traffic Class algorithms */ 2777 total_weight = pdata->netdev->mtu * pdata->hw_feat.tc_cnt; 2778 min_weight = total_weight / 100; 2779 if (!min_weight) 2780 min_weight = 1; 2781 2782 for (i = 0; i < pdata->hw_feat.tc_cnt; i++) { 2783 /* Map the priorities to the traffic class */ 2784 mask = 0; 2785 for (prio = 0; prio < IEEE_8021QAZ_MAX_TCS; prio++) { 2786 if (ets->prio_tc[prio] == i) 2787 mask |= (1 << prio); 2788 } 2789 mask &= 0xff; 2790 2791 netif_dbg(pdata, drv, pdata->netdev, "TC%u PRIO mask=%#x\n", 2792 i, mask); 2793 reg = MTL_TCPM0R + (MTL_TCPM_INC * (i / MTL_TCPM_TC_PER_REG)); 2794 reg_val = XGMAC_IOREAD(pdata, reg); 2795 2796 reg_val &= ~(0xff << ((i % MTL_TCPM_TC_PER_REG) << 3)); 2797 reg_val |= (mask << ((i % MTL_TCPM_TC_PER_REG) << 3)); 2798 2799 XGMAC_IOWRITE(pdata, reg, reg_val); 2800 2801 /* Set the traffic class algorithm */ 2802 switch (ets->tc_tsa[i]) { 2803 case IEEE_8021QAZ_TSA_STRICT: 2804 netif_dbg(pdata, drv, pdata->netdev, 2805 "TC%u using SP\n", i); 2806 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA, 2807 MTL_TSA_SP); 2808 break; 2809 case IEEE_8021QAZ_TSA_ETS: 2810 weight = total_weight * ets->tc_tx_bw[i] / 100; 2811 weight = clamp(weight, min_weight, total_weight); 2812 2813 netif_dbg(pdata, drv, pdata->netdev, 2814 "TC%u using DWRR (weight %u)\n", i, weight); 2815 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA, 2816 MTL_TSA_ETS); 2817 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW, 2818 weight); 2819 break; 2820 } 2821 } 2822 2823 xgbe_config_tc(pdata); 2824 } 2825 2826 static void xgbe_config_dcb_pfc(struct xgbe_prv_data *pdata) 2827 { 2828 if (!test_bit(XGBE_DOWN, &pdata->dev_state)) { 2829 /* Just stop the Tx queues while Rx fifo is changed */ 2830 netif_tx_stop_all_queues(pdata->netdev); 2831 2832 /* Suspend Rx so that fifo's can be adjusted */ 2833 pdata->hw_if.disable_rx(pdata); 2834 } 2835 2836 xgbe_config_rx_fifo_size(pdata); 2837 xgbe_config_flow_control(pdata); 2838 2839 if (!test_bit(XGBE_DOWN, &pdata->dev_state)) { 2840 /* Resume Rx */ 2841 pdata->hw_if.enable_rx(pdata); 2842 2843 /* Resume Tx queues */ 2844 netif_tx_start_all_queues(pdata->netdev); 2845 } 2846 } 2847 2848 static void xgbe_config_mac_address(struct xgbe_prv_data *pdata) 2849 { 2850 xgbe_set_mac_address(pdata, pdata->netdev->dev_addr); 2851 2852 /* Filtering is done using perfect filtering and hash filtering */ 2853 if (pdata->hw_feat.hash_table_size) { 2854 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 1); 2855 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 1); 2856 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HMC, 1); 2857 } 2858 } 2859 2860 static void xgbe_config_jumbo_enable(struct xgbe_prv_data *pdata) 2861 { 2862 unsigned int val; 2863 2864 val = (pdata->netdev->mtu > XGMAC_STD_PACKET_MTU) ? 1 : 0; 2865 2866 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, JE, val); 2867 } 2868 2869 static void xgbe_config_mac_speed(struct xgbe_prv_data *pdata) 2870 { 2871 xgbe_set_speed(pdata, pdata->phy_speed); 2872 } 2873 2874 static void xgbe_config_checksum_offload(struct xgbe_prv_data *pdata) 2875 { 2876 if (pdata->netdev->features & NETIF_F_RXCSUM) 2877 xgbe_enable_rx_csum(pdata); 2878 else 2879 xgbe_disable_rx_csum(pdata); 2880 } 2881 2882 static void xgbe_config_vlan_support(struct xgbe_prv_data *pdata) 2883 { 2884 /* Indicate that VLAN Tx CTAGs come from context descriptors */ 2885 XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, CSVL, 0); 2886 XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, VLTI, 1); 2887 2888 /* Set the current VLAN Hash Table register value */ 2889 xgbe_update_vlan_hash_table(pdata); 2890 2891 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER) 2892 xgbe_enable_rx_vlan_filtering(pdata); 2893 else 2894 xgbe_disable_rx_vlan_filtering(pdata); 2895 2896 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) 2897 xgbe_enable_rx_vlan_stripping(pdata); 2898 else 2899 xgbe_disable_rx_vlan_stripping(pdata); 2900 } 2901 2902 static u64 xgbe_mmc_read(struct xgbe_prv_data *pdata, unsigned int reg_lo) 2903 { 2904 bool read_hi; 2905 u64 val; 2906 2907 if (pdata->vdata->mmc_64bit) { 2908 switch (reg_lo) { 2909 /* These registers are always 32 bit */ 2910 case MMC_RXRUNTERROR: 2911 case MMC_RXJABBERERROR: 2912 case MMC_RXUNDERSIZE_G: 2913 case MMC_RXOVERSIZE_G: 2914 case MMC_RXWATCHDOGERROR: 2915 read_hi = false; 2916 break; 2917 2918 default: 2919 read_hi = true; 2920 } 2921 } else { 2922 switch (reg_lo) { 2923 /* These registers are always 64 bit */ 2924 case MMC_TXOCTETCOUNT_GB_LO: 2925 case MMC_TXOCTETCOUNT_G_LO: 2926 case MMC_RXOCTETCOUNT_GB_LO: 2927 case MMC_RXOCTETCOUNT_G_LO: 2928 read_hi = true; 2929 break; 2930 2931 default: 2932 read_hi = false; 2933 } 2934 } 2935 2936 val = XGMAC_IOREAD(pdata, reg_lo); 2937 2938 if (read_hi) 2939 val |= ((u64)XGMAC_IOREAD(pdata, reg_lo + 4) << 32); 2940 2941 return val; 2942 } 2943 2944 static void xgbe_tx_mmc_int(struct xgbe_prv_data *pdata) 2945 { 2946 struct xgbe_mmc_stats *stats = &pdata->mmc_stats; 2947 unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_TISR); 2948 2949 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXOCTETCOUNT_GB)) 2950 stats->txoctetcount_gb += 2951 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO); 2952 2953 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXFRAMECOUNT_GB)) 2954 stats->txframecount_gb += 2955 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO); 2956 2957 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXBROADCASTFRAMES_G)) 2958 stats->txbroadcastframes_g += 2959 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO); 2960 2961 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXMULTICASTFRAMES_G)) 2962 stats->txmulticastframes_g += 2963 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO); 2964 2965 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX64OCTETS_GB)) 2966 stats->tx64octets_gb += 2967 xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO); 2968 2969 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX65TO127OCTETS_GB)) 2970 stats->tx65to127octets_gb += 2971 xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO); 2972 2973 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX128TO255OCTETS_GB)) 2974 stats->tx128to255octets_gb += 2975 xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO); 2976 2977 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX256TO511OCTETS_GB)) 2978 stats->tx256to511octets_gb += 2979 xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO); 2980 2981 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX512TO1023OCTETS_GB)) 2982 stats->tx512to1023octets_gb += 2983 xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO); 2984 2985 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX1024TOMAXOCTETS_GB)) 2986 stats->tx1024tomaxoctets_gb += 2987 xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO); 2988 2989 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXUNICASTFRAMES_GB)) 2990 stats->txunicastframes_gb += 2991 xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO); 2992 2993 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXMULTICASTFRAMES_GB)) 2994 stats->txmulticastframes_gb += 2995 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO); 2996 2997 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXBROADCASTFRAMES_GB)) 2998 stats->txbroadcastframes_g += 2999 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO); 3000 3001 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXUNDERFLOWERROR)) 3002 stats->txunderflowerror += 3003 xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO); 3004 3005 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXOCTETCOUNT_G)) 3006 stats->txoctetcount_g += 3007 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO); 3008 3009 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXFRAMECOUNT_G)) 3010 stats->txframecount_g += 3011 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO); 3012 3013 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXPAUSEFRAMES)) 3014 stats->txpauseframes += 3015 xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO); 3016 3017 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXVLANFRAMES_G)) 3018 stats->txvlanframes_g += 3019 xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO); 3020 } 3021 3022 static void xgbe_rx_mmc_int(struct xgbe_prv_data *pdata) 3023 { 3024 struct xgbe_mmc_stats *stats = &pdata->mmc_stats; 3025 unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_RISR); 3026 3027 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXFRAMECOUNT_GB)) 3028 stats->rxframecount_gb += 3029 xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO); 3030 3031 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOCTETCOUNT_GB)) 3032 stats->rxoctetcount_gb += 3033 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO); 3034 3035 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOCTETCOUNT_G)) 3036 stats->rxoctetcount_g += 3037 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO); 3038 3039 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXBROADCASTFRAMES_G)) 3040 stats->rxbroadcastframes_g += 3041 xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO); 3042 3043 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXMULTICASTFRAMES_G)) 3044 stats->rxmulticastframes_g += 3045 xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO); 3046 3047 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXCRCERROR)) 3048 stats->rxcrcerror += 3049 xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO); 3050 3051 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXRUNTERROR)) 3052 stats->rxrunterror += 3053 xgbe_mmc_read(pdata, MMC_RXRUNTERROR); 3054 3055 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXJABBERERROR)) 3056 stats->rxjabbererror += 3057 xgbe_mmc_read(pdata, MMC_RXJABBERERROR); 3058 3059 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXUNDERSIZE_G)) 3060 stats->rxundersize_g += 3061 xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G); 3062 3063 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOVERSIZE_G)) 3064 stats->rxoversize_g += 3065 xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G); 3066 3067 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX64OCTETS_GB)) 3068 stats->rx64octets_gb += 3069 xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO); 3070 3071 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX65TO127OCTETS_GB)) 3072 stats->rx65to127octets_gb += 3073 xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO); 3074 3075 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX128TO255OCTETS_GB)) 3076 stats->rx128to255octets_gb += 3077 xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO); 3078 3079 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX256TO511OCTETS_GB)) 3080 stats->rx256to511octets_gb += 3081 xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO); 3082 3083 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX512TO1023OCTETS_GB)) 3084 stats->rx512to1023octets_gb += 3085 xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO); 3086 3087 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX1024TOMAXOCTETS_GB)) 3088 stats->rx1024tomaxoctets_gb += 3089 xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO); 3090 3091 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXUNICASTFRAMES_G)) 3092 stats->rxunicastframes_g += 3093 xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO); 3094 3095 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXLENGTHERROR)) 3096 stats->rxlengtherror += 3097 xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO); 3098 3099 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOUTOFRANGETYPE)) 3100 stats->rxoutofrangetype += 3101 xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO); 3102 3103 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXPAUSEFRAMES)) 3104 stats->rxpauseframes += 3105 xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO); 3106 3107 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXFIFOOVERFLOW)) 3108 stats->rxfifooverflow += 3109 xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO); 3110 3111 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXVLANFRAMES_GB)) 3112 stats->rxvlanframes_gb += 3113 xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO); 3114 3115 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXWATCHDOGERROR)) 3116 stats->rxwatchdogerror += 3117 xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR); 3118 } 3119 3120 static void xgbe_read_mmc_stats(struct xgbe_prv_data *pdata) 3121 { 3122 struct xgbe_mmc_stats *stats = &pdata->mmc_stats; 3123 3124 /* Freeze counters */ 3125 XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 1); 3126 3127 stats->txoctetcount_gb += 3128 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO); 3129 3130 stats->txframecount_gb += 3131 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO); 3132 3133 stats->txbroadcastframes_g += 3134 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO); 3135 3136 stats->txmulticastframes_g += 3137 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO); 3138 3139 stats->tx64octets_gb += 3140 xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO); 3141 3142 stats->tx65to127octets_gb += 3143 xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO); 3144 3145 stats->tx128to255octets_gb += 3146 xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO); 3147 3148 stats->tx256to511octets_gb += 3149 xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO); 3150 3151 stats->tx512to1023octets_gb += 3152 xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO); 3153 3154 stats->tx1024tomaxoctets_gb += 3155 xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO); 3156 3157 stats->txunicastframes_gb += 3158 xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO); 3159 3160 stats->txmulticastframes_gb += 3161 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO); 3162 3163 stats->txbroadcastframes_g += 3164 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO); 3165 3166 stats->txunderflowerror += 3167 xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO); 3168 3169 stats->txoctetcount_g += 3170 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO); 3171 3172 stats->txframecount_g += 3173 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO); 3174 3175 stats->txpauseframes += 3176 xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO); 3177 3178 stats->txvlanframes_g += 3179 xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO); 3180 3181 stats->rxframecount_gb += 3182 xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO); 3183 3184 stats->rxoctetcount_gb += 3185 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO); 3186 3187 stats->rxoctetcount_g += 3188 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO); 3189 3190 stats->rxbroadcastframes_g += 3191 xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO); 3192 3193 stats->rxmulticastframes_g += 3194 xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO); 3195 3196 stats->rxcrcerror += 3197 xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO); 3198 3199 stats->rxrunterror += 3200 xgbe_mmc_read(pdata, MMC_RXRUNTERROR); 3201 3202 stats->rxjabbererror += 3203 xgbe_mmc_read(pdata, MMC_RXJABBERERROR); 3204 3205 stats->rxundersize_g += 3206 xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G); 3207 3208 stats->rxoversize_g += 3209 xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G); 3210 3211 stats->rx64octets_gb += 3212 xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO); 3213 3214 stats->rx65to127octets_gb += 3215 xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO); 3216 3217 stats->rx128to255octets_gb += 3218 xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO); 3219 3220 stats->rx256to511octets_gb += 3221 xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO); 3222 3223 stats->rx512to1023octets_gb += 3224 xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO); 3225 3226 stats->rx1024tomaxoctets_gb += 3227 xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO); 3228 3229 stats->rxunicastframes_g += 3230 xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO); 3231 3232 stats->rxlengtherror += 3233 xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO); 3234 3235 stats->rxoutofrangetype += 3236 xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO); 3237 3238 stats->rxpauseframes += 3239 xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO); 3240 3241 stats->rxfifooverflow += 3242 xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO); 3243 3244 stats->rxvlanframes_gb += 3245 xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO); 3246 3247 stats->rxwatchdogerror += 3248 xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR); 3249 3250 /* Un-freeze counters */ 3251 XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 0); 3252 } 3253 3254 static void xgbe_config_mmc(struct xgbe_prv_data *pdata) 3255 { 3256 /* Set counters to reset on read */ 3257 XGMAC_IOWRITE_BITS(pdata, MMC_CR, ROR, 1); 3258 3259 /* Reset the counters */ 3260 XGMAC_IOWRITE_BITS(pdata, MMC_CR, CR, 1); 3261 } 3262 3263 static void xgbe_txq_prepare_tx_stop(struct xgbe_prv_data *pdata, 3264 unsigned int queue) 3265 { 3266 unsigned int tx_status; 3267 unsigned long tx_timeout; 3268 3269 /* The Tx engine cannot be stopped if it is actively processing 3270 * packets. Wait for the Tx queue to empty the Tx fifo. Don't 3271 * wait forever though... 3272 */ 3273 tx_timeout = jiffies + (XGBE_DMA_STOP_TIMEOUT * HZ); 3274 while (time_before(jiffies, tx_timeout)) { 3275 tx_status = XGMAC_MTL_IOREAD(pdata, queue, MTL_Q_TQDR); 3276 if ((XGMAC_GET_BITS(tx_status, MTL_Q_TQDR, TRCSTS) != 1) && 3277 (XGMAC_GET_BITS(tx_status, MTL_Q_TQDR, TXQSTS) == 0)) 3278 break; 3279 3280 usleep_range(500, 1000); 3281 } 3282 3283 if (!time_before(jiffies, tx_timeout)) 3284 netdev_info(pdata->netdev, 3285 "timed out waiting for Tx queue %u to empty\n", 3286 queue); 3287 } 3288 3289 static void xgbe_prepare_tx_stop(struct xgbe_prv_data *pdata, 3290 unsigned int queue) 3291 { 3292 unsigned int tx_dsr, tx_pos, tx_qidx; 3293 unsigned int tx_status; 3294 unsigned long tx_timeout; 3295 3296 if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) > 0x20) 3297 return xgbe_txq_prepare_tx_stop(pdata, queue); 3298 3299 /* Calculate the status register to read and the position within */ 3300 if (queue < DMA_DSRX_FIRST_QUEUE) { 3301 tx_dsr = DMA_DSR0; 3302 tx_pos = (queue * DMA_DSR_Q_WIDTH) + DMA_DSR0_TPS_START; 3303 } else { 3304 tx_qidx = queue - DMA_DSRX_FIRST_QUEUE; 3305 3306 tx_dsr = DMA_DSR1 + ((tx_qidx / DMA_DSRX_QPR) * DMA_DSRX_INC); 3307 tx_pos = ((tx_qidx % DMA_DSRX_QPR) * DMA_DSR_Q_WIDTH) + 3308 DMA_DSRX_TPS_START; 3309 } 3310 3311 /* The Tx engine cannot be stopped if it is actively processing 3312 * descriptors. Wait for the Tx engine to enter the stopped or 3313 * suspended state. Don't wait forever though... 3314 */ 3315 tx_timeout = jiffies + (XGBE_DMA_STOP_TIMEOUT * HZ); 3316 while (time_before(jiffies, tx_timeout)) { 3317 tx_status = XGMAC_IOREAD(pdata, tx_dsr); 3318 tx_status = GET_BITS(tx_status, tx_pos, DMA_DSR_TPS_WIDTH); 3319 if ((tx_status == DMA_TPS_STOPPED) || 3320 (tx_status == DMA_TPS_SUSPENDED)) 3321 break; 3322 3323 usleep_range(500, 1000); 3324 } 3325 3326 if (!time_before(jiffies, tx_timeout)) 3327 netdev_info(pdata->netdev, 3328 "timed out waiting for Tx DMA channel %u to stop\n", 3329 queue); 3330 } 3331 3332 static void xgbe_enable_tx(struct xgbe_prv_data *pdata) 3333 { 3334 unsigned int i; 3335 3336 /* Enable each Tx DMA channel */ 3337 for (i = 0; i < pdata->channel_count; i++) { 3338 if (!pdata->channel[i]->tx_ring) 3339 break; 3340 3341 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 1); 3342 } 3343 3344 /* Enable each Tx queue */ 3345 for (i = 0; i < pdata->tx_q_count; i++) 3346 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN, 3347 MTL_Q_ENABLED); 3348 3349 /* Enable MAC Tx */ 3350 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1); 3351 } 3352 3353 static void xgbe_disable_tx(struct xgbe_prv_data *pdata) 3354 { 3355 unsigned int i; 3356 3357 /* Prepare for Tx DMA channel stop */ 3358 for (i = 0; i < pdata->tx_q_count; i++) 3359 xgbe_prepare_tx_stop(pdata, i); 3360 3361 /* Disable MAC Tx */ 3362 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0); 3363 3364 /* Disable each Tx queue */ 3365 for (i = 0; i < pdata->tx_q_count; i++) 3366 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN, 0); 3367 3368 /* Disable each Tx DMA channel */ 3369 for (i = 0; i < pdata->channel_count; i++) { 3370 if (!pdata->channel[i]->tx_ring) 3371 break; 3372 3373 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 0); 3374 } 3375 } 3376 3377 static void xgbe_prepare_rx_stop(struct xgbe_prv_data *pdata, 3378 unsigned int queue) 3379 { 3380 unsigned int rx_status; 3381 unsigned long rx_timeout; 3382 3383 /* The Rx engine cannot be stopped if it is actively processing 3384 * packets. Wait for the Rx queue to empty the Rx fifo. Don't 3385 * wait forever though... 3386 */ 3387 rx_timeout = jiffies + (XGBE_DMA_STOP_TIMEOUT * HZ); 3388 while (time_before(jiffies, rx_timeout)) { 3389 rx_status = XGMAC_MTL_IOREAD(pdata, queue, MTL_Q_RQDR); 3390 if ((XGMAC_GET_BITS(rx_status, MTL_Q_RQDR, PRXQ) == 0) && 3391 (XGMAC_GET_BITS(rx_status, MTL_Q_RQDR, RXQSTS) == 0)) 3392 break; 3393 3394 usleep_range(500, 1000); 3395 } 3396 3397 if (!time_before(jiffies, rx_timeout)) 3398 netdev_info(pdata->netdev, 3399 "timed out waiting for Rx queue %u to empty\n", 3400 queue); 3401 } 3402 3403 static void xgbe_enable_rx(struct xgbe_prv_data *pdata) 3404 { 3405 unsigned int reg_val, i; 3406 3407 /* Enable each Rx DMA channel */ 3408 for (i = 0; i < pdata->channel_count; i++) { 3409 if (!pdata->channel[i]->rx_ring) 3410 break; 3411 3412 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 1); 3413 } 3414 3415 /* Enable each Rx queue */ 3416 reg_val = 0; 3417 for (i = 0; i < pdata->rx_q_count; i++) 3418 reg_val |= (0x02 << (i << 1)); 3419 XGMAC_IOWRITE(pdata, MAC_RQC0R, reg_val); 3420 3421 /* Enable MAC Rx */ 3422 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 1); 3423 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 1); 3424 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 1); 3425 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 1); 3426 } 3427 3428 static void xgbe_disable_rx(struct xgbe_prv_data *pdata) 3429 { 3430 unsigned int i; 3431 3432 /* Disable MAC Rx */ 3433 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 0); 3434 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 0); 3435 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 0); 3436 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 0); 3437 3438 /* Prepare for Rx DMA channel stop */ 3439 for (i = 0; i < pdata->rx_q_count; i++) 3440 xgbe_prepare_rx_stop(pdata, i); 3441 3442 /* Disable each Rx queue */ 3443 XGMAC_IOWRITE(pdata, MAC_RQC0R, 0); 3444 3445 /* Disable each Rx DMA channel */ 3446 for (i = 0; i < pdata->channel_count; i++) { 3447 if (!pdata->channel[i]->rx_ring) 3448 break; 3449 3450 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 0); 3451 } 3452 } 3453 3454 static void xgbe_powerup_tx(struct xgbe_prv_data *pdata) 3455 { 3456 unsigned int i; 3457 3458 /* Enable each Tx DMA channel */ 3459 for (i = 0; i < pdata->channel_count; i++) { 3460 if (!pdata->channel[i]->tx_ring) 3461 break; 3462 3463 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 1); 3464 } 3465 3466 /* Enable MAC Tx */ 3467 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1); 3468 } 3469 3470 static void xgbe_powerdown_tx(struct xgbe_prv_data *pdata) 3471 { 3472 unsigned int i; 3473 3474 /* Prepare for Tx DMA channel stop */ 3475 for (i = 0; i < pdata->tx_q_count; i++) 3476 xgbe_prepare_tx_stop(pdata, i); 3477 3478 /* Disable MAC Tx */ 3479 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0); 3480 3481 /* Disable each Tx DMA channel */ 3482 for (i = 0; i < pdata->channel_count; i++) { 3483 if (!pdata->channel[i]->tx_ring) 3484 break; 3485 3486 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 0); 3487 } 3488 } 3489 3490 static void xgbe_powerup_rx(struct xgbe_prv_data *pdata) 3491 { 3492 unsigned int i; 3493 3494 /* Enable each Rx DMA channel */ 3495 for (i = 0; i < pdata->channel_count; i++) { 3496 if (!pdata->channel[i]->rx_ring) 3497 break; 3498 3499 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 1); 3500 } 3501 } 3502 3503 static void xgbe_powerdown_rx(struct xgbe_prv_data *pdata) 3504 { 3505 unsigned int i; 3506 3507 /* Disable each Rx DMA channel */ 3508 for (i = 0; i < pdata->channel_count; i++) { 3509 if (!pdata->channel[i]->rx_ring) 3510 break; 3511 3512 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 0); 3513 } 3514 } 3515 3516 static int xgbe_init(struct xgbe_prv_data *pdata) 3517 { 3518 struct xgbe_desc_if *desc_if = &pdata->desc_if; 3519 int ret; 3520 3521 DBGPR("-->xgbe_init\n"); 3522 3523 /* Flush Tx queues */ 3524 ret = xgbe_flush_tx_queues(pdata); 3525 if (ret) { 3526 netdev_err(pdata->netdev, "error flushing TX queues\n"); 3527 return ret; 3528 } 3529 3530 /* 3531 * Initialize DMA related features 3532 */ 3533 xgbe_config_dma_bus(pdata); 3534 xgbe_config_dma_cache(pdata); 3535 xgbe_config_osp_mode(pdata); 3536 xgbe_config_pbl_val(pdata); 3537 xgbe_config_rx_coalesce(pdata); 3538 xgbe_config_tx_coalesce(pdata); 3539 xgbe_config_rx_buffer_size(pdata); 3540 xgbe_config_tso_mode(pdata); 3541 xgbe_config_sph_mode(pdata); 3542 xgbe_config_rss(pdata); 3543 desc_if->wrapper_tx_desc_init(pdata); 3544 desc_if->wrapper_rx_desc_init(pdata); 3545 xgbe_enable_dma_interrupts(pdata); 3546 3547 /* 3548 * Initialize MTL related features 3549 */ 3550 xgbe_config_mtl_mode(pdata); 3551 xgbe_config_queue_mapping(pdata); 3552 xgbe_config_tsf_mode(pdata, pdata->tx_sf_mode); 3553 xgbe_config_rsf_mode(pdata, pdata->rx_sf_mode); 3554 xgbe_config_tx_threshold(pdata, pdata->tx_threshold); 3555 xgbe_config_rx_threshold(pdata, pdata->rx_threshold); 3556 xgbe_config_tx_fifo_size(pdata); 3557 xgbe_config_rx_fifo_size(pdata); 3558 /*TODO: Error Packet and undersized good Packet forwarding enable 3559 (FEP and FUP) 3560 */ 3561 xgbe_config_dcb_tc(pdata); 3562 xgbe_enable_mtl_interrupts(pdata); 3563 3564 /* 3565 * Initialize MAC related features 3566 */ 3567 xgbe_config_mac_address(pdata); 3568 xgbe_config_rx_mode(pdata); 3569 xgbe_config_jumbo_enable(pdata); 3570 xgbe_config_flow_control(pdata); 3571 xgbe_config_mac_speed(pdata); 3572 xgbe_config_checksum_offload(pdata); 3573 xgbe_config_vlan_support(pdata); 3574 xgbe_config_mmc(pdata); 3575 xgbe_enable_mac_interrupts(pdata); 3576 3577 /* 3578 * Initialize ECC related features 3579 */ 3580 xgbe_enable_ecc_interrupts(pdata); 3581 3582 DBGPR("<--xgbe_init\n"); 3583 3584 return 0; 3585 } 3586 3587 void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *hw_if) 3588 { 3589 DBGPR("-->xgbe_init_function_ptrs\n"); 3590 3591 hw_if->tx_complete = xgbe_tx_complete; 3592 3593 hw_if->set_mac_address = xgbe_set_mac_address; 3594 hw_if->config_rx_mode = xgbe_config_rx_mode; 3595 3596 hw_if->enable_rx_csum = xgbe_enable_rx_csum; 3597 hw_if->disable_rx_csum = xgbe_disable_rx_csum; 3598 3599 hw_if->enable_rx_vlan_stripping = xgbe_enable_rx_vlan_stripping; 3600 hw_if->disable_rx_vlan_stripping = xgbe_disable_rx_vlan_stripping; 3601 hw_if->enable_rx_vlan_filtering = xgbe_enable_rx_vlan_filtering; 3602 hw_if->disable_rx_vlan_filtering = xgbe_disable_rx_vlan_filtering; 3603 hw_if->update_vlan_hash_table = xgbe_update_vlan_hash_table; 3604 3605 hw_if->read_mmd_regs = xgbe_read_mmd_regs; 3606 hw_if->write_mmd_regs = xgbe_write_mmd_regs; 3607 3608 hw_if->set_speed = xgbe_set_speed; 3609 3610 hw_if->set_ext_mii_mode = xgbe_set_ext_mii_mode; 3611 hw_if->read_ext_mii_regs_c22 = xgbe_read_ext_mii_regs_c22; 3612 hw_if->write_ext_mii_regs_c22 = xgbe_write_ext_mii_regs_c22; 3613 hw_if->read_ext_mii_regs_c45 = xgbe_read_ext_mii_regs_c45; 3614 hw_if->write_ext_mii_regs_c45 = xgbe_write_ext_mii_regs_c45; 3615 3616 hw_if->set_gpio = xgbe_set_gpio; 3617 hw_if->clr_gpio = xgbe_clr_gpio; 3618 3619 hw_if->enable_tx = xgbe_enable_tx; 3620 hw_if->disable_tx = xgbe_disable_tx; 3621 hw_if->enable_rx = xgbe_enable_rx; 3622 hw_if->disable_rx = xgbe_disable_rx; 3623 3624 hw_if->powerup_tx = xgbe_powerup_tx; 3625 hw_if->powerdown_tx = xgbe_powerdown_tx; 3626 hw_if->powerup_rx = xgbe_powerup_rx; 3627 hw_if->powerdown_rx = xgbe_powerdown_rx; 3628 3629 hw_if->dev_xmit = xgbe_dev_xmit; 3630 hw_if->dev_read = xgbe_dev_read; 3631 hw_if->enable_int = xgbe_enable_int; 3632 hw_if->disable_int = xgbe_disable_int; 3633 hw_if->init = xgbe_init; 3634 hw_if->exit = xgbe_exit; 3635 3636 /* Descriptor related Sequences have to be initialized here */ 3637 hw_if->tx_desc_init = xgbe_tx_desc_init; 3638 hw_if->rx_desc_init = xgbe_rx_desc_init; 3639 hw_if->tx_desc_reset = xgbe_tx_desc_reset; 3640 hw_if->rx_desc_reset = xgbe_rx_desc_reset; 3641 hw_if->is_last_desc = xgbe_is_last_desc; 3642 hw_if->is_context_desc = xgbe_is_context_desc; 3643 hw_if->tx_start_xmit = xgbe_tx_start_xmit; 3644 3645 /* For FLOW ctrl */ 3646 hw_if->config_tx_flow_control = xgbe_config_tx_flow_control; 3647 hw_if->config_rx_flow_control = xgbe_config_rx_flow_control; 3648 3649 /* For RX coalescing */ 3650 hw_if->config_rx_coalesce = xgbe_config_rx_coalesce; 3651 hw_if->config_tx_coalesce = xgbe_config_tx_coalesce; 3652 hw_if->usec_to_riwt = xgbe_usec_to_riwt; 3653 hw_if->riwt_to_usec = xgbe_riwt_to_usec; 3654 3655 /* For RX and TX threshold config */ 3656 hw_if->config_rx_threshold = xgbe_config_rx_threshold; 3657 hw_if->config_tx_threshold = xgbe_config_tx_threshold; 3658 3659 /* For RX and TX Store and Forward Mode config */ 3660 hw_if->config_rsf_mode = xgbe_config_rsf_mode; 3661 hw_if->config_tsf_mode = xgbe_config_tsf_mode; 3662 3663 /* For TX DMA Operating on Second Frame config */ 3664 hw_if->config_osp_mode = xgbe_config_osp_mode; 3665 3666 /* For MMC statistics support */ 3667 hw_if->tx_mmc_int = xgbe_tx_mmc_int; 3668 hw_if->rx_mmc_int = xgbe_rx_mmc_int; 3669 hw_if->read_mmc_stats = xgbe_read_mmc_stats; 3670 3671 /* For PTP config */ 3672 hw_if->config_tstamp = xgbe_config_tstamp; 3673 hw_if->update_tstamp_addend = xgbe_update_tstamp_addend; 3674 hw_if->set_tstamp_time = xgbe_set_tstamp_time; 3675 hw_if->get_tstamp_time = xgbe_get_tstamp_time; 3676 hw_if->get_tx_tstamp = xgbe_get_tx_tstamp; 3677 3678 /* For Data Center Bridging config */ 3679 hw_if->config_tc = xgbe_config_tc; 3680 hw_if->config_dcb_tc = xgbe_config_dcb_tc; 3681 hw_if->config_dcb_pfc = xgbe_config_dcb_pfc; 3682 3683 /* For Receive Side Scaling */ 3684 hw_if->enable_rss = xgbe_enable_rss; 3685 hw_if->disable_rss = xgbe_disable_rss; 3686 hw_if->set_rss_hash_key = xgbe_set_rss_hash_key; 3687 hw_if->set_rss_lookup_table = xgbe_set_rss_lookup_table; 3688 3689 /* For ECC */ 3690 hw_if->disable_ecc_ded = xgbe_disable_ecc_ded; 3691 hw_if->disable_ecc_sec = xgbe_disable_ecc_sec; 3692 3693 /* For VXLAN */ 3694 hw_if->enable_vxlan = xgbe_enable_vxlan; 3695 hw_if->disable_vxlan = xgbe_disable_vxlan; 3696 hw_if->set_vxlan_id = xgbe_set_vxlan_id; 3697 3698 DBGPR("<--xgbe_init_function_ptrs\n"); 3699 } 3700