1 /* 2 * AMD 10Gb Ethernet driver 3 * 4 * This file is available to you under your choice of the following two 5 * licenses: 6 * 7 * License 1: GPLv2 8 * 9 * Copyright (c) 2014 Advanced Micro Devices, Inc. 10 * 11 * This file is free software; you may copy, redistribute and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation, either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program. If not, see <http://www.gnu.org/licenses/>. 23 * 24 * This file incorporates work covered by the following copyright and 25 * permission notice: 26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 28 * Inc. unless otherwise expressly agreed to in writing between Synopsys 29 * and you. 30 * 31 * The Software IS NOT an item of Licensed Software or Licensed Product 32 * under any End User Software License Agreement or Agreement for Licensed 33 * Product with Synopsys or any supplement thereto. Permission is hereby 34 * granted, free of charge, to any person obtaining a copy of this software 35 * annotated with this license and the Software, to deal in the Software 36 * without restriction, including without limitation the rights to use, 37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 38 * of the Software, and to permit persons to whom the Software is furnished 39 * to do so, subject to the following conditions: 40 * 41 * The above copyright notice and this permission notice shall be included 42 * in all copies or substantial portions of the Software. 43 * 44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 54 * THE POSSIBILITY OF SUCH DAMAGE. 55 * 56 * 57 * License 2: Modified BSD 58 * 59 * Copyright (c) 2014 Advanced Micro Devices, Inc. 60 * All rights reserved. 61 * 62 * Redistribution and use in source and binary forms, with or without 63 * modification, are permitted provided that the following conditions are met: 64 * * Redistributions of source code must retain the above copyright 65 * notice, this list of conditions and the following disclaimer. 66 * * Redistributions in binary form must reproduce the above copyright 67 * notice, this list of conditions and the following disclaimer in the 68 * documentation and/or other materials provided with the distribution. 69 * * Neither the name of Advanced Micro Devices, Inc. nor the 70 * names of its contributors may be used to endorse or promote products 71 * derived from this software without specific prior written permission. 72 * 73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY 77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 83 * 84 * This file incorporates work covered by the following copyright and 85 * permission notice: 86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 88 * Inc. unless otherwise expressly agreed to in writing between Synopsys 89 * and you. 90 * 91 * The Software IS NOT an item of Licensed Software or Licensed Product 92 * under any End User Software License Agreement or Agreement for Licensed 93 * Product with Synopsys or any supplement thereto. Permission is hereby 94 * granted, free of charge, to any person obtaining a copy of this software 95 * annotated with this license and the Software, to deal in the Software 96 * without restriction, including without limitation the rights to use, 97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 98 * of the Software, and to permit persons to whom the Software is furnished 99 * to do so, subject to the following conditions: 100 * 101 * The above copyright notice and this permission notice shall be included 102 * in all copies or substantial portions of the Software. 103 * 104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 114 * THE POSSIBILITY OF SUCH DAMAGE. 115 */ 116 117 #include "xgbe.h" 118 #include "xgbe-common.h" 119 120 static void xgbe_unmap_rdata(struct xgbe_prv_data *, struct xgbe_ring_data *); 121 122 static void xgbe_free_ring(struct xgbe_prv_data *pdata, 123 struct xgbe_ring *ring) 124 { 125 struct xgbe_ring_data *rdata; 126 unsigned int i; 127 128 if (!ring) 129 return; 130 131 if (ring->rdata) { 132 for (i = 0; i < ring->rdesc_count; i++) { 133 rdata = XGBE_GET_DESC_DATA(ring, i); 134 xgbe_unmap_rdata(pdata, rdata); 135 } 136 137 kfree(ring->rdata); 138 ring->rdata = NULL; 139 } 140 141 if (ring->rx_hdr_pa.pages) { 142 dma_unmap_page(pdata->dev, ring->rx_hdr_pa.pages_dma, 143 ring->rx_hdr_pa.pages_len, DMA_FROM_DEVICE); 144 put_page(ring->rx_hdr_pa.pages); 145 146 ring->rx_hdr_pa.pages = NULL; 147 ring->rx_hdr_pa.pages_len = 0; 148 ring->rx_hdr_pa.pages_offset = 0; 149 ring->rx_hdr_pa.pages_dma = 0; 150 } 151 152 if (ring->rx_buf_pa.pages) { 153 dma_unmap_page(pdata->dev, ring->rx_buf_pa.pages_dma, 154 ring->rx_buf_pa.pages_len, DMA_FROM_DEVICE); 155 put_page(ring->rx_buf_pa.pages); 156 157 ring->rx_buf_pa.pages = NULL; 158 ring->rx_buf_pa.pages_len = 0; 159 ring->rx_buf_pa.pages_offset = 0; 160 ring->rx_buf_pa.pages_dma = 0; 161 } 162 163 if (ring->rdesc) { 164 dma_free_coherent(pdata->dev, 165 (sizeof(struct xgbe_ring_desc) * 166 ring->rdesc_count), 167 ring->rdesc, ring->rdesc_dma); 168 ring->rdesc = NULL; 169 } 170 } 171 172 static void xgbe_free_ring_resources(struct xgbe_prv_data *pdata) 173 { 174 struct xgbe_channel *channel; 175 unsigned int i; 176 177 DBGPR("-->xgbe_free_ring_resources\n"); 178 179 channel = pdata->channel; 180 for (i = 0; i < pdata->channel_count; i++, channel++) { 181 xgbe_free_ring(pdata, channel->tx_ring); 182 xgbe_free_ring(pdata, channel->rx_ring); 183 } 184 185 DBGPR("<--xgbe_free_ring_resources\n"); 186 } 187 188 static int xgbe_init_ring(struct xgbe_prv_data *pdata, 189 struct xgbe_ring *ring, unsigned int rdesc_count) 190 { 191 DBGPR("-->xgbe_init_ring\n"); 192 193 if (!ring) 194 return 0; 195 196 /* Descriptors */ 197 ring->rdesc_count = rdesc_count; 198 ring->rdesc = dma_alloc_coherent(pdata->dev, 199 (sizeof(struct xgbe_ring_desc) * 200 rdesc_count), &ring->rdesc_dma, 201 GFP_KERNEL); 202 if (!ring->rdesc) 203 return -ENOMEM; 204 205 /* Descriptor information */ 206 ring->rdata = kcalloc(rdesc_count, sizeof(struct xgbe_ring_data), 207 GFP_KERNEL); 208 if (!ring->rdata) 209 return -ENOMEM; 210 211 DBGPR(" rdesc=0x%p, rdesc_dma=0x%llx, rdata=0x%p\n", 212 ring->rdesc, ring->rdesc_dma, ring->rdata); 213 214 DBGPR("<--xgbe_init_ring\n"); 215 216 return 0; 217 } 218 219 static int xgbe_alloc_ring_resources(struct xgbe_prv_data *pdata) 220 { 221 struct xgbe_channel *channel; 222 unsigned int i; 223 int ret; 224 225 DBGPR("-->xgbe_alloc_ring_resources\n"); 226 227 channel = pdata->channel; 228 for (i = 0; i < pdata->channel_count; i++, channel++) { 229 DBGPR(" %s - tx_ring:\n", channel->name); 230 ret = xgbe_init_ring(pdata, channel->tx_ring, 231 pdata->tx_desc_count); 232 if (ret) { 233 netdev_alert(pdata->netdev, 234 "error initializing Tx ring\n"); 235 goto err_ring; 236 } 237 238 DBGPR(" %s - rx_ring:\n", channel->name); 239 ret = xgbe_init_ring(pdata, channel->rx_ring, 240 pdata->rx_desc_count); 241 if (ret) { 242 netdev_alert(pdata->netdev, 243 "error initializing Tx ring\n"); 244 goto err_ring; 245 } 246 } 247 248 DBGPR("<--xgbe_alloc_ring_resources\n"); 249 250 return 0; 251 252 err_ring: 253 xgbe_free_ring_resources(pdata); 254 255 return ret; 256 } 257 258 static int xgbe_alloc_pages(struct xgbe_prv_data *pdata, 259 struct xgbe_page_alloc *pa, gfp_t gfp, int order) 260 { 261 struct page *pages = NULL; 262 dma_addr_t pages_dma; 263 int ret; 264 265 /* Try to obtain pages, decreasing order if necessary */ 266 gfp |= __GFP_COLD | __GFP_COMP; 267 while (order >= 0) { 268 pages = alloc_pages(gfp, order); 269 if (pages) 270 break; 271 272 order--; 273 } 274 if (!pages) 275 return -ENOMEM; 276 277 /* Map the pages */ 278 pages_dma = dma_map_page(pdata->dev, pages, 0, 279 PAGE_SIZE << order, DMA_FROM_DEVICE); 280 ret = dma_mapping_error(pdata->dev, pages_dma); 281 if (ret) { 282 put_page(pages); 283 return ret; 284 } 285 286 pa->pages = pages; 287 pa->pages_len = PAGE_SIZE << order; 288 pa->pages_offset = 0; 289 pa->pages_dma = pages_dma; 290 291 return 0; 292 } 293 294 static void xgbe_set_buffer_data(struct xgbe_buffer_data *bd, 295 struct xgbe_page_alloc *pa, 296 unsigned int len) 297 { 298 get_page(pa->pages); 299 bd->pa = *pa; 300 301 bd->dma = pa->pages_dma + pa->pages_offset; 302 bd->dma_len = len; 303 304 pa->pages_offset += len; 305 if ((pa->pages_offset + len) > pa->pages_len) { 306 /* This data descriptor is responsible for unmapping page(s) */ 307 bd->pa_unmap = *pa; 308 309 /* Get a new allocation next time */ 310 pa->pages = NULL; 311 pa->pages_len = 0; 312 pa->pages_offset = 0; 313 pa->pages_dma = 0; 314 } 315 } 316 317 static int xgbe_map_rx_buffer(struct xgbe_prv_data *pdata, 318 struct xgbe_ring *ring, 319 struct xgbe_ring_data *rdata) 320 { 321 int order, ret; 322 323 if (!ring->rx_hdr_pa.pages) { 324 ret = xgbe_alloc_pages(pdata, &ring->rx_hdr_pa, GFP_ATOMIC, 0); 325 if (ret) 326 return ret; 327 } 328 329 if (!ring->rx_buf_pa.pages) { 330 order = max_t(int, PAGE_ALLOC_COSTLY_ORDER - 1, 0); 331 ret = xgbe_alloc_pages(pdata, &ring->rx_buf_pa, GFP_ATOMIC, 332 order); 333 if (ret) 334 return ret; 335 } 336 337 /* Set up the header page info */ 338 xgbe_set_buffer_data(&rdata->rx.hdr, &ring->rx_hdr_pa, 339 XGBE_SKB_ALLOC_SIZE); 340 341 /* Set up the buffer page info */ 342 xgbe_set_buffer_data(&rdata->rx.buf, &ring->rx_buf_pa, 343 pdata->rx_buf_size); 344 345 return 0; 346 } 347 348 static void xgbe_wrapper_tx_descriptor_init(struct xgbe_prv_data *pdata) 349 { 350 struct xgbe_hw_if *hw_if = &pdata->hw_if; 351 struct xgbe_channel *channel; 352 struct xgbe_ring *ring; 353 struct xgbe_ring_data *rdata; 354 struct xgbe_ring_desc *rdesc; 355 dma_addr_t rdesc_dma; 356 unsigned int i, j; 357 358 DBGPR("-->xgbe_wrapper_tx_descriptor_init\n"); 359 360 channel = pdata->channel; 361 for (i = 0; i < pdata->channel_count; i++, channel++) { 362 ring = channel->tx_ring; 363 if (!ring) 364 break; 365 366 rdesc = ring->rdesc; 367 rdesc_dma = ring->rdesc_dma; 368 369 for (j = 0; j < ring->rdesc_count; j++) { 370 rdata = XGBE_GET_DESC_DATA(ring, j); 371 372 rdata->rdesc = rdesc; 373 rdata->rdesc_dma = rdesc_dma; 374 375 rdesc++; 376 rdesc_dma += sizeof(struct xgbe_ring_desc); 377 } 378 379 ring->cur = 0; 380 ring->dirty = 0; 381 memset(&ring->tx, 0, sizeof(ring->tx)); 382 383 hw_if->tx_desc_init(channel); 384 } 385 386 DBGPR("<--xgbe_wrapper_tx_descriptor_init\n"); 387 } 388 389 static void xgbe_wrapper_rx_descriptor_init(struct xgbe_prv_data *pdata) 390 { 391 struct xgbe_hw_if *hw_if = &pdata->hw_if; 392 struct xgbe_channel *channel; 393 struct xgbe_ring *ring; 394 struct xgbe_ring_desc *rdesc; 395 struct xgbe_ring_data *rdata; 396 dma_addr_t rdesc_dma; 397 unsigned int i, j; 398 399 DBGPR("-->xgbe_wrapper_rx_descriptor_init\n"); 400 401 channel = pdata->channel; 402 for (i = 0; i < pdata->channel_count; i++, channel++) { 403 ring = channel->rx_ring; 404 if (!ring) 405 break; 406 407 rdesc = ring->rdesc; 408 rdesc_dma = ring->rdesc_dma; 409 410 for (j = 0; j < ring->rdesc_count; j++) { 411 rdata = XGBE_GET_DESC_DATA(ring, j); 412 413 rdata->rdesc = rdesc; 414 rdata->rdesc_dma = rdesc_dma; 415 416 if (xgbe_map_rx_buffer(pdata, ring, rdata)) 417 break; 418 419 rdesc++; 420 rdesc_dma += sizeof(struct xgbe_ring_desc); 421 } 422 423 ring->cur = 0; 424 ring->dirty = 0; 425 426 hw_if->rx_desc_init(channel); 427 } 428 429 DBGPR("<--xgbe_wrapper_rx_descriptor_init\n"); 430 } 431 432 static void xgbe_unmap_rdata(struct xgbe_prv_data *pdata, 433 struct xgbe_ring_data *rdata) 434 { 435 if (rdata->skb_dma) { 436 if (rdata->mapped_as_page) { 437 dma_unmap_page(pdata->dev, rdata->skb_dma, 438 rdata->skb_dma_len, DMA_TO_DEVICE); 439 } else { 440 dma_unmap_single(pdata->dev, rdata->skb_dma, 441 rdata->skb_dma_len, DMA_TO_DEVICE); 442 } 443 rdata->skb_dma = 0; 444 rdata->skb_dma_len = 0; 445 } 446 447 if (rdata->skb) { 448 dev_kfree_skb_any(rdata->skb); 449 rdata->skb = NULL; 450 } 451 452 if (rdata->rx.hdr.pa.pages) 453 put_page(rdata->rx.hdr.pa.pages); 454 455 if (rdata->rx.hdr.pa_unmap.pages) { 456 dma_unmap_page(pdata->dev, rdata->rx.hdr.pa_unmap.pages_dma, 457 rdata->rx.hdr.pa_unmap.pages_len, 458 DMA_FROM_DEVICE); 459 put_page(rdata->rx.hdr.pa_unmap.pages); 460 } 461 462 if (rdata->rx.buf.pa.pages) 463 put_page(rdata->rx.buf.pa.pages); 464 465 if (rdata->rx.buf.pa_unmap.pages) { 466 dma_unmap_page(pdata->dev, rdata->rx.buf.pa_unmap.pages_dma, 467 rdata->rx.buf.pa_unmap.pages_len, 468 DMA_FROM_DEVICE); 469 put_page(rdata->rx.buf.pa_unmap.pages); 470 } 471 472 memset(&rdata->tx, 0, sizeof(rdata->tx)); 473 memset(&rdata->rx, 0, sizeof(rdata->rx)); 474 475 rdata->mapped_as_page = 0; 476 477 if (rdata->state_saved) { 478 rdata->state_saved = 0; 479 rdata->state.incomplete = 0; 480 rdata->state.context_next = 0; 481 rdata->state.skb = NULL; 482 rdata->state.len = 0; 483 rdata->state.error = 0; 484 } 485 } 486 487 static int xgbe_map_tx_skb(struct xgbe_channel *channel, struct sk_buff *skb) 488 { 489 struct xgbe_prv_data *pdata = channel->pdata; 490 struct xgbe_ring *ring = channel->tx_ring; 491 struct xgbe_ring_data *rdata; 492 struct xgbe_packet_data *packet; 493 struct skb_frag_struct *frag; 494 dma_addr_t skb_dma; 495 unsigned int start_index, cur_index; 496 unsigned int offset, tso, vlan, datalen, len; 497 unsigned int i; 498 499 DBGPR("-->xgbe_map_tx_skb: cur = %d\n", ring->cur); 500 501 offset = 0; 502 start_index = ring->cur; 503 cur_index = ring->cur; 504 505 packet = &ring->packet_data; 506 packet->rdesc_count = 0; 507 packet->length = 0; 508 509 tso = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, 510 TSO_ENABLE); 511 vlan = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, 512 VLAN_CTAG); 513 514 /* Save space for a context descriptor if needed */ 515 if ((tso && (packet->mss != ring->tx.cur_mss)) || 516 (vlan && (packet->vlan_ctag != ring->tx.cur_vlan_ctag))) 517 cur_index++; 518 rdata = XGBE_GET_DESC_DATA(ring, cur_index); 519 520 if (tso) { 521 DBGPR(" TSO packet\n"); 522 523 /* Map the TSO header */ 524 skb_dma = dma_map_single(pdata->dev, skb->data, 525 packet->header_len, DMA_TO_DEVICE); 526 if (dma_mapping_error(pdata->dev, skb_dma)) { 527 netdev_alert(pdata->netdev, "dma_map_single failed\n"); 528 goto err_out; 529 } 530 rdata->skb_dma = skb_dma; 531 rdata->skb_dma_len = packet->header_len; 532 533 offset = packet->header_len; 534 535 packet->length += packet->header_len; 536 537 cur_index++; 538 rdata = XGBE_GET_DESC_DATA(ring, cur_index); 539 } 540 541 /* Map the (remainder of the) packet */ 542 for (datalen = skb_headlen(skb) - offset; datalen; ) { 543 len = min_t(unsigned int, datalen, XGBE_TX_MAX_BUF_SIZE); 544 545 skb_dma = dma_map_single(pdata->dev, skb->data + offset, len, 546 DMA_TO_DEVICE); 547 if (dma_mapping_error(pdata->dev, skb_dma)) { 548 netdev_alert(pdata->netdev, "dma_map_single failed\n"); 549 goto err_out; 550 } 551 rdata->skb_dma = skb_dma; 552 rdata->skb_dma_len = len; 553 DBGPR(" skb data: index=%u, dma=0x%llx, len=%u\n", 554 cur_index, skb_dma, len); 555 556 datalen -= len; 557 offset += len; 558 559 packet->length += len; 560 561 cur_index++; 562 rdata = XGBE_GET_DESC_DATA(ring, cur_index); 563 } 564 565 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 566 DBGPR(" mapping frag %u\n", i); 567 568 frag = &skb_shinfo(skb)->frags[i]; 569 offset = 0; 570 571 for (datalen = skb_frag_size(frag); datalen; ) { 572 len = min_t(unsigned int, datalen, 573 XGBE_TX_MAX_BUF_SIZE); 574 575 skb_dma = skb_frag_dma_map(pdata->dev, frag, offset, 576 len, DMA_TO_DEVICE); 577 if (dma_mapping_error(pdata->dev, skb_dma)) { 578 netdev_alert(pdata->netdev, 579 "skb_frag_dma_map failed\n"); 580 goto err_out; 581 } 582 rdata->skb_dma = skb_dma; 583 rdata->skb_dma_len = len; 584 rdata->mapped_as_page = 1; 585 DBGPR(" skb data: index=%u, dma=0x%llx, len=%u\n", 586 cur_index, skb_dma, len); 587 588 datalen -= len; 589 offset += len; 590 591 packet->length += len; 592 593 cur_index++; 594 rdata = XGBE_GET_DESC_DATA(ring, cur_index); 595 } 596 } 597 598 /* Save the skb address in the last entry. We always have some data 599 * that has been mapped so rdata is always advanced past the last 600 * piece of mapped data - use the entry pointed to by cur_index - 1. 601 */ 602 rdata = XGBE_GET_DESC_DATA(ring, cur_index - 1); 603 rdata->skb = skb; 604 605 /* Save the number of descriptor entries used */ 606 packet->rdesc_count = cur_index - start_index; 607 608 DBGPR("<--xgbe_map_tx_skb: count=%u\n", packet->rdesc_count); 609 610 return packet->rdesc_count; 611 612 err_out: 613 while (start_index < cur_index) { 614 rdata = XGBE_GET_DESC_DATA(ring, start_index++); 615 xgbe_unmap_rdata(pdata, rdata); 616 } 617 618 DBGPR("<--xgbe_map_tx_skb: count=0\n"); 619 620 return 0; 621 } 622 623 void xgbe_init_function_ptrs_desc(struct xgbe_desc_if *desc_if) 624 { 625 DBGPR("-->xgbe_init_function_ptrs_desc\n"); 626 627 desc_if->alloc_ring_resources = xgbe_alloc_ring_resources; 628 desc_if->free_ring_resources = xgbe_free_ring_resources; 629 desc_if->map_tx_skb = xgbe_map_tx_skb; 630 desc_if->map_rx_buffer = xgbe_map_rx_buffer; 631 desc_if->unmap_rdata = xgbe_unmap_rdata; 632 desc_if->wrapper_tx_desc_init = xgbe_wrapper_tx_descriptor_init; 633 desc_if->wrapper_rx_desc_init = xgbe_wrapper_rx_descriptor_init; 634 635 DBGPR("<--xgbe_init_function_ptrs_desc\n"); 636 } 637