1 /* 2 * AMD 10Gb Ethernet driver 3 * 4 * This file is available to you under your choice of the following two 5 * licenses: 6 * 7 * License 1: GPLv2 8 * 9 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc. 10 * 11 * This file is free software; you may copy, redistribute and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation, either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program. If not, see <http://www.gnu.org/licenses/>. 23 * 24 * This file incorporates work covered by the following copyright and 25 * permission notice: 26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 28 * Inc. unless otherwise expressly agreed to in writing between Synopsys 29 * and you. 30 * 31 * The Software IS NOT an item of Licensed Software or Licensed Product 32 * under any End User Software License Agreement or Agreement for Licensed 33 * Product with Synopsys or any supplement thereto. Permission is hereby 34 * granted, free of charge, to any person obtaining a copy of this software 35 * annotated with this license and the Software, to deal in the Software 36 * without restriction, including without limitation the rights to use, 37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 38 * of the Software, and to permit persons to whom the Software is furnished 39 * to do so, subject to the following conditions: 40 * 41 * The above copyright notice and this permission notice shall be included 42 * in all copies or substantial portions of the Software. 43 * 44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 54 * THE POSSIBILITY OF SUCH DAMAGE. 55 * 56 * 57 * License 2: Modified BSD 58 * 59 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc. 60 * All rights reserved. 61 * 62 * Redistribution and use in source and binary forms, with or without 63 * modification, are permitted provided that the following conditions are met: 64 * * Redistributions of source code must retain the above copyright 65 * notice, this list of conditions and the following disclaimer. 66 * * Redistributions in binary form must reproduce the above copyright 67 * notice, this list of conditions and the following disclaimer in the 68 * documentation and/or other materials provided with the distribution. 69 * * Neither the name of Advanced Micro Devices, Inc. nor the 70 * names of its contributors may be used to endorse or promote products 71 * derived from this software without specific prior written permission. 72 * 73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY 77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 83 * 84 * This file incorporates work covered by the following copyright and 85 * permission notice: 86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 88 * Inc. unless otherwise expressly agreed to in writing between Synopsys 89 * and you. 90 * 91 * The Software IS NOT an item of Licensed Software or Licensed Product 92 * under any End User Software License Agreement or Agreement for Licensed 93 * Product with Synopsys or any supplement thereto. Permission is hereby 94 * granted, free of charge, to any person obtaining a copy of this software 95 * annotated with this license and the Software, to deal in the Software 96 * without restriction, including without limitation the rights to use, 97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 98 * of the Software, and to permit persons to whom the Software is furnished 99 * to do so, subject to the following conditions: 100 * 101 * The above copyright notice and this permission notice shall be included 102 * in all copies or substantial portions of the Software. 103 * 104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 114 * THE POSSIBILITY OF SUCH DAMAGE. 115 */ 116 117 #ifndef __XGBE_COMMON_H__ 118 #define __XGBE_COMMON_H__ 119 120 /* DMA register offsets */ 121 #define DMA_MR 0x3000 122 #define DMA_SBMR 0x3004 123 #define DMA_ISR 0x3008 124 #define DMA_AXIARCR 0x3010 125 #define DMA_AXIAWCR 0x3018 126 #define DMA_AXIAWARCR 0x301c 127 #define DMA_DSR0 0x3020 128 #define DMA_DSR1 0x3024 129 #define DMA_TXEDMACR 0x3040 130 #define DMA_RXEDMACR 0x3044 131 132 /* DMA register entry bit positions and sizes */ 133 #define DMA_ISR_MACIS_INDEX 17 134 #define DMA_ISR_MACIS_WIDTH 1 135 #define DMA_ISR_MTLIS_INDEX 16 136 #define DMA_ISR_MTLIS_WIDTH 1 137 #define DMA_MR_INTM_INDEX 12 138 #define DMA_MR_INTM_WIDTH 2 139 #define DMA_MR_SWR_INDEX 0 140 #define DMA_MR_SWR_WIDTH 1 141 #define DMA_RXEDMACR_RDPS_INDEX 0 142 #define DMA_RXEDMACR_RDPS_WIDTH 3 143 #define DMA_SBMR_AAL_INDEX 12 144 #define DMA_SBMR_AAL_WIDTH 1 145 #define DMA_SBMR_EAME_INDEX 11 146 #define DMA_SBMR_EAME_WIDTH 1 147 #define DMA_SBMR_BLEN_INDEX 1 148 #define DMA_SBMR_BLEN_WIDTH 7 149 #define DMA_SBMR_RD_OSR_LMT_INDEX 16 150 #define DMA_SBMR_RD_OSR_LMT_WIDTH 6 151 #define DMA_SBMR_UNDEF_INDEX 0 152 #define DMA_SBMR_UNDEF_WIDTH 1 153 #define DMA_SBMR_WR_OSR_LMT_INDEX 24 154 #define DMA_SBMR_WR_OSR_LMT_WIDTH 6 155 #define DMA_TXEDMACR_TDPS_INDEX 0 156 #define DMA_TXEDMACR_TDPS_WIDTH 3 157 158 /* DMA register values */ 159 #define DMA_SBMR_BLEN_256 256 160 #define DMA_SBMR_BLEN_128 128 161 #define DMA_SBMR_BLEN_64 64 162 #define DMA_SBMR_BLEN_32 32 163 #define DMA_SBMR_BLEN_16 16 164 #define DMA_SBMR_BLEN_8 8 165 #define DMA_SBMR_BLEN_4 4 166 #define DMA_DSR_RPS_WIDTH 4 167 #define DMA_DSR_TPS_WIDTH 4 168 #define DMA_DSR_Q_WIDTH (DMA_DSR_RPS_WIDTH + DMA_DSR_TPS_WIDTH) 169 #define DMA_DSR0_RPS_START 8 170 #define DMA_DSR0_TPS_START 12 171 #define DMA_DSRX_FIRST_QUEUE 3 172 #define DMA_DSRX_INC 4 173 #define DMA_DSRX_QPR 4 174 #define DMA_DSRX_RPS_START 0 175 #define DMA_DSRX_TPS_START 4 176 #define DMA_TPS_STOPPED 0x00 177 #define DMA_TPS_SUSPENDED 0x06 178 179 /* DMA channel register offsets 180 * Multiple channels can be active. The first channel has registers 181 * that begin at 0x3100. Each subsequent channel has registers that 182 * are accessed using an offset of 0x80 from the previous channel. 183 */ 184 #define DMA_CH_BASE 0x3100 185 #define DMA_CH_INC 0x80 186 187 #define DMA_CH_CR 0x00 188 #define DMA_CH_TCR 0x04 189 #define DMA_CH_RCR 0x08 190 #define DMA_CH_TDLR_HI 0x10 191 #define DMA_CH_TDLR_LO 0x14 192 #define DMA_CH_RDLR_HI 0x18 193 #define DMA_CH_RDLR_LO 0x1c 194 #define DMA_CH_TDTR_LO 0x24 195 #define DMA_CH_RDTR_LO 0x2c 196 #define DMA_CH_TDRLR 0x30 197 #define DMA_CH_RDRLR 0x34 198 #define DMA_CH_IER 0x38 199 #define DMA_CH_RIWT 0x3c 200 #define DMA_CH_CATDR_LO 0x44 201 #define DMA_CH_CARDR_LO 0x4c 202 #define DMA_CH_CATBR_HI 0x50 203 #define DMA_CH_CATBR_LO 0x54 204 #define DMA_CH_CARBR_HI 0x58 205 #define DMA_CH_CARBR_LO 0x5c 206 #define DMA_CH_SR 0x60 207 208 /* DMA channel register entry bit positions and sizes */ 209 #define DMA_CH_CR_PBLX8_INDEX 16 210 #define DMA_CH_CR_PBLX8_WIDTH 1 211 #define DMA_CH_CR_SPH_INDEX 24 212 #define DMA_CH_CR_SPH_WIDTH 1 213 #define DMA_CH_IER_AIE_INDEX 15 214 #define DMA_CH_IER_AIE_WIDTH 1 215 #define DMA_CH_IER_FBEE_INDEX 12 216 #define DMA_CH_IER_FBEE_WIDTH 1 217 #define DMA_CH_IER_NIE_INDEX 16 218 #define DMA_CH_IER_NIE_WIDTH 1 219 #define DMA_CH_IER_RBUE_INDEX 7 220 #define DMA_CH_IER_RBUE_WIDTH 1 221 #define DMA_CH_IER_RIE_INDEX 6 222 #define DMA_CH_IER_RIE_WIDTH 1 223 #define DMA_CH_IER_RSE_INDEX 8 224 #define DMA_CH_IER_RSE_WIDTH 1 225 #define DMA_CH_IER_TBUE_INDEX 2 226 #define DMA_CH_IER_TBUE_WIDTH 1 227 #define DMA_CH_IER_TIE_INDEX 0 228 #define DMA_CH_IER_TIE_WIDTH 1 229 #define DMA_CH_IER_TXSE_INDEX 1 230 #define DMA_CH_IER_TXSE_WIDTH 1 231 #define DMA_CH_RCR_PBL_INDEX 16 232 #define DMA_CH_RCR_PBL_WIDTH 6 233 #define DMA_CH_RCR_RBSZ_INDEX 1 234 #define DMA_CH_RCR_RBSZ_WIDTH 14 235 #define DMA_CH_RCR_SR_INDEX 0 236 #define DMA_CH_RCR_SR_WIDTH 1 237 #define DMA_CH_RIWT_RWT_INDEX 0 238 #define DMA_CH_RIWT_RWT_WIDTH 8 239 #define DMA_CH_SR_FBE_INDEX 12 240 #define DMA_CH_SR_FBE_WIDTH 1 241 #define DMA_CH_SR_RBU_INDEX 7 242 #define DMA_CH_SR_RBU_WIDTH 1 243 #define DMA_CH_SR_RI_INDEX 6 244 #define DMA_CH_SR_RI_WIDTH 1 245 #define DMA_CH_SR_RPS_INDEX 8 246 #define DMA_CH_SR_RPS_WIDTH 1 247 #define DMA_CH_SR_TBU_INDEX 2 248 #define DMA_CH_SR_TBU_WIDTH 1 249 #define DMA_CH_SR_TI_INDEX 0 250 #define DMA_CH_SR_TI_WIDTH 1 251 #define DMA_CH_SR_TPS_INDEX 1 252 #define DMA_CH_SR_TPS_WIDTH 1 253 #define DMA_CH_TCR_OSP_INDEX 4 254 #define DMA_CH_TCR_OSP_WIDTH 1 255 #define DMA_CH_TCR_PBL_INDEX 16 256 #define DMA_CH_TCR_PBL_WIDTH 6 257 #define DMA_CH_TCR_ST_INDEX 0 258 #define DMA_CH_TCR_ST_WIDTH 1 259 #define DMA_CH_TCR_TSE_INDEX 12 260 #define DMA_CH_TCR_TSE_WIDTH 1 261 262 /* DMA channel register values */ 263 #define DMA_OSP_DISABLE 0x00 264 #define DMA_OSP_ENABLE 0x01 265 #define DMA_PBL_1 1 266 #define DMA_PBL_2 2 267 #define DMA_PBL_4 4 268 #define DMA_PBL_8 8 269 #define DMA_PBL_16 16 270 #define DMA_PBL_32 32 271 #define DMA_PBL_64 64 /* 8 x 8 */ 272 #define DMA_PBL_128 128 /* 8 x 16 */ 273 #define DMA_PBL_256 256 /* 8 x 32 */ 274 #define DMA_PBL_X8_DISABLE 0x00 275 #define DMA_PBL_X8_ENABLE 0x01 276 277 /* MAC register offsets */ 278 #define MAC_TCR 0x0000 279 #define MAC_RCR 0x0004 280 #define MAC_PFR 0x0008 281 #define MAC_WTR 0x000c 282 #define MAC_HTR0 0x0010 283 #define MAC_VLANTR 0x0050 284 #define MAC_VLANHTR 0x0058 285 #define MAC_VLANIR 0x0060 286 #define MAC_IVLANIR 0x0064 287 #define MAC_RETMR 0x006c 288 #define MAC_Q0TFCR 0x0070 289 #define MAC_RFCR 0x0090 290 #define MAC_RQC0R 0x00a0 291 #define MAC_RQC1R 0x00a4 292 #define MAC_RQC2R 0x00a8 293 #define MAC_RQC3R 0x00ac 294 #define MAC_ISR 0x00b0 295 #define MAC_IER 0x00b4 296 #define MAC_RTSR 0x00b8 297 #define MAC_PMTCSR 0x00c0 298 #define MAC_RWKPFR 0x00c4 299 #define MAC_LPICSR 0x00d0 300 #define MAC_LPITCR 0x00d4 301 #define MAC_VR 0x0110 302 #define MAC_DR 0x0114 303 #define MAC_HWF0R 0x011c 304 #define MAC_HWF1R 0x0120 305 #define MAC_HWF2R 0x0124 306 #define MAC_MDIOSCAR 0x0200 307 #define MAC_MDIOSCCDR 0x0204 308 #define MAC_MDIOISR 0x0214 309 #define MAC_MDIOIER 0x0218 310 #define MAC_MDIOCL22R 0x0220 311 #define MAC_GPIOCR 0x0278 312 #define MAC_GPIOSR 0x027c 313 #define MAC_MACA0HR 0x0300 314 #define MAC_MACA0LR 0x0304 315 #define MAC_MACA1HR 0x0308 316 #define MAC_MACA1LR 0x030c 317 #define MAC_RSSCR 0x0c80 318 #define MAC_RSSAR 0x0c88 319 #define MAC_RSSDR 0x0c8c 320 #define MAC_TSCR 0x0d00 321 #define MAC_SSIR 0x0d04 322 #define MAC_STSR 0x0d08 323 #define MAC_STNR 0x0d0c 324 #define MAC_STSUR 0x0d10 325 #define MAC_STNUR 0x0d14 326 #define MAC_TSAR 0x0d18 327 #define MAC_TSSR 0x0d20 328 #define MAC_TXSNR 0x0d30 329 #define MAC_TXSSR 0x0d34 330 331 #define MAC_QTFCR_INC 4 332 #define MAC_MACA_INC 4 333 #define MAC_HTR_INC 4 334 335 #define MAC_RQC2_INC 4 336 #define MAC_RQC2_Q_PER_REG 4 337 338 /* MAC register entry bit positions and sizes */ 339 #define MAC_HWF0R_ADDMACADRSEL_INDEX 18 340 #define MAC_HWF0R_ADDMACADRSEL_WIDTH 5 341 #define MAC_HWF0R_ARPOFFSEL_INDEX 9 342 #define MAC_HWF0R_ARPOFFSEL_WIDTH 1 343 #define MAC_HWF0R_EEESEL_INDEX 13 344 #define MAC_HWF0R_EEESEL_WIDTH 1 345 #define MAC_HWF0R_GMIISEL_INDEX 1 346 #define MAC_HWF0R_GMIISEL_WIDTH 1 347 #define MAC_HWF0R_MGKSEL_INDEX 7 348 #define MAC_HWF0R_MGKSEL_WIDTH 1 349 #define MAC_HWF0R_MMCSEL_INDEX 8 350 #define MAC_HWF0R_MMCSEL_WIDTH 1 351 #define MAC_HWF0R_RWKSEL_INDEX 6 352 #define MAC_HWF0R_RWKSEL_WIDTH 1 353 #define MAC_HWF0R_RXCOESEL_INDEX 16 354 #define MAC_HWF0R_RXCOESEL_WIDTH 1 355 #define MAC_HWF0R_SAVLANINS_INDEX 27 356 #define MAC_HWF0R_SAVLANINS_WIDTH 1 357 #define MAC_HWF0R_SMASEL_INDEX 5 358 #define MAC_HWF0R_SMASEL_WIDTH 1 359 #define MAC_HWF0R_TSSEL_INDEX 12 360 #define MAC_HWF0R_TSSEL_WIDTH 1 361 #define MAC_HWF0R_TSSTSSEL_INDEX 25 362 #define MAC_HWF0R_TSSTSSEL_WIDTH 2 363 #define MAC_HWF0R_TXCOESEL_INDEX 14 364 #define MAC_HWF0R_TXCOESEL_WIDTH 1 365 #define MAC_HWF0R_VLHASH_INDEX 4 366 #define MAC_HWF0R_VLHASH_WIDTH 1 367 #define MAC_HWF1R_ADDR64_INDEX 14 368 #define MAC_HWF1R_ADDR64_WIDTH 2 369 #define MAC_HWF1R_ADVTHWORD_INDEX 13 370 #define MAC_HWF1R_ADVTHWORD_WIDTH 1 371 #define MAC_HWF1R_DBGMEMA_INDEX 19 372 #define MAC_HWF1R_DBGMEMA_WIDTH 1 373 #define MAC_HWF1R_DCBEN_INDEX 16 374 #define MAC_HWF1R_DCBEN_WIDTH 1 375 #define MAC_HWF1R_HASHTBLSZ_INDEX 24 376 #define MAC_HWF1R_HASHTBLSZ_WIDTH 3 377 #define MAC_HWF1R_L3L4FNUM_INDEX 27 378 #define MAC_HWF1R_L3L4FNUM_WIDTH 4 379 #define MAC_HWF1R_NUMTC_INDEX 21 380 #define MAC_HWF1R_NUMTC_WIDTH 3 381 #define MAC_HWF1R_RSSEN_INDEX 20 382 #define MAC_HWF1R_RSSEN_WIDTH 1 383 #define MAC_HWF1R_RXFIFOSIZE_INDEX 0 384 #define MAC_HWF1R_RXFIFOSIZE_WIDTH 5 385 #define MAC_HWF1R_SPHEN_INDEX 17 386 #define MAC_HWF1R_SPHEN_WIDTH 1 387 #define MAC_HWF1R_TSOEN_INDEX 18 388 #define MAC_HWF1R_TSOEN_WIDTH 1 389 #define MAC_HWF1R_TXFIFOSIZE_INDEX 6 390 #define MAC_HWF1R_TXFIFOSIZE_WIDTH 5 391 #define MAC_HWF2R_AUXSNAPNUM_INDEX 28 392 #define MAC_HWF2R_AUXSNAPNUM_WIDTH 3 393 #define MAC_HWF2R_PPSOUTNUM_INDEX 24 394 #define MAC_HWF2R_PPSOUTNUM_WIDTH 3 395 #define MAC_HWF2R_RXCHCNT_INDEX 12 396 #define MAC_HWF2R_RXCHCNT_WIDTH 4 397 #define MAC_HWF2R_RXQCNT_INDEX 0 398 #define MAC_HWF2R_RXQCNT_WIDTH 4 399 #define MAC_HWF2R_TXCHCNT_INDEX 18 400 #define MAC_HWF2R_TXCHCNT_WIDTH 4 401 #define MAC_HWF2R_TXQCNT_INDEX 6 402 #define MAC_HWF2R_TXQCNT_WIDTH 4 403 #define MAC_IER_TSIE_INDEX 12 404 #define MAC_IER_TSIE_WIDTH 1 405 #define MAC_ISR_MMCRXIS_INDEX 9 406 #define MAC_ISR_MMCRXIS_WIDTH 1 407 #define MAC_ISR_MMCTXIS_INDEX 10 408 #define MAC_ISR_MMCTXIS_WIDTH 1 409 #define MAC_ISR_PMTIS_INDEX 4 410 #define MAC_ISR_PMTIS_WIDTH 1 411 #define MAC_ISR_SMI_INDEX 1 412 #define MAC_ISR_SMI_WIDTH 1 413 #define MAC_ISR_TSIS_INDEX 12 414 #define MAC_ISR_TSIS_WIDTH 1 415 #define MAC_MACA1HR_AE_INDEX 31 416 #define MAC_MACA1HR_AE_WIDTH 1 417 #define MAC_MDIOIER_SNGLCOMPIE_INDEX 12 418 #define MAC_MDIOIER_SNGLCOMPIE_WIDTH 1 419 #define MAC_MDIOISR_SNGLCOMPINT_INDEX 12 420 #define MAC_MDIOISR_SNGLCOMPINT_WIDTH 1 421 #define MAC_MDIOSCAR_DA_INDEX 21 422 #define MAC_MDIOSCAR_DA_WIDTH 5 423 #define MAC_MDIOSCAR_PA_INDEX 16 424 #define MAC_MDIOSCAR_PA_WIDTH 5 425 #define MAC_MDIOSCAR_RA_INDEX 0 426 #define MAC_MDIOSCAR_RA_WIDTH 16 427 #define MAC_MDIOSCAR_REG_INDEX 0 428 #define MAC_MDIOSCAR_REG_WIDTH 21 429 #define MAC_MDIOSCCDR_BUSY_INDEX 22 430 #define MAC_MDIOSCCDR_BUSY_WIDTH 1 431 #define MAC_MDIOSCCDR_CMD_INDEX 16 432 #define MAC_MDIOSCCDR_CMD_WIDTH 2 433 #define MAC_MDIOSCCDR_CR_INDEX 19 434 #define MAC_MDIOSCCDR_CR_WIDTH 3 435 #define MAC_MDIOSCCDR_DATA_INDEX 0 436 #define MAC_MDIOSCCDR_DATA_WIDTH 16 437 #define MAC_MDIOSCCDR_SADDR_INDEX 18 438 #define MAC_MDIOSCCDR_SADDR_WIDTH 1 439 #define MAC_PFR_HMC_INDEX 2 440 #define MAC_PFR_HMC_WIDTH 1 441 #define MAC_PFR_HPF_INDEX 10 442 #define MAC_PFR_HPF_WIDTH 1 443 #define MAC_PFR_HUC_INDEX 1 444 #define MAC_PFR_HUC_WIDTH 1 445 #define MAC_PFR_PM_INDEX 4 446 #define MAC_PFR_PM_WIDTH 1 447 #define MAC_PFR_PR_INDEX 0 448 #define MAC_PFR_PR_WIDTH 1 449 #define MAC_PFR_VTFE_INDEX 16 450 #define MAC_PFR_VTFE_WIDTH 1 451 #define MAC_PMTCSR_MGKPKTEN_INDEX 1 452 #define MAC_PMTCSR_MGKPKTEN_WIDTH 1 453 #define MAC_PMTCSR_PWRDWN_INDEX 0 454 #define MAC_PMTCSR_PWRDWN_WIDTH 1 455 #define MAC_PMTCSR_RWKFILTRST_INDEX 31 456 #define MAC_PMTCSR_RWKFILTRST_WIDTH 1 457 #define MAC_PMTCSR_RWKPKTEN_INDEX 2 458 #define MAC_PMTCSR_RWKPKTEN_WIDTH 1 459 #define MAC_Q0TFCR_PT_INDEX 16 460 #define MAC_Q0TFCR_PT_WIDTH 16 461 #define MAC_Q0TFCR_TFE_INDEX 1 462 #define MAC_Q0TFCR_TFE_WIDTH 1 463 #define MAC_RCR_ACS_INDEX 1 464 #define MAC_RCR_ACS_WIDTH 1 465 #define MAC_RCR_CST_INDEX 2 466 #define MAC_RCR_CST_WIDTH 1 467 #define MAC_RCR_DCRCC_INDEX 3 468 #define MAC_RCR_DCRCC_WIDTH 1 469 #define MAC_RCR_HDSMS_INDEX 12 470 #define MAC_RCR_HDSMS_WIDTH 3 471 #define MAC_RCR_IPC_INDEX 9 472 #define MAC_RCR_IPC_WIDTH 1 473 #define MAC_RCR_JE_INDEX 8 474 #define MAC_RCR_JE_WIDTH 1 475 #define MAC_RCR_LM_INDEX 10 476 #define MAC_RCR_LM_WIDTH 1 477 #define MAC_RCR_RE_INDEX 0 478 #define MAC_RCR_RE_WIDTH 1 479 #define MAC_RFCR_PFCE_INDEX 8 480 #define MAC_RFCR_PFCE_WIDTH 1 481 #define MAC_RFCR_RFE_INDEX 0 482 #define MAC_RFCR_RFE_WIDTH 1 483 #define MAC_RFCR_UP_INDEX 1 484 #define MAC_RFCR_UP_WIDTH 1 485 #define MAC_RQC0R_RXQ0EN_INDEX 0 486 #define MAC_RQC0R_RXQ0EN_WIDTH 2 487 #define MAC_RSSAR_ADDRT_INDEX 2 488 #define MAC_RSSAR_ADDRT_WIDTH 1 489 #define MAC_RSSAR_CT_INDEX 1 490 #define MAC_RSSAR_CT_WIDTH 1 491 #define MAC_RSSAR_OB_INDEX 0 492 #define MAC_RSSAR_OB_WIDTH 1 493 #define MAC_RSSAR_RSSIA_INDEX 8 494 #define MAC_RSSAR_RSSIA_WIDTH 8 495 #define MAC_RSSCR_IP2TE_INDEX 1 496 #define MAC_RSSCR_IP2TE_WIDTH 1 497 #define MAC_RSSCR_RSSE_INDEX 0 498 #define MAC_RSSCR_RSSE_WIDTH 1 499 #define MAC_RSSCR_TCP4TE_INDEX 2 500 #define MAC_RSSCR_TCP4TE_WIDTH 1 501 #define MAC_RSSCR_UDP4TE_INDEX 3 502 #define MAC_RSSCR_UDP4TE_WIDTH 1 503 #define MAC_RSSDR_DMCH_INDEX 0 504 #define MAC_RSSDR_DMCH_WIDTH 4 505 #define MAC_SSIR_SNSINC_INDEX 8 506 #define MAC_SSIR_SNSINC_WIDTH 8 507 #define MAC_SSIR_SSINC_INDEX 16 508 #define MAC_SSIR_SSINC_WIDTH 8 509 #define MAC_TCR_SS_INDEX 29 510 #define MAC_TCR_SS_WIDTH 2 511 #define MAC_TCR_TE_INDEX 0 512 #define MAC_TCR_TE_WIDTH 1 513 #define MAC_TSCR_AV8021ASMEN_INDEX 28 514 #define MAC_TSCR_AV8021ASMEN_WIDTH 1 515 #define MAC_TSCR_SNAPTYPSEL_INDEX 16 516 #define MAC_TSCR_SNAPTYPSEL_WIDTH 2 517 #define MAC_TSCR_TSADDREG_INDEX 5 518 #define MAC_TSCR_TSADDREG_WIDTH 1 519 #define MAC_TSCR_TSCFUPDT_INDEX 1 520 #define MAC_TSCR_TSCFUPDT_WIDTH 1 521 #define MAC_TSCR_TSCTRLSSR_INDEX 9 522 #define MAC_TSCR_TSCTRLSSR_WIDTH 1 523 #define MAC_TSCR_TSENA_INDEX 0 524 #define MAC_TSCR_TSENA_WIDTH 1 525 #define MAC_TSCR_TSENALL_INDEX 8 526 #define MAC_TSCR_TSENALL_WIDTH 1 527 #define MAC_TSCR_TSEVNTENA_INDEX 14 528 #define MAC_TSCR_TSEVNTENA_WIDTH 1 529 #define MAC_TSCR_TSINIT_INDEX 2 530 #define MAC_TSCR_TSINIT_WIDTH 1 531 #define MAC_TSCR_TSIPENA_INDEX 11 532 #define MAC_TSCR_TSIPENA_WIDTH 1 533 #define MAC_TSCR_TSIPV4ENA_INDEX 13 534 #define MAC_TSCR_TSIPV4ENA_WIDTH 1 535 #define MAC_TSCR_TSIPV6ENA_INDEX 12 536 #define MAC_TSCR_TSIPV6ENA_WIDTH 1 537 #define MAC_TSCR_TSMSTRENA_INDEX 15 538 #define MAC_TSCR_TSMSTRENA_WIDTH 1 539 #define MAC_TSCR_TSVER2ENA_INDEX 10 540 #define MAC_TSCR_TSVER2ENA_WIDTH 1 541 #define MAC_TSCR_TXTSSTSM_INDEX 24 542 #define MAC_TSCR_TXTSSTSM_WIDTH 1 543 #define MAC_TSSR_TXTSC_INDEX 15 544 #define MAC_TSSR_TXTSC_WIDTH 1 545 #define MAC_TXSNR_TXTSSTSMIS_INDEX 31 546 #define MAC_TXSNR_TXTSSTSMIS_WIDTH 1 547 #define MAC_VLANHTR_VLHT_INDEX 0 548 #define MAC_VLANHTR_VLHT_WIDTH 16 549 #define MAC_VLANIR_VLTI_INDEX 20 550 #define MAC_VLANIR_VLTI_WIDTH 1 551 #define MAC_VLANIR_CSVL_INDEX 19 552 #define MAC_VLANIR_CSVL_WIDTH 1 553 #define MAC_VLANTR_DOVLTC_INDEX 20 554 #define MAC_VLANTR_DOVLTC_WIDTH 1 555 #define MAC_VLANTR_ERSVLM_INDEX 19 556 #define MAC_VLANTR_ERSVLM_WIDTH 1 557 #define MAC_VLANTR_ESVL_INDEX 18 558 #define MAC_VLANTR_ESVL_WIDTH 1 559 #define MAC_VLANTR_ETV_INDEX 16 560 #define MAC_VLANTR_ETV_WIDTH 1 561 #define MAC_VLANTR_EVLS_INDEX 21 562 #define MAC_VLANTR_EVLS_WIDTH 2 563 #define MAC_VLANTR_EVLRXS_INDEX 24 564 #define MAC_VLANTR_EVLRXS_WIDTH 1 565 #define MAC_VLANTR_VL_INDEX 0 566 #define MAC_VLANTR_VL_WIDTH 16 567 #define MAC_VLANTR_VTHM_INDEX 25 568 #define MAC_VLANTR_VTHM_WIDTH 1 569 #define MAC_VLANTR_VTIM_INDEX 17 570 #define MAC_VLANTR_VTIM_WIDTH 1 571 #define MAC_VR_DEVID_INDEX 8 572 #define MAC_VR_DEVID_WIDTH 8 573 #define MAC_VR_SNPSVER_INDEX 0 574 #define MAC_VR_SNPSVER_WIDTH 8 575 #define MAC_VR_USERVER_INDEX 16 576 #define MAC_VR_USERVER_WIDTH 8 577 578 /* MMC register offsets */ 579 #define MMC_CR 0x0800 580 #define MMC_RISR 0x0804 581 #define MMC_TISR 0x0808 582 #define MMC_RIER 0x080c 583 #define MMC_TIER 0x0810 584 #define MMC_TXOCTETCOUNT_GB_LO 0x0814 585 #define MMC_TXOCTETCOUNT_GB_HI 0x0818 586 #define MMC_TXFRAMECOUNT_GB_LO 0x081c 587 #define MMC_TXFRAMECOUNT_GB_HI 0x0820 588 #define MMC_TXBROADCASTFRAMES_G_LO 0x0824 589 #define MMC_TXBROADCASTFRAMES_G_HI 0x0828 590 #define MMC_TXMULTICASTFRAMES_G_LO 0x082c 591 #define MMC_TXMULTICASTFRAMES_G_HI 0x0830 592 #define MMC_TX64OCTETS_GB_LO 0x0834 593 #define MMC_TX64OCTETS_GB_HI 0x0838 594 #define MMC_TX65TO127OCTETS_GB_LO 0x083c 595 #define MMC_TX65TO127OCTETS_GB_HI 0x0840 596 #define MMC_TX128TO255OCTETS_GB_LO 0x0844 597 #define MMC_TX128TO255OCTETS_GB_HI 0x0848 598 #define MMC_TX256TO511OCTETS_GB_LO 0x084c 599 #define MMC_TX256TO511OCTETS_GB_HI 0x0850 600 #define MMC_TX512TO1023OCTETS_GB_LO 0x0854 601 #define MMC_TX512TO1023OCTETS_GB_HI 0x0858 602 #define MMC_TX1024TOMAXOCTETS_GB_LO 0x085c 603 #define MMC_TX1024TOMAXOCTETS_GB_HI 0x0860 604 #define MMC_TXUNICASTFRAMES_GB_LO 0x0864 605 #define MMC_TXUNICASTFRAMES_GB_HI 0x0868 606 #define MMC_TXMULTICASTFRAMES_GB_LO 0x086c 607 #define MMC_TXMULTICASTFRAMES_GB_HI 0x0870 608 #define MMC_TXBROADCASTFRAMES_GB_LO 0x0874 609 #define MMC_TXBROADCASTFRAMES_GB_HI 0x0878 610 #define MMC_TXUNDERFLOWERROR_LO 0x087c 611 #define MMC_TXUNDERFLOWERROR_HI 0x0880 612 #define MMC_TXOCTETCOUNT_G_LO 0x0884 613 #define MMC_TXOCTETCOUNT_G_HI 0x0888 614 #define MMC_TXFRAMECOUNT_G_LO 0x088c 615 #define MMC_TXFRAMECOUNT_G_HI 0x0890 616 #define MMC_TXPAUSEFRAMES_LO 0x0894 617 #define MMC_TXPAUSEFRAMES_HI 0x0898 618 #define MMC_TXVLANFRAMES_G_LO 0x089c 619 #define MMC_TXVLANFRAMES_G_HI 0x08a0 620 #define MMC_RXFRAMECOUNT_GB_LO 0x0900 621 #define MMC_RXFRAMECOUNT_GB_HI 0x0904 622 #define MMC_RXOCTETCOUNT_GB_LO 0x0908 623 #define MMC_RXOCTETCOUNT_GB_HI 0x090c 624 #define MMC_RXOCTETCOUNT_G_LO 0x0910 625 #define MMC_RXOCTETCOUNT_G_HI 0x0914 626 #define MMC_RXBROADCASTFRAMES_G_LO 0x0918 627 #define MMC_RXBROADCASTFRAMES_G_HI 0x091c 628 #define MMC_RXMULTICASTFRAMES_G_LO 0x0920 629 #define MMC_RXMULTICASTFRAMES_G_HI 0x0924 630 #define MMC_RXCRCERROR_LO 0x0928 631 #define MMC_RXCRCERROR_HI 0x092c 632 #define MMC_RXRUNTERROR 0x0930 633 #define MMC_RXJABBERERROR 0x0934 634 #define MMC_RXUNDERSIZE_G 0x0938 635 #define MMC_RXOVERSIZE_G 0x093c 636 #define MMC_RX64OCTETS_GB_LO 0x0940 637 #define MMC_RX64OCTETS_GB_HI 0x0944 638 #define MMC_RX65TO127OCTETS_GB_LO 0x0948 639 #define MMC_RX65TO127OCTETS_GB_HI 0x094c 640 #define MMC_RX128TO255OCTETS_GB_LO 0x0950 641 #define MMC_RX128TO255OCTETS_GB_HI 0x0954 642 #define MMC_RX256TO511OCTETS_GB_LO 0x0958 643 #define MMC_RX256TO511OCTETS_GB_HI 0x095c 644 #define MMC_RX512TO1023OCTETS_GB_LO 0x0960 645 #define MMC_RX512TO1023OCTETS_GB_HI 0x0964 646 #define MMC_RX1024TOMAXOCTETS_GB_LO 0x0968 647 #define MMC_RX1024TOMAXOCTETS_GB_HI 0x096c 648 #define MMC_RXUNICASTFRAMES_G_LO 0x0970 649 #define MMC_RXUNICASTFRAMES_G_HI 0x0974 650 #define MMC_RXLENGTHERROR_LO 0x0978 651 #define MMC_RXLENGTHERROR_HI 0x097c 652 #define MMC_RXOUTOFRANGETYPE_LO 0x0980 653 #define MMC_RXOUTOFRANGETYPE_HI 0x0984 654 #define MMC_RXPAUSEFRAMES_LO 0x0988 655 #define MMC_RXPAUSEFRAMES_HI 0x098c 656 #define MMC_RXFIFOOVERFLOW_LO 0x0990 657 #define MMC_RXFIFOOVERFLOW_HI 0x0994 658 #define MMC_RXVLANFRAMES_GB_LO 0x0998 659 #define MMC_RXVLANFRAMES_GB_HI 0x099c 660 #define MMC_RXWATCHDOGERROR 0x09a0 661 662 /* MMC register entry bit positions and sizes */ 663 #define MMC_CR_CR_INDEX 0 664 #define MMC_CR_CR_WIDTH 1 665 #define MMC_CR_CSR_INDEX 1 666 #define MMC_CR_CSR_WIDTH 1 667 #define MMC_CR_ROR_INDEX 2 668 #define MMC_CR_ROR_WIDTH 1 669 #define MMC_CR_MCF_INDEX 3 670 #define MMC_CR_MCF_WIDTH 1 671 #define MMC_CR_MCT_INDEX 4 672 #define MMC_CR_MCT_WIDTH 2 673 #define MMC_RIER_ALL_INTERRUPTS_INDEX 0 674 #define MMC_RIER_ALL_INTERRUPTS_WIDTH 23 675 #define MMC_RISR_RXFRAMECOUNT_GB_INDEX 0 676 #define MMC_RISR_RXFRAMECOUNT_GB_WIDTH 1 677 #define MMC_RISR_RXOCTETCOUNT_GB_INDEX 1 678 #define MMC_RISR_RXOCTETCOUNT_GB_WIDTH 1 679 #define MMC_RISR_RXOCTETCOUNT_G_INDEX 2 680 #define MMC_RISR_RXOCTETCOUNT_G_WIDTH 1 681 #define MMC_RISR_RXBROADCASTFRAMES_G_INDEX 3 682 #define MMC_RISR_RXBROADCASTFRAMES_G_WIDTH 1 683 #define MMC_RISR_RXMULTICASTFRAMES_G_INDEX 4 684 #define MMC_RISR_RXMULTICASTFRAMES_G_WIDTH 1 685 #define MMC_RISR_RXCRCERROR_INDEX 5 686 #define MMC_RISR_RXCRCERROR_WIDTH 1 687 #define MMC_RISR_RXRUNTERROR_INDEX 6 688 #define MMC_RISR_RXRUNTERROR_WIDTH 1 689 #define MMC_RISR_RXJABBERERROR_INDEX 7 690 #define MMC_RISR_RXJABBERERROR_WIDTH 1 691 #define MMC_RISR_RXUNDERSIZE_G_INDEX 8 692 #define MMC_RISR_RXUNDERSIZE_G_WIDTH 1 693 #define MMC_RISR_RXOVERSIZE_G_INDEX 9 694 #define MMC_RISR_RXOVERSIZE_G_WIDTH 1 695 #define MMC_RISR_RX64OCTETS_GB_INDEX 10 696 #define MMC_RISR_RX64OCTETS_GB_WIDTH 1 697 #define MMC_RISR_RX65TO127OCTETS_GB_INDEX 11 698 #define MMC_RISR_RX65TO127OCTETS_GB_WIDTH 1 699 #define MMC_RISR_RX128TO255OCTETS_GB_INDEX 12 700 #define MMC_RISR_RX128TO255OCTETS_GB_WIDTH 1 701 #define MMC_RISR_RX256TO511OCTETS_GB_INDEX 13 702 #define MMC_RISR_RX256TO511OCTETS_GB_WIDTH 1 703 #define MMC_RISR_RX512TO1023OCTETS_GB_INDEX 14 704 #define MMC_RISR_RX512TO1023OCTETS_GB_WIDTH 1 705 #define MMC_RISR_RX1024TOMAXOCTETS_GB_INDEX 15 706 #define MMC_RISR_RX1024TOMAXOCTETS_GB_WIDTH 1 707 #define MMC_RISR_RXUNICASTFRAMES_G_INDEX 16 708 #define MMC_RISR_RXUNICASTFRAMES_G_WIDTH 1 709 #define MMC_RISR_RXLENGTHERROR_INDEX 17 710 #define MMC_RISR_RXLENGTHERROR_WIDTH 1 711 #define MMC_RISR_RXOUTOFRANGETYPE_INDEX 18 712 #define MMC_RISR_RXOUTOFRANGETYPE_WIDTH 1 713 #define MMC_RISR_RXPAUSEFRAMES_INDEX 19 714 #define MMC_RISR_RXPAUSEFRAMES_WIDTH 1 715 #define MMC_RISR_RXFIFOOVERFLOW_INDEX 20 716 #define MMC_RISR_RXFIFOOVERFLOW_WIDTH 1 717 #define MMC_RISR_RXVLANFRAMES_GB_INDEX 21 718 #define MMC_RISR_RXVLANFRAMES_GB_WIDTH 1 719 #define MMC_RISR_RXWATCHDOGERROR_INDEX 22 720 #define MMC_RISR_RXWATCHDOGERROR_WIDTH 1 721 #define MMC_TIER_ALL_INTERRUPTS_INDEX 0 722 #define MMC_TIER_ALL_INTERRUPTS_WIDTH 18 723 #define MMC_TISR_TXOCTETCOUNT_GB_INDEX 0 724 #define MMC_TISR_TXOCTETCOUNT_GB_WIDTH 1 725 #define MMC_TISR_TXFRAMECOUNT_GB_INDEX 1 726 #define MMC_TISR_TXFRAMECOUNT_GB_WIDTH 1 727 #define MMC_TISR_TXBROADCASTFRAMES_G_INDEX 2 728 #define MMC_TISR_TXBROADCASTFRAMES_G_WIDTH 1 729 #define MMC_TISR_TXMULTICASTFRAMES_G_INDEX 3 730 #define MMC_TISR_TXMULTICASTFRAMES_G_WIDTH 1 731 #define MMC_TISR_TX64OCTETS_GB_INDEX 4 732 #define MMC_TISR_TX64OCTETS_GB_WIDTH 1 733 #define MMC_TISR_TX65TO127OCTETS_GB_INDEX 5 734 #define MMC_TISR_TX65TO127OCTETS_GB_WIDTH 1 735 #define MMC_TISR_TX128TO255OCTETS_GB_INDEX 6 736 #define MMC_TISR_TX128TO255OCTETS_GB_WIDTH 1 737 #define MMC_TISR_TX256TO511OCTETS_GB_INDEX 7 738 #define MMC_TISR_TX256TO511OCTETS_GB_WIDTH 1 739 #define MMC_TISR_TX512TO1023OCTETS_GB_INDEX 8 740 #define MMC_TISR_TX512TO1023OCTETS_GB_WIDTH 1 741 #define MMC_TISR_TX1024TOMAXOCTETS_GB_INDEX 9 742 #define MMC_TISR_TX1024TOMAXOCTETS_GB_WIDTH 1 743 #define MMC_TISR_TXUNICASTFRAMES_GB_INDEX 10 744 #define MMC_TISR_TXUNICASTFRAMES_GB_WIDTH 1 745 #define MMC_TISR_TXMULTICASTFRAMES_GB_INDEX 11 746 #define MMC_TISR_TXMULTICASTFRAMES_GB_WIDTH 1 747 #define MMC_TISR_TXBROADCASTFRAMES_GB_INDEX 12 748 #define MMC_TISR_TXBROADCASTFRAMES_GB_WIDTH 1 749 #define MMC_TISR_TXUNDERFLOWERROR_INDEX 13 750 #define MMC_TISR_TXUNDERFLOWERROR_WIDTH 1 751 #define MMC_TISR_TXOCTETCOUNT_G_INDEX 14 752 #define MMC_TISR_TXOCTETCOUNT_G_WIDTH 1 753 #define MMC_TISR_TXFRAMECOUNT_G_INDEX 15 754 #define MMC_TISR_TXFRAMECOUNT_G_WIDTH 1 755 #define MMC_TISR_TXPAUSEFRAMES_INDEX 16 756 #define MMC_TISR_TXPAUSEFRAMES_WIDTH 1 757 #define MMC_TISR_TXVLANFRAMES_G_INDEX 17 758 #define MMC_TISR_TXVLANFRAMES_G_WIDTH 1 759 760 /* MTL register offsets */ 761 #define MTL_OMR 0x1000 762 #define MTL_FDCR 0x1008 763 #define MTL_FDSR 0x100c 764 #define MTL_FDDR 0x1010 765 #define MTL_ISR 0x1020 766 #define MTL_RQDCM0R 0x1030 767 #define MTL_TCPM0R 0x1040 768 #define MTL_TCPM1R 0x1044 769 770 #define MTL_RQDCM_INC 4 771 #define MTL_RQDCM_Q_PER_REG 4 772 #define MTL_TCPM_INC 4 773 #define MTL_TCPM_TC_PER_REG 4 774 775 /* MTL register entry bit positions and sizes */ 776 #define MTL_OMR_ETSALG_INDEX 5 777 #define MTL_OMR_ETSALG_WIDTH 2 778 #define MTL_OMR_RAA_INDEX 2 779 #define MTL_OMR_RAA_WIDTH 1 780 781 /* MTL queue register offsets 782 * Multiple queues can be active. The first queue has registers 783 * that begin at 0x1100. Each subsequent queue has registers that 784 * are accessed using an offset of 0x80 from the previous queue. 785 */ 786 #define MTL_Q_BASE 0x1100 787 #define MTL_Q_INC 0x80 788 789 #define MTL_Q_TQOMR 0x00 790 #define MTL_Q_TQUR 0x04 791 #define MTL_Q_TQDR 0x08 792 #define MTL_Q_RQOMR 0x40 793 #define MTL_Q_RQMPOCR 0x44 794 #define MTL_Q_RQDR 0x48 795 #define MTL_Q_RQFCR 0x50 796 #define MTL_Q_IER 0x70 797 #define MTL_Q_ISR 0x74 798 799 /* MTL queue register entry bit positions and sizes */ 800 #define MTL_Q_RQDR_PRXQ_INDEX 16 801 #define MTL_Q_RQDR_PRXQ_WIDTH 14 802 #define MTL_Q_RQDR_RXQSTS_INDEX 4 803 #define MTL_Q_RQDR_RXQSTS_WIDTH 2 804 #define MTL_Q_RQFCR_RFA_INDEX 1 805 #define MTL_Q_RQFCR_RFA_WIDTH 6 806 #define MTL_Q_RQFCR_RFD_INDEX 17 807 #define MTL_Q_RQFCR_RFD_WIDTH 6 808 #define MTL_Q_RQOMR_EHFC_INDEX 7 809 #define MTL_Q_RQOMR_EHFC_WIDTH 1 810 #define MTL_Q_RQOMR_RQS_INDEX 16 811 #define MTL_Q_RQOMR_RQS_WIDTH 9 812 #define MTL_Q_RQOMR_RSF_INDEX 5 813 #define MTL_Q_RQOMR_RSF_WIDTH 1 814 #define MTL_Q_RQOMR_RTC_INDEX 0 815 #define MTL_Q_RQOMR_RTC_WIDTH 2 816 #define MTL_Q_TQDR_TRCSTS_INDEX 1 817 #define MTL_Q_TQDR_TRCSTS_WIDTH 2 818 #define MTL_Q_TQDR_TXQSTS_INDEX 4 819 #define MTL_Q_TQDR_TXQSTS_WIDTH 1 820 #define MTL_Q_TQOMR_FTQ_INDEX 0 821 #define MTL_Q_TQOMR_FTQ_WIDTH 1 822 #define MTL_Q_TQOMR_Q2TCMAP_INDEX 8 823 #define MTL_Q_TQOMR_Q2TCMAP_WIDTH 3 824 #define MTL_Q_TQOMR_TQS_INDEX 16 825 #define MTL_Q_TQOMR_TQS_WIDTH 10 826 #define MTL_Q_TQOMR_TSF_INDEX 1 827 #define MTL_Q_TQOMR_TSF_WIDTH 1 828 #define MTL_Q_TQOMR_TTC_INDEX 4 829 #define MTL_Q_TQOMR_TTC_WIDTH 3 830 #define MTL_Q_TQOMR_TXQEN_INDEX 2 831 #define MTL_Q_TQOMR_TXQEN_WIDTH 2 832 833 /* MTL queue register value */ 834 #define MTL_RSF_DISABLE 0x00 835 #define MTL_RSF_ENABLE 0x01 836 #define MTL_TSF_DISABLE 0x00 837 #define MTL_TSF_ENABLE 0x01 838 839 #define MTL_RX_THRESHOLD_64 0x00 840 #define MTL_RX_THRESHOLD_96 0x02 841 #define MTL_RX_THRESHOLD_128 0x03 842 #define MTL_TX_THRESHOLD_32 0x01 843 #define MTL_TX_THRESHOLD_64 0x00 844 #define MTL_TX_THRESHOLD_96 0x02 845 #define MTL_TX_THRESHOLD_128 0x03 846 #define MTL_TX_THRESHOLD_192 0x04 847 #define MTL_TX_THRESHOLD_256 0x05 848 #define MTL_TX_THRESHOLD_384 0x06 849 #define MTL_TX_THRESHOLD_512 0x07 850 851 #define MTL_ETSALG_WRR 0x00 852 #define MTL_ETSALG_WFQ 0x01 853 #define MTL_ETSALG_DWRR 0x02 854 #define MTL_RAA_SP 0x00 855 #define MTL_RAA_WSP 0x01 856 857 #define MTL_Q_DISABLED 0x00 858 #define MTL_Q_ENABLED 0x02 859 860 /* MTL traffic class register offsets 861 * Multiple traffic classes can be active. The first class has registers 862 * that begin at 0x1100. Each subsequent queue has registers that 863 * are accessed using an offset of 0x80 from the previous queue. 864 */ 865 #define MTL_TC_BASE MTL_Q_BASE 866 #define MTL_TC_INC MTL_Q_INC 867 868 #define MTL_TC_ETSCR 0x10 869 #define MTL_TC_ETSSR 0x14 870 #define MTL_TC_QWR 0x18 871 872 /* MTL traffic class register entry bit positions and sizes */ 873 #define MTL_TC_ETSCR_TSA_INDEX 0 874 #define MTL_TC_ETSCR_TSA_WIDTH 2 875 #define MTL_TC_QWR_QW_INDEX 0 876 #define MTL_TC_QWR_QW_WIDTH 21 877 878 /* MTL traffic class register value */ 879 #define MTL_TSA_SP 0x00 880 #define MTL_TSA_ETS 0x02 881 882 /* PCS register offsets */ 883 #define PCS_V1_WINDOW_SELECT 0x03fc 884 #define PCS_V2_WINDOW_DEF 0x9060 885 #define PCS_V2_WINDOW_SELECT 0x9064 886 #define PCS_V2_RV_WINDOW_DEF 0x1060 887 #define PCS_V2_RV_WINDOW_SELECT 0x1064 888 889 /* PCS register entry bit positions and sizes */ 890 #define PCS_V2_WINDOW_DEF_OFFSET_INDEX 6 891 #define PCS_V2_WINDOW_DEF_OFFSET_WIDTH 14 892 #define PCS_V2_WINDOW_DEF_SIZE_INDEX 2 893 #define PCS_V2_WINDOW_DEF_SIZE_WIDTH 4 894 895 /* SerDes integration register offsets */ 896 #define SIR0_KR_RT_1 0x002c 897 #define SIR0_STATUS 0x0040 898 #define SIR1_SPEED 0x0000 899 900 /* SerDes integration register entry bit positions and sizes */ 901 #define SIR0_KR_RT_1_RESET_INDEX 11 902 #define SIR0_KR_RT_1_RESET_WIDTH 1 903 #define SIR0_STATUS_RX_READY_INDEX 0 904 #define SIR0_STATUS_RX_READY_WIDTH 1 905 #define SIR0_STATUS_TX_READY_INDEX 8 906 #define SIR0_STATUS_TX_READY_WIDTH 1 907 #define SIR1_SPEED_CDR_RATE_INDEX 12 908 #define SIR1_SPEED_CDR_RATE_WIDTH 4 909 #define SIR1_SPEED_DATARATE_INDEX 4 910 #define SIR1_SPEED_DATARATE_WIDTH 2 911 #define SIR1_SPEED_PLLSEL_INDEX 3 912 #define SIR1_SPEED_PLLSEL_WIDTH 1 913 #define SIR1_SPEED_RATECHANGE_INDEX 6 914 #define SIR1_SPEED_RATECHANGE_WIDTH 1 915 #define SIR1_SPEED_TXAMP_INDEX 8 916 #define SIR1_SPEED_TXAMP_WIDTH 4 917 #define SIR1_SPEED_WORDMODE_INDEX 0 918 #define SIR1_SPEED_WORDMODE_WIDTH 3 919 920 /* SerDes RxTx register offsets */ 921 #define RXTX_REG6 0x0018 922 #define RXTX_REG20 0x0050 923 #define RXTX_REG22 0x0058 924 #define RXTX_REG114 0x01c8 925 #define RXTX_REG129 0x0204 926 927 /* SerDes RxTx register entry bit positions and sizes */ 928 #define RXTX_REG6_RESETB_RXD_INDEX 8 929 #define RXTX_REG6_RESETB_RXD_WIDTH 1 930 #define RXTX_REG20_BLWC_ENA_INDEX 2 931 #define RXTX_REG20_BLWC_ENA_WIDTH 1 932 #define RXTX_REG114_PQ_REG_INDEX 9 933 #define RXTX_REG114_PQ_REG_WIDTH 7 934 #define RXTX_REG129_RXDFE_CONFIG_INDEX 14 935 #define RXTX_REG129_RXDFE_CONFIG_WIDTH 2 936 937 /* MAC Control register offsets */ 938 #define XP_PROP_0 0x0000 939 #define XP_PROP_1 0x0004 940 #define XP_PROP_2 0x0008 941 #define XP_PROP_3 0x000c 942 #define XP_PROP_4 0x0010 943 #define XP_PROP_5 0x0014 944 #define XP_MAC_ADDR_LO 0x0020 945 #define XP_MAC_ADDR_HI 0x0024 946 #define XP_ECC_ISR 0x0030 947 #define XP_ECC_IER 0x0034 948 #define XP_ECC_CNT0 0x003c 949 #define XP_ECC_CNT1 0x0040 950 #define XP_DRIVER_INT_REQ 0x0060 951 #define XP_DRIVER_INT_RO 0x0064 952 #define XP_DRIVER_SCRATCH_0 0x0068 953 #define XP_DRIVER_SCRATCH_1 0x006c 954 #define XP_INT_REISSUE_EN 0x0074 955 #define XP_INT_EN 0x0078 956 #define XP_I2C_MUTEX 0x0080 957 #define XP_MDIO_MUTEX 0x0084 958 959 /* MAC Control register entry bit positions and sizes */ 960 #define XP_DRIVER_INT_REQ_REQUEST_INDEX 0 961 #define XP_DRIVER_INT_REQ_REQUEST_WIDTH 1 962 #define XP_DRIVER_INT_RO_STATUS_INDEX 0 963 #define XP_DRIVER_INT_RO_STATUS_WIDTH 1 964 #define XP_DRIVER_SCRATCH_0_COMMAND_INDEX 0 965 #define XP_DRIVER_SCRATCH_0_COMMAND_WIDTH 8 966 #define XP_DRIVER_SCRATCH_0_SUB_COMMAND_INDEX 8 967 #define XP_DRIVER_SCRATCH_0_SUB_COMMAND_WIDTH 8 968 #define XP_ECC_CNT0_RX_DED_INDEX 24 969 #define XP_ECC_CNT0_RX_DED_WIDTH 8 970 #define XP_ECC_CNT0_RX_SEC_INDEX 16 971 #define XP_ECC_CNT0_RX_SEC_WIDTH 8 972 #define XP_ECC_CNT0_TX_DED_INDEX 8 973 #define XP_ECC_CNT0_TX_DED_WIDTH 8 974 #define XP_ECC_CNT0_TX_SEC_INDEX 0 975 #define XP_ECC_CNT0_TX_SEC_WIDTH 8 976 #define XP_ECC_CNT1_DESC_DED_INDEX 8 977 #define XP_ECC_CNT1_DESC_DED_WIDTH 8 978 #define XP_ECC_CNT1_DESC_SEC_INDEX 0 979 #define XP_ECC_CNT1_DESC_SEC_WIDTH 8 980 #define XP_ECC_IER_DESC_DED_INDEX 5 981 #define XP_ECC_IER_DESC_DED_WIDTH 1 982 #define XP_ECC_IER_DESC_SEC_INDEX 4 983 #define XP_ECC_IER_DESC_SEC_WIDTH 1 984 #define XP_ECC_IER_RX_DED_INDEX 3 985 #define XP_ECC_IER_RX_DED_WIDTH 1 986 #define XP_ECC_IER_RX_SEC_INDEX 2 987 #define XP_ECC_IER_RX_SEC_WIDTH 1 988 #define XP_ECC_IER_TX_DED_INDEX 1 989 #define XP_ECC_IER_TX_DED_WIDTH 1 990 #define XP_ECC_IER_TX_SEC_INDEX 0 991 #define XP_ECC_IER_TX_SEC_WIDTH 1 992 #define XP_ECC_ISR_DESC_DED_INDEX 5 993 #define XP_ECC_ISR_DESC_DED_WIDTH 1 994 #define XP_ECC_ISR_DESC_SEC_INDEX 4 995 #define XP_ECC_ISR_DESC_SEC_WIDTH 1 996 #define XP_ECC_ISR_RX_DED_INDEX 3 997 #define XP_ECC_ISR_RX_DED_WIDTH 1 998 #define XP_ECC_ISR_RX_SEC_INDEX 2 999 #define XP_ECC_ISR_RX_SEC_WIDTH 1 1000 #define XP_ECC_ISR_TX_DED_INDEX 1 1001 #define XP_ECC_ISR_TX_DED_WIDTH 1 1002 #define XP_ECC_ISR_TX_SEC_INDEX 0 1003 #define XP_ECC_ISR_TX_SEC_WIDTH 1 1004 #define XP_I2C_MUTEX_BUSY_INDEX 31 1005 #define XP_I2C_MUTEX_BUSY_WIDTH 1 1006 #define XP_I2C_MUTEX_ID_INDEX 29 1007 #define XP_I2C_MUTEX_ID_WIDTH 2 1008 #define XP_I2C_MUTEX_ACTIVE_INDEX 0 1009 #define XP_I2C_MUTEX_ACTIVE_WIDTH 1 1010 #define XP_MAC_ADDR_HI_VALID_INDEX 31 1011 #define XP_MAC_ADDR_HI_VALID_WIDTH 1 1012 #define XP_PROP_0_CONN_TYPE_INDEX 28 1013 #define XP_PROP_0_CONN_TYPE_WIDTH 3 1014 #define XP_PROP_0_MDIO_ADDR_INDEX 16 1015 #define XP_PROP_0_MDIO_ADDR_WIDTH 5 1016 #define XP_PROP_0_PORT_ID_INDEX 0 1017 #define XP_PROP_0_PORT_ID_WIDTH 8 1018 #define XP_PROP_0_PORT_MODE_INDEX 8 1019 #define XP_PROP_0_PORT_MODE_WIDTH 4 1020 #define XP_PROP_0_PORT_SPEEDS_INDEX 23 1021 #define XP_PROP_0_PORT_SPEEDS_WIDTH 4 1022 #define XP_PROP_1_MAX_RX_DMA_INDEX 24 1023 #define XP_PROP_1_MAX_RX_DMA_WIDTH 5 1024 #define XP_PROP_1_MAX_RX_QUEUES_INDEX 8 1025 #define XP_PROP_1_MAX_RX_QUEUES_WIDTH 5 1026 #define XP_PROP_1_MAX_TX_DMA_INDEX 16 1027 #define XP_PROP_1_MAX_TX_DMA_WIDTH 5 1028 #define XP_PROP_1_MAX_TX_QUEUES_INDEX 0 1029 #define XP_PROP_1_MAX_TX_QUEUES_WIDTH 5 1030 #define XP_PROP_2_RX_FIFO_SIZE_INDEX 16 1031 #define XP_PROP_2_RX_FIFO_SIZE_WIDTH 16 1032 #define XP_PROP_2_TX_FIFO_SIZE_INDEX 0 1033 #define XP_PROP_2_TX_FIFO_SIZE_WIDTH 16 1034 #define XP_PROP_3_GPIO_MASK_INDEX 28 1035 #define XP_PROP_3_GPIO_MASK_WIDTH 4 1036 #define XP_PROP_3_GPIO_MOD_ABS_INDEX 20 1037 #define XP_PROP_3_GPIO_MOD_ABS_WIDTH 4 1038 #define XP_PROP_3_GPIO_RATE_SELECT_INDEX 16 1039 #define XP_PROP_3_GPIO_RATE_SELECT_WIDTH 4 1040 #define XP_PROP_3_GPIO_RX_LOS_INDEX 24 1041 #define XP_PROP_3_GPIO_RX_LOS_WIDTH 4 1042 #define XP_PROP_3_GPIO_TX_FAULT_INDEX 12 1043 #define XP_PROP_3_GPIO_TX_FAULT_WIDTH 4 1044 #define XP_PROP_3_GPIO_ADDR_INDEX 8 1045 #define XP_PROP_3_GPIO_ADDR_WIDTH 3 1046 #define XP_PROP_3_MDIO_RESET_INDEX 0 1047 #define XP_PROP_3_MDIO_RESET_WIDTH 2 1048 #define XP_PROP_3_MDIO_RESET_I2C_ADDR_INDEX 8 1049 #define XP_PROP_3_MDIO_RESET_I2C_ADDR_WIDTH 3 1050 #define XP_PROP_3_MDIO_RESET_I2C_GPIO_INDEX 12 1051 #define XP_PROP_3_MDIO_RESET_I2C_GPIO_WIDTH 4 1052 #define XP_PROP_3_MDIO_RESET_INT_GPIO_INDEX 4 1053 #define XP_PROP_3_MDIO_RESET_INT_GPIO_WIDTH 2 1054 #define XP_PROP_4_MUX_ADDR_HI_INDEX 8 1055 #define XP_PROP_4_MUX_ADDR_HI_WIDTH 5 1056 #define XP_PROP_4_MUX_ADDR_LO_INDEX 0 1057 #define XP_PROP_4_MUX_ADDR_LO_WIDTH 3 1058 #define XP_PROP_4_MUX_CHAN_INDEX 4 1059 #define XP_PROP_4_MUX_CHAN_WIDTH 3 1060 #define XP_PROP_4_REDRV_ADDR_INDEX 16 1061 #define XP_PROP_4_REDRV_ADDR_WIDTH 7 1062 #define XP_PROP_4_REDRV_IF_INDEX 23 1063 #define XP_PROP_4_REDRV_IF_WIDTH 1 1064 #define XP_PROP_4_REDRV_LANE_INDEX 24 1065 #define XP_PROP_4_REDRV_LANE_WIDTH 3 1066 #define XP_PROP_4_REDRV_MODEL_INDEX 28 1067 #define XP_PROP_4_REDRV_MODEL_WIDTH 3 1068 #define XP_PROP_4_REDRV_PRESENT_INDEX 31 1069 #define XP_PROP_4_REDRV_PRESENT_WIDTH 1 1070 1071 /* I2C Control register offsets */ 1072 #define IC_CON 0x0000 1073 #define IC_TAR 0x0004 1074 #define IC_DATA_CMD 0x0010 1075 #define IC_INTR_STAT 0x002c 1076 #define IC_INTR_MASK 0x0030 1077 #define IC_RAW_INTR_STAT 0x0034 1078 #define IC_CLR_INTR 0x0040 1079 #define IC_CLR_TX_ABRT 0x0054 1080 #define IC_CLR_STOP_DET 0x0060 1081 #define IC_ENABLE 0x006c 1082 #define IC_TXFLR 0x0074 1083 #define IC_RXFLR 0x0078 1084 #define IC_TX_ABRT_SOURCE 0x0080 1085 #define IC_ENABLE_STATUS 0x009c 1086 #define IC_COMP_PARAM_1 0x00f4 1087 1088 /* I2C Control register entry bit positions and sizes */ 1089 #define IC_COMP_PARAM_1_MAX_SPEED_MODE_INDEX 2 1090 #define IC_COMP_PARAM_1_MAX_SPEED_MODE_WIDTH 2 1091 #define IC_COMP_PARAM_1_RX_BUFFER_DEPTH_INDEX 8 1092 #define IC_COMP_PARAM_1_RX_BUFFER_DEPTH_WIDTH 8 1093 #define IC_COMP_PARAM_1_TX_BUFFER_DEPTH_INDEX 16 1094 #define IC_COMP_PARAM_1_TX_BUFFER_DEPTH_WIDTH 8 1095 #define IC_CON_MASTER_MODE_INDEX 0 1096 #define IC_CON_MASTER_MODE_WIDTH 1 1097 #define IC_CON_RESTART_EN_INDEX 5 1098 #define IC_CON_RESTART_EN_WIDTH 1 1099 #define IC_CON_RX_FIFO_FULL_HOLD_INDEX 9 1100 #define IC_CON_RX_FIFO_FULL_HOLD_WIDTH 1 1101 #define IC_CON_SLAVE_DISABLE_INDEX 6 1102 #define IC_CON_SLAVE_DISABLE_WIDTH 1 1103 #define IC_CON_SPEED_INDEX 1 1104 #define IC_CON_SPEED_WIDTH 2 1105 #define IC_DATA_CMD_CMD_INDEX 8 1106 #define IC_DATA_CMD_CMD_WIDTH 1 1107 #define IC_DATA_CMD_STOP_INDEX 9 1108 #define IC_DATA_CMD_STOP_WIDTH 1 1109 #define IC_ENABLE_ABORT_INDEX 1 1110 #define IC_ENABLE_ABORT_WIDTH 1 1111 #define IC_ENABLE_EN_INDEX 0 1112 #define IC_ENABLE_EN_WIDTH 1 1113 #define IC_ENABLE_STATUS_EN_INDEX 0 1114 #define IC_ENABLE_STATUS_EN_WIDTH 1 1115 #define IC_INTR_MASK_TX_EMPTY_INDEX 4 1116 #define IC_INTR_MASK_TX_EMPTY_WIDTH 1 1117 #define IC_RAW_INTR_STAT_RX_FULL_INDEX 2 1118 #define IC_RAW_INTR_STAT_RX_FULL_WIDTH 1 1119 #define IC_RAW_INTR_STAT_STOP_DET_INDEX 9 1120 #define IC_RAW_INTR_STAT_STOP_DET_WIDTH 1 1121 #define IC_RAW_INTR_STAT_TX_ABRT_INDEX 6 1122 #define IC_RAW_INTR_STAT_TX_ABRT_WIDTH 1 1123 #define IC_RAW_INTR_STAT_TX_EMPTY_INDEX 4 1124 #define IC_RAW_INTR_STAT_TX_EMPTY_WIDTH 1 1125 1126 /* I2C Control register value */ 1127 #define IC_TX_ABRT_7B_ADDR_NOACK 0x0001 1128 #define IC_TX_ABRT_ARB_LOST 0x1000 1129 1130 /* Descriptor/Packet entry bit positions and sizes */ 1131 #define RX_PACKET_ERRORS_CRC_INDEX 2 1132 #define RX_PACKET_ERRORS_CRC_WIDTH 1 1133 #define RX_PACKET_ERRORS_FRAME_INDEX 3 1134 #define RX_PACKET_ERRORS_FRAME_WIDTH 1 1135 #define RX_PACKET_ERRORS_LENGTH_INDEX 0 1136 #define RX_PACKET_ERRORS_LENGTH_WIDTH 1 1137 #define RX_PACKET_ERRORS_OVERRUN_INDEX 1 1138 #define RX_PACKET_ERRORS_OVERRUN_WIDTH 1 1139 1140 #define RX_PACKET_ATTRIBUTES_CSUM_DONE_INDEX 0 1141 #define RX_PACKET_ATTRIBUTES_CSUM_DONE_WIDTH 1 1142 #define RX_PACKET_ATTRIBUTES_VLAN_CTAG_INDEX 1 1143 #define RX_PACKET_ATTRIBUTES_VLAN_CTAG_WIDTH 1 1144 #define RX_PACKET_ATTRIBUTES_LAST_INDEX 2 1145 #define RX_PACKET_ATTRIBUTES_LAST_WIDTH 1 1146 #define RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_INDEX 3 1147 #define RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_WIDTH 1 1148 #define RX_PACKET_ATTRIBUTES_CONTEXT_INDEX 4 1149 #define RX_PACKET_ATTRIBUTES_CONTEXT_WIDTH 1 1150 #define RX_PACKET_ATTRIBUTES_RX_TSTAMP_INDEX 5 1151 #define RX_PACKET_ATTRIBUTES_RX_TSTAMP_WIDTH 1 1152 #define RX_PACKET_ATTRIBUTES_RSS_HASH_INDEX 6 1153 #define RX_PACKET_ATTRIBUTES_RSS_HASH_WIDTH 1 1154 #define RX_PACKET_ATTRIBUTES_FIRST_INDEX 7 1155 #define RX_PACKET_ATTRIBUTES_FIRST_WIDTH 1 1156 1157 #define RX_NORMAL_DESC0_OVT_INDEX 0 1158 #define RX_NORMAL_DESC0_OVT_WIDTH 16 1159 #define RX_NORMAL_DESC2_HL_INDEX 0 1160 #define RX_NORMAL_DESC2_HL_WIDTH 10 1161 #define RX_NORMAL_DESC3_CDA_INDEX 27 1162 #define RX_NORMAL_DESC3_CDA_WIDTH 1 1163 #define RX_NORMAL_DESC3_CTXT_INDEX 30 1164 #define RX_NORMAL_DESC3_CTXT_WIDTH 1 1165 #define RX_NORMAL_DESC3_ES_INDEX 15 1166 #define RX_NORMAL_DESC3_ES_WIDTH 1 1167 #define RX_NORMAL_DESC3_ETLT_INDEX 16 1168 #define RX_NORMAL_DESC3_ETLT_WIDTH 4 1169 #define RX_NORMAL_DESC3_FD_INDEX 29 1170 #define RX_NORMAL_DESC3_FD_WIDTH 1 1171 #define RX_NORMAL_DESC3_INTE_INDEX 30 1172 #define RX_NORMAL_DESC3_INTE_WIDTH 1 1173 #define RX_NORMAL_DESC3_L34T_INDEX 20 1174 #define RX_NORMAL_DESC3_L34T_WIDTH 4 1175 #define RX_NORMAL_DESC3_LD_INDEX 28 1176 #define RX_NORMAL_DESC3_LD_WIDTH 1 1177 #define RX_NORMAL_DESC3_OWN_INDEX 31 1178 #define RX_NORMAL_DESC3_OWN_WIDTH 1 1179 #define RX_NORMAL_DESC3_PL_INDEX 0 1180 #define RX_NORMAL_DESC3_PL_WIDTH 14 1181 #define RX_NORMAL_DESC3_RSV_INDEX 26 1182 #define RX_NORMAL_DESC3_RSV_WIDTH 1 1183 1184 #define RX_DESC3_L34T_IPV4_TCP 1 1185 #define RX_DESC3_L34T_IPV4_UDP 2 1186 #define RX_DESC3_L34T_IPV4_ICMP 3 1187 #define RX_DESC3_L34T_IPV6_TCP 9 1188 #define RX_DESC3_L34T_IPV6_UDP 10 1189 #define RX_DESC3_L34T_IPV6_ICMP 11 1190 1191 #define RX_CONTEXT_DESC3_TSA_INDEX 4 1192 #define RX_CONTEXT_DESC3_TSA_WIDTH 1 1193 #define RX_CONTEXT_DESC3_TSD_INDEX 6 1194 #define RX_CONTEXT_DESC3_TSD_WIDTH 1 1195 1196 #define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_INDEX 0 1197 #define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_WIDTH 1 1198 #define TX_PACKET_ATTRIBUTES_TSO_ENABLE_INDEX 1 1199 #define TX_PACKET_ATTRIBUTES_TSO_ENABLE_WIDTH 1 1200 #define TX_PACKET_ATTRIBUTES_VLAN_CTAG_INDEX 2 1201 #define TX_PACKET_ATTRIBUTES_VLAN_CTAG_WIDTH 1 1202 #define TX_PACKET_ATTRIBUTES_PTP_INDEX 3 1203 #define TX_PACKET_ATTRIBUTES_PTP_WIDTH 1 1204 1205 #define TX_CONTEXT_DESC2_MSS_INDEX 0 1206 #define TX_CONTEXT_DESC2_MSS_WIDTH 15 1207 #define TX_CONTEXT_DESC3_CTXT_INDEX 30 1208 #define TX_CONTEXT_DESC3_CTXT_WIDTH 1 1209 #define TX_CONTEXT_DESC3_TCMSSV_INDEX 26 1210 #define TX_CONTEXT_DESC3_TCMSSV_WIDTH 1 1211 #define TX_CONTEXT_DESC3_VLTV_INDEX 16 1212 #define TX_CONTEXT_DESC3_VLTV_WIDTH 1 1213 #define TX_CONTEXT_DESC3_VT_INDEX 0 1214 #define TX_CONTEXT_DESC3_VT_WIDTH 16 1215 1216 #define TX_NORMAL_DESC2_HL_B1L_INDEX 0 1217 #define TX_NORMAL_DESC2_HL_B1L_WIDTH 14 1218 #define TX_NORMAL_DESC2_IC_INDEX 31 1219 #define TX_NORMAL_DESC2_IC_WIDTH 1 1220 #define TX_NORMAL_DESC2_TTSE_INDEX 30 1221 #define TX_NORMAL_DESC2_TTSE_WIDTH 1 1222 #define TX_NORMAL_DESC2_VTIR_INDEX 14 1223 #define TX_NORMAL_DESC2_VTIR_WIDTH 2 1224 #define TX_NORMAL_DESC3_CIC_INDEX 16 1225 #define TX_NORMAL_DESC3_CIC_WIDTH 2 1226 #define TX_NORMAL_DESC3_CPC_INDEX 26 1227 #define TX_NORMAL_DESC3_CPC_WIDTH 2 1228 #define TX_NORMAL_DESC3_CTXT_INDEX 30 1229 #define TX_NORMAL_DESC3_CTXT_WIDTH 1 1230 #define TX_NORMAL_DESC3_FD_INDEX 29 1231 #define TX_NORMAL_DESC3_FD_WIDTH 1 1232 #define TX_NORMAL_DESC3_FL_INDEX 0 1233 #define TX_NORMAL_DESC3_FL_WIDTH 15 1234 #define TX_NORMAL_DESC3_LD_INDEX 28 1235 #define TX_NORMAL_DESC3_LD_WIDTH 1 1236 #define TX_NORMAL_DESC3_OWN_INDEX 31 1237 #define TX_NORMAL_DESC3_OWN_WIDTH 1 1238 #define TX_NORMAL_DESC3_TCPHDRLEN_INDEX 19 1239 #define TX_NORMAL_DESC3_TCPHDRLEN_WIDTH 4 1240 #define TX_NORMAL_DESC3_TCPPL_INDEX 0 1241 #define TX_NORMAL_DESC3_TCPPL_WIDTH 18 1242 #define TX_NORMAL_DESC3_TSE_INDEX 18 1243 #define TX_NORMAL_DESC3_TSE_WIDTH 1 1244 1245 #define TX_NORMAL_DESC2_VLAN_INSERT 0x2 1246 1247 /* MDIO undefined or vendor specific registers */ 1248 #ifndef MDIO_PMA_10GBR_PMD_CTRL 1249 #define MDIO_PMA_10GBR_PMD_CTRL 0x0096 1250 #endif 1251 1252 #ifndef MDIO_PMA_10GBR_FECCTRL 1253 #define MDIO_PMA_10GBR_FECCTRL 0x00ab 1254 #endif 1255 1256 #ifndef MDIO_PCS_DIG_CTRL 1257 #define MDIO_PCS_DIG_CTRL 0x8000 1258 #endif 1259 1260 #ifndef MDIO_AN_XNP 1261 #define MDIO_AN_XNP 0x0016 1262 #endif 1263 1264 #ifndef MDIO_AN_LPX 1265 #define MDIO_AN_LPX 0x0019 1266 #endif 1267 1268 #ifndef MDIO_AN_COMP_STAT 1269 #define MDIO_AN_COMP_STAT 0x0030 1270 #endif 1271 1272 #ifndef MDIO_AN_INTMASK 1273 #define MDIO_AN_INTMASK 0x8001 1274 #endif 1275 1276 #ifndef MDIO_AN_INT 1277 #define MDIO_AN_INT 0x8002 1278 #endif 1279 1280 #ifndef MDIO_VEND2_AN_ADVERTISE 1281 #define MDIO_VEND2_AN_ADVERTISE 0x0004 1282 #endif 1283 1284 #ifndef MDIO_VEND2_AN_LP_ABILITY 1285 #define MDIO_VEND2_AN_LP_ABILITY 0x0005 1286 #endif 1287 1288 #ifndef MDIO_VEND2_AN_CTRL 1289 #define MDIO_VEND2_AN_CTRL 0x8001 1290 #endif 1291 1292 #ifndef MDIO_VEND2_AN_STAT 1293 #define MDIO_VEND2_AN_STAT 0x8002 1294 #endif 1295 1296 #ifndef MDIO_CTRL1_SPEED1G 1297 #define MDIO_CTRL1_SPEED1G (MDIO_CTRL1_SPEED10G & ~BMCR_SPEED100) 1298 #endif 1299 1300 #ifndef MDIO_VEND2_CTRL1_AN_ENABLE 1301 #define MDIO_VEND2_CTRL1_AN_ENABLE BIT(12) 1302 #endif 1303 1304 #ifndef MDIO_VEND2_CTRL1_AN_RESTART 1305 #define MDIO_VEND2_CTRL1_AN_RESTART BIT(9) 1306 #endif 1307 1308 #ifndef MDIO_VEND2_CTRL1_SS6 1309 #define MDIO_VEND2_CTRL1_SS6 BIT(6) 1310 #endif 1311 1312 #ifndef MDIO_VEND2_CTRL1_SS13 1313 #define MDIO_VEND2_CTRL1_SS13 BIT(13) 1314 #endif 1315 1316 /* MDIO mask values */ 1317 #define XGBE_AN_CL73_INT_CMPLT BIT(0) 1318 #define XGBE_AN_CL73_INC_LINK BIT(1) 1319 #define XGBE_AN_CL73_PG_RCV BIT(2) 1320 #define XGBE_AN_CL73_INT_MASK 0x07 1321 1322 #define XGBE_XNP_MCF_NULL_MESSAGE 0x001 1323 #define XGBE_XNP_ACK_PROCESSED BIT(12) 1324 #define XGBE_XNP_MP_FORMATTED BIT(13) 1325 #define XGBE_XNP_NP_EXCHANGE BIT(15) 1326 1327 #define XGBE_KR_TRAINING_START BIT(0) 1328 #define XGBE_KR_TRAINING_ENABLE BIT(1) 1329 1330 #define XGBE_PCS_CL37_BP BIT(12) 1331 1332 #define XGBE_AN_CL37_INT_CMPLT BIT(0) 1333 #define XGBE_AN_CL37_INT_MASK 0x01 1334 1335 #define XGBE_AN_CL37_HD_MASK 0x40 1336 #define XGBE_AN_CL37_FD_MASK 0x20 1337 1338 #define XGBE_AN_CL37_PCS_MODE_MASK 0x06 1339 #define XGBE_AN_CL37_PCS_MODE_BASEX 0x00 1340 #define XGBE_AN_CL37_PCS_MODE_SGMII 0x04 1341 #define XGBE_AN_CL37_TX_CONFIG_MASK 0x08 1342 1343 /* Bit setting and getting macros 1344 * The get macro will extract the current bit field value from within 1345 * the variable 1346 * 1347 * The set macro will clear the current bit field value within the 1348 * variable and then set the bit field of the variable to the 1349 * specified value 1350 */ 1351 #define GET_BITS(_var, _index, _width) \ 1352 (((_var) >> (_index)) & ((0x1 << (_width)) - 1)) 1353 1354 #define SET_BITS(_var, _index, _width, _val) \ 1355 do { \ 1356 (_var) &= ~(((0x1 << (_width)) - 1) << (_index)); \ 1357 (_var) |= (((_val) & ((0x1 << (_width)) - 1)) << (_index)); \ 1358 } while (0) 1359 1360 #define GET_BITS_LE(_var, _index, _width) \ 1361 ((le32_to_cpu((_var)) >> (_index)) & ((0x1 << (_width)) - 1)) 1362 1363 #define SET_BITS_LE(_var, _index, _width, _val) \ 1364 do { \ 1365 (_var) &= cpu_to_le32(~(((0x1 << (_width)) - 1) << (_index))); \ 1366 (_var) |= cpu_to_le32((((_val) & \ 1367 ((0x1 << (_width)) - 1)) << (_index))); \ 1368 } while (0) 1369 1370 /* Bit setting and getting macros based on register fields 1371 * The get macro uses the bit field definitions formed using the input 1372 * names to extract the current bit field value from within the 1373 * variable 1374 * 1375 * The set macro uses the bit field definitions formed using the input 1376 * names to set the bit field of the variable to the specified value 1377 */ 1378 #define XGMAC_GET_BITS(_var, _prefix, _field) \ 1379 GET_BITS((_var), \ 1380 _prefix##_##_field##_INDEX, \ 1381 _prefix##_##_field##_WIDTH) 1382 1383 #define XGMAC_SET_BITS(_var, _prefix, _field, _val) \ 1384 SET_BITS((_var), \ 1385 _prefix##_##_field##_INDEX, \ 1386 _prefix##_##_field##_WIDTH, (_val)) 1387 1388 #define XGMAC_GET_BITS_LE(_var, _prefix, _field) \ 1389 GET_BITS_LE((_var), \ 1390 _prefix##_##_field##_INDEX, \ 1391 _prefix##_##_field##_WIDTH) 1392 1393 #define XGMAC_SET_BITS_LE(_var, _prefix, _field, _val) \ 1394 SET_BITS_LE((_var), \ 1395 _prefix##_##_field##_INDEX, \ 1396 _prefix##_##_field##_WIDTH, (_val)) 1397 1398 /* Macros for reading or writing registers 1399 * The ioread macros will get bit fields or full values using the 1400 * register definitions formed using the input names 1401 * 1402 * The iowrite macros will set bit fields or full values using the 1403 * register definitions formed using the input names 1404 */ 1405 #define XGMAC_IOREAD(_pdata, _reg) \ 1406 ioread32((_pdata)->xgmac_regs + _reg) 1407 1408 #define XGMAC_IOREAD_BITS(_pdata, _reg, _field) \ 1409 GET_BITS(XGMAC_IOREAD((_pdata), _reg), \ 1410 _reg##_##_field##_INDEX, \ 1411 _reg##_##_field##_WIDTH) 1412 1413 #define XGMAC_IOWRITE(_pdata, _reg, _val) \ 1414 iowrite32((_val), (_pdata)->xgmac_regs + _reg) 1415 1416 #define XGMAC_IOWRITE_BITS(_pdata, _reg, _field, _val) \ 1417 do { \ 1418 u32 reg_val = XGMAC_IOREAD((_pdata), _reg); \ 1419 SET_BITS(reg_val, \ 1420 _reg##_##_field##_INDEX, \ 1421 _reg##_##_field##_WIDTH, (_val)); \ 1422 XGMAC_IOWRITE((_pdata), _reg, reg_val); \ 1423 } while (0) 1424 1425 /* Macros for reading or writing MTL queue or traffic class registers 1426 * Similar to the standard read and write macros except that the 1427 * base register value is calculated by the queue or traffic class number 1428 */ 1429 #define XGMAC_MTL_IOREAD(_pdata, _n, _reg) \ 1430 ioread32((_pdata)->xgmac_regs + \ 1431 MTL_Q_BASE + ((_n) * MTL_Q_INC) + _reg) 1432 1433 #define XGMAC_MTL_IOREAD_BITS(_pdata, _n, _reg, _field) \ 1434 GET_BITS(XGMAC_MTL_IOREAD((_pdata), (_n), _reg), \ 1435 _reg##_##_field##_INDEX, \ 1436 _reg##_##_field##_WIDTH) 1437 1438 #define XGMAC_MTL_IOWRITE(_pdata, _n, _reg, _val) \ 1439 iowrite32((_val), (_pdata)->xgmac_regs + \ 1440 MTL_Q_BASE + ((_n) * MTL_Q_INC) + _reg) 1441 1442 #define XGMAC_MTL_IOWRITE_BITS(_pdata, _n, _reg, _field, _val) \ 1443 do { \ 1444 u32 reg_val = XGMAC_MTL_IOREAD((_pdata), (_n), _reg); \ 1445 SET_BITS(reg_val, \ 1446 _reg##_##_field##_INDEX, \ 1447 _reg##_##_field##_WIDTH, (_val)); \ 1448 XGMAC_MTL_IOWRITE((_pdata), (_n), _reg, reg_val); \ 1449 } while (0) 1450 1451 /* Macros for reading or writing DMA channel registers 1452 * Similar to the standard read and write macros except that the 1453 * base register value is obtained from the ring 1454 */ 1455 #define XGMAC_DMA_IOREAD(_channel, _reg) \ 1456 ioread32((_channel)->dma_regs + _reg) 1457 1458 #define XGMAC_DMA_IOREAD_BITS(_channel, _reg, _field) \ 1459 GET_BITS(XGMAC_DMA_IOREAD((_channel), _reg), \ 1460 _reg##_##_field##_INDEX, \ 1461 _reg##_##_field##_WIDTH) 1462 1463 #define XGMAC_DMA_IOWRITE(_channel, _reg, _val) \ 1464 iowrite32((_val), (_channel)->dma_regs + _reg) 1465 1466 #define XGMAC_DMA_IOWRITE_BITS(_channel, _reg, _field, _val) \ 1467 do { \ 1468 u32 reg_val = XGMAC_DMA_IOREAD((_channel), _reg); \ 1469 SET_BITS(reg_val, \ 1470 _reg##_##_field##_INDEX, \ 1471 _reg##_##_field##_WIDTH, (_val)); \ 1472 XGMAC_DMA_IOWRITE((_channel), _reg, reg_val); \ 1473 } while (0) 1474 1475 /* Macros for building, reading or writing register values or bits 1476 * within the register values of XPCS registers. 1477 */ 1478 #define XPCS_GET_BITS(_var, _prefix, _field) \ 1479 GET_BITS((_var), \ 1480 _prefix##_##_field##_INDEX, \ 1481 _prefix##_##_field##_WIDTH) 1482 1483 #define XPCS_SET_BITS(_var, _prefix, _field, _val) \ 1484 SET_BITS((_var), \ 1485 _prefix##_##_field##_INDEX, \ 1486 _prefix##_##_field##_WIDTH, (_val)) 1487 1488 #define XPCS32_IOWRITE(_pdata, _off, _val) \ 1489 iowrite32(_val, (_pdata)->xpcs_regs + (_off)) 1490 1491 #define XPCS32_IOREAD(_pdata, _off) \ 1492 ioread32((_pdata)->xpcs_regs + (_off)) 1493 1494 #define XPCS16_IOWRITE(_pdata, _off, _val) \ 1495 iowrite16(_val, (_pdata)->xpcs_regs + (_off)) 1496 1497 #define XPCS16_IOREAD(_pdata, _off) \ 1498 ioread16((_pdata)->xpcs_regs + (_off)) 1499 1500 /* Macros for building, reading or writing register values or bits 1501 * within the register values of SerDes integration registers. 1502 */ 1503 #define XSIR_GET_BITS(_var, _prefix, _field) \ 1504 GET_BITS((_var), \ 1505 _prefix##_##_field##_INDEX, \ 1506 _prefix##_##_field##_WIDTH) 1507 1508 #define XSIR_SET_BITS(_var, _prefix, _field, _val) \ 1509 SET_BITS((_var), \ 1510 _prefix##_##_field##_INDEX, \ 1511 _prefix##_##_field##_WIDTH, (_val)) 1512 1513 #define XSIR0_IOREAD(_pdata, _reg) \ 1514 ioread16((_pdata)->sir0_regs + _reg) 1515 1516 #define XSIR0_IOREAD_BITS(_pdata, _reg, _field) \ 1517 GET_BITS(XSIR0_IOREAD((_pdata), _reg), \ 1518 _reg##_##_field##_INDEX, \ 1519 _reg##_##_field##_WIDTH) 1520 1521 #define XSIR0_IOWRITE(_pdata, _reg, _val) \ 1522 iowrite16((_val), (_pdata)->sir0_regs + _reg) 1523 1524 #define XSIR0_IOWRITE_BITS(_pdata, _reg, _field, _val) \ 1525 do { \ 1526 u16 reg_val = XSIR0_IOREAD((_pdata), _reg); \ 1527 SET_BITS(reg_val, \ 1528 _reg##_##_field##_INDEX, \ 1529 _reg##_##_field##_WIDTH, (_val)); \ 1530 XSIR0_IOWRITE((_pdata), _reg, reg_val); \ 1531 } while (0) 1532 1533 #define XSIR1_IOREAD(_pdata, _reg) \ 1534 ioread16((_pdata)->sir1_regs + _reg) 1535 1536 #define XSIR1_IOREAD_BITS(_pdata, _reg, _field) \ 1537 GET_BITS(XSIR1_IOREAD((_pdata), _reg), \ 1538 _reg##_##_field##_INDEX, \ 1539 _reg##_##_field##_WIDTH) 1540 1541 #define XSIR1_IOWRITE(_pdata, _reg, _val) \ 1542 iowrite16((_val), (_pdata)->sir1_regs + _reg) 1543 1544 #define XSIR1_IOWRITE_BITS(_pdata, _reg, _field, _val) \ 1545 do { \ 1546 u16 reg_val = XSIR1_IOREAD((_pdata), _reg); \ 1547 SET_BITS(reg_val, \ 1548 _reg##_##_field##_INDEX, \ 1549 _reg##_##_field##_WIDTH, (_val)); \ 1550 XSIR1_IOWRITE((_pdata), _reg, reg_val); \ 1551 } while (0) 1552 1553 /* Macros for building, reading or writing register values or bits 1554 * within the register values of SerDes RxTx registers. 1555 */ 1556 #define XRXTX_IOREAD(_pdata, _reg) \ 1557 ioread16((_pdata)->rxtx_regs + _reg) 1558 1559 #define XRXTX_IOREAD_BITS(_pdata, _reg, _field) \ 1560 GET_BITS(XRXTX_IOREAD((_pdata), _reg), \ 1561 _reg##_##_field##_INDEX, \ 1562 _reg##_##_field##_WIDTH) 1563 1564 #define XRXTX_IOWRITE(_pdata, _reg, _val) \ 1565 iowrite16((_val), (_pdata)->rxtx_regs + _reg) 1566 1567 #define XRXTX_IOWRITE_BITS(_pdata, _reg, _field, _val) \ 1568 do { \ 1569 u16 reg_val = XRXTX_IOREAD((_pdata), _reg); \ 1570 SET_BITS(reg_val, \ 1571 _reg##_##_field##_INDEX, \ 1572 _reg##_##_field##_WIDTH, (_val)); \ 1573 XRXTX_IOWRITE((_pdata), _reg, reg_val); \ 1574 } while (0) 1575 1576 /* Macros for building, reading or writing register values or bits 1577 * within the register values of MAC Control registers. 1578 */ 1579 #define XP_GET_BITS(_var, _prefix, _field) \ 1580 GET_BITS((_var), \ 1581 _prefix##_##_field##_INDEX, \ 1582 _prefix##_##_field##_WIDTH) 1583 1584 #define XP_SET_BITS(_var, _prefix, _field, _val) \ 1585 SET_BITS((_var), \ 1586 _prefix##_##_field##_INDEX, \ 1587 _prefix##_##_field##_WIDTH, (_val)) 1588 1589 #define XP_IOREAD(_pdata, _reg) \ 1590 ioread32((_pdata)->xprop_regs + (_reg)) 1591 1592 #define XP_IOREAD_BITS(_pdata, _reg, _field) \ 1593 GET_BITS(XP_IOREAD((_pdata), (_reg)), \ 1594 _reg##_##_field##_INDEX, \ 1595 _reg##_##_field##_WIDTH) 1596 1597 #define XP_IOWRITE(_pdata, _reg, _val) \ 1598 iowrite32((_val), (_pdata)->xprop_regs + (_reg)) 1599 1600 #define XP_IOWRITE_BITS(_pdata, _reg, _field, _val) \ 1601 do { \ 1602 u32 reg_val = XP_IOREAD((_pdata), (_reg)); \ 1603 SET_BITS(reg_val, \ 1604 _reg##_##_field##_INDEX, \ 1605 _reg##_##_field##_WIDTH, (_val)); \ 1606 XP_IOWRITE((_pdata), (_reg), reg_val); \ 1607 } while (0) 1608 1609 /* Macros for building, reading or writing register values or bits 1610 * within the register values of I2C Control registers. 1611 */ 1612 #define XI2C_GET_BITS(_var, _prefix, _field) \ 1613 GET_BITS((_var), \ 1614 _prefix##_##_field##_INDEX, \ 1615 _prefix##_##_field##_WIDTH) 1616 1617 #define XI2C_SET_BITS(_var, _prefix, _field, _val) \ 1618 SET_BITS((_var), \ 1619 _prefix##_##_field##_INDEX, \ 1620 _prefix##_##_field##_WIDTH, (_val)) 1621 1622 #define XI2C_IOREAD(_pdata, _reg) \ 1623 ioread32((_pdata)->xi2c_regs + (_reg)) 1624 1625 #define XI2C_IOREAD_BITS(_pdata, _reg, _field) \ 1626 GET_BITS(XI2C_IOREAD((_pdata), (_reg)), \ 1627 _reg##_##_field##_INDEX, \ 1628 _reg##_##_field##_WIDTH) 1629 1630 #define XI2C_IOWRITE(_pdata, _reg, _val) \ 1631 iowrite32((_val), (_pdata)->xi2c_regs + (_reg)) 1632 1633 #define XI2C_IOWRITE_BITS(_pdata, _reg, _field, _val) \ 1634 do { \ 1635 u32 reg_val = XI2C_IOREAD((_pdata), (_reg)); \ 1636 SET_BITS(reg_val, \ 1637 _reg##_##_field##_INDEX, \ 1638 _reg##_##_field##_WIDTH, (_val)); \ 1639 XI2C_IOWRITE((_pdata), (_reg), reg_val); \ 1640 } while (0) 1641 1642 /* Macros for building, reading or writing register values or bits 1643 * using MDIO. Different from above because of the use of standardized 1644 * Linux include values. No shifting is performed with the bit 1645 * operations, everything works on mask values. 1646 */ 1647 #define XMDIO_READ(_pdata, _mmd, _reg) \ 1648 ((_pdata)->hw_if.read_mmd_regs((_pdata), 0, \ 1649 MII_ADDR_C45 | (_mmd << 16) | ((_reg) & 0xffff))) 1650 1651 #define XMDIO_READ_BITS(_pdata, _mmd, _reg, _mask) \ 1652 (XMDIO_READ((_pdata), _mmd, _reg) & _mask) 1653 1654 #define XMDIO_WRITE(_pdata, _mmd, _reg, _val) \ 1655 ((_pdata)->hw_if.write_mmd_regs((_pdata), 0, \ 1656 MII_ADDR_C45 | (_mmd << 16) | ((_reg) & 0xffff), (_val))) 1657 1658 #define XMDIO_WRITE_BITS(_pdata, _mmd, _reg, _mask, _val) \ 1659 do { \ 1660 u32 mmd_val = XMDIO_READ((_pdata), _mmd, _reg); \ 1661 mmd_val &= ~_mask; \ 1662 mmd_val |= (_val); \ 1663 XMDIO_WRITE((_pdata), _mmd, _reg, mmd_val); \ 1664 } while (0) 1665 1666 #endif 1667