1 /* 2 * AMD 10Gb Ethernet driver 3 * 4 * This file is available to you under your choice of the following two 5 * licenses: 6 * 7 * License 1: GPLv2 8 * 9 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc. 10 * 11 * This file is free software; you may copy, redistribute and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation, either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program. If not, see <http://www.gnu.org/licenses/>. 23 * 24 * This file incorporates work covered by the following copyright and 25 * permission notice: 26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 28 * Inc. unless otherwise expressly agreed to in writing between Synopsys 29 * and you. 30 * 31 * The Software IS NOT an item of Licensed Software or Licensed Product 32 * under any End User Software License Agreement or Agreement for Licensed 33 * Product with Synopsys or any supplement thereto. Permission is hereby 34 * granted, free of charge, to any person obtaining a copy of this software 35 * annotated with this license and the Software, to deal in the Software 36 * without restriction, including without limitation the rights to use, 37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 38 * of the Software, and to permit persons to whom the Software is furnished 39 * to do so, subject to the following conditions: 40 * 41 * The above copyright notice and this permission notice shall be included 42 * in all copies or substantial portions of the Software. 43 * 44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 54 * THE POSSIBILITY OF SUCH DAMAGE. 55 * 56 * 57 * License 2: Modified BSD 58 * 59 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc. 60 * All rights reserved. 61 * 62 * Redistribution and use in source and binary forms, with or without 63 * modification, are permitted provided that the following conditions are met: 64 * * Redistributions of source code must retain the above copyright 65 * notice, this list of conditions and the following disclaimer. 66 * * Redistributions in binary form must reproduce the above copyright 67 * notice, this list of conditions and the following disclaimer in the 68 * documentation and/or other materials provided with the distribution. 69 * * Neither the name of Advanced Micro Devices, Inc. nor the 70 * names of its contributors may be used to endorse or promote products 71 * derived from this software without specific prior written permission. 72 * 73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY 77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 83 * 84 * This file incorporates work covered by the following copyright and 85 * permission notice: 86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 88 * Inc. unless otherwise expressly agreed to in writing between Synopsys 89 * and you. 90 * 91 * The Software IS NOT an item of Licensed Software or Licensed Product 92 * under any End User Software License Agreement or Agreement for Licensed 93 * Product with Synopsys or any supplement thereto. Permission is hereby 94 * granted, free of charge, to any person obtaining a copy of this software 95 * annotated with this license and the Software, to deal in the Software 96 * without restriction, including without limitation the rights to use, 97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 98 * of the Software, and to permit persons to whom the Software is furnished 99 * to do so, subject to the following conditions: 100 * 101 * The above copyright notice and this permission notice shall be included 102 * in all copies or substantial portions of the Software. 103 * 104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 114 * THE POSSIBILITY OF SUCH DAMAGE. 115 */ 116 117 #ifndef __XGBE_COMMON_H__ 118 #define __XGBE_COMMON_H__ 119 120 /* DMA register offsets */ 121 #define DMA_MR 0x3000 122 #define DMA_SBMR 0x3004 123 #define DMA_ISR 0x3008 124 #define DMA_AXIARCR 0x3010 125 #define DMA_AXIAWCR 0x3018 126 #define DMA_DSR0 0x3020 127 #define DMA_DSR1 0x3024 128 129 /* DMA register entry bit positions and sizes */ 130 #define DMA_AXIARCR_DRC_INDEX 0 131 #define DMA_AXIARCR_DRC_WIDTH 4 132 #define DMA_AXIARCR_DRD_INDEX 4 133 #define DMA_AXIARCR_DRD_WIDTH 2 134 #define DMA_AXIARCR_TEC_INDEX 8 135 #define DMA_AXIARCR_TEC_WIDTH 4 136 #define DMA_AXIARCR_TED_INDEX 12 137 #define DMA_AXIARCR_TED_WIDTH 2 138 #define DMA_AXIARCR_THC_INDEX 16 139 #define DMA_AXIARCR_THC_WIDTH 4 140 #define DMA_AXIARCR_THD_INDEX 20 141 #define DMA_AXIARCR_THD_WIDTH 2 142 #define DMA_AXIAWCR_DWC_INDEX 0 143 #define DMA_AXIAWCR_DWC_WIDTH 4 144 #define DMA_AXIAWCR_DWD_INDEX 4 145 #define DMA_AXIAWCR_DWD_WIDTH 2 146 #define DMA_AXIAWCR_RPC_INDEX 8 147 #define DMA_AXIAWCR_RPC_WIDTH 4 148 #define DMA_AXIAWCR_RPD_INDEX 12 149 #define DMA_AXIAWCR_RPD_WIDTH 2 150 #define DMA_AXIAWCR_RHC_INDEX 16 151 #define DMA_AXIAWCR_RHC_WIDTH 4 152 #define DMA_AXIAWCR_RHD_INDEX 20 153 #define DMA_AXIAWCR_RHD_WIDTH 2 154 #define DMA_AXIAWCR_TDC_INDEX 24 155 #define DMA_AXIAWCR_TDC_WIDTH 4 156 #define DMA_AXIAWCR_TDD_INDEX 28 157 #define DMA_AXIAWCR_TDD_WIDTH 2 158 #define DMA_ISR_MACIS_INDEX 17 159 #define DMA_ISR_MACIS_WIDTH 1 160 #define DMA_ISR_MTLIS_INDEX 16 161 #define DMA_ISR_MTLIS_WIDTH 1 162 #define DMA_MR_INTM_INDEX 12 163 #define DMA_MR_INTM_WIDTH 2 164 #define DMA_MR_SWR_INDEX 0 165 #define DMA_MR_SWR_WIDTH 1 166 #define DMA_SBMR_EAME_INDEX 11 167 #define DMA_SBMR_EAME_WIDTH 1 168 #define DMA_SBMR_BLEN_256_INDEX 7 169 #define DMA_SBMR_BLEN_256_WIDTH 1 170 #define DMA_SBMR_UNDEF_INDEX 0 171 #define DMA_SBMR_UNDEF_WIDTH 1 172 173 /* DMA register values */ 174 #define DMA_DSR_RPS_WIDTH 4 175 #define DMA_DSR_TPS_WIDTH 4 176 #define DMA_DSR_Q_WIDTH (DMA_DSR_RPS_WIDTH + DMA_DSR_TPS_WIDTH) 177 #define DMA_DSR0_RPS_START 8 178 #define DMA_DSR0_TPS_START 12 179 #define DMA_DSRX_FIRST_QUEUE 3 180 #define DMA_DSRX_INC 4 181 #define DMA_DSRX_QPR 4 182 #define DMA_DSRX_RPS_START 0 183 #define DMA_DSRX_TPS_START 4 184 #define DMA_TPS_STOPPED 0x00 185 #define DMA_TPS_SUSPENDED 0x06 186 187 /* DMA channel register offsets 188 * Multiple channels can be active. The first channel has registers 189 * that begin at 0x3100. Each subsequent channel has registers that 190 * are accessed using an offset of 0x80 from the previous channel. 191 */ 192 #define DMA_CH_BASE 0x3100 193 #define DMA_CH_INC 0x80 194 195 #define DMA_CH_CR 0x00 196 #define DMA_CH_TCR 0x04 197 #define DMA_CH_RCR 0x08 198 #define DMA_CH_TDLR_HI 0x10 199 #define DMA_CH_TDLR_LO 0x14 200 #define DMA_CH_RDLR_HI 0x18 201 #define DMA_CH_RDLR_LO 0x1c 202 #define DMA_CH_TDTR_LO 0x24 203 #define DMA_CH_RDTR_LO 0x2c 204 #define DMA_CH_TDRLR 0x30 205 #define DMA_CH_RDRLR 0x34 206 #define DMA_CH_IER 0x38 207 #define DMA_CH_RIWT 0x3c 208 #define DMA_CH_CATDR_LO 0x44 209 #define DMA_CH_CARDR_LO 0x4c 210 #define DMA_CH_CATBR_HI 0x50 211 #define DMA_CH_CATBR_LO 0x54 212 #define DMA_CH_CARBR_HI 0x58 213 #define DMA_CH_CARBR_LO 0x5c 214 #define DMA_CH_SR 0x60 215 216 /* DMA channel register entry bit positions and sizes */ 217 #define DMA_CH_CR_PBLX8_INDEX 16 218 #define DMA_CH_CR_PBLX8_WIDTH 1 219 #define DMA_CH_CR_SPH_INDEX 24 220 #define DMA_CH_CR_SPH_WIDTH 1 221 #define DMA_CH_IER_AIE_INDEX 15 222 #define DMA_CH_IER_AIE_WIDTH 1 223 #define DMA_CH_IER_FBEE_INDEX 12 224 #define DMA_CH_IER_FBEE_WIDTH 1 225 #define DMA_CH_IER_NIE_INDEX 16 226 #define DMA_CH_IER_NIE_WIDTH 1 227 #define DMA_CH_IER_RBUE_INDEX 7 228 #define DMA_CH_IER_RBUE_WIDTH 1 229 #define DMA_CH_IER_RIE_INDEX 6 230 #define DMA_CH_IER_RIE_WIDTH 1 231 #define DMA_CH_IER_RSE_INDEX 8 232 #define DMA_CH_IER_RSE_WIDTH 1 233 #define DMA_CH_IER_TBUE_INDEX 2 234 #define DMA_CH_IER_TBUE_WIDTH 1 235 #define DMA_CH_IER_TIE_INDEX 0 236 #define DMA_CH_IER_TIE_WIDTH 1 237 #define DMA_CH_IER_TXSE_INDEX 1 238 #define DMA_CH_IER_TXSE_WIDTH 1 239 #define DMA_CH_RCR_PBL_INDEX 16 240 #define DMA_CH_RCR_PBL_WIDTH 6 241 #define DMA_CH_RCR_RBSZ_INDEX 1 242 #define DMA_CH_RCR_RBSZ_WIDTH 14 243 #define DMA_CH_RCR_SR_INDEX 0 244 #define DMA_CH_RCR_SR_WIDTH 1 245 #define DMA_CH_RIWT_RWT_INDEX 0 246 #define DMA_CH_RIWT_RWT_WIDTH 8 247 #define DMA_CH_SR_FBE_INDEX 12 248 #define DMA_CH_SR_FBE_WIDTH 1 249 #define DMA_CH_SR_RBU_INDEX 7 250 #define DMA_CH_SR_RBU_WIDTH 1 251 #define DMA_CH_SR_RI_INDEX 6 252 #define DMA_CH_SR_RI_WIDTH 1 253 #define DMA_CH_SR_RPS_INDEX 8 254 #define DMA_CH_SR_RPS_WIDTH 1 255 #define DMA_CH_SR_TBU_INDEX 2 256 #define DMA_CH_SR_TBU_WIDTH 1 257 #define DMA_CH_SR_TI_INDEX 0 258 #define DMA_CH_SR_TI_WIDTH 1 259 #define DMA_CH_SR_TPS_INDEX 1 260 #define DMA_CH_SR_TPS_WIDTH 1 261 #define DMA_CH_TCR_OSP_INDEX 4 262 #define DMA_CH_TCR_OSP_WIDTH 1 263 #define DMA_CH_TCR_PBL_INDEX 16 264 #define DMA_CH_TCR_PBL_WIDTH 6 265 #define DMA_CH_TCR_ST_INDEX 0 266 #define DMA_CH_TCR_ST_WIDTH 1 267 #define DMA_CH_TCR_TSE_INDEX 12 268 #define DMA_CH_TCR_TSE_WIDTH 1 269 270 /* DMA channel register values */ 271 #define DMA_OSP_DISABLE 0x00 272 #define DMA_OSP_ENABLE 0x01 273 #define DMA_PBL_1 1 274 #define DMA_PBL_2 2 275 #define DMA_PBL_4 4 276 #define DMA_PBL_8 8 277 #define DMA_PBL_16 16 278 #define DMA_PBL_32 32 279 #define DMA_PBL_64 64 /* 8 x 8 */ 280 #define DMA_PBL_128 128 /* 8 x 16 */ 281 #define DMA_PBL_256 256 /* 8 x 32 */ 282 #define DMA_PBL_X8_DISABLE 0x00 283 #define DMA_PBL_X8_ENABLE 0x01 284 285 /* MAC register offsets */ 286 #define MAC_TCR 0x0000 287 #define MAC_RCR 0x0004 288 #define MAC_PFR 0x0008 289 #define MAC_WTR 0x000c 290 #define MAC_HTR0 0x0010 291 #define MAC_VLANTR 0x0050 292 #define MAC_VLANHTR 0x0058 293 #define MAC_VLANIR 0x0060 294 #define MAC_IVLANIR 0x0064 295 #define MAC_RETMR 0x006c 296 #define MAC_Q0TFCR 0x0070 297 #define MAC_RFCR 0x0090 298 #define MAC_RQC0R 0x00a0 299 #define MAC_RQC1R 0x00a4 300 #define MAC_RQC2R 0x00a8 301 #define MAC_RQC3R 0x00ac 302 #define MAC_ISR 0x00b0 303 #define MAC_IER 0x00b4 304 #define MAC_RTSR 0x00b8 305 #define MAC_PMTCSR 0x00c0 306 #define MAC_RWKPFR 0x00c4 307 #define MAC_LPICSR 0x00d0 308 #define MAC_LPITCR 0x00d4 309 #define MAC_VR 0x0110 310 #define MAC_DR 0x0114 311 #define MAC_HWF0R 0x011c 312 #define MAC_HWF1R 0x0120 313 #define MAC_HWF2R 0x0124 314 #define MAC_MDIOSCAR 0x0200 315 #define MAC_MDIOSCCDR 0x0204 316 #define MAC_MDIOISR 0x0214 317 #define MAC_MDIOIER 0x0218 318 #define MAC_MDIOCL22R 0x0220 319 #define MAC_GPIOCR 0x0278 320 #define MAC_GPIOSR 0x027c 321 #define MAC_MACA0HR 0x0300 322 #define MAC_MACA0LR 0x0304 323 #define MAC_MACA1HR 0x0308 324 #define MAC_MACA1LR 0x030c 325 #define MAC_RSSCR 0x0c80 326 #define MAC_RSSAR 0x0c88 327 #define MAC_RSSDR 0x0c8c 328 #define MAC_TSCR 0x0d00 329 #define MAC_SSIR 0x0d04 330 #define MAC_STSR 0x0d08 331 #define MAC_STNR 0x0d0c 332 #define MAC_STSUR 0x0d10 333 #define MAC_STNUR 0x0d14 334 #define MAC_TSAR 0x0d18 335 #define MAC_TSSR 0x0d20 336 #define MAC_TXSNR 0x0d30 337 #define MAC_TXSSR 0x0d34 338 339 #define MAC_QTFCR_INC 4 340 #define MAC_MACA_INC 4 341 #define MAC_HTR_INC 4 342 343 #define MAC_RQC2_INC 4 344 #define MAC_RQC2_Q_PER_REG 4 345 346 /* MAC register entry bit positions and sizes */ 347 #define MAC_HWF0R_ADDMACADRSEL_INDEX 18 348 #define MAC_HWF0R_ADDMACADRSEL_WIDTH 5 349 #define MAC_HWF0R_ARPOFFSEL_INDEX 9 350 #define MAC_HWF0R_ARPOFFSEL_WIDTH 1 351 #define MAC_HWF0R_EEESEL_INDEX 13 352 #define MAC_HWF0R_EEESEL_WIDTH 1 353 #define MAC_HWF0R_GMIISEL_INDEX 1 354 #define MAC_HWF0R_GMIISEL_WIDTH 1 355 #define MAC_HWF0R_MGKSEL_INDEX 7 356 #define MAC_HWF0R_MGKSEL_WIDTH 1 357 #define MAC_HWF0R_MMCSEL_INDEX 8 358 #define MAC_HWF0R_MMCSEL_WIDTH 1 359 #define MAC_HWF0R_RWKSEL_INDEX 6 360 #define MAC_HWF0R_RWKSEL_WIDTH 1 361 #define MAC_HWF0R_RXCOESEL_INDEX 16 362 #define MAC_HWF0R_RXCOESEL_WIDTH 1 363 #define MAC_HWF0R_SAVLANINS_INDEX 27 364 #define MAC_HWF0R_SAVLANINS_WIDTH 1 365 #define MAC_HWF0R_SMASEL_INDEX 5 366 #define MAC_HWF0R_SMASEL_WIDTH 1 367 #define MAC_HWF0R_TSSEL_INDEX 12 368 #define MAC_HWF0R_TSSEL_WIDTH 1 369 #define MAC_HWF0R_TSSTSSEL_INDEX 25 370 #define MAC_HWF0R_TSSTSSEL_WIDTH 2 371 #define MAC_HWF0R_TXCOESEL_INDEX 14 372 #define MAC_HWF0R_TXCOESEL_WIDTH 1 373 #define MAC_HWF0R_VLHASH_INDEX 4 374 #define MAC_HWF0R_VLHASH_WIDTH 1 375 #define MAC_HWF1R_ADDR64_INDEX 14 376 #define MAC_HWF1R_ADDR64_WIDTH 2 377 #define MAC_HWF1R_ADVTHWORD_INDEX 13 378 #define MAC_HWF1R_ADVTHWORD_WIDTH 1 379 #define MAC_HWF1R_DBGMEMA_INDEX 19 380 #define MAC_HWF1R_DBGMEMA_WIDTH 1 381 #define MAC_HWF1R_DCBEN_INDEX 16 382 #define MAC_HWF1R_DCBEN_WIDTH 1 383 #define MAC_HWF1R_HASHTBLSZ_INDEX 24 384 #define MAC_HWF1R_HASHTBLSZ_WIDTH 3 385 #define MAC_HWF1R_L3L4FNUM_INDEX 27 386 #define MAC_HWF1R_L3L4FNUM_WIDTH 4 387 #define MAC_HWF1R_NUMTC_INDEX 21 388 #define MAC_HWF1R_NUMTC_WIDTH 3 389 #define MAC_HWF1R_RSSEN_INDEX 20 390 #define MAC_HWF1R_RSSEN_WIDTH 1 391 #define MAC_HWF1R_RXFIFOSIZE_INDEX 0 392 #define MAC_HWF1R_RXFIFOSIZE_WIDTH 5 393 #define MAC_HWF1R_SPHEN_INDEX 17 394 #define MAC_HWF1R_SPHEN_WIDTH 1 395 #define MAC_HWF1R_TSOEN_INDEX 18 396 #define MAC_HWF1R_TSOEN_WIDTH 1 397 #define MAC_HWF1R_TXFIFOSIZE_INDEX 6 398 #define MAC_HWF1R_TXFIFOSIZE_WIDTH 5 399 #define MAC_HWF2R_AUXSNAPNUM_INDEX 28 400 #define MAC_HWF2R_AUXSNAPNUM_WIDTH 3 401 #define MAC_HWF2R_PPSOUTNUM_INDEX 24 402 #define MAC_HWF2R_PPSOUTNUM_WIDTH 3 403 #define MAC_HWF2R_RXCHCNT_INDEX 12 404 #define MAC_HWF2R_RXCHCNT_WIDTH 4 405 #define MAC_HWF2R_RXQCNT_INDEX 0 406 #define MAC_HWF2R_RXQCNT_WIDTH 4 407 #define MAC_HWF2R_TXCHCNT_INDEX 18 408 #define MAC_HWF2R_TXCHCNT_WIDTH 4 409 #define MAC_HWF2R_TXQCNT_INDEX 6 410 #define MAC_HWF2R_TXQCNT_WIDTH 4 411 #define MAC_IER_TSIE_INDEX 12 412 #define MAC_IER_TSIE_WIDTH 1 413 #define MAC_ISR_MMCRXIS_INDEX 9 414 #define MAC_ISR_MMCRXIS_WIDTH 1 415 #define MAC_ISR_MMCTXIS_INDEX 10 416 #define MAC_ISR_MMCTXIS_WIDTH 1 417 #define MAC_ISR_PMTIS_INDEX 4 418 #define MAC_ISR_PMTIS_WIDTH 1 419 #define MAC_ISR_SMI_INDEX 1 420 #define MAC_ISR_SMI_WIDTH 1 421 #define MAC_ISR_TSIS_INDEX 12 422 #define MAC_ISR_TSIS_WIDTH 1 423 #define MAC_MACA1HR_AE_INDEX 31 424 #define MAC_MACA1HR_AE_WIDTH 1 425 #define MAC_MDIOIER_SNGLCOMPIE_INDEX 12 426 #define MAC_MDIOIER_SNGLCOMPIE_WIDTH 1 427 #define MAC_MDIOISR_SNGLCOMPINT_INDEX 12 428 #define MAC_MDIOISR_SNGLCOMPINT_WIDTH 1 429 #define MAC_MDIOSCAR_DA_INDEX 21 430 #define MAC_MDIOSCAR_DA_WIDTH 5 431 #define MAC_MDIOSCAR_PA_INDEX 16 432 #define MAC_MDIOSCAR_PA_WIDTH 5 433 #define MAC_MDIOSCAR_RA_INDEX 0 434 #define MAC_MDIOSCAR_RA_WIDTH 16 435 #define MAC_MDIOSCAR_REG_INDEX 0 436 #define MAC_MDIOSCAR_REG_WIDTH 21 437 #define MAC_MDIOSCCDR_BUSY_INDEX 22 438 #define MAC_MDIOSCCDR_BUSY_WIDTH 1 439 #define MAC_MDIOSCCDR_CMD_INDEX 16 440 #define MAC_MDIOSCCDR_CMD_WIDTH 2 441 #define MAC_MDIOSCCDR_CR_INDEX 19 442 #define MAC_MDIOSCCDR_CR_WIDTH 3 443 #define MAC_MDIOSCCDR_DATA_INDEX 0 444 #define MAC_MDIOSCCDR_DATA_WIDTH 16 445 #define MAC_MDIOSCCDR_SADDR_INDEX 18 446 #define MAC_MDIOSCCDR_SADDR_WIDTH 1 447 #define MAC_PFR_HMC_INDEX 2 448 #define MAC_PFR_HMC_WIDTH 1 449 #define MAC_PFR_HPF_INDEX 10 450 #define MAC_PFR_HPF_WIDTH 1 451 #define MAC_PFR_HUC_INDEX 1 452 #define MAC_PFR_HUC_WIDTH 1 453 #define MAC_PFR_PM_INDEX 4 454 #define MAC_PFR_PM_WIDTH 1 455 #define MAC_PFR_PR_INDEX 0 456 #define MAC_PFR_PR_WIDTH 1 457 #define MAC_PFR_VTFE_INDEX 16 458 #define MAC_PFR_VTFE_WIDTH 1 459 #define MAC_PMTCSR_MGKPKTEN_INDEX 1 460 #define MAC_PMTCSR_MGKPKTEN_WIDTH 1 461 #define MAC_PMTCSR_PWRDWN_INDEX 0 462 #define MAC_PMTCSR_PWRDWN_WIDTH 1 463 #define MAC_PMTCSR_RWKFILTRST_INDEX 31 464 #define MAC_PMTCSR_RWKFILTRST_WIDTH 1 465 #define MAC_PMTCSR_RWKPKTEN_INDEX 2 466 #define MAC_PMTCSR_RWKPKTEN_WIDTH 1 467 #define MAC_Q0TFCR_PT_INDEX 16 468 #define MAC_Q0TFCR_PT_WIDTH 16 469 #define MAC_Q0TFCR_TFE_INDEX 1 470 #define MAC_Q0TFCR_TFE_WIDTH 1 471 #define MAC_RCR_ACS_INDEX 1 472 #define MAC_RCR_ACS_WIDTH 1 473 #define MAC_RCR_CST_INDEX 2 474 #define MAC_RCR_CST_WIDTH 1 475 #define MAC_RCR_DCRCC_INDEX 3 476 #define MAC_RCR_DCRCC_WIDTH 1 477 #define MAC_RCR_HDSMS_INDEX 12 478 #define MAC_RCR_HDSMS_WIDTH 3 479 #define MAC_RCR_IPC_INDEX 9 480 #define MAC_RCR_IPC_WIDTH 1 481 #define MAC_RCR_JE_INDEX 8 482 #define MAC_RCR_JE_WIDTH 1 483 #define MAC_RCR_LM_INDEX 10 484 #define MAC_RCR_LM_WIDTH 1 485 #define MAC_RCR_RE_INDEX 0 486 #define MAC_RCR_RE_WIDTH 1 487 #define MAC_RFCR_PFCE_INDEX 8 488 #define MAC_RFCR_PFCE_WIDTH 1 489 #define MAC_RFCR_RFE_INDEX 0 490 #define MAC_RFCR_RFE_WIDTH 1 491 #define MAC_RFCR_UP_INDEX 1 492 #define MAC_RFCR_UP_WIDTH 1 493 #define MAC_RQC0R_RXQ0EN_INDEX 0 494 #define MAC_RQC0R_RXQ0EN_WIDTH 2 495 #define MAC_RSSAR_ADDRT_INDEX 2 496 #define MAC_RSSAR_ADDRT_WIDTH 1 497 #define MAC_RSSAR_CT_INDEX 1 498 #define MAC_RSSAR_CT_WIDTH 1 499 #define MAC_RSSAR_OB_INDEX 0 500 #define MAC_RSSAR_OB_WIDTH 1 501 #define MAC_RSSAR_RSSIA_INDEX 8 502 #define MAC_RSSAR_RSSIA_WIDTH 8 503 #define MAC_RSSCR_IP2TE_INDEX 1 504 #define MAC_RSSCR_IP2TE_WIDTH 1 505 #define MAC_RSSCR_RSSE_INDEX 0 506 #define MAC_RSSCR_RSSE_WIDTH 1 507 #define MAC_RSSCR_TCP4TE_INDEX 2 508 #define MAC_RSSCR_TCP4TE_WIDTH 1 509 #define MAC_RSSCR_UDP4TE_INDEX 3 510 #define MAC_RSSCR_UDP4TE_WIDTH 1 511 #define MAC_RSSDR_DMCH_INDEX 0 512 #define MAC_RSSDR_DMCH_WIDTH 4 513 #define MAC_SSIR_SNSINC_INDEX 8 514 #define MAC_SSIR_SNSINC_WIDTH 8 515 #define MAC_SSIR_SSINC_INDEX 16 516 #define MAC_SSIR_SSINC_WIDTH 8 517 #define MAC_TCR_SS_INDEX 29 518 #define MAC_TCR_SS_WIDTH 2 519 #define MAC_TCR_TE_INDEX 0 520 #define MAC_TCR_TE_WIDTH 1 521 #define MAC_TSCR_AV8021ASMEN_INDEX 28 522 #define MAC_TSCR_AV8021ASMEN_WIDTH 1 523 #define MAC_TSCR_SNAPTYPSEL_INDEX 16 524 #define MAC_TSCR_SNAPTYPSEL_WIDTH 2 525 #define MAC_TSCR_TSADDREG_INDEX 5 526 #define MAC_TSCR_TSADDREG_WIDTH 1 527 #define MAC_TSCR_TSCFUPDT_INDEX 1 528 #define MAC_TSCR_TSCFUPDT_WIDTH 1 529 #define MAC_TSCR_TSCTRLSSR_INDEX 9 530 #define MAC_TSCR_TSCTRLSSR_WIDTH 1 531 #define MAC_TSCR_TSENA_INDEX 0 532 #define MAC_TSCR_TSENA_WIDTH 1 533 #define MAC_TSCR_TSENALL_INDEX 8 534 #define MAC_TSCR_TSENALL_WIDTH 1 535 #define MAC_TSCR_TSEVNTENA_INDEX 14 536 #define MAC_TSCR_TSEVNTENA_WIDTH 1 537 #define MAC_TSCR_TSINIT_INDEX 2 538 #define MAC_TSCR_TSINIT_WIDTH 1 539 #define MAC_TSCR_TSIPENA_INDEX 11 540 #define MAC_TSCR_TSIPENA_WIDTH 1 541 #define MAC_TSCR_TSIPV4ENA_INDEX 13 542 #define MAC_TSCR_TSIPV4ENA_WIDTH 1 543 #define MAC_TSCR_TSIPV6ENA_INDEX 12 544 #define MAC_TSCR_TSIPV6ENA_WIDTH 1 545 #define MAC_TSCR_TSMSTRENA_INDEX 15 546 #define MAC_TSCR_TSMSTRENA_WIDTH 1 547 #define MAC_TSCR_TSVER2ENA_INDEX 10 548 #define MAC_TSCR_TSVER2ENA_WIDTH 1 549 #define MAC_TSCR_TXTSSTSM_INDEX 24 550 #define MAC_TSCR_TXTSSTSM_WIDTH 1 551 #define MAC_TSSR_TXTSC_INDEX 15 552 #define MAC_TSSR_TXTSC_WIDTH 1 553 #define MAC_TXSNR_TXTSSTSMIS_INDEX 31 554 #define MAC_TXSNR_TXTSSTSMIS_WIDTH 1 555 #define MAC_VLANHTR_VLHT_INDEX 0 556 #define MAC_VLANHTR_VLHT_WIDTH 16 557 #define MAC_VLANIR_VLTI_INDEX 20 558 #define MAC_VLANIR_VLTI_WIDTH 1 559 #define MAC_VLANIR_CSVL_INDEX 19 560 #define MAC_VLANIR_CSVL_WIDTH 1 561 #define MAC_VLANTR_DOVLTC_INDEX 20 562 #define MAC_VLANTR_DOVLTC_WIDTH 1 563 #define MAC_VLANTR_ERSVLM_INDEX 19 564 #define MAC_VLANTR_ERSVLM_WIDTH 1 565 #define MAC_VLANTR_ESVL_INDEX 18 566 #define MAC_VLANTR_ESVL_WIDTH 1 567 #define MAC_VLANTR_ETV_INDEX 16 568 #define MAC_VLANTR_ETV_WIDTH 1 569 #define MAC_VLANTR_EVLS_INDEX 21 570 #define MAC_VLANTR_EVLS_WIDTH 2 571 #define MAC_VLANTR_EVLRXS_INDEX 24 572 #define MAC_VLANTR_EVLRXS_WIDTH 1 573 #define MAC_VLANTR_VL_INDEX 0 574 #define MAC_VLANTR_VL_WIDTH 16 575 #define MAC_VLANTR_VTHM_INDEX 25 576 #define MAC_VLANTR_VTHM_WIDTH 1 577 #define MAC_VLANTR_VTIM_INDEX 17 578 #define MAC_VLANTR_VTIM_WIDTH 1 579 #define MAC_VR_DEVID_INDEX 8 580 #define MAC_VR_DEVID_WIDTH 8 581 #define MAC_VR_SNPSVER_INDEX 0 582 #define MAC_VR_SNPSVER_WIDTH 8 583 #define MAC_VR_USERVER_INDEX 16 584 #define MAC_VR_USERVER_WIDTH 8 585 586 /* MMC register offsets */ 587 #define MMC_CR 0x0800 588 #define MMC_RISR 0x0804 589 #define MMC_TISR 0x0808 590 #define MMC_RIER 0x080c 591 #define MMC_TIER 0x0810 592 #define MMC_TXOCTETCOUNT_GB_LO 0x0814 593 #define MMC_TXOCTETCOUNT_GB_HI 0x0818 594 #define MMC_TXFRAMECOUNT_GB_LO 0x081c 595 #define MMC_TXFRAMECOUNT_GB_HI 0x0820 596 #define MMC_TXBROADCASTFRAMES_G_LO 0x0824 597 #define MMC_TXBROADCASTFRAMES_G_HI 0x0828 598 #define MMC_TXMULTICASTFRAMES_G_LO 0x082c 599 #define MMC_TXMULTICASTFRAMES_G_HI 0x0830 600 #define MMC_TX64OCTETS_GB_LO 0x0834 601 #define MMC_TX64OCTETS_GB_HI 0x0838 602 #define MMC_TX65TO127OCTETS_GB_LO 0x083c 603 #define MMC_TX65TO127OCTETS_GB_HI 0x0840 604 #define MMC_TX128TO255OCTETS_GB_LO 0x0844 605 #define MMC_TX128TO255OCTETS_GB_HI 0x0848 606 #define MMC_TX256TO511OCTETS_GB_LO 0x084c 607 #define MMC_TX256TO511OCTETS_GB_HI 0x0850 608 #define MMC_TX512TO1023OCTETS_GB_LO 0x0854 609 #define MMC_TX512TO1023OCTETS_GB_HI 0x0858 610 #define MMC_TX1024TOMAXOCTETS_GB_LO 0x085c 611 #define MMC_TX1024TOMAXOCTETS_GB_HI 0x0860 612 #define MMC_TXUNICASTFRAMES_GB_LO 0x0864 613 #define MMC_TXUNICASTFRAMES_GB_HI 0x0868 614 #define MMC_TXMULTICASTFRAMES_GB_LO 0x086c 615 #define MMC_TXMULTICASTFRAMES_GB_HI 0x0870 616 #define MMC_TXBROADCASTFRAMES_GB_LO 0x0874 617 #define MMC_TXBROADCASTFRAMES_GB_HI 0x0878 618 #define MMC_TXUNDERFLOWERROR_LO 0x087c 619 #define MMC_TXUNDERFLOWERROR_HI 0x0880 620 #define MMC_TXOCTETCOUNT_G_LO 0x0884 621 #define MMC_TXOCTETCOUNT_G_HI 0x0888 622 #define MMC_TXFRAMECOUNT_G_LO 0x088c 623 #define MMC_TXFRAMECOUNT_G_HI 0x0890 624 #define MMC_TXPAUSEFRAMES_LO 0x0894 625 #define MMC_TXPAUSEFRAMES_HI 0x0898 626 #define MMC_TXVLANFRAMES_G_LO 0x089c 627 #define MMC_TXVLANFRAMES_G_HI 0x08a0 628 #define MMC_RXFRAMECOUNT_GB_LO 0x0900 629 #define MMC_RXFRAMECOUNT_GB_HI 0x0904 630 #define MMC_RXOCTETCOUNT_GB_LO 0x0908 631 #define MMC_RXOCTETCOUNT_GB_HI 0x090c 632 #define MMC_RXOCTETCOUNT_G_LO 0x0910 633 #define MMC_RXOCTETCOUNT_G_HI 0x0914 634 #define MMC_RXBROADCASTFRAMES_G_LO 0x0918 635 #define MMC_RXBROADCASTFRAMES_G_HI 0x091c 636 #define MMC_RXMULTICASTFRAMES_G_LO 0x0920 637 #define MMC_RXMULTICASTFRAMES_G_HI 0x0924 638 #define MMC_RXCRCERROR_LO 0x0928 639 #define MMC_RXCRCERROR_HI 0x092c 640 #define MMC_RXRUNTERROR 0x0930 641 #define MMC_RXJABBERERROR 0x0934 642 #define MMC_RXUNDERSIZE_G 0x0938 643 #define MMC_RXOVERSIZE_G 0x093c 644 #define MMC_RX64OCTETS_GB_LO 0x0940 645 #define MMC_RX64OCTETS_GB_HI 0x0944 646 #define MMC_RX65TO127OCTETS_GB_LO 0x0948 647 #define MMC_RX65TO127OCTETS_GB_HI 0x094c 648 #define MMC_RX128TO255OCTETS_GB_LO 0x0950 649 #define MMC_RX128TO255OCTETS_GB_HI 0x0954 650 #define MMC_RX256TO511OCTETS_GB_LO 0x0958 651 #define MMC_RX256TO511OCTETS_GB_HI 0x095c 652 #define MMC_RX512TO1023OCTETS_GB_LO 0x0960 653 #define MMC_RX512TO1023OCTETS_GB_HI 0x0964 654 #define MMC_RX1024TOMAXOCTETS_GB_LO 0x0968 655 #define MMC_RX1024TOMAXOCTETS_GB_HI 0x096c 656 #define MMC_RXUNICASTFRAMES_G_LO 0x0970 657 #define MMC_RXUNICASTFRAMES_G_HI 0x0974 658 #define MMC_RXLENGTHERROR_LO 0x0978 659 #define MMC_RXLENGTHERROR_HI 0x097c 660 #define MMC_RXOUTOFRANGETYPE_LO 0x0980 661 #define MMC_RXOUTOFRANGETYPE_HI 0x0984 662 #define MMC_RXPAUSEFRAMES_LO 0x0988 663 #define MMC_RXPAUSEFRAMES_HI 0x098c 664 #define MMC_RXFIFOOVERFLOW_LO 0x0990 665 #define MMC_RXFIFOOVERFLOW_HI 0x0994 666 #define MMC_RXVLANFRAMES_GB_LO 0x0998 667 #define MMC_RXVLANFRAMES_GB_HI 0x099c 668 #define MMC_RXWATCHDOGERROR 0x09a0 669 670 /* MMC register entry bit positions and sizes */ 671 #define MMC_CR_CR_INDEX 0 672 #define MMC_CR_CR_WIDTH 1 673 #define MMC_CR_CSR_INDEX 1 674 #define MMC_CR_CSR_WIDTH 1 675 #define MMC_CR_ROR_INDEX 2 676 #define MMC_CR_ROR_WIDTH 1 677 #define MMC_CR_MCF_INDEX 3 678 #define MMC_CR_MCF_WIDTH 1 679 #define MMC_CR_MCT_INDEX 4 680 #define MMC_CR_MCT_WIDTH 2 681 #define MMC_RIER_ALL_INTERRUPTS_INDEX 0 682 #define MMC_RIER_ALL_INTERRUPTS_WIDTH 23 683 #define MMC_RISR_RXFRAMECOUNT_GB_INDEX 0 684 #define MMC_RISR_RXFRAMECOUNT_GB_WIDTH 1 685 #define MMC_RISR_RXOCTETCOUNT_GB_INDEX 1 686 #define MMC_RISR_RXOCTETCOUNT_GB_WIDTH 1 687 #define MMC_RISR_RXOCTETCOUNT_G_INDEX 2 688 #define MMC_RISR_RXOCTETCOUNT_G_WIDTH 1 689 #define MMC_RISR_RXBROADCASTFRAMES_G_INDEX 3 690 #define MMC_RISR_RXBROADCASTFRAMES_G_WIDTH 1 691 #define MMC_RISR_RXMULTICASTFRAMES_G_INDEX 4 692 #define MMC_RISR_RXMULTICASTFRAMES_G_WIDTH 1 693 #define MMC_RISR_RXCRCERROR_INDEX 5 694 #define MMC_RISR_RXCRCERROR_WIDTH 1 695 #define MMC_RISR_RXRUNTERROR_INDEX 6 696 #define MMC_RISR_RXRUNTERROR_WIDTH 1 697 #define MMC_RISR_RXJABBERERROR_INDEX 7 698 #define MMC_RISR_RXJABBERERROR_WIDTH 1 699 #define MMC_RISR_RXUNDERSIZE_G_INDEX 8 700 #define MMC_RISR_RXUNDERSIZE_G_WIDTH 1 701 #define MMC_RISR_RXOVERSIZE_G_INDEX 9 702 #define MMC_RISR_RXOVERSIZE_G_WIDTH 1 703 #define MMC_RISR_RX64OCTETS_GB_INDEX 10 704 #define MMC_RISR_RX64OCTETS_GB_WIDTH 1 705 #define MMC_RISR_RX65TO127OCTETS_GB_INDEX 11 706 #define MMC_RISR_RX65TO127OCTETS_GB_WIDTH 1 707 #define MMC_RISR_RX128TO255OCTETS_GB_INDEX 12 708 #define MMC_RISR_RX128TO255OCTETS_GB_WIDTH 1 709 #define MMC_RISR_RX256TO511OCTETS_GB_INDEX 13 710 #define MMC_RISR_RX256TO511OCTETS_GB_WIDTH 1 711 #define MMC_RISR_RX512TO1023OCTETS_GB_INDEX 14 712 #define MMC_RISR_RX512TO1023OCTETS_GB_WIDTH 1 713 #define MMC_RISR_RX1024TOMAXOCTETS_GB_INDEX 15 714 #define MMC_RISR_RX1024TOMAXOCTETS_GB_WIDTH 1 715 #define MMC_RISR_RXUNICASTFRAMES_G_INDEX 16 716 #define MMC_RISR_RXUNICASTFRAMES_G_WIDTH 1 717 #define MMC_RISR_RXLENGTHERROR_INDEX 17 718 #define MMC_RISR_RXLENGTHERROR_WIDTH 1 719 #define MMC_RISR_RXOUTOFRANGETYPE_INDEX 18 720 #define MMC_RISR_RXOUTOFRANGETYPE_WIDTH 1 721 #define MMC_RISR_RXPAUSEFRAMES_INDEX 19 722 #define MMC_RISR_RXPAUSEFRAMES_WIDTH 1 723 #define MMC_RISR_RXFIFOOVERFLOW_INDEX 20 724 #define MMC_RISR_RXFIFOOVERFLOW_WIDTH 1 725 #define MMC_RISR_RXVLANFRAMES_GB_INDEX 21 726 #define MMC_RISR_RXVLANFRAMES_GB_WIDTH 1 727 #define MMC_RISR_RXWATCHDOGERROR_INDEX 22 728 #define MMC_RISR_RXWATCHDOGERROR_WIDTH 1 729 #define MMC_TIER_ALL_INTERRUPTS_INDEX 0 730 #define MMC_TIER_ALL_INTERRUPTS_WIDTH 18 731 #define MMC_TISR_TXOCTETCOUNT_GB_INDEX 0 732 #define MMC_TISR_TXOCTETCOUNT_GB_WIDTH 1 733 #define MMC_TISR_TXFRAMECOUNT_GB_INDEX 1 734 #define MMC_TISR_TXFRAMECOUNT_GB_WIDTH 1 735 #define MMC_TISR_TXBROADCASTFRAMES_G_INDEX 2 736 #define MMC_TISR_TXBROADCASTFRAMES_G_WIDTH 1 737 #define MMC_TISR_TXMULTICASTFRAMES_G_INDEX 3 738 #define MMC_TISR_TXMULTICASTFRAMES_G_WIDTH 1 739 #define MMC_TISR_TX64OCTETS_GB_INDEX 4 740 #define MMC_TISR_TX64OCTETS_GB_WIDTH 1 741 #define MMC_TISR_TX65TO127OCTETS_GB_INDEX 5 742 #define MMC_TISR_TX65TO127OCTETS_GB_WIDTH 1 743 #define MMC_TISR_TX128TO255OCTETS_GB_INDEX 6 744 #define MMC_TISR_TX128TO255OCTETS_GB_WIDTH 1 745 #define MMC_TISR_TX256TO511OCTETS_GB_INDEX 7 746 #define MMC_TISR_TX256TO511OCTETS_GB_WIDTH 1 747 #define MMC_TISR_TX512TO1023OCTETS_GB_INDEX 8 748 #define MMC_TISR_TX512TO1023OCTETS_GB_WIDTH 1 749 #define MMC_TISR_TX1024TOMAXOCTETS_GB_INDEX 9 750 #define MMC_TISR_TX1024TOMAXOCTETS_GB_WIDTH 1 751 #define MMC_TISR_TXUNICASTFRAMES_GB_INDEX 10 752 #define MMC_TISR_TXUNICASTFRAMES_GB_WIDTH 1 753 #define MMC_TISR_TXMULTICASTFRAMES_GB_INDEX 11 754 #define MMC_TISR_TXMULTICASTFRAMES_GB_WIDTH 1 755 #define MMC_TISR_TXBROADCASTFRAMES_GB_INDEX 12 756 #define MMC_TISR_TXBROADCASTFRAMES_GB_WIDTH 1 757 #define MMC_TISR_TXUNDERFLOWERROR_INDEX 13 758 #define MMC_TISR_TXUNDERFLOWERROR_WIDTH 1 759 #define MMC_TISR_TXOCTETCOUNT_G_INDEX 14 760 #define MMC_TISR_TXOCTETCOUNT_G_WIDTH 1 761 #define MMC_TISR_TXFRAMECOUNT_G_INDEX 15 762 #define MMC_TISR_TXFRAMECOUNT_G_WIDTH 1 763 #define MMC_TISR_TXPAUSEFRAMES_INDEX 16 764 #define MMC_TISR_TXPAUSEFRAMES_WIDTH 1 765 #define MMC_TISR_TXVLANFRAMES_G_INDEX 17 766 #define MMC_TISR_TXVLANFRAMES_G_WIDTH 1 767 768 /* MTL register offsets */ 769 #define MTL_OMR 0x1000 770 #define MTL_FDCR 0x1008 771 #define MTL_FDSR 0x100c 772 #define MTL_FDDR 0x1010 773 #define MTL_ISR 0x1020 774 #define MTL_RQDCM0R 0x1030 775 #define MTL_TCPM0R 0x1040 776 #define MTL_TCPM1R 0x1044 777 778 #define MTL_RQDCM_INC 4 779 #define MTL_RQDCM_Q_PER_REG 4 780 #define MTL_TCPM_INC 4 781 #define MTL_TCPM_TC_PER_REG 4 782 783 /* MTL register entry bit positions and sizes */ 784 #define MTL_OMR_ETSALG_INDEX 5 785 #define MTL_OMR_ETSALG_WIDTH 2 786 #define MTL_OMR_RAA_INDEX 2 787 #define MTL_OMR_RAA_WIDTH 1 788 789 /* MTL queue register offsets 790 * Multiple queues can be active. The first queue has registers 791 * that begin at 0x1100. Each subsequent queue has registers that 792 * are accessed using an offset of 0x80 from the previous queue. 793 */ 794 #define MTL_Q_BASE 0x1100 795 #define MTL_Q_INC 0x80 796 797 #define MTL_Q_TQOMR 0x00 798 #define MTL_Q_TQUR 0x04 799 #define MTL_Q_TQDR 0x08 800 #define MTL_Q_RQOMR 0x40 801 #define MTL_Q_RQMPOCR 0x44 802 #define MTL_Q_RQDR 0x48 803 #define MTL_Q_RQFCR 0x50 804 #define MTL_Q_IER 0x70 805 #define MTL_Q_ISR 0x74 806 807 /* MTL queue register entry bit positions and sizes */ 808 #define MTL_Q_RQDR_PRXQ_INDEX 16 809 #define MTL_Q_RQDR_PRXQ_WIDTH 14 810 #define MTL_Q_RQDR_RXQSTS_INDEX 4 811 #define MTL_Q_RQDR_RXQSTS_WIDTH 2 812 #define MTL_Q_RQFCR_RFA_INDEX 1 813 #define MTL_Q_RQFCR_RFA_WIDTH 6 814 #define MTL_Q_RQFCR_RFD_INDEX 17 815 #define MTL_Q_RQFCR_RFD_WIDTH 6 816 #define MTL_Q_RQOMR_EHFC_INDEX 7 817 #define MTL_Q_RQOMR_EHFC_WIDTH 1 818 #define MTL_Q_RQOMR_RQS_INDEX 16 819 #define MTL_Q_RQOMR_RQS_WIDTH 9 820 #define MTL_Q_RQOMR_RSF_INDEX 5 821 #define MTL_Q_RQOMR_RSF_WIDTH 1 822 #define MTL_Q_RQOMR_RTC_INDEX 0 823 #define MTL_Q_RQOMR_RTC_WIDTH 2 824 #define MTL_Q_TQDR_TRCSTS_INDEX 1 825 #define MTL_Q_TQDR_TRCSTS_WIDTH 2 826 #define MTL_Q_TQDR_TXQSTS_INDEX 4 827 #define MTL_Q_TQDR_TXQSTS_WIDTH 1 828 #define MTL_Q_TQOMR_FTQ_INDEX 0 829 #define MTL_Q_TQOMR_FTQ_WIDTH 1 830 #define MTL_Q_TQOMR_Q2TCMAP_INDEX 8 831 #define MTL_Q_TQOMR_Q2TCMAP_WIDTH 3 832 #define MTL_Q_TQOMR_TQS_INDEX 16 833 #define MTL_Q_TQOMR_TQS_WIDTH 10 834 #define MTL_Q_TQOMR_TSF_INDEX 1 835 #define MTL_Q_TQOMR_TSF_WIDTH 1 836 #define MTL_Q_TQOMR_TTC_INDEX 4 837 #define MTL_Q_TQOMR_TTC_WIDTH 3 838 #define MTL_Q_TQOMR_TXQEN_INDEX 2 839 #define MTL_Q_TQOMR_TXQEN_WIDTH 2 840 841 /* MTL queue register value */ 842 #define MTL_RSF_DISABLE 0x00 843 #define MTL_RSF_ENABLE 0x01 844 #define MTL_TSF_DISABLE 0x00 845 #define MTL_TSF_ENABLE 0x01 846 847 #define MTL_RX_THRESHOLD_64 0x00 848 #define MTL_RX_THRESHOLD_96 0x02 849 #define MTL_RX_THRESHOLD_128 0x03 850 #define MTL_TX_THRESHOLD_32 0x01 851 #define MTL_TX_THRESHOLD_64 0x00 852 #define MTL_TX_THRESHOLD_96 0x02 853 #define MTL_TX_THRESHOLD_128 0x03 854 #define MTL_TX_THRESHOLD_192 0x04 855 #define MTL_TX_THRESHOLD_256 0x05 856 #define MTL_TX_THRESHOLD_384 0x06 857 #define MTL_TX_THRESHOLD_512 0x07 858 859 #define MTL_ETSALG_WRR 0x00 860 #define MTL_ETSALG_WFQ 0x01 861 #define MTL_ETSALG_DWRR 0x02 862 #define MTL_RAA_SP 0x00 863 #define MTL_RAA_WSP 0x01 864 865 #define MTL_Q_DISABLED 0x00 866 #define MTL_Q_ENABLED 0x02 867 868 /* MTL traffic class register offsets 869 * Multiple traffic classes can be active. The first class has registers 870 * that begin at 0x1100. Each subsequent queue has registers that 871 * are accessed using an offset of 0x80 from the previous queue. 872 */ 873 #define MTL_TC_BASE MTL_Q_BASE 874 #define MTL_TC_INC MTL_Q_INC 875 876 #define MTL_TC_ETSCR 0x10 877 #define MTL_TC_ETSSR 0x14 878 #define MTL_TC_QWR 0x18 879 880 /* MTL traffic class register entry bit positions and sizes */ 881 #define MTL_TC_ETSCR_TSA_INDEX 0 882 #define MTL_TC_ETSCR_TSA_WIDTH 2 883 #define MTL_TC_QWR_QW_INDEX 0 884 #define MTL_TC_QWR_QW_WIDTH 21 885 886 /* MTL traffic class register value */ 887 #define MTL_TSA_SP 0x00 888 #define MTL_TSA_ETS 0x02 889 890 /* PCS register offsets */ 891 #define PCS_V1_WINDOW_SELECT 0x03fc 892 #define PCS_V2_WINDOW_DEF 0x9060 893 #define PCS_V2_WINDOW_SELECT 0x9064 894 895 /* PCS register entry bit positions and sizes */ 896 #define PCS_V2_WINDOW_DEF_OFFSET_INDEX 6 897 #define PCS_V2_WINDOW_DEF_OFFSET_WIDTH 14 898 #define PCS_V2_WINDOW_DEF_SIZE_INDEX 2 899 #define PCS_V2_WINDOW_DEF_SIZE_WIDTH 4 900 901 /* SerDes integration register offsets */ 902 #define SIR0_KR_RT_1 0x002c 903 #define SIR0_STATUS 0x0040 904 #define SIR1_SPEED 0x0000 905 906 /* SerDes integration register entry bit positions and sizes */ 907 #define SIR0_KR_RT_1_RESET_INDEX 11 908 #define SIR0_KR_RT_1_RESET_WIDTH 1 909 #define SIR0_STATUS_RX_READY_INDEX 0 910 #define SIR0_STATUS_RX_READY_WIDTH 1 911 #define SIR0_STATUS_TX_READY_INDEX 8 912 #define SIR0_STATUS_TX_READY_WIDTH 1 913 #define SIR1_SPEED_CDR_RATE_INDEX 12 914 #define SIR1_SPEED_CDR_RATE_WIDTH 4 915 #define SIR1_SPEED_DATARATE_INDEX 4 916 #define SIR1_SPEED_DATARATE_WIDTH 2 917 #define SIR1_SPEED_PLLSEL_INDEX 3 918 #define SIR1_SPEED_PLLSEL_WIDTH 1 919 #define SIR1_SPEED_RATECHANGE_INDEX 6 920 #define SIR1_SPEED_RATECHANGE_WIDTH 1 921 #define SIR1_SPEED_TXAMP_INDEX 8 922 #define SIR1_SPEED_TXAMP_WIDTH 4 923 #define SIR1_SPEED_WORDMODE_INDEX 0 924 #define SIR1_SPEED_WORDMODE_WIDTH 3 925 926 /* SerDes RxTx register offsets */ 927 #define RXTX_REG6 0x0018 928 #define RXTX_REG20 0x0050 929 #define RXTX_REG22 0x0058 930 #define RXTX_REG114 0x01c8 931 #define RXTX_REG129 0x0204 932 933 /* SerDes RxTx register entry bit positions and sizes */ 934 #define RXTX_REG6_RESETB_RXD_INDEX 8 935 #define RXTX_REG6_RESETB_RXD_WIDTH 1 936 #define RXTX_REG20_BLWC_ENA_INDEX 2 937 #define RXTX_REG20_BLWC_ENA_WIDTH 1 938 #define RXTX_REG114_PQ_REG_INDEX 9 939 #define RXTX_REG114_PQ_REG_WIDTH 7 940 #define RXTX_REG129_RXDFE_CONFIG_INDEX 14 941 #define RXTX_REG129_RXDFE_CONFIG_WIDTH 2 942 943 /* MAC Control register offsets */ 944 #define XP_PROP_0 0x0000 945 #define XP_PROP_1 0x0004 946 #define XP_PROP_2 0x0008 947 #define XP_PROP_3 0x000c 948 #define XP_PROP_4 0x0010 949 #define XP_PROP_5 0x0014 950 #define XP_MAC_ADDR_LO 0x0020 951 #define XP_MAC_ADDR_HI 0x0024 952 #define XP_ECC_ISR 0x0030 953 #define XP_ECC_IER 0x0034 954 #define XP_ECC_CNT0 0x003c 955 #define XP_ECC_CNT1 0x0040 956 #define XP_DRIVER_INT_REQ 0x0060 957 #define XP_DRIVER_INT_RO 0x0064 958 #define XP_DRIVER_SCRATCH_0 0x0068 959 #define XP_DRIVER_SCRATCH_1 0x006c 960 #define XP_INT_EN 0x0078 961 #define XP_I2C_MUTEX 0x0080 962 #define XP_MDIO_MUTEX 0x0084 963 964 /* MAC Control register entry bit positions and sizes */ 965 #define XP_DRIVER_INT_REQ_REQUEST_INDEX 0 966 #define XP_DRIVER_INT_REQ_REQUEST_WIDTH 1 967 #define XP_DRIVER_INT_RO_STATUS_INDEX 0 968 #define XP_DRIVER_INT_RO_STATUS_WIDTH 1 969 #define XP_DRIVER_SCRATCH_0_COMMAND_INDEX 0 970 #define XP_DRIVER_SCRATCH_0_COMMAND_WIDTH 8 971 #define XP_DRIVER_SCRATCH_0_SUB_COMMAND_INDEX 8 972 #define XP_DRIVER_SCRATCH_0_SUB_COMMAND_WIDTH 8 973 #define XP_ECC_CNT0_RX_DED_INDEX 24 974 #define XP_ECC_CNT0_RX_DED_WIDTH 8 975 #define XP_ECC_CNT0_RX_SEC_INDEX 16 976 #define XP_ECC_CNT0_RX_SEC_WIDTH 8 977 #define XP_ECC_CNT0_TX_DED_INDEX 8 978 #define XP_ECC_CNT0_TX_DED_WIDTH 8 979 #define XP_ECC_CNT0_TX_SEC_INDEX 0 980 #define XP_ECC_CNT0_TX_SEC_WIDTH 8 981 #define XP_ECC_CNT1_DESC_DED_INDEX 8 982 #define XP_ECC_CNT1_DESC_DED_WIDTH 8 983 #define XP_ECC_CNT1_DESC_SEC_INDEX 0 984 #define XP_ECC_CNT1_DESC_SEC_WIDTH 8 985 #define XP_ECC_IER_DESC_DED_INDEX 0 986 #define XP_ECC_IER_DESC_DED_WIDTH 1 987 #define XP_ECC_IER_DESC_SEC_INDEX 1 988 #define XP_ECC_IER_DESC_SEC_WIDTH 1 989 #define XP_ECC_IER_RX_DED_INDEX 2 990 #define XP_ECC_IER_RX_DED_WIDTH 1 991 #define XP_ECC_IER_RX_SEC_INDEX 3 992 #define XP_ECC_IER_RX_SEC_WIDTH 1 993 #define XP_ECC_IER_TX_DED_INDEX 4 994 #define XP_ECC_IER_TX_DED_WIDTH 1 995 #define XP_ECC_IER_TX_SEC_INDEX 5 996 #define XP_ECC_IER_TX_SEC_WIDTH 1 997 #define XP_ECC_ISR_DESC_DED_INDEX 0 998 #define XP_ECC_ISR_DESC_DED_WIDTH 1 999 #define XP_ECC_ISR_DESC_SEC_INDEX 1 1000 #define XP_ECC_ISR_DESC_SEC_WIDTH 1 1001 #define XP_ECC_ISR_RX_DED_INDEX 2 1002 #define XP_ECC_ISR_RX_DED_WIDTH 1 1003 #define XP_ECC_ISR_RX_SEC_INDEX 3 1004 #define XP_ECC_ISR_RX_SEC_WIDTH 1 1005 #define XP_ECC_ISR_TX_DED_INDEX 4 1006 #define XP_ECC_ISR_TX_DED_WIDTH 1 1007 #define XP_ECC_ISR_TX_SEC_INDEX 5 1008 #define XP_ECC_ISR_TX_SEC_WIDTH 1 1009 #define XP_I2C_MUTEX_BUSY_INDEX 31 1010 #define XP_I2C_MUTEX_BUSY_WIDTH 1 1011 #define XP_I2C_MUTEX_ID_INDEX 29 1012 #define XP_I2C_MUTEX_ID_WIDTH 2 1013 #define XP_I2C_MUTEX_ACTIVE_INDEX 0 1014 #define XP_I2C_MUTEX_ACTIVE_WIDTH 1 1015 #define XP_MAC_ADDR_HI_VALID_INDEX 31 1016 #define XP_MAC_ADDR_HI_VALID_WIDTH 1 1017 #define XP_PROP_0_CONN_TYPE_INDEX 28 1018 #define XP_PROP_0_CONN_TYPE_WIDTH 3 1019 #define XP_PROP_0_MDIO_ADDR_INDEX 16 1020 #define XP_PROP_0_MDIO_ADDR_WIDTH 5 1021 #define XP_PROP_0_PORT_ID_INDEX 0 1022 #define XP_PROP_0_PORT_ID_WIDTH 8 1023 #define XP_PROP_0_PORT_MODE_INDEX 8 1024 #define XP_PROP_0_PORT_MODE_WIDTH 4 1025 #define XP_PROP_0_PORT_SPEEDS_INDEX 23 1026 #define XP_PROP_0_PORT_SPEEDS_WIDTH 4 1027 #define XP_PROP_1_MAX_RX_DMA_INDEX 24 1028 #define XP_PROP_1_MAX_RX_DMA_WIDTH 5 1029 #define XP_PROP_1_MAX_RX_QUEUES_INDEX 8 1030 #define XP_PROP_1_MAX_RX_QUEUES_WIDTH 5 1031 #define XP_PROP_1_MAX_TX_DMA_INDEX 16 1032 #define XP_PROP_1_MAX_TX_DMA_WIDTH 5 1033 #define XP_PROP_1_MAX_TX_QUEUES_INDEX 0 1034 #define XP_PROP_1_MAX_TX_QUEUES_WIDTH 5 1035 #define XP_PROP_2_RX_FIFO_SIZE_INDEX 16 1036 #define XP_PROP_2_RX_FIFO_SIZE_WIDTH 16 1037 #define XP_PROP_2_TX_FIFO_SIZE_INDEX 0 1038 #define XP_PROP_2_TX_FIFO_SIZE_WIDTH 16 1039 #define XP_PROP_3_GPIO_MASK_INDEX 28 1040 #define XP_PROP_3_GPIO_MASK_WIDTH 4 1041 #define XP_PROP_3_GPIO_MOD_ABS_INDEX 20 1042 #define XP_PROP_3_GPIO_MOD_ABS_WIDTH 4 1043 #define XP_PROP_3_GPIO_RATE_SELECT_INDEX 16 1044 #define XP_PROP_3_GPIO_RATE_SELECT_WIDTH 4 1045 #define XP_PROP_3_GPIO_RX_LOS_INDEX 24 1046 #define XP_PROP_3_GPIO_RX_LOS_WIDTH 4 1047 #define XP_PROP_3_GPIO_TX_FAULT_INDEX 12 1048 #define XP_PROP_3_GPIO_TX_FAULT_WIDTH 4 1049 #define XP_PROP_3_GPIO_ADDR_INDEX 8 1050 #define XP_PROP_3_GPIO_ADDR_WIDTH 3 1051 #define XP_PROP_3_MDIO_RESET_INDEX 0 1052 #define XP_PROP_3_MDIO_RESET_WIDTH 2 1053 #define XP_PROP_3_MDIO_RESET_I2C_ADDR_INDEX 8 1054 #define XP_PROP_3_MDIO_RESET_I2C_ADDR_WIDTH 3 1055 #define XP_PROP_3_MDIO_RESET_I2C_GPIO_INDEX 12 1056 #define XP_PROP_3_MDIO_RESET_I2C_GPIO_WIDTH 4 1057 #define XP_PROP_3_MDIO_RESET_INT_GPIO_INDEX 4 1058 #define XP_PROP_3_MDIO_RESET_INT_GPIO_WIDTH 2 1059 #define XP_PROP_4_MUX_ADDR_HI_INDEX 8 1060 #define XP_PROP_4_MUX_ADDR_HI_WIDTH 5 1061 #define XP_PROP_4_MUX_ADDR_LO_INDEX 0 1062 #define XP_PROP_4_MUX_ADDR_LO_WIDTH 3 1063 #define XP_PROP_4_MUX_CHAN_INDEX 4 1064 #define XP_PROP_4_MUX_CHAN_WIDTH 3 1065 #define XP_PROP_4_REDRV_ADDR_INDEX 16 1066 #define XP_PROP_4_REDRV_ADDR_WIDTH 7 1067 #define XP_PROP_4_REDRV_IF_INDEX 23 1068 #define XP_PROP_4_REDRV_IF_WIDTH 1 1069 #define XP_PROP_4_REDRV_LANE_INDEX 24 1070 #define XP_PROP_4_REDRV_LANE_WIDTH 3 1071 #define XP_PROP_4_REDRV_MODEL_INDEX 28 1072 #define XP_PROP_4_REDRV_MODEL_WIDTH 3 1073 #define XP_PROP_4_REDRV_PRESENT_INDEX 31 1074 #define XP_PROP_4_REDRV_PRESENT_WIDTH 1 1075 1076 /* I2C Control register offsets */ 1077 #define IC_CON 0x0000 1078 #define IC_TAR 0x0004 1079 #define IC_DATA_CMD 0x0010 1080 #define IC_INTR_STAT 0x002c 1081 #define IC_INTR_MASK 0x0030 1082 #define IC_RAW_INTR_STAT 0x0034 1083 #define IC_CLR_INTR 0x0040 1084 #define IC_CLR_TX_ABRT 0x0054 1085 #define IC_CLR_STOP_DET 0x0060 1086 #define IC_ENABLE 0x006c 1087 #define IC_TXFLR 0x0074 1088 #define IC_RXFLR 0x0078 1089 #define IC_TX_ABRT_SOURCE 0x0080 1090 #define IC_ENABLE_STATUS 0x009c 1091 #define IC_COMP_PARAM_1 0x00f4 1092 1093 /* I2C Control register entry bit positions and sizes */ 1094 #define IC_COMP_PARAM_1_MAX_SPEED_MODE_INDEX 2 1095 #define IC_COMP_PARAM_1_MAX_SPEED_MODE_WIDTH 2 1096 #define IC_COMP_PARAM_1_RX_BUFFER_DEPTH_INDEX 8 1097 #define IC_COMP_PARAM_1_RX_BUFFER_DEPTH_WIDTH 8 1098 #define IC_COMP_PARAM_1_TX_BUFFER_DEPTH_INDEX 16 1099 #define IC_COMP_PARAM_1_TX_BUFFER_DEPTH_WIDTH 8 1100 #define IC_CON_MASTER_MODE_INDEX 0 1101 #define IC_CON_MASTER_MODE_WIDTH 1 1102 #define IC_CON_RESTART_EN_INDEX 5 1103 #define IC_CON_RESTART_EN_WIDTH 1 1104 #define IC_CON_RX_FIFO_FULL_HOLD_INDEX 9 1105 #define IC_CON_RX_FIFO_FULL_HOLD_WIDTH 1 1106 #define IC_CON_SLAVE_DISABLE_INDEX 6 1107 #define IC_CON_SLAVE_DISABLE_WIDTH 1 1108 #define IC_CON_SPEED_INDEX 1 1109 #define IC_CON_SPEED_WIDTH 2 1110 #define IC_DATA_CMD_CMD_INDEX 8 1111 #define IC_DATA_CMD_CMD_WIDTH 1 1112 #define IC_DATA_CMD_STOP_INDEX 9 1113 #define IC_DATA_CMD_STOP_WIDTH 1 1114 #define IC_ENABLE_ABORT_INDEX 1 1115 #define IC_ENABLE_ABORT_WIDTH 1 1116 #define IC_ENABLE_EN_INDEX 0 1117 #define IC_ENABLE_EN_WIDTH 1 1118 #define IC_ENABLE_STATUS_EN_INDEX 0 1119 #define IC_ENABLE_STATUS_EN_WIDTH 1 1120 #define IC_INTR_MASK_TX_EMPTY_INDEX 4 1121 #define IC_INTR_MASK_TX_EMPTY_WIDTH 1 1122 #define IC_RAW_INTR_STAT_RX_FULL_INDEX 2 1123 #define IC_RAW_INTR_STAT_RX_FULL_WIDTH 1 1124 #define IC_RAW_INTR_STAT_STOP_DET_INDEX 9 1125 #define IC_RAW_INTR_STAT_STOP_DET_WIDTH 1 1126 #define IC_RAW_INTR_STAT_TX_ABRT_INDEX 6 1127 #define IC_RAW_INTR_STAT_TX_ABRT_WIDTH 1 1128 #define IC_RAW_INTR_STAT_TX_EMPTY_INDEX 4 1129 #define IC_RAW_INTR_STAT_TX_EMPTY_WIDTH 1 1130 1131 /* I2C Control register value */ 1132 #define IC_TX_ABRT_7B_ADDR_NOACK 0x0001 1133 #define IC_TX_ABRT_ARB_LOST 0x1000 1134 1135 /* Descriptor/Packet entry bit positions and sizes */ 1136 #define RX_PACKET_ERRORS_CRC_INDEX 2 1137 #define RX_PACKET_ERRORS_CRC_WIDTH 1 1138 #define RX_PACKET_ERRORS_FRAME_INDEX 3 1139 #define RX_PACKET_ERRORS_FRAME_WIDTH 1 1140 #define RX_PACKET_ERRORS_LENGTH_INDEX 0 1141 #define RX_PACKET_ERRORS_LENGTH_WIDTH 1 1142 #define RX_PACKET_ERRORS_OVERRUN_INDEX 1 1143 #define RX_PACKET_ERRORS_OVERRUN_WIDTH 1 1144 1145 #define RX_PACKET_ATTRIBUTES_CSUM_DONE_INDEX 0 1146 #define RX_PACKET_ATTRIBUTES_CSUM_DONE_WIDTH 1 1147 #define RX_PACKET_ATTRIBUTES_VLAN_CTAG_INDEX 1 1148 #define RX_PACKET_ATTRIBUTES_VLAN_CTAG_WIDTH 1 1149 #define RX_PACKET_ATTRIBUTES_INCOMPLETE_INDEX 2 1150 #define RX_PACKET_ATTRIBUTES_INCOMPLETE_WIDTH 1 1151 #define RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_INDEX 3 1152 #define RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_WIDTH 1 1153 #define RX_PACKET_ATTRIBUTES_CONTEXT_INDEX 4 1154 #define RX_PACKET_ATTRIBUTES_CONTEXT_WIDTH 1 1155 #define RX_PACKET_ATTRIBUTES_RX_TSTAMP_INDEX 5 1156 #define RX_PACKET_ATTRIBUTES_RX_TSTAMP_WIDTH 1 1157 #define RX_PACKET_ATTRIBUTES_RSS_HASH_INDEX 6 1158 #define RX_PACKET_ATTRIBUTES_RSS_HASH_WIDTH 1 1159 1160 #define RX_NORMAL_DESC0_OVT_INDEX 0 1161 #define RX_NORMAL_DESC0_OVT_WIDTH 16 1162 #define RX_NORMAL_DESC2_HL_INDEX 0 1163 #define RX_NORMAL_DESC2_HL_WIDTH 10 1164 #define RX_NORMAL_DESC3_CDA_INDEX 27 1165 #define RX_NORMAL_DESC3_CDA_WIDTH 1 1166 #define RX_NORMAL_DESC3_CTXT_INDEX 30 1167 #define RX_NORMAL_DESC3_CTXT_WIDTH 1 1168 #define RX_NORMAL_DESC3_ES_INDEX 15 1169 #define RX_NORMAL_DESC3_ES_WIDTH 1 1170 #define RX_NORMAL_DESC3_ETLT_INDEX 16 1171 #define RX_NORMAL_DESC3_ETLT_WIDTH 4 1172 #define RX_NORMAL_DESC3_FD_INDEX 29 1173 #define RX_NORMAL_DESC3_FD_WIDTH 1 1174 #define RX_NORMAL_DESC3_INTE_INDEX 30 1175 #define RX_NORMAL_DESC3_INTE_WIDTH 1 1176 #define RX_NORMAL_DESC3_L34T_INDEX 20 1177 #define RX_NORMAL_DESC3_L34T_WIDTH 4 1178 #define RX_NORMAL_DESC3_LD_INDEX 28 1179 #define RX_NORMAL_DESC3_LD_WIDTH 1 1180 #define RX_NORMAL_DESC3_OWN_INDEX 31 1181 #define RX_NORMAL_DESC3_OWN_WIDTH 1 1182 #define RX_NORMAL_DESC3_PL_INDEX 0 1183 #define RX_NORMAL_DESC3_PL_WIDTH 14 1184 #define RX_NORMAL_DESC3_RSV_INDEX 26 1185 #define RX_NORMAL_DESC3_RSV_WIDTH 1 1186 1187 #define RX_DESC3_L34T_IPV4_TCP 1 1188 #define RX_DESC3_L34T_IPV4_UDP 2 1189 #define RX_DESC3_L34T_IPV4_ICMP 3 1190 #define RX_DESC3_L34T_IPV6_TCP 9 1191 #define RX_DESC3_L34T_IPV6_UDP 10 1192 #define RX_DESC3_L34T_IPV6_ICMP 11 1193 1194 #define RX_CONTEXT_DESC3_TSA_INDEX 4 1195 #define RX_CONTEXT_DESC3_TSA_WIDTH 1 1196 #define RX_CONTEXT_DESC3_TSD_INDEX 6 1197 #define RX_CONTEXT_DESC3_TSD_WIDTH 1 1198 1199 #define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_INDEX 0 1200 #define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_WIDTH 1 1201 #define TX_PACKET_ATTRIBUTES_TSO_ENABLE_INDEX 1 1202 #define TX_PACKET_ATTRIBUTES_TSO_ENABLE_WIDTH 1 1203 #define TX_PACKET_ATTRIBUTES_VLAN_CTAG_INDEX 2 1204 #define TX_PACKET_ATTRIBUTES_VLAN_CTAG_WIDTH 1 1205 #define TX_PACKET_ATTRIBUTES_PTP_INDEX 3 1206 #define TX_PACKET_ATTRIBUTES_PTP_WIDTH 1 1207 1208 #define TX_CONTEXT_DESC2_MSS_INDEX 0 1209 #define TX_CONTEXT_DESC2_MSS_WIDTH 15 1210 #define TX_CONTEXT_DESC3_CTXT_INDEX 30 1211 #define TX_CONTEXT_DESC3_CTXT_WIDTH 1 1212 #define TX_CONTEXT_DESC3_TCMSSV_INDEX 26 1213 #define TX_CONTEXT_DESC3_TCMSSV_WIDTH 1 1214 #define TX_CONTEXT_DESC3_VLTV_INDEX 16 1215 #define TX_CONTEXT_DESC3_VLTV_WIDTH 1 1216 #define TX_CONTEXT_DESC3_VT_INDEX 0 1217 #define TX_CONTEXT_DESC3_VT_WIDTH 16 1218 1219 #define TX_NORMAL_DESC2_HL_B1L_INDEX 0 1220 #define TX_NORMAL_DESC2_HL_B1L_WIDTH 14 1221 #define TX_NORMAL_DESC2_IC_INDEX 31 1222 #define TX_NORMAL_DESC2_IC_WIDTH 1 1223 #define TX_NORMAL_DESC2_TTSE_INDEX 30 1224 #define TX_NORMAL_DESC2_TTSE_WIDTH 1 1225 #define TX_NORMAL_DESC2_VTIR_INDEX 14 1226 #define TX_NORMAL_DESC2_VTIR_WIDTH 2 1227 #define TX_NORMAL_DESC3_CIC_INDEX 16 1228 #define TX_NORMAL_DESC3_CIC_WIDTH 2 1229 #define TX_NORMAL_DESC3_CPC_INDEX 26 1230 #define TX_NORMAL_DESC3_CPC_WIDTH 2 1231 #define TX_NORMAL_DESC3_CTXT_INDEX 30 1232 #define TX_NORMAL_DESC3_CTXT_WIDTH 1 1233 #define TX_NORMAL_DESC3_FD_INDEX 29 1234 #define TX_NORMAL_DESC3_FD_WIDTH 1 1235 #define TX_NORMAL_DESC3_FL_INDEX 0 1236 #define TX_NORMAL_DESC3_FL_WIDTH 15 1237 #define TX_NORMAL_DESC3_LD_INDEX 28 1238 #define TX_NORMAL_DESC3_LD_WIDTH 1 1239 #define TX_NORMAL_DESC3_OWN_INDEX 31 1240 #define TX_NORMAL_DESC3_OWN_WIDTH 1 1241 #define TX_NORMAL_DESC3_TCPHDRLEN_INDEX 19 1242 #define TX_NORMAL_DESC3_TCPHDRLEN_WIDTH 4 1243 #define TX_NORMAL_DESC3_TCPPL_INDEX 0 1244 #define TX_NORMAL_DESC3_TCPPL_WIDTH 18 1245 #define TX_NORMAL_DESC3_TSE_INDEX 18 1246 #define TX_NORMAL_DESC3_TSE_WIDTH 1 1247 1248 #define TX_NORMAL_DESC2_VLAN_INSERT 0x2 1249 1250 /* MDIO undefined or vendor specific registers */ 1251 #ifndef MDIO_PMA_10GBR_PMD_CTRL 1252 #define MDIO_PMA_10GBR_PMD_CTRL 0x0096 1253 #endif 1254 1255 #ifndef MDIO_PMA_10GBR_FECCTRL 1256 #define MDIO_PMA_10GBR_FECCTRL 0x00ab 1257 #endif 1258 1259 #ifndef MDIO_PCS_DIG_CTRL 1260 #define MDIO_PCS_DIG_CTRL 0x8000 1261 #endif 1262 1263 #ifndef MDIO_AN_XNP 1264 #define MDIO_AN_XNP 0x0016 1265 #endif 1266 1267 #ifndef MDIO_AN_LPX 1268 #define MDIO_AN_LPX 0x0019 1269 #endif 1270 1271 #ifndef MDIO_AN_COMP_STAT 1272 #define MDIO_AN_COMP_STAT 0x0030 1273 #endif 1274 1275 #ifndef MDIO_AN_INTMASK 1276 #define MDIO_AN_INTMASK 0x8001 1277 #endif 1278 1279 #ifndef MDIO_AN_INT 1280 #define MDIO_AN_INT 0x8002 1281 #endif 1282 1283 #ifndef MDIO_VEND2_AN_ADVERTISE 1284 #define MDIO_VEND2_AN_ADVERTISE 0x0004 1285 #endif 1286 1287 #ifndef MDIO_VEND2_AN_LP_ABILITY 1288 #define MDIO_VEND2_AN_LP_ABILITY 0x0005 1289 #endif 1290 1291 #ifndef MDIO_VEND2_AN_CTRL 1292 #define MDIO_VEND2_AN_CTRL 0x8001 1293 #endif 1294 1295 #ifndef MDIO_VEND2_AN_STAT 1296 #define MDIO_VEND2_AN_STAT 0x8002 1297 #endif 1298 1299 #ifndef MDIO_CTRL1_SPEED1G 1300 #define MDIO_CTRL1_SPEED1G (MDIO_CTRL1_SPEED10G & ~BMCR_SPEED100) 1301 #endif 1302 1303 #ifndef MDIO_VEND2_CTRL1_AN_ENABLE 1304 #define MDIO_VEND2_CTRL1_AN_ENABLE BIT(12) 1305 #endif 1306 1307 #ifndef MDIO_VEND2_CTRL1_AN_RESTART 1308 #define MDIO_VEND2_CTRL1_AN_RESTART BIT(9) 1309 #endif 1310 1311 #ifndef MDIO_VEND2_CTRL1_SS6 1312 #define MDIO_VEND2_CTRL1_SS6 BIT(6) 1313 #endif 1314 1315 #ifndef MDIO_VEND2_CTRL1_SS13 1316 #define MDIO_VEND2_CTRL1_SS13 BIT(13) 1317 #endif 1318 1319 /* MDIO mask values */ 1320 #define XGBE_AN_CL73_INT_CMPLT BIT(0) 1321 #define XGBE_AN_CL73_INC_LINK BIT(1) 1322 #define XGBE_AN_CL73_PG_RCV BIT(2) 1323 #define XGBE_AN_CL73_INT_MASK 0x07 1324 1325 #define XGBE_XNP_MCF_NULL_MESSAGE 0x001 1326 #define XGBE_XNP_ACK_PROCESSED BIT(12) 1327 #define XGBE_XNP_MP_FORMATTED BIT(13) 1328 #define XGBE_XNP_NP_EXCHANGE BIT(15) 1329 1330 #define XGBE_KR_TRAINING_START BIT(0) 1331 #define XGBE_KR_TRAINING_ENABLE BIT(1) 1332 1333 #define XGBE_PCS_CL37_BP BIT(12) 1334 1335 #define XGBE_AN_CL37_INT_CMPLT BIT(0) 1336 #define XGBE_AN_CL37_INT_MASK 0x01 1337 1338 #define XGBE_AN_CL37_HD_MASK 0x40 1339 #define XGBE_AN_CL37_FD_MASK 0x20 1340 1341 #define XGBE_AN_CL37_PCS_MODE_MASK 0x06 1342 #define XGBE_AN_CL37_PCS_MODE_BASEX 0x00 1343 #define XGBE_AN_CL37_PCS_MODE_SGMII 0x04 1344 #define XGBE_AN_CL37_TX_CONFIG_MASK 0x08 1345 1346 /* Bit setting and getting macros 1347 * The get macro will extract the current bit field value from within 1348 * the variable 1349 * 1350 * The set macro will clear the current bit field value within the 1351 * variable and then set the bit field of the variable to the 1352 * specified value 1353 */ 1354 #define GET_BITS(_var, _index, _width) \ 1355 (((_var) >> (_index)) & ((0x1 << (_width)) - 1)) 1356 1357 #define SET_BITS(_var, _index, _width, _val) \ 1358 do { \ 1359 (_var) &= ~(((0x1 << (_width)) - 1) << (_index)); \ 1360 (_var) |= (((_val) & ((0x1 << (_width)) - 1)) << (_index)); \ 1361 } while (0) 1362 1363 #define GET_BITS_LE(_var, _index, _width) \ 1364 ((le32_to_cpu((_var)) >> (_index)) & ((0x1 << (_width)) - 1)) 1365 1366 #define SET_BITS_LE(_var, _index, _width, _val) \ 1367 do { \ 1368 (_var) &= cpu_to_le32(~(((0x1 << (_width)) - 1) << (_index))); \ 1369 (_var) |= cpu_to_le32((((_val) & \ 1370 ((0x1 << (_width)) - 1)) << (_index))); \ 1371 } while (0) 1372 1373 /* Bit setting and getting macros based on register fields 1374 * The get macro uses the bit field definitions formed using the input 1375 * names to extract the current bit field value from within the 1376 * variable 1377 * 1378 * The set macro uses the bit field definitions formed using the input 1379 * names to set the bit field of the variable to the specified value 1380 */ 1381 #define XGMAC_GET_BITS(_var, _prefix, _field) \ 1382 GET_BITS((_var), \ 1383 _prefix##_##_field##_INDEX, \ 1384 _prefix##_##_field##_WIDTH) 1385 1386 #define XGMAC_SET_BITS(_var, _prefix, _field, _val) \ 1387 SET_BITS((_var), \ 1388 _prefix##_##_field##_INDEX, \ 1389 _prefix##_##_field##_WIDTH, (_val)) 1390 1391 #define XGMAC_GET_BITS_LE(_var, _prefix, _field) \ 1392 GET_BITS_LE((_var), \ 1393 _prefix##_##_field##_INDEX, \ 1394 _prefix##_##_field##_WIDTH) 1395 1396 #define XGMAC_SET_BITS_LE(_var, _prefix, _field, _val) \ 1397 SET_BITS_LE((_var), \ 1398 _prefix##_##_field##_INDEX, \ 1399 _prefix##_##_field##_WIDTH, (_val)) 1400 1401 /* Macros for reading or writing registers 1402 * The ioread macros will get bit fields or full values using the 1403 * register definitions formed using the input names 1404 * 1405 * The iowrite macros will set bit fields or full values using the 1406 * register definitions formed using the input names 1407 */ 1408 #define XGMAC_IOREAD(_pdata, _reg) \ 1409 ioread32((_pdata)->xgmac_regs + _reg) 1410 1411 #define XGMAC_IOREAD_BITS(_pdata, _reg, _field) \ 1412 GET_BITS(XGMAC_IOREAD((_pdata), _reg), \ 1413 _reg##_##_field##_INDEX, \ 1414 _reg##_##_field##_WIDTH) 1415 1416 #define XGMAC_IOWRITE(_pdata, _reg, _val) \ 1417 iowrite32((_val), (_pdata)->xgmac_regs + _reg) 1418 1419 #define XGMAC_IOWRITE_BITS(_pdata, _reg, _field, _val) \ 1420 do { \ 1421 u32 reg_val = XGMAC_IOREAD((_pdata), _reg); \ 1422 SET_BITS(reg_val, \ 1423 _reg##_##_field##_INDEX, \ 1424 _reg##_##_field##_WIDTH, (_val)); \ 1425 XGMAC_IOWRITE((_pdata), _reg, reg_val); \ 1426 } while (0) 1427 1428 /* Macros for reading or writing MTL queue or traffic class registers 1429 * Similar to the standard read and write macros except that the 1430 * base register value is calculated by the queue or traffic class number 1431 */ 1432 #define XGMAC_MTL_IOREAD(_pdata, _n, _reg) \ 1433 ioread32((_pdata)->xgmac_regs + \ 1434 MTL_Q_BASE + ((_n) * MTL_Q_INC) + _reg) 1435 1436 #define XGMAC_MTL_IOREAD_BITS(_pdata, _n, _reg, _field) \ 1437 GET_BITS(XGMAC_MTL_IOREAD((_pdata), (_n), _reg), \ 1438 _reg##_##_field##_INDEX, \ 1439 _reg##_##_field##_WIDTH) 1440 1441 #define XGMAC_MTL_IOWRITE(_pdata, _n, _reg, _val) \ 1442 iowrite32((_val), (_pdata)->xgmac_regs + \ 1443 MTL_Q_BASE + ((_n) * MTL_Q_INC) + _reg) 1444 1445 #define XGMAC_MTL_IOWRITE_BITS(_pdata, _n, _reg, _field, _val) \ 1446 do { \ 1447 u32 reg_val = XGMAC_MTL_IOREAD((_pdata), (_n), _reg); \ 1448 SET_BITS(reg_val, \ 1449 _reg##_##_field##_INDEX, \ 1450 _reg##_##_field##_WIDTH, (_val)); \ 1451 XGMAC_MTL_IOWRITE((_pdata), (_n), _reg, reg_val); \ 1452 } while (0) 1453 1454 /* Macros for reading or writing DMA channel registers 1455 * Similar to the standard read and write macros except that the 1456 * base register value is obtained from the ring 1457 */ 1458 #define XGMAC_DMA_IOREAD(_channel, _reg) \ 1459 ioread32((_channel)->dma_regs + _reg) 1460 1461 #define XGMAC_DMA_IOREAD_BITS(_channel, _reg, _field) \ 1462 GET_BITS(XGMAC_DMA_IOREAD((_channel), _reg), \ 1463 _reg##_##_field##_INDEX, \ 1464 _reg##_##_field##_WIDTH) 1465 1466 #define XGMAC_DMA_IOWRITE(_channel, _reg, _val) \ 1467 iowrite32((_val), (_channel)->dma_regs + _reg) 1468 1469 #define XGMAC_DMA_IOWRITE_BITS(_channel, _reg, _field, _val) \ 1470 do { \ 1471 u32 reg_val = XGMAC_DMA_IOREAD((_channel), _reg); \ 1472 SET_BITS(reg_val, \ 1473 _reg##_##_field##_INDEX, \ 1474 _reg##_##_field##_WIDTH, (_val)); \ 1475 XGMAC_DMA_IOWRITE((_channel), _reg, reg_val); \ 1476 } while (0) 1477 1478 /* Macros for building, reading or writing register values or bits 1479 * within the register values of XPCS registers. 1480 */ 1481 #define XPCS_GET_BITS(_var, _prefix, _field) \ 1482 GET_BITS((_var), \ 1483 _prefix##_##_field##_INDEX, \ 1484 _prefix##_##_field##_WIDTH) 1485 1486 #define XPCS_SET_BITS(_var, _prefix, _field, _val) \ 1487 SET_BITS((_var), \ 1488 _prefix##_##_field##_INDEX, \ 1489 _prefix##_##_field##_WIDTH, (_val)) 1490 1491 #define XPCS32_IOWRITE(_pdata, _off, _val) \ 1492 iowrite32(_val, (_pdata)->xpcs_regs + (_off)) 1493 1494 #define XPCS32_IOREAD(_pdata, _off) \ 1495 ioread32((_pdata)->xpcs_regs + (_off)) 1496 1497 #define XPCS16_IOWRITE(_pdata, _off, _val) \ 1498 iowrite16(_val, (_pdata)->xpcs_regs + (_off)) 1499 1500 #define XPCS16_IOREAD(_pdata, _off) \ 1501 ioread16((_pdata)->xpcs_regs + (_off)) 1502 1503 /* Macros for building, reading or writing register values or bits 1504 * within the register values of SerDes integration registers. 1505 */ 1506 #define XSIR_GET_BITS(_var, _prefix, _field) \ 1507 GET_BITS((_var), \ 1508 _prefix##_##_field##_INDEX, \ 1509 _prefix##_##_field##_WIDTH) 1510 1511 #define XSIR_SET_BITS(_var, _prefix, _field, _val) \ 1512 SET_BITS((_var), \ 1513 _prefix##_##_field##_INDEX, \ 1514 _prefix##_##_field##_WIDTH, (_val)) 1515 1516 #define XSIR0_IOREAD(_pdata, _reg) \ 1517 ioread16((_pdata)->sir0_regs + _reg) 1518 1519 #define XSIR0_IOREAD_BITS(_pdata, _reg, _field) \ 1520 GET_BITS(XSIR0_IOREAD((_pdata), _reg), \ 1521 _reg##_##_field##_INDEX, \ 1522 _reg##_##_field##_WIDTH) 1523 1524 #define XSIR0_IOWRITE(_pdata, _reg, _val) \ 1525 iowrite16((_val), (_pdata)->sir0_regs + _reg) 1526 1527 #define XSIR0_IOWRITE_BITS(_pdata, _reg, _field, _val) \ 1528 do { \ 1529 u16 reg_val = XSIR0_IOREAD((_pdata), _reg); \ 1530 SET_BITS(reg_val, \ 1531 _reg##_##_field##_INDEX, \ 1532 _reg##_##_field##_WIDTH, (_val)); \ 1533 XSIR0_IOWRITE((_pdata), _reg, reg_val); \ 1534 } while (0) 1535 1536 #define XSIR1_IOREAD(_pdata, _reg) \ 1537 ioread16((_pdata)->sir1_regs + _reg) 1538 1539 #define XSIR1_IOREAD_BITS(_pdata, _reg, _field) \ 1540 GET_BITS(XSIR1_IOREAD((_pdata), _reg), \ 1541 _reg##_##_field##_INDEX, \ 1542 _reg##_##_field##_WIDTH) 1543 1544 #define XSIR1_IOWRITE(_pdata, _reg, _val) \ 1545 iowrite16((_val), (_pdata)->sir1_regs + _reg) 1546 1547 #define XSIR1_IOWRITE_BITS(_pdata, _reg, _field, _val) \ 1548 do { \ 1549 u16 reg_val = XSIR1_IOREAD((_pdata), _reg); \ 1550 SET_BITS(reg_val, \ 1551 _reg##_##_field##_INDEX, \ 1552 _reg##_##_field##_WIDTH, (_val)); \ 1553 XSIR1_IOWRITE((_pdata), _reg, reg_val); \ 1554 } while (0) 1555 1556 /* Macros for building, reading or writing register values or bits 1557 * within the register values of SerDes RxTx registers. 1558 */ 1559 #define XRXTX_IOREAD(_pdata, _reg) \ 1560 ioread16((_pdata)->rxtx_regs + _reg) 1561 1562 #define XRXTX_IOREAD_BITS(_pdata, _reg, _field) \ 1563 GET_BITS(XRXTX_IOREAD((_pdata), _reg), \ 1564 _reg##_##_field##_INDEX, \ 1565 _reg##_##_field##_WIDTH) 1566 1567 #define XRXTX_IOWRITE(_pdata, _reg, _val) \ 1568 iowrite16((_val), (_pdata)->rxtx_regs + _reg) 1569 1570 #define XRXTX_IOWRITE_BITS(_pdata, _reg, _field, _val) \ 1571 do { \ 1572 u16 reg_val = XRXTX_IOREAD((_pdata), _reg); \ 1573 SET_BITS(reg_val, \ 1574 _reg##_##_field##_INDEX, \ 1575 _reg##_##_field##_WIDTH, (_val)); \ 1576 XRXTX_IOWRITE((_pdata), _reg, reg_val); \ 1577 } while (0) 1578 1579 /* Macros for building, reading or writing register values or bits 1580 * within the register values of MAC Control registers. 1581 */ 1582 #define XP_GET_BITS(_var, _prefix, _field) \ 1583 GET_BITS((_var), \ 1584 _prefix##_##_field##_INDEX, \ 1585 _prefix##_##_field##_WIDTH) 1586 1587 #define XP_SET_BITS(_var, _prefix, _field, _val) \ 1588 SET_BITS((_var), \ 1589 _prefix##_##_field##_INDEX, \ 1590 _prefix##_##_field##_WIDTH, (_val)) 1591 1592 #define XP_IOREAD(_pdata, _reg) \ 1593 ioread32((_pdata)->xprop_regs + (_reg)) 1594 1595 #define XP_IOREAD_BITS(_pdata, _reg, _field) \ 1596 GET_BITS(XP_IOREAD((_pdata), (_reg)), \ 1597 _reg##_##_field##_INDEX, \ 1598 _reg##_##_field##_WIDTH) 1599 1600 #define XP_IOWRITE(_pdata, _reg, _val) \ 1601 iowrite32((_val), (_pdata)->xprop_regs + (_reg)) 1602 1603 #define XP_IOWRITE_BITS(_pdata, _reg, _field, _val) \ 1604 do { \ 1605 u32 reg_val = XP_IOREAD((_pdata), (_reg)); \ 1606 SET_BITS(reg_val, \ 1607 _reg##_##_field##_INDEX, \ 1608 _reg##_##_field##_WIDTH, (_val)); \ 1609 XP_IOWRITE((_pdata), (_reg), reg_val); \ 1610 } while (0) 1611 1612 /* Macros for building, reading or writing register values or bits 1613 * within the register values of I2C Control registers. 1614 */ 1615 #define XI2C_GET_BITS(_var, _prefix, _field) \ 1616 GET_BITS((_var), \ 1617 _prefix##_##_field##_INDEX, \ 1618 _prefix##_##_field##_WIDTH) 1619 1620 #define XI2C_SET_BITS(_var, _prefix, _field, _val) \ 1621 SET_BITS((_var), \ 1622 _prefix##_##_field##_INDEX, \ 1623 _prefix##_##_field##_WIDTH, (_val)) 1624 1625 #define XI2C_IOREAD(_pdata, _reg) \ 1626 ioread32((_pdata)->xi2c_regs + (_reg)) 1627 1628 #define XI2C_IOREAD_BITS(_pdata, _reg, _field) \ 1629 GET_BITS(XI2C_IOREAD((_pdata), (_reg)), \ 1630 _reg##_##_field##_INDEX, \ 1631 _reg##_##_field##_WIDTH) 1632 1633 #define XI2C_IOWRITE(_pdata, _reg, _val) \ 1634 iowrite32((_val), (_pdata)->xi2c_regs + (_reg)) 1635 1636 #define XI2C_IOWRITE_BITS(_pdata, _reg, _field, _val) \ 1637 do { \ 1638 u32 reg_val = XI2C_IOREAD((_pdata), (_reg)); \ 1639 SET_BITS(reg_val, \ 1640 _reg##_##_field##_INDEX, \ 1641 _reg##_##_field##_WIDTH, (_val)); \ 1642 XI2C_IOWRITE((_pdata), (_reg), reg_val); \ 1643 } while (0) 1644 1645 /* Macros for building, reading or writing register values or bits 1646 * using MDIO. Different from above because of the use of standardized 1647 * Linux include values. No shifting is performed with the bit 1648 * operations, everything works on mask values. 1649 */ 1650 #define XMDIO_READ(_pdata, _mmd, _reg) \ 1651 ((_pdata)->hw_if.read_mmd_regs((_pdata), 0, \ 1652 MII_ADDR_C45 | (_mmd << 16) | ((_reg) & 0xffff))) 1653 1654 #define XMDIO_READ_BITS(_pdata, _mmd, _reg, _mask) \ 1655 (XMDIO_READ((_pdata), _mmd, _reg) & _mask) 1656 1657 #define XMDIO_WRITE(_pdata, _mmd, _reg, _val) \ 1658 ((_pdata)->hw_if.write_mmd_regs((_pdata), 0, \ 1659 MII_ADDR_C45 | (_mmd << 16) | ((_reg) & 0xffff), (_val))) 1660 1661 #define XMDIO_WRITE_BITS(_pdata, _mmd, _reg, _mask, _val) \ 1662 do { \ 1663 u32 mmd_val = XMDIO_READ((_pdata), _mmd, _reg); \ 1664 mmd_val &= ~_mask; \ 1665 mmd_val |= (_val); \ 1666 XMDIO_WRITE((_pdata), _mmd, _reg, mmd_val); \ 1667 } while (0) 1668 1669 #endif 1670