1 /* 2 * AMD 10Gb Ethernet driver 3 * 4 * This file is available to you under your choice of the following two 5 * licenses: 6 * 7 * License 1: GPLv2 8 * 9 * Copyright (c) 2014 Advanced Micro Devices, Inc. 10 * 11 * This file is free software; you may copy, redistribute and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation, either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program. If not, see <http://www.gnu.org/licenses/>. 23 * 24 * This file incorporates work covered by the following copyright and 25 * permission notice: 26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 28 * Inc. unless otherwise expressly agreed to in writing between Synopsys 29 * and you. 30 * 31 * The Software IS NOT an item of Licensed Software or Licensed Product 32 * under any End User Software License Agreement or Agreement for Licensed 33 * Product with Synopsys or any supplement thereto. Permission is hereby 34 * granted, free of charge, to any person obtaining a copy of this software 35 * annotated with this license and the Software, to deal in the Software 36 * without restriction, including without limitation the rights to use, 37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 38 * of the Software, and to permit persons to whom the Software is furnished 39 * to do so, subject to the following conditions: 40 * 41 * The above copyright notice and this permission notice shall be included 42 * in all copies or substantial portions of the Software. 43 * 44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 54 * THE POSSIBILITY OF SUCH DAMAGE. 55 * 56 * 57 * License 2: Modified BSD 58 * 59 * Copyright (c) 2014 Advanced Micro Devices, Inc. 60 * All rights reserved. 61 * 62 * Redistribution and use in source and binary forms, with or without 63 * modification, are permitted provided that the following conditions are met: 64 * * Redistributions of source code must retain the above copyright 65 * notice, this list of conditions and the following disclaimer. 66 * * Redistributions in binary form must reproduce the above copyright 67 * notice, this list of conditions and the following disclaimer in the 68 * documentation and/or other materials provided with the distribution. 69 * * Neither the name of Advanced Micro Devices, Inc. nor the 70 * names of its contributors may be used to endorse or promote products 71 * derived from this software without specific prior written permission. 72 * 73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY 77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 83 * 84 * This file incorporates work covered by the following copyright and 85 * permission notice: 86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 88 * Inc. unless otherwise expressly agreed to in writing between Synopsys 89 * and you. 90 * 91 * The Software IS NOT an item of Licensed Software or Licensed Product 92 * under any End User Software License Agreement or Agreement for Licensed 93 * Product with Synopsys or any supplement thereto. Permission is hereby 94 * granted, free of charge, to any person obtaining a copy of this software 95 * annotated with this license and the Software, to deal in the Software 96 * without restriction, including without limitation the rights to use, 97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 98 * of the Software, and to permit persons to whom the Software is furnished 99 * to do so, subject to the following conditions: 100 * 101 * The above copyright notice and this permission notice shall be included 102 * in all copies or substantial portions of the Software. 103 * 104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 114 * THE POSSIBILITY OF SUCH DAMAGE. 115 */ 116 117 #ifndef __XGBE_COMMON_H__ 118 #define __XGBE_COMMON_H__ 119 120 /* DMA register offsets */ 121 #define DMA_MR 0x3000 122 #define DMA_SBMR 0x3004 123 #define DMA_ISR 0x3008 124 #define DMA_AXIARCR 0x3010 125 #define DMA_AXIAWCR 0x3018 126 #define DMA_DSR0 0x3020 127 #define DMA_DSR1 0x3024 128 #define DMA_DSR2 0x3028 129 #define DMA_DSR3 0x302c 130 #define DMA_DSR4 0x3030 131 132 /* DMA register entry bit positions and sizes */ 133 #define DMA_AXIARCR_DRC_INDEX 0 134 #define DMA_AXIARCR_DRC_WIDTH 4 135 #define DMA_AXIARCR_DRD_INDEX 4 136 #define DMA_AXIARCR_DRD_WIDTH 2 137 #define DMA_AXIARCR_TEC_INDEX 8 138 #define DMA_AXIARCR_TEC_WIDTH 4 139 #define DMA_AXIARCR_TED_INDEX 12 140 #define DMA_AXIARCR_TED_WIDTH 2 141 #define DMA_AXIARCR_THC_INDEX 16 142 #define DMA_AXIARCR_THC_WIDTH 4 143 #define DMA_AXIARCR_THD_INDEX 20 144 #define DMA_AXIARCR_THD_WIDTH 2 145 #define DMA_AXIAWCR_DWC_INDEX 0 146 #define DMA_AXIAWCR_DWC_WIDTH 4 147 #define DMA_AXIAWCR_DWD_INDEX 4 148 #define DMA_AXIAWCR_DWD_WIDTH 2 149 #define DMA_AXIAWCR_RPC_INDEX 8 150 #define DMA_AXIAWCR_RPC_WIDTH 4 151 #define DMA_AXIAWCR_RPD_INDEX 12 152 #define DMA_AXIAWCR_RPD_WIDTH 2 153 #define DMA_AXIAWCR_RHC_INDEX 16 154 #define DMA_AXIAWCR_RHC_WIDTH 4 155 #define DMA_AXIAWCR_RHD_INDEX 20 156 #define DMA_AXIAWCR_RHD_WIDTH 2 157 #define DMA_AXIAWCR_TDC_INDEX 24 158 #define DMA_AXIAWCR_TDC_WIDTH 4 159 #define DMA_AXIAWCR_TDD_INDEX 28 160 #define DMA_AXIAWCR_TDD_WIDTH 2 161 #define DMA_DSR0_RPS_INDEX 8 162 #define DMA_DSR0_RPS_WIDTH 4 163 #define DMA_DSR0_TPS_INDEX 12 164 #define DMA_DSR0_TPS_WIDTH 4 165 #define DMA_ISR_MACIS_INDEX 17 166 #define DMA_ISR_MACIS_WIDTH 1 167 #define DMA_ISR_MTLIS_INDEX 16 168 #define DMA_ISR_MTLIS_WIDTH 1 169 #define DMA_MR_SWR_INDEX 0 170 #define DMA_MR_SWR_WIDTH 1 171 #define DMA_SBMR_EAME_INDEX 11 172 #define DMA_SBMR_EAME_WIDTH 1 173 #define DMA_SBMR_BLEN_256_INDEX 7 174 #define DMA_SBMR_BLEN_256_WIDTH 1 175 #define DMA_SBMR_UNDEF_INDEX 0 176 #define DMA_SBMR_UNDEF_WIDTH 1 177 178 /* DMA channel register offsets 179 * Multiple channels can be active. The first channel has registers 180 * that begin at 0x3100. Each subsequent channel has registers that 181 * are accessed using an offset of 0x80 from the previous channel. 182 */ 183 #define DMA_CH_BASE 0x3100 184 #define DMA_CH_INC 0x80 185 186 #define DMA_CH_CR 0x00 187 #define DMA_CH_TCR 0x04 188 #define DMA_CH_RCR 0x08 189 #define DMA_CH_TDLR_HI 0x10 190 #define DMA_CH_TDLR_LO 0x14 191 #define DMA_CH_RDLR_HI 0x18 192 #define DMA_CH_RDLR_LO 0x1c 193 #define DMA_CH_TDTR_LO 0x24 194 #define DMA_CH_RDTR_LO 0x2c 195 #define DMA_CH_TDRLR 0x30 196 #define DMA_CH_RDRLR 0x34 197 #define DMA_CH_IER 0x38 198 #define DMA_CH_RIWT 0x3c 199 #define DMA_CH_CATDR_LO 0x44 200 #define DMA_CH_CARDR_LO 0x4c 201 #define DMA_CH_CATBR_HI 0x50 202 #define DMA_CH_CATBR_LO 0x54 203 #define DMA_CH_CARBR_HI 0x58 204 #define DMA_CH_CARBR_LO 0x5c 205 #define DMA_CH_SR 0x60 206 207 /* DMA channel register entry bit positions and sizes */ 208 #define DMA_CH_CR_PBLX8_INDEX 16 209 #define DMA_CH_CR_PBLX8_WIDTH 1 210 #define DMA_CH_IER_AIE_INDEX 15 211 #define DMA_CH_IER_AIE_WIDTH 1 212 #define DMA_CH_IER_FBEE_INDEX 12 213 #define DMA_CH_IER_FBEE_WIDTH 1 214 #define DMA_CH_IER_NIE_INDEX 16 215 #define DMA_CH_IER_NIE_WIDTH 1 216 #define DMA_CH_IER_RBUE_INDEX 7 217 #define DMA_CH_IER_RBUE_WIDTH 1 218 #define DMA_CH_IER_RIE_INDEX 6 219 #define DMA_CH_IER_RIE_WIDTH 1 220 #define DMA_CH_IER_RSE_INDEX 8 221 #define DMA_CH_IER_RSE_WIDTH 1 222 #define DMA_CH_IER_TBUE_INDEX 2 223 #define DMA_CH_IER_TBUE_WIDTH 1 224 #define DMA_CH_IER_TIE_INDEX 0 225 #define DMA_CH_IER_TIE_WIDTH 1 226 #define DMA_CH_IER_TXSE_INDEX 1 227 #define DMA_CH_IER_TXSE_WIDTH 1 228 #define DMA_CH_RCR_PBL_INDEX 16 229 #define DMA_CH_RCR_PBL_WIDTH 6 230 #define DMA_CH_RCR_RBSZ_INDEX 1 231 #define DMA_CH_RCR_RBSZ_WIDTH 14 232 #define DMA_CH_RCR_SR_INDEX 0 233 #define DMA_CH_RCR_SR_WIDTH 1 234 #define DMA_CH_RIWT_RWT_INDEX 0 235 #define DMA_CH_RIWT_RWT_WIDTH 8 236 #define DMA_CH_SR_FBE_INDEX 12 237 #define DMA_CH_SR_FBE_WIDTH 1 238 #define DMA_CH_SR_RBU_INDEX 7 239 #define DMA_CH_SR_RBU_WIDTH 1 240 #define DMA_CH_SR_RI_INDEX 6 241 #define DMA_CH_SR_RI_WIDTH 1 242 #define DMA_CH_SR_RPS_INDEX 8 243 #define DMA_CH_SR_RPS_WIDTH 1 244 #define DMA_CH_SR_TBU_INDEX 2 245 #define DMA_CH_SR_TBU_WIDTH 1 246 #define DMA_CH_SR_TI_INDEX 0 247 #define DMA_CH_SR_TI_WIDTH 1 248 #define DMA_CH_SR_TPS_INDEX 1 249 #define DMA_CH_SR_TPS_WIDTH 1 250 #define DMA_CH_TCR_OSP_INDEX 4 251 #define DMA_CH_TCR_OSP_WIDTH 1 252 #define DMA_CH_TCR_PBL_INDEX 16 253 #define DMA_CH_TCR_PBL_WIDTH 6 254 #define DMA_CH_TCR_ST_INDEX 0 255 #define DMA_CH_TCR_ST_WIDTH 1 256 #define DMA_CH_TCR_TSE_INDEX 12 257 #define DMA_CH_TCR_TSE_WIDTH 1 258 259 /* DMA channel register values */ 260 #define DMA_OSP_DISABLE 0x00 261 #define DMA_OSP_ENABLE 0x01 262 #define DMA_PBL_1 1 263 #define DMA_PBL_2 2 264 #define DMA_PBL_4 4 265 #define DMA_PBL_8 8 266 #define DMA_PBL_16 16 267 #define DMA_PBL_32 32 268 #define DMA_PBL_64 64 /* 8 x 8 */ 269 #define DMA_PBL_128 128 /* 8 x 16 */ 270 #define DMA_PBL_256 256 /* 8 x 32 */ 271 #define DMA_PBL_X8_DISABLE 0x00 272 #define DMA_PBL_X8_ENABLE 0x01 273 274 275 /* MAC register offsets */ 276 #define MAC_TCR 0x0000 277 #define MAC_RCR 0x0004 278 #define MAC_PFR 0x0008 279 #define MAC_WTR 0x000c 280 #define MAC_HTR0 0x0010 281 #define MAC_VLANTR 0x0050 282 #define MAC_VLANHTR 0x0058 283 #define MAC_VLANIR 0x0060 284 #define MAC_IVLANIR 0x0064 285 #define MAC_RETMR 0x006c 286 #define MAC_Q0TFCR 0x0070 287 #define MAC_RFCR 0x0090 288 #define MAC_RQC0R 0x00a0 289 #define MAC_RQC1R 0x00a4 290 #define MAC_RQC2R 0x00a8 291 #define MAC_RQC3R 0x00ac 292 #define MAC_ISR 0x00b0 293 #define MAC_IER 0x00b4 294 #define MAC_RTSR 0x00b8 295 #define MAC_PMTCSR 0x00c0 296 #define MAC_RWKPFR 0x00c4 297 #define MAC_LPICSR 0x00d0 298 #define MAC_LPITCR 0x00d4 299 #define MAC_VR 0x0110 300 #define MAC_DR 0x0114 301 #define MAC_HWF0R 0x011c 302 #define MAC_HWF1R 0x0120 303 #define MAC_HWF2R 0x0124 304 #define MAC_GPIOCR 0x0278 305 #define MAC_GPIOSR 0x027c 306 #define MAC_MACA0HR 0x0300 307 #define MAC_MACA0LR 0x0304 308 #define MAC_MACA1HR 0x0308 309 #define MAC_MACA1LR 0x030c 310 #define MAC_TSCR 0x0d00 311 #define MAC_SSIR 0x0d04 312 #define MAC_STSR 0x0d08 313 #define MAC_STNR 0x0d0c 314 #define MAC_STSUR 0x0d10 315 #define MAC_STNUR 0x0d14 316 #define MAC_TSAR 0x0d18 317 #define MAC_TSSR 0x0d20 318 #define MAC_TXSNR 0x0d30 319 #define MAC_TXSSR 0x0d34 320 321 #define MAC_QTFCR_INC 4 322 #define MAC_MACA_INC 4 323 #define MAC_HTR_INC 4 324 325 #define MAC_RQC2_INC 4 326 #define MAC_RQC2_Q_PER_REG 4 327 328 /* MAC register entry bit positions and sizes */ 329 #define MAC_HWF0R_ADDMACADRSEL_INDEX 18 330 #define MAC_HWF0R_ADDMACADRSEL_WIDTH 5 331 #define MAC_HWF0R_ARPOFFSEL_INDEX 9 332 #define MAC_HWF0R_ARPOFFSEL_WIDTH 1 333 #define MAC_HWF0R_EEESEL_INDEX 13 334 #define MAC_HWF0R_EEESEL_WIDTH 1 335 #define MAC_HWF0R_GMIISEL_INDEX 1 336 #define MAC_HWF0R_GMIISEL_WIDTH 1 337 #define MAC_HWF0R_MGKSEL_INDEX 7 338 #define MAC_HWF0R_MGKSEL_WIDTH 1 339 #define MAC_HWF0R_MMCSEL_INDEX 8 340 #define MAC_HWF0R_MMCSEL_WIDTH 1 341 #define MAC_HWF0R_RWKSEL_INDEX 6 342 #define MAC_HWF0R_RWKSEL_WIDTH 1 343 #define MAC_HWF0R_RXCOESEL_INDEX 16 344 #define MAC_HWF0R_RXCOESEL_WIDTH 1 345 #define MAC_HWF0R_SAVLANINS_INDEX 27 346 #define MAC_HWF0R_SAVLANINS_WIDTH 1 347 #define MAC_HWF0R_SMASEL_INDEX 5 348 #define MAC_HWF0R_SMASEL_WIDTH 1 349 #define MAC_HWF0R_TSSEL_INDEX 12 350 #define MAC_HWF0R_TSSEL_WIDTH 1 351 #define MAC_HWF0R_TSSTSSEL_INDEX 25 352 #define MAC_HWF0R_TSSTSSEL_WIDTH 2 353 #define MAC_HWF0R_TXCOESEL_INDEX 14 354 #define MAC_HWF0R_TXCOESEL_WIDTH 1 355 #define MAC_HWF0R_VLHASH_INDEX 4 356 #define MAC_HWF0R_VLHASH_WIDTH 1 357 #define MAC_HWF1R_ADVTHWORD_INDEX 13 358 #define MAC_HWF1R_ADVTHWORD_WIDTH 1 359 #define MAC_HWF1R_DBGMEMA_INDEX 19 360 #define MAC_HWF1R_DBGMEMA_WIDTH 1 361 #define MAC_HWF1R_DCBEN_INDEX 16 362 #define MAC_HWF1R_DCBEN_WIDTH 1 363 #define MAC_HWF1R_HASHTBLSZ_INDEX 24 364 #define MAC_HWF1R_HASHTBLSZ_WIDTH 3 365 #define MAC_HWF1R_L3L4FNUM_INDEX 27 366 #define MAC_HWF1R_L3L4FNUM_WIDTH 4 367 #define MAC_HWF1R_NUMTC_INDEX 21 368 #define MAC_HWF1R_NUMTC_WIDTH 3 369 #define MAC_HWF1R_RSSEN_INDEX 20 370 #define MAC_HWF1R_RSSEN_WIDTH 1 371 #define MAC_HWF1R_RXFIFOSIZE_INDEX 0 372 #define MAC_HWF1R_RXFIFOSIZE_WIDTH 5 373 #define MAC_HWF1R_SPHEN_INDEX 17 374 #define MAC_HWF1R_SPHEN_WIDTH 1 375 #define MAC_HWF1R_TSOEN_INDEX 18 376 #define MAC_HWF1R_TSOEN_WIDTH 1 377 #define MAC_HWF1R_TXFIFOSIZE_INDEX 6 378 #define MAC_HWF1R_TXFIFOSIZE_WIDTH 5 379 #define MAC_HWF2R_AUXSNAPNUM_INDEX 28 380 #define MAC_HWF2R_AUXSNAPNUM_WIDTH 3 381 #define MAC_HWF2R_PPSOUTNUM_INDEX 24 382 #define MAC_HWF2R_PPSOUTNUM_WIDTH 3 383 #define MAC_HWF2R_RXCHCNT_INDEX 12 384 #define MAC_HWF2R_RXCHCNT_WIDTH 4 385 #define MAC_HWF2R_RXQCNT_INDEX 0 386 #define MAC_HWF2R_RXQCNT_WIDTH 4 387 #define MAC_HWF2R_TXCHCNT_INDEX 18 388 #define MAC_HWF2R_TXCHCNT_WIDTH 4 389 #define MAC_HWF2R_TXQCNT_INDEX 6 390 #define MAC_HWF2R_TXQCNT_WIDTH 4 391 #define MAC_IER_TSIE_INDEX 12 392 #define MAC_IER_TSIE_WIDTH 1 393 #define MAC_ISR_MMCRXIS_INDEX 9 394 #define MAC_ISR_MMCRXIS_WIDTH 1 395 #define MAC_ISR_MMCTXIS_INDEX 10 396 #define MAC_ISR_MMCTXIS_WIDTH 1 397 #define MAC_ISR_PMTIS_INDEX 4 398 #define MAC_ISR_PMTIS_WIDTH 1 399 #define MAC_ISR_TSIS_INDEX 12 400 #define MAC_ISR_TSIS_WIDTH 1 401 #define MAC_MACA1HR_AE_INDEX 31 402 #define MAC_MACA1HR_AE_WIDTH 1 403 #define MAC_PFR_HMC_INDEX 2 404 #define MAC_PFR_HMC_WIDTH 1 405 #define MAC_PFR_HPF_INDEX 10 406 #define MAC_PFR_HPF_WIDTH 1 407 #define MAC_PFR_HUC_INDEX 1 408 #define MAC_PFR_HUC_WIDTH 1 409 #define MAC_PFR_PM_INDEX 4 410 #define MAC_PFR_PM_WIDTH 1 411 #define MAC_PFR_PR_INDEX 0 412 #define MAC_PFR_PR_WIDTH 1 413 #define MAC_PFR_VTFE_INDEX 16 414 #define MAC_PFR_VTFE_WIDTH 1 415 #define MAC_PMTCSR_MGKPKTEN_INDEX 1 416 #define MAC_PMTCSR_MGKPKTEN_WIDTH 1 417 #define MAC_PMTCSR_PWRDWN_INDEX 0 418 #define MAC_PMTCSR_PWRDWN_WIDTH 1 419 #define MAC_PMTCSR_RWKFILTRST_INDEX 31 420 #define MAC_PMTCSR_RWKFILTRST_WIDTH 1 421 #define MAC_PMTCSR_RWKPKTEN_INDEX 2 422 #define MAC_PMTCSR_RWKPKTEN_WIDTH 1 423 #define MAC_Q0TFCR_PT_INDEX 16 424 #define MAC_Q0TFCR_PT_WIDTH 16 425 #define MAC_Q0TFCR_TFE_INDEX 1 426 #define MAC_Q0TFCR_TFE_WIDTH 1 427 #define MAC_RCR_ACS_INDEX 1 428 #define MAC_RCR_ACS_WIDTH 1 429 #define MAC_RCR_CST_INDEX 2 430 #define MAC_RCR_CST_WIDTH 1 431 #define MAC_RCR_DCRCC_INDEX 3 432 #define MAC_RCR_DCRCC_WIDTH 1 433 #define MAC_RCR_IPC_INDEX 9 434 #define MAC_RCR_IPC_WIDTH 1 435 #define MAC_RCR_JE_INDEX 8 436 #define MAC_RCR_JE_WIDTH 1 437 #define MAC_RCR_LM_INDEX 10 438 #define MAC_RCR_LM_WIDTH 1 439 #define MAC_RCR_RE_INDEX 0 440 #define MAC_RCR_RE_WIDTH 1 441 #define MAC_RFCR_PFCE_INDEX 8 442 #define MAC_RFCR_PFCE_WIDTH 1 443 #define MAC_RFCR_RFE_INDEX 0 444 #define MAC_RFCR_RFE_WIDTH 1 445 #define MAC_RFCR_UP_INDEX 1 446 #define MAC_RFCR_UP_WIDTH 1 447 #define MAC_RQC0R_RXQ0EN_INDEX 0 448 #define MAC_RQC0R_RXQ0EN_WIDTH 2 449 #define MAC_SSIR_SNSINC_INDEX 8 450 #define MAC_SSIR_SNSINC_WIDTH 8 451 #define MAC_SSIR_SSINC_INDEX 16 452 #define MAC_SSIR_SSINC_WIDTH 8 453 #define MAC_TCR_SS_INDEX 29 454 #define MAC_TCR_SS_WIDTH 2 455 #define MAC_TCR_TE_INDEX 0 456 #define MAC_TCR_TE_WIDTH 1 457 #define MAC_TSCR_AV8021ASMEN_INDEX 28 458 #define MAC_TSCR_AV8021ASMEN_WIDTH 1 459 #define MAC_TSCR_SNAPTYPSEL_INDEX 16 460 #define MAC_TSCR_SNAPTYPSEL_WIDTH 2 461 #define MAC_TSCR_TSADDREG_INDEX 5 462 #define MAC_TSCR_TSADDREG_WIDTH 1 463 #define MAC_TSCR_TSCFUPDT_INDEX 1 464 #define MAC_TSCR_TSCFUPDT_WIDTH 1 465 #define MAC_TSCR_TSCTRLSSR_INDEX 9 466 #define MAC_TSCR_TSCTRLSSR_WIDTH 1 467 #define MAC_TSCR_TSENA_INDEX 0 468 #define MAC_TSCR_TSENA_WIDTH 1 469 #define MAC_TSCR_TSENALL_INDEX 8 470 #define MAC_TSCR_TSENALL_WIDTH 1 471 #define MAC_TSCR_TSEVNTENA_INDEX 14 472 #define MAC_TSCR_TSEVNTENA_WIDTH 1 473 #define MAC_TSCR_TSINIT_INDEX 2 474 #define MAC_TSCR_TSINIT_WIDTH 1 475 #define MAC_TSCR_TSIPENA_INDEX 11 476 #define MAC_TSCR_TSIPENA_WIDTH 1 477 #define MAC_TSCR_TSIPV4ENA_INDEX 13 478 #define MAC_TSCR_TSIPV4ENA_WIDTH 1 479 #define MAC_TSCR_TSIPV6ENA_INDEX 12 480 #define MAC_TSCR_TSIPV6ENA_WIDTH 1 481 #define MAC_TSCR_TSMSTRENA_INDEX 15 482 #define MAC_TSCR_TSMSTRENA_WIDTH 1 483 #define MAC_TSCR_TSVER2ENA_INDEX 10 484 #define MAC_TSCR_TSVER2ENA_WIDTH 1 485 #define MAC_TSCR_TXTSSTSM_INDEX 24 486 #define MAC_TSCR_TXTSSTSM_WIDTH 1 487 #define MAC_TSSR_TXTSC_INDEX 15 488 #define MAC_TSSR_TXTSC_WIDTH 1 489 #define MAC_TXSNR_TXTSSTSMIS_INDEX 31 490 #define MAC_TXSNR_TXTSSTSMIS_WIDTH 1 491 #define MAC_VLANHTR_VLHT_INDEX 0 492 #define MAC_VLANHTR_VLHT_WIDTH 16 493 #define MAC_VLANIR_VLTI_INDEX 20 494 #define MAC_VLANIR_VLTI_WIDTH 1 495 #define MAC_VLANIR_CSVL_INDEX 19 496 #define MAC_VLANIR_CSVL_WIDTH 1 497 #define MAC_VLANTR_DOVLTC_INDEX 20 498 #define MAC_VLANTR_DOVLTC_WIDTH 1 499 #define MAC_VLANTR_ERSVLM_INDEX 19 500 #define MAC_VLANTR_ERSVLM_WIDTH 1 501 #define MAC_VLANTR_ESVL_INDEX 18 502 #define MAC_VLANTR_ESVL_WIDTH 1 503 #define MAC_VLANTR_ETV_INDEX 16 504 #define MAC_VLANTR_ETV_WIDTH 1 505 #define MAC_VLANTR_EVLS_INDEX 21 506 #define MAC_VLANTR_EVLS_WIDTH 2 507 #define MAC_VLANTR_EVLRXS_INDEX 24 508 #define MAC_VLANTR_EVLRXS_WIDTH 1 509 #define MAC_VLANTR_VL_INDEX 0 510 #define MAC_VLANTR_VL_WIDTH 16 511 #define MAC_VLANTR_VTHM_INDEX 25 512 #define MAC_VLANTR_VTHM_WIDTH 1 513 #define MAC_VLANTR_VTIM_INDEX 17 514 #define MAC_VLANTR_VTIM_WIDTH 1 515 #define MAC_VR_DEVID_INDEX 8 516 #define MAC_VR_DEVID_WIDTH 8 517 #define MAC_VR_SNPSVER_INDEX 0 518 #define MAC_VR_SNPSVER_WIDTH 8 519 #define MAC_VR_USERVER_INDEX 16 520 #define MAC_VR_USERVER_WIDTH 8 521 522 /* MMC register offsets */ 523 #define MMC_CR 0x0800 524 #define MMC_RISR 0x0804 525 #define MMC_TISR 0x0808 526 #define MMC_RIER 0x080c 527 #define MMC_TIER 0x0810 528 #define MMC_TXOCTETCOUNT_GB_LO 0x0814 529 #define MMC_TXOCTETCOUNT_GB_HI 0x0818 530 #define MMC_TXFRAMECOUNT_GB_LO 0x081c 531 #define MMC_TXFRAMECOUNT_GB_HI 0x0820 532 #define MMC_TXBROADCASTFRAMES_G_LO 0x0824 533 #define MMC_TXBROADCASTFRAMES_G_HI 0x0828 534 #define MMC_TXMULTICASTFRAMES_G_LO 0x082c 535 #define MMC_TXMULTICASTFRAMES_G_HI 0x0830 536 #define MMC_TX64OCTETS_GB_LO 0x0834 537 #define MMC_TX64OCTETS_GB_HI 0x0838 538 #define MMC_TX65TO127OCTETS_GB_LO 0x083c 539 #define MMC_TX65TO127OCTETS_GB_HI 0x0840 540 #define MMC_TX128TO255OCTETS_GB_LO 0x0844 541 #define MMC_TX128TO255OCTETS_GB_HI 0x0848 542 #define MMC_TX256TO511OCTETS_GB_LO 0x084c 543 #define MMC_TX256TO511OCTETS_GB_HI 0x0850 544 #define MMC_TX512TO1023OCTETS_GB_LO 0x0854 545 #define MMC_TX512TO1023OCTETS_GB_HI 0x0858 546 #define MMC_TX1024TOMAXOCTETS_GB_LO 0x085c 547 #define MMC_TX1024TOMAXOCTETS_GB_HI 0x0860 548 #define MMC_TXUNICASTFRAMES_GB_LO 0x0864 549 #define MMC_TXUNICASTFRAMES_GB_HI 0x0868 550 #define MMC_TXMULTICASTFRAMES_GB_LO 0x086c 551 #define MMC_TXMULTICASTFRAMES_GB_HI 0x0870 552 #define MMC_TXBROADCASTFRAMES_GB_LO 0x0874 553 #define MMC_TXBROADCASTFRAMES_GB_HI 0x0878 554 #define MMC_TXUNDERFLOWERROR_LO 0x087c 555 #define MMC_TXUNDERFLOWERROR_HI 0x0880 556 #define MMC_TXOCTETCOUNT_G_LO 0x0884 557 #define MMC_TXOCTETCOUNT_G_HI 0x0888 558 #define MMC_TXFRAMECOUNT_G_LO 0x088c 559 #define MMC_TXFRAMECOUNT_G_HI 0x0890 560 #define MMC_TXPAUSEFRAMES_LO 0x0894 561 #define MMC_TXPAUSEFRAMES_HI 0x0898 562 #define MMC_TXVLANFRAMES_G_LO 0x089c 563 #define MMC_TXVLANFRAMES_G_HI 0x08a0 564 #define MMC_RXFRAMECOUNT_GB_LO 0x0900 565 #define MMC_RXFRAMECOUNT_GB_HI 0x0904 566 #define MMC_RXOCTETCOUNT_GB_LO 0x0908 567 #define MMC_RXOCTETCOUNT_GB_HI 0x090c 568 #define MMC_RXOCTETCOUNT_G_LO 0x0910 569 #define MMC_RXOCTETCOUNT_G_HI 0x0914 570 #define MMC_RXBROADCASTFRAMES_G_LO 0x0918 571 #define MMC_RXBROADCASTFRAMES_G_HI 0x091c 572 #define MMC_RXMULTICASTFRAMES_G_LO 0x0920 573 #define MMC_RXMULTICASTFRAMES_G_HI 0x0924 574 #define MMC_RXCRCERROR_LO 0x0928 575 #define MMC_RXCRCERROR_HI 0x092c 576 #define MMC_RXRUNTERROR 0x0930 577 #define MMC_RXJABBERERROR 0x0934 578 #define MMC_RXUNDERSIZE_G 0x0938 579 #define MMC_RXOVERSIZE_G 0x093c 580 #define MMC_RX64OCTETS_GB_LO 0x0940 581 #define MMC_RX64OCTETS_GB_HI 0x0944 582 #define MMC_RX65TO127OCTETS_GB_LO 0x0948 583 #define MMC_RX65TO127OCTETS_GB_HI 0x094c 584 #define MMC_RX128TO255OCTETS_GB_LO 0x0950 585 #define MMC_RX128TO255OCTETS_GB_HI 0x0954 586 #define MMC_RX256TO511OCTETS_GB_LO 0x0958 587 #define MMC_RX256TO511OCTETS_GB_HI 0x095c 588 #define MMC_RX512TO1023OCTETS_GB_LO 0x0960 589 #define MMC_RX512TO1023OCTETS_GB_HI 0x0964 590 #define MMC_RX1024TOMAXOCTETS_GB_LO 0x0968 591 #define MMC_RX1024TOMAXOCTETS_GB_HI 0x096c 592 #define MMC_RXUNICASTFRAMES_G_LO 0x0970 593 #define MMC_RXUNICASTFRAMES_G_HI 0x0974 594 #define MMC_RXLENGTHERROR_LO 0x0978 595 #define MMC_RXLENGTHERROR_HI 0x097c 596 #define MMC_RXOUTOFRANGETYPE_LO 0x0980 597 #define MMC_RXOUTOFRANGETYPE_HI 0x0984 598 #define MMC_RXPAUSEFRAMES_LO 0x0988 599 #define MMC_RXPAUSEFRAMES_HI 0x098c 600 #define MMC_RXFIFOOVERFLOW_LO 0x0990 601 #define MMC_RXFIFOOVERFLOW_HI 0x0994 602 #define MMC_RXVLANFRAMES_GB_LO 0x0998 603 #define MMC_RXVLANFRAMES_GB_HI 0x099c 604 #define MMC_RXWATCHDOGERROR 0x09a0 605 606 /* MMC register entry bit positions and sizes */ 607 #define MMC_CR_CR_INDEX 0 608 #define MMC_CR_CR_WIDTH 1 609 #define MMC_CR_CSR_INDEX 1 610 #define MMC_CR_CSR_WIDTH 1 611 #define MMC_CR_ROR_INDEX 2 612 #define MMC_CR_ROR_WIDTH 1 613 #define MMC_CR_MCF_INDEX 3 614 #define MMC_CR_MCF_WIDTH 1 615 #define MMC_CR_MCT_INDEX 4 616 #define MMC_CR_MCT_WIDTH 2 617 #define MMC_RIER_ALL_INTERRUPTS_INDEX 0 618 #define MMC_RIER_ALL_INTERRUPTS_WIDTH 23 619 #define MMC_RISR_RXFRAMECOUNT_GB_INDEX 0 620 #define MMC_RISR_RXFRAMECOUNT_GB_WIDTH 1 621 #define MMC_RISR_RXOCTETCOUNT_GB_INDEX 1 622 #define MMC_RISR_RXOCTETCOUNT_GB_WIDTH 1 623 #define MMC_RISR_RXOCTETCOUNT_G_INDEX 2 624 #define MMC_RISR_RXOCTETCOUNT_G_WIDTH 1 625 #define MMC_RISR_RXBROADCASTFRAMES_G_INDEX 3 626 #define MMC_RISR_RXBROADCASTFRAMES_G_WIDTH 1 627 #define MMC_RISR_RXMULTICASTFRAMES_G_INDEX 4 628 #define MMC_RISR_RXMULTICASTFRAMES_G_WIDTH 1 629 #define MMC_RISR_RXCRCERROR_INDEX 5 630 #define MMC_RISR_RXCRCERROR_WIDTH 1 631 #define MMC_RISR_RXRUNTERROR_INDEX 6 632 #define MMC_RISR_RXRUNTERROR_WIDTH 1 633 #define MMC_RISR_RXJABBERERROR_INDEX 7 634 #define MMC_RISR_RXJABBERERROR_WIDTH 1 635 #define MMC_RISR_RXUNDERSIZE_G_INDEX 8 636 #define MMC_RISR_RXUNDERSIZE_G_WIDTH 1 637 #define MMC_RISR_RXOVERSIZE_G_INDEX 9 638 #define MMC_RISR_RXOVERSIZE_G_WIDTH 1 639 #define MMC_RISR_RX64OCTETS_GB_INDEX 10 640 #define MMC_RISR_RX64OCTETS_GB_WIDTH 1 641 #define MMC_RISR_RX65TO127OCTETS_GB_INDEX 11 642 #define MMC_RISR_RX65TO127OCTETS_GB_WIDTH 1 643 #define MMC_RISR_RX128TO255OCTETS_GB_INDEX 12 644 #define MMC_RISR_RX128TO255OCTETS_GB_WIDTH 1 645 #define MMC_RISR_RX256TO511OCTETS_GB_INDEX 13 646 #define MMC_RISR_RX256TO511OCTETS_GB_WIDTH 1 647 #define MMC_RISR_RX512TO1023OCTETS_GB_INDEX 14 648 #define MMC_RISR_RX512TO1023OCTETS_GB_WIDTH 1 649 #define MMC_RISR_RX1024TOMAXOCTETS_GB_INDEX 15 650 #define MMC_RISR_RX1024TOMAXOCTETS_GB_WIDTH 1 651 #define MMC_RISR_RXUNICASTFRAMES_G_INDEX 16 652 #define MMC_RISR_RXUNICASTFRAMES_G_WIDTH 1 653 #define MMC_RISR_RXLENGTHERROR_INDEX 17 654 #define MMC_RISR_RXLENGTHERROR_WIDTH 1 655 #define MMC_RISR_RXOUTOFRANGETYPE_INDEX 18 656 #define MMC_RISR_RXOUTOFRANGETYPE_WIDTH 1 657 #define MMC_RISR_RXPAUSEFRAMES_INDEX 19 658 #define MMC_RISR_RXPAUSEFRAMES_WIDTH 1 659 #define MMC_RISR_RXFIFOOVERFLOW_INDEX 20 660 #define MMC_RISR_RXFIFOOVERFLOW_WIDTH 1 661 #define MMC_RISR_RXVLANFRAMES_GB_INDEX 21 662 #define MMC_RISR_RXVLANFRAMES_GB_WIDTH 1 663 #define MMC_RISR_RXWATCHDOGERROR_INDEX 22 664 #define MMC_RISR_RXWATCHDOGERROR_WIDTH 1 665 #define MMC_TIER_ALL_INTERRUPTS_INDEX 0 666 #define MMC_TIER_ALL_INTERRUPTS_WIDTH 18 667 #define MMC_TISR_TXOCTETCOUNT_GB_INDEX 0 668 #define MMC_TISR_TXOCTETCOUNT_GB_WIDTH 1 669 #define MMC_TISR_TXFRAMECOUNT_GB_INDEX 1 670 #define MMC_TISR_TXFRAMECOUNT_GB_WIDTH 1 671 #define MMC_TISR_TXBROADCASTFRAMES_G_INDEX 2 672 #define MMC_TISR_TXBROADCASTFRAMES_G_WIDTH 1 673 #define MMC_TISR_TXMULTICASTFRAMES_G_INDEX 3 674 #define MMC_TISR_TXMULTICASTFRAMES_G_WIDTH 1 675 #define MMC_TISR_TX64OCTETS_GB_INDEX 4 676 #define MMC_TISR_TX64OCTETS_GB_WIDTH 1 677 #define MMC_TISR_TX65TO127OCTETS_GB_INDEX 5 678 #define MMC_TISR_TX65TO127OCTETS_GB_WIDTH 1 679 #define MMC_TISR_TX128TO255OCTETS_GB_INDEX 6 680 #define MMC_TISR_TX128TO255OCTETS_GB_WIDTH 1 681 #define MMC_TISR_TX256TO511OCTETS_GB_INDEX 7 682 #define MMC_TISR_TX256TO511OCTETS_GB_WIDTH 1 683 #define MMC_TISR_TX512TO1023OCTETS_GB_INDEX 8 684 #define MMC_TISR_TX512TO1023OCTETS_GB_WIDTH 1 685 #define MMC_TISR_TX1024TOMAXOCTETS_GB_INDEX 9 686 #define MMC_TISR_TX1024TOMAXOCTETS_GB_WIDTH 1 687 #define MMC_TISR_TXUNICASTFRAMES_GB_INDEX 10 688 #define MMC_TISR_TXUNICASTFRAMES_GB_WIDTH 1 689 #define MMC_TISR_TXMULTICASTFRAMES_GB_INDEX 11 690 #define MMC_TISR_TXMULTICASTFRAMES_GB_WIDTH 1 691 #define MMC_TISR_TXBROADCASTFRAMES_GB_INDEX 12 692 #define MMC_TISR_TXBROADCASTFRAMES_GB_WIDTH 1 693 #define MMC_TISR_TXUNDERFLOWERROR_INDEX 13 694 #define MMC_TISR_TXUNDERFLOWERROR_WIDTH 1 695 #define MMC_TISR_TXOCTETCOUNT_G_INDEX 14 696 #define MMC_TISR_TXOCTETCOUNT_G_WIDTH 1 697 #define MMC_TISR_TXFRAMECOUNT_G_INDEX 15 698 #define MMC_TISR_TXFRAMECOUNT_G_WIDTH 1 699 #define MMC_TISR_TXPAUSEFRAMES_INDEX 16 700 #define MMC_TISR_TXPAUSEFRAMES_WIDTH 1 701 #define MMC_TISR_TXVLANFRAMES_G_INDEX 17 702 #define MMC_TISR_TXVLANFRAMES_G_WIDTH 1 703 704 /* MTL register offsets */ 705 #define MTL_OMR 0x1000 706 #define MTL_FDCR 0x1008 707 #define MTL_FDSR 0x100c 708 #define MTL_FDDR 0x1010 709 #define MTL_ISR 0x1020 710 #define MTL_RQDCM0R 0x1030 711 #define MTL_TCPM0R 0x1040 712 #define MTL_TCPM1R 0x1044 713 714 #define MTL_RQDCM_INC 4 715 #define MTL_RQDCM_Q_PER_REG 4 716 #define MTL_TCPM_INC 4 717 #define MTL_TCPM_TC_PER_REG 4 718 719 /* MTL register entry bit positions and sizes */ 720 #define MTL_OMR_ETSALG_INDEX 5 721 #define MTL_OMR_ETSALG_WIDTH 2 722 #define MTL_OMR_RAA_INDEX 2 723 #define MTL_OMR_RAA_WIDTH 1 724 725 /* MTL queue register offsets 726 * Multiple queues can be active. The first queue has registers 727 * that begin at 0x1100. Each subsequent queue has registers that 728 * are accessed using an offset of 0x80 from the previous queue. 729 */ 730 #define MTL_Q_BASE 0x1100 731 #define MTL_Q_INC 0x80 732 733 #define MTL_Q_TQOMR 0x00 734 #define MTL_Q_TQUR 0x04 735 #define MTL_Q_TQDR 0x08 736 #define MTL_Q_RQOMR 0x40 737 #define MTL_Q_RQMPOCR 0x44 738 #define MTL_Q_RQDR 0x4c 739 #define MTL_Q_IER 0x70 740 #define MTL_Q_ISR 0x74 741 742 /* MTL queue register entry bit positions and sizes */ 743 #define MTL_Q_RQOMR_EHFC_INDEX 7 744 #define MTL_Q_RQOMR_EHFC_WIDTH 1 745 #define MTL_Q_RQOMR_RFA_INDEX 8 746 #define MTL_Q_RQOMR_RFA_WIDTH 3 747 #define MTL_Q_RQOMR_RFD_INDEX 13 748 #define MTL_Q_RQOMR_RFD_WIDTH 3 749 #define MTL_Q_RQOMR_RQS_INDEX 16 750 #define MTL_Q_RQOMR_RQS_WIDTH 9 751 #define MTL_Q_RQOMR_RSF_INDEX 5 752 #define MTL_Q_RQOMR_RSF_WIDTH 1 753 #define MTL_Q_RQOMR_RTC_INDEX 0 754 #define MTL_Q_RQOMR_RTC_WIDTH 2 755 #define MTL_Q_TQOMR_FTQ_INDEX 0 756 #define MTL_Q_TQOMR_FTQ_WIDTH 1 757 #define MTL_Q_TQOMR_Q2TCMAP_INDEX 8 758 #define MTL_Q_TQOMR_Q2TCMAP_WIDTH 3 759 #define MTL_Q_TQOMR_TQS_INDEX 16 760 #define MTL_Q_TQOMR_TQS_WIDTH 10 761 #define MTL_Q_TQOMR_TSF_INDEX 1 762 #define MTL_Q_TQOMR_TSF_WIDTH 1 763 #define MTL_Q_TQOMR_TTC_INDEX 4 764 #define MTL_Q_TQOMR_TTC_WIDTH 3 765 #define MTL_Q_TQOMR_TXQEN_INDEX 2 766 #define MTL_Q_TQOMR_TXQEN_WIDTH 2 767 768 /* MTL queue register value */ 769 #define MTL_RSF_DISABLE 0x00 770 #define MTL_RSF_ENABLE 0x01 771 #define MTL_TSF_DISABLE 0x00 772 #define MTL_TSF_ENABLE 0x01 773 774 #define MTL_RX_THRESHOLD_64 0x00 775 #define MTL_RX_THRESHOLD_96 0x02 776 #define MTL_RX_THRESHOLD_128 0x03 777 #define MTL_TX_THRESHOLD_32 0x01 778 #define MTL_TX_THRESHOLD_64 0x00 779 #define MTL_TX_THRESHOLD_96 0x02 780 #define MTL_TX_THRESHOLD_128 0x03 781 #define MTL_TX_THRESHOLD_192 0x04 782 #define MTL_TX_THRESHOLD_256 0x05 783 #define MTL_TX_THRESHOLD_384 0x06 784 #define MTL_TX_THRESHOLD_512 0x07 785 786 #define MTL_ETSALG_WRR 0x00 787 #define MTL_ETSALG_WFQ 0x01 788 #define MTL_ETSALG_DWRR 0x02 789 #define MTL_RAA_SP 0x00 790 #define MTL_RAA_WSP 0x01 791 792 #define MTL_Q_DISABLED 0x00 793 #define MTL_Q_ENABLED 0x02 794 795 796 /* MTL traffic class register offsets 797 * Multiple traffic classes can be active. The first class has registers 798 * that begin at 0x1100. Each subsequent queue has registers that 799 * are accessed using an offset of 0x80 from the previous queue. 800 */ 801 #define MTL_TC_BASE MTL_Q_BASE 802 #define MTL_TC_INC MTL_Q_INC 803 804 #define MTL_TC_ETSCR 0x10 805 #define MTL_TC_ETSSR 0x14 806 #define MTL_TC_QWR 0x18 807 808 /* MTL traffic class register entry bit positions and sizes */ 809 #define MTL_TC_ETSCR_TSA_INDEX 0 810 #define MTL_TC_ETSCR_TSA_WIDTH 2 811 #define MTL_TC_QWR_QW_INDEX 0 812 #define MTL_TC_QWR_QW_WIDTH 21 813 814 /* MTL traffic class register value */ 815 #define MTL_TSA_SP 0x00 816 #define MTL_TSA_ETS 0x02 817 818 819 /* PCS MMD select register offset 820 * The MMD select register is used for accessing PCS registers 821 * when the underlying APB3 interface is using indirect addressing. 822 * Indirect addressing requires accessing registers in two phases, 823 * an address phase and a data phase. The address phases requires 824 * writing an address selection value to the MMD select regiesters. 825 */ 826 #define PCS_MMD_SELECT 0xff 827 828 829 /* Descriptor/Packet entry bit positions and sizes */ 830 #define RX_PACKET_ERRORS_CRC_INDEX 2 831 #define RX_PACKET_ERRORS_CRC_WIDTH 1 832 #define RX_PACKET_ERRORS_FRAME_INDEX 3 833 #define RX_PACKET_ERRORS_FRAME_WIDTH 1 834 #define RX_PACKET_ERRORS_LENGTH_INDEX 0 835 #define RX_PACKET_ERRORS_LENGTH_WIDTH 1 836 #define RX_PACKET_ERRORS_OVERRUN_INDEX 1 837 #define RX_PACKET_ERRORS_OVERRUN_WIDTH 1 838 839 #define RX_PACKET_ATTRIBUTES_CSUM_DONE_INDEX 0 840 #define RX_PACKET_ATTRIBUTES_CSUM_DONE_WIDTH 1 841 #define RX_PACKET_ATTRIBUTES_VLAN_CTAG_INDEX 1 842 #define RX_PACKET_ATTRIBUTES_VLAN_CTAG_WIDTH 1 843 #define RX_PACKET_ATTRIBUTES_INCOMPLETE_INDEX 2 844 #define RX_PACKET_ATTRIBUTES_INCOMPLETE_WIDTH 1 845 #define RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_INDEX 3 846 #define RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_WIDTH 1 847 #define RX_PACKET_ATTRIBUTES_CONTEXT_INDEX 4 848 #define RX_PACKET_ATTRIBUTES_CONTEXT_WIDTH 1 849 #define RX_PACKET_ATTRIBUTES_RX_TSTAMP_INDEX 5 850 #define RX_PACKET_ATTRIBUTES_RX_TSTAMP_WIDTH 1 851 852 #define RX_NORMAL_DESC0_OVT_INDEX 0 853 #define RX_NORMAL_DESC0_OVT_WIDTH 16 854 #define RX_NORMAL_DESC3_CDA_INDEX 27 855 #define RX_NORMAL_DESC3_CDA_WIDTH 1 856 #define RX_NORMAL_DESC3_CTXT_INDEX 30 857 #define RX_NORMAL_DESC3_CTXT_WIDTH 1 858 #define RX_NORMAL_DESC3_ES_INDEX 15 859 #define RX_NORMAL_DESC3_ES_WIDTH 1 860 #define RX_NORMAL_DESC3_ETLT_INDEX 16 861 #define RX_NORMAL_DESC3_ETLT_WIDTH 4 862 #define RX_NORMAL_DESC3_INTE_INDEX 30 863 #define RX_NORMAL_DESC3_INTE_WIDTH 1 864 #define RX_NORMAL_DESC3_LD_INDEX 28 865 #define RX_NORMAL_DESC3_LD_WIDTH 1 866 #define RX_NORMAL_DESC3_OWN_INDEX 31 867 #define RX_NORMAL_DESC3_OWN_WIDTH 1 868 #define RX_NORMAL_DESC3_PL_INDEX 0 869 #define RX_NORMAL_DESC3_PL_WIDTH 14 870 871 #define RX_CONTEXT_DESC3_TSA_INDEX 4 872 #define RX_CONTEXT_DESC3_TSA_WIDTH 1 873 #define RX_CONTEXT_DESC3_TSD_INDEX 6 874 #define RX_CONTEXT_DESC3_TSD_WIDTH 1 875 876 #define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_INDEX 0 877 #define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_WIDTH 1 878 #define TX_PACKET_ATTRIBUTES_TSO_ENABLE_INDEX 1 879 #define TX_PACKET_ATTRIBUTES_TSO_ENABLE_WIDTH 1 880 #define TX_PACKET_ATTRIBUTES_VLAN_CTAG_INDEX 2 881 #define TX_PACKET_ATTRIBUTES_VLAN_CTAG_WIDTH 1 882 #define TX_PACKET_ATTRIBUTES_PTP_INDEX 3 883 #define TX_PACKET_ATTRIBUTES_PTP_WIDTH 1 884 885 #define TX_CONTEXT_DESC2_MSS_INDEX 0 886 #define TX_CONTEXT_DESC2_MSS_WIDTH 15 887 #define TX_CONTEXT_DESC3_CTXT_INDEX 30 888 #define TX_CONTEXT_DESC3_CTXT_WIDTH 1 889 #define TX_CONTEXT_DESC3_TCMSSV_INDEX 26 890 #define TX_CONTEXT_DESC3_TCMSSV_WIDTH 1 891 #define TX_CONTEXT_DESC3_VLTV_INDEX 16 892 #define TX_CONTEXT_DESC3_VLTV_WIDTH 1 893 #define TX_CONTEXT_DESC3_VT_INDEX 0 894 #define TX_CONTEXT_DESC3_VT_WIDTH 16 895 896 #define TX_NORMAL_DESC2_HL_B1L_INDEX 0 897 #define TX_NORMAL_DESC2_HL_B1L_WIDTH 14 898 #define TX_NORMAL_DESC2_IC_INDEX 31 899 #define TX_NORMAL_DESC2_IC_WIDTH 1 900 #define TX_NORMAL_DESC2_TTSE_INDEX 30 901 #define TX_NORMAL_DESC2_TTSE_WIDTH 1 902 #define TX_NORMAL_DESC2_VTIR_INDEX 14 903 #define TX_NORMAL_DESC2_VTIR_WIDTH 2 904 #define TX_NORMAL_DESC3_CIC_INDEX 16 905 #define TX_NORMAL_DESC3_CIC_WIDTH 2 906 #define TX_NORMAL_DESC3_CPC_INDEX 26 907 #define TX_NORMAL_DESC3_CPC_WIDTH 2 908 #define TX_NORMAL_DESC3_CTXT_INDEX 30 909 #define TX_NORMAL_DESC3_CTXT_WIDTH 1 910 #define TX_NORMAL_DESC3_FD_INDEX 29 911 #define TX_NORMAL_DESC3_FD_WIDTH 1 912 #define TX_NORMAL_DESC3_FL_INDEX 0 913 #define TX_NORMAL_DESC3_FL_WIDTH 15 914 #define TX_NORMAL_DESC3_LD_INDEX 28 915 #define TX_NORMAL_DESC3_LD_WIDTH 1 916 #define TX_NORMAL_DESC3_OWN_INDEX 31 917 #define TX_NORMAL_DESC3_OWN_WIDTH 1 918 #define TX_NORMAL_DESC3_TCPHDRLEN_INDEX 19 919 #define TX_NORMAL_DESC3_TCPHDRLEN_WIDTH 4 920 #define TX_NORMAL_DESC3_TCPPL_INDEX 0 921 #define TX_NORMAL_DESC3_TCPPL_WIDTH 18 922 #define TX_NORMAL_DESC3_TSE_INDEX 18 923 #define TX_NORMAL_DESC3_TSE_WIDTH 1 924 925 #define TX_NORMAL_DESC2_VLAN_INSERT 0x2 926 927 /* MDIO undefined or vendor specific registers */ 928 #ifndef MDIO_AN_COMP_STAT 929 #define MDIO_AN_COMP_STAT 0x0030 930 #endif 931 932 933 /* Bit setting and getting macros 934 * The get macro will extract the current bit field value from within 935 * the variable 936 * 937 * The set macro will clear the current bit field value within the 938 * variable and then set the bit field of the variable to the 939 * specified value 940 */ 941 #define GET_BITS(_var, _index, _width) \ 942 (((_var) >> (_index)) & ((0x1 << (_width)) - 1)) 943 944 #define SET_BITS(_var, _index, _width, _val) \ 945 do { \ 946 (_var) &= ~(((0x1 << (_width)) - 1) << (_index)); \ 947 (_var) |= (((_val) & ((0x1 << (_width)) - 1)) << (_index)); \ 948 } while (0) 949 950 #define GET_BITS_LE(_var, _index, _width) \ 951 ((le32_to_cpu((_var)) >> (_index)) & ((0x1 << (_width)) - 1)) 952 953 #define SET_BITS_LE(_var, _index, _width, _val) \ 954 do { \ 955 (_var) &= cpu_to_le32(~(((0x1 << (_width)) - 1) << (_index))); \ 956 (_var) |= cpu_to_le32((((_val) & \ 957 ((0x1 << (_width)) - 1)) << (_index))); \ 958 } while (0) 959 960 961 /* Bit setting and getting macros based on register fields 962 * The get macro uses the bit field definitions formed using the input 963 * names to extract the current bit field value from within the 964 * variable 965 * 966 * The set macro uses the bit field definitions formed using the input 967 * names to set the bit field of the variable to the specified value 968 */ 969 #define XGMAC_GET_BITS(_var, _prefix, _field) \ 970 GET_BITS((_var), \ 971 _prefix##_##_field##_INDEX, \ 972 _prefix##_##_field##_WIDTH) 973 974 #define XGMAC_SET_BITS(_var, _prefix, _field, _val) \ 975 SET_BITS((_var), \ 976 _prefix##_##_field##_INDEX, \ 977 _prefix##_##_field##_WIDTH, (_val)) 978 979 #define XGMAC_GET_BITS_LE(_var, _prefix, _field) \ 980 GET_BITS_LE((_var), \ 981 _prefix##_##_field##_INDEX, \ 982 _prefix##_##_field##_WIDTH) 983 984 #define XGMAC_SET_BITS_LE(_var, _prefix, _field, _val) \ 985 SET_BITS_LE((_var), \ 986 _prefix##_##_field##_INDEX, \ 987 _prefix##_##_field##_WIDTH, (_val)) 988 989 990 /* Macros for reading or writing registers 991 * The ioread macros will get bit fields or full values using the 992 * register definitions formed using the input names 993 * 994 * The iowrite macros will set bit fields or full values using the 995 * register definitions formed using the input names 996 */ 997 #define XGMAC_IOREAD(_pdata, _reg) \ 998 ioread32((_pdata)->xgmac_regs + _reg) 999 1000 #define XGMAC_IOREAD_BITS(_pdata, _reg, _field) \ 1001 GET_BITS(XGMAC_IOREAD((_pdata), _reg), \ 1002 _reg##_##_field##_INDEX, \ 1003 _reg##_##_field##_WIDTH) 1004 1005 #define XGMAC_IOWRITE(_pdata, _reg, _val) \ 1006 iowrite32((_val), (_pdata)->xgmac_regs + _reg) 1007 1008 #define XGMAC_IOWRITE_BITS(_pdata, _reg, _field, _val) \ 1009 do { \ 1010 u32 reg_val = XGMAC_IOREAD((_pdata), _reg); \ 1011 SET_BITS(reg_val, \ 1012 _reg##_##_field##_INDEX, \ 1013 _reg##_##_field##_WIDTH, (_val)); \ 1014 XGMAC_IOWRITE((_pdata), _reg, reg_val); \ 1015 } while (0) 1016 1017 1018 /* Macros for reading or writing MTL queue or traffic class registers 1019 * Similar to the standard read and write macros except that the 1020 * base register value is calculated by the queue or traffic class number 1021 */ 1022 #define XGMAC_MTL_IOREAD(_pdata, _n, _reg) \ 1023 ioread32((_pdata)->xgmac_regs + \ 1024 MTL_Q_BASE + ((_n) * MTL_Q_INC) + _reg) 1025 1026 #define XGMAC_MTL_IOREAD_BITS(_pdata, _n, _reg, _field) \ 1027 GET_BITS(XGMAC_MTL_IOREAD((_pdata), (_n), _reg), \ 1028 _reg##_##_field##_INDEX, \ 1029 _reg##_##_field##_WIDTH) 1030 1031 #define XGMAC_MTL_IOWRITE(_pdata, _n, _reg, _val) \ 1032 iowrite32((_val), (_pdata)->xgmac_regs + \ 1033 MTL_Q_BASE + ((_n) * MTL_Q_INC) + _reg) 1034 1035 #define XGMAC_MTL_IOWRITE_BITS(_pdata, _n, _reg, _field, _val) \ 1036 do { \ 1037 u32 reg_val = XGMAC_MTL_IOREAD((_pdata), (_n), _reg); \ 1038 SET_BITS(reg_val, \ 1039 _reg##_##_field##_INDEX, \ 1040 _reg##_##_field##_WIDTH, (_val)); \ 1041 XGMAC_MTL_IOWRITE((_pdata), (_n), _reg, reg_val); \ 1042 } while (0) 1043 1044 1045 /* Macros for reading or writing DMA channel registers 1046 * Similar to the standard read and write macros except that the 1047 * base register value is obtained from the ring 1048 */ 1049 #define XGMAC_DMA_IOREAD(_channel, _reg) \ 1050 ioread32((_channel)->dma_regs + _reg) 1051 1052 #define XGMAC_DMA_IOREAD_BITS(_channel, _reg, _field) \ 1053 GET_BITS(XGMAC_DMA_IOREAD((_channel), _reg), \ 1054 _reg##_##_field##_INDEX, \ 1055 _reg##_##_field##_WIDTH) 1056 1057 #define XGMAC_DMA_IOWRITE(_channel, _reg, _val) \ 1058 iowrite32((_val), (_channel)->dma_regs + _reg) 1059 1060 #define XGMAC_DMA_IOWRITE_BITS(_channel, _reg, _field, _val) \ 1061 do { \ 1062 u32 reg_val = XGMAC_DMA_IOREAD((_channel), _reg); \ 1063 SET_BITS(reg_val, \ 1064 _reg##_##_field##_INDEX, \ 1065 _reg##_##_field##_WIDTH, (_val)); \ 1066 XGMAC_DMA_IOWRITE((_channel), _reg, reg_val); \ 1067 } while (0) 1068 1069 1070 /* Macros for building, reading or writing register values or bits 1071 * within the register values of XPCS registers. 1072 */ 1073 #define XPCS_IOWRITE(_pdata, _off, _val) \ 1074 iowrite32(_val, (_pdata)->xpcs_regs + (_off)) 1075 1076 #define XPCS_IOREAD(_pdata, _off) \ 1077 ioread32((_pdata)->xpcs_regs + (_off)) 1078 1079 1080 /* Macros for building, reading or writing register values or bits 1081 * using MDIO. Different from above because of the use of standardized 1082 * Linux include values. No shifting is performed with the bit 1083 * operations, everything works on mask values. 1084 */ 1085 #define XMDIO_READ(_pdata, _mmd, _reg) \ 1086 ((_pdata)->hw_if.read_mmd_regs((_pdata), 0, \ 1087 MII_ADDR_C45 | (_mmd << 16) | ((_reg) & 0xffff))) 1088 1089 #define XMDIO_READ_BITS(_pdata, _mmd, _reg, _mask) \ 1090 (XMDIO_READ((_pdata), _mmd, _reg) & _mask) 1091 1092 #define XMDIO_WRITE(_pdata, _mmd, _reg, _val) \ 1093 ((_pdata)->hw_if.write_mmd_regs((_pdata), 0, \ 1094 MII_ADDR_C45 | (_mmd << 16) | ((_reg) & 0xffff), (_val))) 1095 1096 #define XMDIO_WRITE_BITS(_pdata, _mmd, _reg, _mask, _val) \ 1097 do { \ 1098 u32 mmd_val = XMDIO_READ((_pdata), _mmd, _reg); \ 1099 mmd_val &= ~_mask; \ 1100 mmd_val |= (_val); \ 1101 XMDIO_WRITE((_pdata), _mmd, _reg, mmd_val); \ 1102 } while (0) 1103 1104 #endif 1105