1 /* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */ 2 /* 3 * Copyright 1996-1999 Thomas Bogendoerfer 4 * 5 * Derived from the lance driver written 1993,1994,1995 by Donald Becker. 6 * 7 * Copyright 1993 United States Government as represented by the 8 * Director, National Security Agency. 9 * 10 * This software may be used and distributed according to the terms 11 * of the GNU General Public License, incorporated herein by reference. 12 * 13 * This driver is for PCnet32 and PCnetPCI based ethercards 14 */ 15 /************************************************************************** 16 * 23 Oct, 2000. 17 * Fixed a few bugs, related to running the controller in 32bit mode. 18 * 19 * Carsten Langgaard, carstenl@mips.com 20 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. 21 * 22 *************************************************************************/ 23 24 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 25 26 #define DRV_NAME "pcnet32" 27 #define DRV_RELDATE "21.Apr.2008" 28 #define PFX DRV_NAME ": " 29 30 #include <linux/module.h> 31 #include <linux/kernel.h> 32 #include <linux/sched.h> 33 #include <linux/string.h> 34 #include <linux/errno.h> 35 #include <linux/ioport.h> 36 #include <linux/slab.h> 37 #include <linux/interrupt.h> 38 #include <linux/pci.h> 39 #include <linux/delay.h> 40 #include <linux/init.h> 41 #include <linux/ethtool.h> 42 #include <linux/mii.h> 43 #include <linux/crc32.h> 44 #include <linux/netdevice.h> 45 #include <linux/etherdevice.h> 46 #include <linux/if_ether.h> 47 #include <linux/skbuff.h> 48 #include <linux/spinlock.h> 49 #include <linux/moduleparam.h> 50 #include <linux/bitops.h> 51 #include <linux/io.h> 52 #include <linux/uaccess.h> 53 54 #include <asm/dma.h> 55 #include <asm/irq.h> 56 57 /* 58 * PCI device identifiers for "new style" Linux PCI Device Drivers 59 */ 60 static const struct pci_device_id pcnet32_pci_tbl[] = { 61 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE_HOME), }, 62 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE), }, 63 64 /* 65 * Adapters that were sold with IBM's RS/6000 or pSeries hardware have 66 * the incorrect vendor id. 67 */ 68 { PCI_DEVICE(PCI_VENDOR_ID_TRIDENT, PCI_DEVICE_ID_AMD_LANCE), 69 .class = (PCI_CLASS_NETWORK_ETHERNET << 8), .class_mask = 0xffff00, }, 70 71 { } /* terminate list */ 72 }; 73 74 MODULE_DEVICE_TABLE(pci, pcnet32_pci_tbl); 75 76 static int cards_found; 77 78 /* 79 * VLB I/O addresses 80 */ 81 static unsigned int pcnet32_portlist[] = 82 { 0x300, 0x320, 0x340, 0x360, 0 }; 83 84 static int pcnet32_debug; 85 static int tx_start = 1; /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */ 86 static int pcnet32vlb; /* check for VLB cards ? */ 87 88 static struct net_device *pcnet32_dev; 89 90 static int max_interrupt_work = 2; 91 static int rx_copybreak = 200; 92 93 #define PCNET32_PORT_AUI 0x00 94 #define PCNET32_PORT_10BT 0x01 95 #define PCNET32_PORT_GPSI 0x02 96 #define PCNET32_PORT_MII 0x03 97 98 #define PCNET32_PORT_PORTSEL 0x03 99 #define PCNET32_PORT_ASEL 0x04 100 #define PCNET32_PORT_100 0x40 101 #define PCNET32_PORT_FD 0x80 102 103 #define PCNET32_DMA_MASK 0xffffffff 104 105 #define PCNET32_WATCHDOG_TIMEOUT (jiffies + (2 * HZ)) 106 #define PCNET32_BLINK_TIMEOUT (jiffies + (HZ/4)) 107 108 /* 109 * table to translate option values from tulip 110 * to internal options 111 */ 112 static const unsigned char options_mapping[] = { 113 PCNET32_PORT_ASEL, /* 0 Auto-select */ 114 PCNET32_PORT_AUI, /* 1 BNC/AUI */ 115 PCNET32_PORT_AUI, /* 2 AUI/BNC */ 116 PCNET32_PORT_ASEL, /* 3 not supported */ 117 PCNET32_PORT_10BT | PCNET32_PORT_FD, /* 4 10baseT-FD */ 118 PCNET32_PORT_ASEL, /* 5 not supported */ 119 PCNET32_PORT_ASEL, /* 6 not supported */ 120 PCNET32_PORT_ASEL, /* 7 not supported */ 121 PCNET32_PORT_ASEL, /* 8 not supported */ 122 PCNET32_PORT_MII, /* 9 MII 10baseT */ 123 PCNET32_PORT_MII | PCNET32_PORT_FD, /* 10 MII 10baseT-FD */ 124 PCNET32_PORT_MII, /* 11 MII (autosel) */ 125 PCNET32_PORT_10BT, /* 12 10BaseT */ 126 PCNET32_PORT_MII | PCNET32_PORT_100, /* 13 MII 100BaseTx */ 127 /* 14 MII 100BaseTx-FD */ 128 PCNET32_PORT_MII | PCNET32_PORT_100 | PCNET32_PORT_FD, 129 PCNET32_PORT_ASEL /* 15 not supported */ 130 }; 131 132 static const char pcnet32_gstrings_test[][ETH_GSTRING_LEN] = { 133 "Loopback test (offline)" 134 }; 135 136 #define PCNET32_TEST_LEN ARRAY_SIZE(pcnet32_gstrings_test) 137 138 #define PCNET32_NUM_REGS 136 139 140 #define MAX_UNITS 8 /* More are supported, limit only on options */ 141 static int options[MAX_UNITS]; 142 static int full_duplex[MAX_UNITS]; 143 static int homepna[MAX_UNITS]; 144 145 /* 146 * Theory of Operation 147 * 148 * This driver uses the same software structure as the normal lance 149 * driver. So look for a verbose description in lance.c. The differences 150 * to the normal lance driver is the use of the 32bit mode of PCnet32 151 * and PCnetPCI chips. Because these chips are 32bit chips, there is no 152 * 16MB limitation and we don't need bounce buffers. 153 */ 154 155 /* 156 * Set the number of Tx and Rx buffers, using Log_2(# buffers). 157 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers. 158 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4). 159 */ 160 #ifndef PCNET32_LOG_TX_BUFFERS 161 #define PCNET32_LOG_TX_BUFFERS 4 162 #define PCNET32_LOG_RX_BUFFERS 5 163 #define PCNET32_LOG_MAX_TX_BUFFERS 9 /* 2^9 == 512 */ 164 #define PCNET32_LOG_MAX_RX_BUFFERS 9 165 #endif 166 167 #define TX_RING_SIZE (1 << (PCNET32_LOG_TX_BUFFERS)) 168 #define TX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_TX_BUFFERS)) 169 170 #define RX_RING_SIZE (1 << (PCNET32_LOG_RX_BUFFERS)) 171 #define RX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_RX_BUFFERS)) 172 173 #define PKT_BUF_SKB 1544 174 /* actual buffer length after being aligned */ 175 #define PKT_BUF_SIZE (PKT_BUF_SKB - NET_IP_ALIGN) 176 /* chip wants twos complement of the (aligned) buffer length */ 177 #define NEG_BUF_SIZE (NET_IP_ALIGN - PKT_BUF_SKB) 178 179 /* Offsets from base I/O address. */ 180 #define PCNET32_WIO_RDP 0x10 181 #define PCNET32_WIO_RAP 0x12 182 #define PCNET32_WIO_RESET 0x14 183 #define PCNET32_WIO_BDP 0x16 184 185 #define PCNET32_DWIO_RDP 0x10 186 #define PCNET32_DWIO_RAP 0x14 187 #define PCNET32_DWIO_RESET 0x18 188 #define PCNET32_DWIO_BDP 0x1C 189 190 #define PCNET32_TOTAL_SIZE 0x20 191 192 #define CSR0 0 193 #define CSR0_INIT 0x1 194 #define CSR0_START 0x2 195 #define CSR0_STOP 0x4 196 #define CSR0_TXPOLL 0x8 197 #define CSR0_INTEN 0x40 198 #define CSR0_IDON 0x0100 199 #define CSR0_NORMAL (CSR0_START | CSR0_INTEN) 200 #define PCNET32_INIT_LOW 1 201 #define PCNET32_INIT_HIGH 2 202 #define CSR3 3 203 #define CSR4 4 204 #define CSR5 5 205 #define CSR5_SUSPEND 0x0001 206 #define CSR15 15 207 #define PCNET32_MC_FILTER 8 208 209 #define PCNET32_79C970A 0x2621 210 211 /* The PCNET32 Rx and Tx ring descriptors. */ 212 struct pcnet32_rx_head { 213 __le32 base; 214 __le16 buf_length; /* two`s complement of length */ 215 __le16 status; 216 __le32 msg_length; 217 __le32 reserved; 218 }; 219 220 struct pcnet32_tx_head { 221 __le32 base; 222 __le16 length; /* two`s complement of length */ 223 __le16 status; 224 __le32 misc; 225 __le32 reserved; 226 }; 227 228 /* The PCNET32 32-Bit initialization block, described in databook. */ 229 struct pcnet32_init_block { 230 __le16 mode; 231 __le16 tlen_rlen; 232 u8 phys_addr[6]; 233 __le16 reserved; 234 __le32 filter[2]; 235 /* Receive and transmit ring base, along with extra bits. */ 236 __le32 rx_ring; 237 __le32 tx_ring; 238 }; 239 240 /* PCnet32 access functions */ 241 struct pcnet32_access { 242 u16 (*read_csr) (unsigned long, int); 243 void (*write_csr) (unsigned long, int, u16); 244 u16 (*read_bcr) (unsigned long, int); 245 void (*write_bcr) (unsigned long, int, u16); 246 u16 (*read_rap) (unsigned long); 247 void (*write_rap) (unsigned long, u16); 248 void (*reset) (unsigned long); 249 }; 250 251 /* 252 * The first field of pcnet32_private is read by the ethernet device 253 * so the structure should be allocated using pci_alloc_consistent(). 254 */ 255 struct pcnet32_private { 256 struct pcnet32_init_block *init_block; 257 /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */ 258 struct pcnet32_rx_head *rx_ring; 259 struct pcnet32_tx_head *tx_ring; 260 dma_addr_t init_dma_addr;/* DMA address of beginning of the init block, 261 returned by pci_alloc_consistent */ 262 struct pci_dev *pci_dev; 263 const char *name; 264 /* The saved address of a sent-in-place packet/buffer, for skfree(). */ 265 struct sk_buff **tx_skbuff; 266 struct sk_buff **rx_skbuff; 267 dma_addr_t *tx_dma_addr; 268 dma_addr_t *rx_dma_addr; 269 const struct pcnet32_access *a; 270 spinlock_t lock; /* Guard lock */ 271 unsigned int cur_rx, cur_tx; /* The next free ring entry */ 272 unsigned int rx_ring_size; /* current rx ring size */ 273 unsigned int tx_ring_size; /* current tx ring size */ 274 unsigned int rx_mod_mask; /* rx ring modular mask */ 275 unsigned int tx_mod_mask; /* tx ring modular mask */ 276 unsigned short rx_len_bits; 277 unsigned short tx_len_bits; 278 dma_addr_t rx_ring_dma_addr; 279 dma_addr_t tx_ring_dma_addr; 280 unsigned int dirty_rx, /* ring entries to be freed. */ 281 dirty_tx; 282 283 struct net_device *dev; 284 struct napi_struct napi; 285 char tx_full; 286 char phycount; /* number of phys found */ 287 int options; 288 unsigned int shared_irq:1, /* shared irq possible */ 289 dxsuflo:1, /* disable transmit stop on uflo */ 290 mii:1, /* mii port available */ 291 autoneg:1, /* autoneg enabled */ 292 port_tp:1, /* port set to TP */ 293 fdx:1; /* full duplex enabled */ 294 struct net_device *next; 295 struct mii_if_info mii_if; 296 struct timer_list watchdog_timer; 297 u32 msg_enable; /* debug message level */ 298 299 /* each bit indicates an available PHY */ 300 u32 phymask; 301 unsigned short chip_version; /* which variant this is */ 302 303 /* saved registers during ethtool blink */ 304 u16 save_regs[4]; 305 }; 306 307 static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *); 308 static int pcnet32_probe1(unsigned long, int, struct pci_dev *); 309 static int pcnet32_open(struct net_device *); 310 static int pcnet32_init_ring(struct net_device *); 311 static netdev_tx_t pcnet32_start_xmit(struct sk_buff *, 312 struct net_device *); 313 static void pcnet32_tx_timeout(struct net_device *dev, unsigned int txqueue); 314 static irqreturn_t pcnet32_interrupt(int, void *); 315 static int pcnet32_close(struct net_device *); 316 static struct net_device_stats *pcnet32_get_stats(struct net_device *); 317 static void pcnet32_load_multicast(struct net_device *dev); 318 static void pcnet32_set_multicast_list(struct net_device *); 319 static int pcnet32_ioctl(struct net_device *, struct ifreq *, int); 320 static void pcnet32_watchdog(struct timer_list *); 321 static int mdio_read(struct net_device *dev, int phy_id, int reg_num); 322 static void mdio_write(struct net_device *dev, int phy_id, int reg_num, 323 int val); 324 static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits); 325 static void pcnet32_ethtool_test(struct net_device *dev, 326 struct ethtool_test *eth_test, u64 * data); 327 static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1); 328 static int pcnet32_get_regs_len(struct net_device *dev); 329 static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs, 330 void *ptr); 331 static void pcnet32_purge_tx_ring(struct net_device *dev); 332 static int pcnet32_alloc_ring(struct net_device *dev, const char *name); 333 static void pcnet32_free_ring(struct net_device *dev); 334 static void pcnet32_check_media(struct net_device *dev, int verbose); 335 336 static u16 pcnet32_wio_read_csr(unsigned long addr, int index) 337 { 338 outw(index, addr + PCNET32_WIO_RAP); 339 return inw(addr + PCNET32_WIO_RDP); 340 } 341 342 static void pcnet32_wio_write_csr(unsigned long addr, int index, u16 val) 343 { 344 outw(index, addr + PCNET32_WIO_RAP); 345 outw(val, addr + PCNET32_WIO_RDP); 346 } 347 348 static u16 pcnet32_wio_read_bcr(unsigned long addr, int index) 349 { 350 outw(index, addr + PCNET32_WIO_RAP); 351 return inw(addr + PCNET32_WIO_BDP); 352 } 353 354 static void pcnet32_wio_write_bcr(unsigned long addr, int index, u16 val) 355 { 356 outw(index, addr + PCNET32_WIO_RAP); 357 outw(val, addr + PCNET32_WIO_BDP); 358 } 359 360 static u16 pcnet32_wio_read_rap(unsigned long addr) 361 { 362 return inw(addr + PCNET32_WIO_RAP); 363 } 364 365 static void pcnet32_wio_write_rap(unsigned long addr, u16 val) 366 { 367 outw(val, addr + PCNET32_WIO_RAP); 368 } 369 370 static void pcnet32_wio_reset(unsigned long addr) 371 { 372 inw(addr + PCNET32_WIO_RESET); 373 } 374 375 static int pcnet32_wio_check(unsigned long addr) 376 { 377 outw(88, addr + PCNET32_WIO_RAP); 378 return inw(addr + PCNET32_WIO_RAP) == 88; 379 } 380 381 static const struct pcnet32_access pcnet32_wio = { 382 .read_csr = pcnet32_wio_read_csr, 383 .write_csr = pcnet32_wio_write_csr, 384 .read_bcr = pcnet32_wio_read_bcr, 385 .write_bcr = pcnet32_wio_write_bcr, 386 .read_rap = pcnet32_wio_read_rap, 387 .write_rap = pcnet32_wio_write_rap, 388 .reset = pcnet32_wio_reset 389 }; 390 391 static u16 pcnet32_dwio_read_csr(unsigned long addr, int index) 392 { 393 outl(index, addr + PCNET32_DWIO_RAP); 394 return inl(addr + PCNET32_DWIO_RDP) & 0xffff; 395 } 396 397 static void pcnet32_dwio_write_csr(unsigned long addr, int index, u16 val) 398 { 399 outl(index, addr + PCNET32_DWIO_RAP); 400 outl(val, addr + PCNET32_DWIO_RDP); 401 } 402 403 static u16 pcnet32_dwio_read_bcr(unsigned long addr, int index) 404 { 405 outl(index, addr + PCNET32_DWIO_RAP); 406 return inl(addr + PCNET32_DWIO_BDP) & 0xffff; 407 } 408 409 static void pcnet32_dwio_write_bcr(unsigned long addr, int index, u16 val) 410 { 411 outl(index, addr + PCNET32_DWIO_RAP); 412 outl(val, addr + PCNET32_DWIO_BDP); 413 } 414 415 static u16 pcnet32_dwio_read_rap(unsigned long addr) 416 { 417 return inl(addr + PCNET32_DWIO_RAP) & 0xffff; 418 } 419 420 static void pcnet32_dwio_write_rap(unsigned long addr, u16 val) 421 { 422 outl(val, addr + PCNET32_DWIO_RAP); 423 } 424 425 static void pcnet32_dwio_reset(unsigned long addr) 426 { 427 inl(addr + PCNET32_DWIO_RESET); 428 } 429 430 static int pcnet32_dwio_check(unsigned long addr) 431 { 432 outl(88, addr + PCNET32_DWIO_RAP); 433 return (inl(addr + PCNET32_DWIO_RAP) & 0xffff) == 88; 434 } 435 436 static const struct pcnet32_access pcnet32_dwio = { 437 .read_csr = pcnet32_dwio_read_csr, 438 .write_csr = pcnet32_dwio_write_csr, 439 .read_bcr = pcnet32_dwio_read_bcr, 440 .write_bcr = pcnet32_dwio_write_bcr, 441 .read_rap = pcnet32_dwio_read_rap, 442 .write_rap = pcnet32_dwio_write_rap, 443 .reset = pcnet32_dwio_reset 444 }; 445 446 static void pcnet32_netif_stop(struct net_device *dev) 447 { 448 struct pcnet32_private *lp = netdev_priv(dev); 449 450 netif_trans_update(dev); /* prevent tx timeout */ 451 napi_disable(&lp->napi); 452 netif_tx_disable(dev); 453 } 454 455 static void pcnet32_netif_start(struct net_device *dev) 456 { 457 struct pcnet32_private *lp = netdev_priv(dev); 458 ulong ioaddr = dev->base_addr; 459 u16 val; 460 461 netif_wake_queue(dev); 462 val = lp->a->read_csr(ioaddr, CSR3); 463 val &= 0x00ff; 464 lp->a->write_csr(ioaddr, CSR3, val); 465 napi_enable(&lp->napi); 466 } 467 468 /* 469 * Allocate space for the new sized tx ring. 470 * Free old resources 471 * Save new resources. 472 * Any failure keeps old resources. 473 * Must be called with lp->lock held. 474 */ 475 static void pcnet32_realloc_tx_ring(struct net_device *dev, 476 struct pcnet32_private *lp, 477 unsigned int size) 478 { 479 dma_addr_t new_ring_dma_addr; 480 dma_addr_t *new_dma_addr_list; 481 struct pcnet32_tx_head *new_tx_ring; 482 struct sk_buff **new_skb_list; 483 unsigned int entries = BIT(size); 484 485 pcnet32_purge_tx_ring(dev); 486 487 new_tx_ring = 488 pci_zalloc_consistent(lp->pci_dev, 489 sizeof(struct pcnet32_tx_head) * entries, 490 &new_ring_dma_addr); 491 if (new_tx_ring == NULL) 492 return; 493 494 new_dma_addr_list = kcalloc(entries, sizeof(dma_addr_t), GFP_ATOMIC); 495 if (!new_dma_addr_list) 496 goto free_new_tx_ring; 497 498 new_skb_list = kcalloc(entries, sizeof(struct sk_buff *), GFP_ATOMIC); 499 if (!new_skb_list) 500 goto free_new_lists; 501 502 kfree(lp->tx_skbuff); 503 kfree(lp->tx_dma_addr); 504 pci_free_consistent(lp->pci_dev, 505 sizeof(struct pcnet32_tx_head) * lp->tx_ring_size, 506 lp->tx_ring, lp->tx_ring_dma_addr); 507 508 lp->tx_ring_size = entries; 509 lp->tx_mod_mask = lp->tx_ring_size - 1; 510 lp->tx_len_bits = (size << 12); 511 lp->tx_ring = new_tx_ring; 512 lp->tx_ring_dma_addr = new_ring_dma_addr; 513 lp->tx_dma_addr = new_dma_addr_list; 514 lp->tx_skbuff = new_skb_list; 515 return; 516 517 free_new_lists: 518 kfree(new_dma_addr_list); 519 free_new_tx_ring: 520 pci_free_consistent(lp->pci_dev, 521 sizeof(struct pcnet32_tx_head) * entries, 522 new_tx_ring, 523 new_ring_dma_addr); 524 } 525 526 /* 527 * Allocate space for the new sized rx ring. 528 * Re-use old receive buffers. 529 * alloc extra buffers 530 * free unneeded buffers 531 * free unneeded buffers 532 * Save new resources. 533 * Any failure keeps old resources. 534 * Must be called with lp->lock held. 535 */ 536 static void pcnet32_realloc_rx_ring(struct net_device *dev, 537 struct pcnet32_private *lp, 538 unsigned int size) 539 { 540 dma_addr_t new_ring_dma_addr; 541 dma_addr_t *new_dma_addr_list; 542 struct pcnet32_rx_head *new_rx_ring; 543 struct sk_buff **new_skb_list; 544 int new, overlap; 545 unsigned int entries = BIT(size); 546 547 new_rx_ring = 548 pci_zalloc_consistent(lp->pci_dev, 549 sizeof(struct pcnet32_rx_head) * entries, 550 &new_ring_dma_addr); 551 if (new_rx_ring == NULL) 552 return; 553 554 new_dma_addr_list = kcalloc(entries, sizeof(dma_addr_t), GFP_ATOMIC); 555 if (!new_dma_addr_list) 556 goto free_new_rx_ring; 557 558 new_skb_list = kcalloc(entries, sizeof(struct sk_buff *), GFP_ATOMIC); 559 if (!new_skb_list) 560 goto free_new_lists; 561 562 /* first copy the current receive buffers */ 563 overlap = min(entries, lp->rx_ring_size); 564 for (new = 0; new < overlap; new++) { 565 new_rx_ring[new] = lp->rx_ring[new]; 566 new_dma_addr_list[new] = lp->rx_dma_addr[new]; 567 new_skb_list[new] = lp->rx_skbuff[new]; 568 } 569 /* now allocate any new buffers needed */ 570 for (; new < entries; new++) { 571 struct sk_buff *rx_skbuff; 572 new_skb_list[new] = netdev_alloc_skb(dev, PKT_BUF_SKB); 573 rx_skbuff = new_skb_list[new]; 574 if (!rx_skbuff) { 575 /* keep the original lists and buffers */ 576 netif_err(lp, drv, dev, "%s netdev_alloc_skb failed\n", 577 __func__); 578 goto free_all_new; 579 } 580 skb_reserve(rx_skbuff, NET_IP_ALIGN); 581 582 new_dma_addr_list[new] = 583 pci_map_single(lp->pci_dev, rx_skbuff->data, 584 PKT_BUF_SIZE, PCI_DMA_FROMDEVICE); 585 if (pci_dma_mapping_error(lp->pci_dev, 586 new_dma_addr_list[new])) { 587 netif_err(lp, drv, dev, "%s dma mapping failed\n", 588 __func__); 589 dev_kfree_skb(new_skb_list[new]); 590 goto free_all_new; 591 } 592 new_rx_ring[new].base = cpu_to_le32(new_dma_addr_list[new]); 593 new_rx_ring[new].buf_length = cpu_to_le16(NEG_BUF_SIZE); 594 new_rx_ring[new].status = cpu_to_le16(0x8000); 595 } 596 /* and free any unneeded buffers */ 597 for (; new < lp->rx_ring_size; new++) { 598 if (lp->rx_skbuff[new]) { 599 if (!pci_dma_mapping_error(lp->pci_dev, 600 lp->rx_dma_addr[new])) 601 pci_unmap_single(lp->pci_dev, 602 lp->rx_dma_addr[new], 603 PKT_BUF_SIZE, 604 PCI_DMA_FROMDEVICE); 605 dev_kfree_skb(lp->rx_skbuff[new]); 606 } 607 } 608 609 kfree(lp->rx_skbuff); 610 kfree(lp->rx_dma_addr); 611 pci_free_consistent(lp->pci_dev, 612 sizeof(struct pcnet32_rx_head) * 613 lp->rx_ring_size, lp->rx_ring, 614 lp->rx_ring_dma_addr); 615 616 lp->rx_ring_size = entries; 617 lp->rx_mod_mask = lp->rx_ring_size - 1; 618 lp->rx_len_bits = (size << 4); 619 lp->rx_ring = new_rx_ring; 620 lp->rx_ring_dma_addr = new_ring_dma_addr; 621 lp->rx_dma_addr = new_dma_addr_list; 622 lp->rx_skbuff = new_skb_list; 623 return; 624 625 free_all_new: 626 while (--new >= lp->rx_ring_size) { 627 if (new_skb_list[new]) { 628 if (!pci_dma_mapping_error(lp->pci_dev, 629 new_dma_addr_list[new])) 630 pci_unmap_single(lp->pci_dev, 631 new_dma_addr_list[new], 632 PKT_BUF_SIZE, 633 PCI_DMA_FROMDEVICE); 634 dev_kfree_skb(new_skb_list[new]); 635 } 636 } 637 kfree(new_skb_list); 638 free_new_lists: 639 kfree(new_dma_addr_list); 640 free_new_rx_ring: 641 pci_free_consistent(lp->pci_dev, 642 sizeof(struct pcnet32_rx_head) * entries, 643 new_rx_ring, 644 new_ring_dma_addr); 645 } 646 647 static void pcnet32_purge_rx_ring(struct net_device *dev) 648 { 649 struct pcnet32_private *lp = netdev_priv(dev); 650 int i; 651 652 /* free all allocated skbuffs */ 653 for (i = 0; i < lp->rx_ring_size; i++) { 654 lp->rx_ring[i].status = 0; /* CPU owns buffer */ 655 wmb(); /* Make sure adapter sees owner change */ 656 if (lp->rx_skbuff[i]) { 657 if (!pci_dma_mapping_error(lp->pci_dev, 658 lp->rx_dma_addr[i])) 659 pci_unmap_single(lp->pci_dev, 660 lp->rx_dma_addr[i], 661 PKT_BUF_SIZE, 662 PCI_DMA_FROMDEVICE); 663 dev_kfree_skb_any(lp->rx_skbuff[i]); 664 } 665 lp->rx_skbuff[i] = NULL; 666 lp->rx_dma_addr[i] = 0; 667 } 668 } 669 670 #ifdef CONFIG_NET_POLL_CONTROLLER 671 static void pcnet32_poll_controller(struct net_device *dev) 672 { 673 disable_irq(dev->irq); 674 pcnet32_interrupt(0, dev); 675 enable_irq(dev->irq); 676 } 677 #endif 678 679 /* 680 * lp->lock must be held. 681 */ 682 static int pcnet32_suspend(struct net_device *dev, unsigned long *flags, 683 int can_sleep) 684 { 685 int csr5; 686 struct pcnet32_private *lp = netdev_priv(dev); 687 const struct pcnet32_access *a = lp->a; 688 ulong ioaddr = dev->base_addr; 689 int ticks; 690 691 /* really old chips have to be stopped. */ 692 if (lp->chip_version < PCNET32_79C970A) 693 return 0; 694 695 /* set SUSPEND (SPND) - CSR5 bit 0 */ 696 csr5 = a->read_csr(ioaddr, CSR5); 697 a->write_csr(ioaddr, CSR5, csr5 | CSR5_SUSPEND); 698 699 /* poll waiting for bit to be set */ 700 ticks = 0; 701 while (!(a->read_csr(ioaddr, CSR5) & CSR5_SUSPEND)) { 702 spin_unlock_irqrestore(&lp->lock, *flags); 703 if (can_sleep) 704 msleep(1); 705 else 706 mdelay(1); 707 spin_lock_irqsave(&lp->lock, *flags); 708 ticks++; 709 if (ticks > 200) { 710 netif_printk(lp, hw, KERN_DEBUG, dev, 711 "Error getting into suspend!\n"); 712 return 0; 713 } 714 } 715 return 1; 716 } 717 718 static void pcnet32_clr_suspend(struct pcnet32_private *lp, ulong ioaddr) 719 { 720 int csr5 = lp->a->read_csr(ioaddr, CSR5); 721 /* clear SUSPEND (SPND) - CSR5 bit 0 */ 722 lp->a->write_csr(ioaddr, CSR5, csr5 & ~CSR5_SUSPEND); 723 } 724 725 static int pcnet32_get_link_ksettings(struct net_device *dev, 726 struct ethtool_link_ksettings *cmd) 727 { 728 struct pcnet32_private *lp = netdev_priv(dev); 729 unsigned long flags; 730 731 spin_lock_irqsave(&lp->lock, flags); 732 if (lp->mii) { 733 mii_ethtool_get_link_ksettings(&lp->mii_if, cmd); 734 } else if (lp->chip_version == PCNET32_79C970A) { 735 if (lp->autoneg) { 736 cmd->base.autoneg = AUTONEG_ENABLE; 737 if (lp->a->read_bcr(dev->base_addr, 4) == 0xc0) 738 cmd->base.port = PORT_AUI; 739 else 740 cmd->base.port = PORT_TP; 741 } else { 742 cmd->base.autoneg = AUTONEG_DISABLE; 743 cmd->base.port = lp->port_tp ? PORT_TP : PORT_AUI; 744 } 745 cmd->base.duplex = lp->fdx ? DUPLEX_FULL : DUPLEX_HALF; 746 cmd->base.speed = SPEED_10; 747 ethtool_convert_legacy_u32_to_link_mode( 748 cmd->link_modes.supported, 749 SUPPORTED_TP | SUPPORTED_AUI); 750 } 751 spin_unlock_irqrestore(&lp->lock, flags); 752 return 0; 753 } 754 755 static int pcnet32_set_link_ksettings(struct net_device *dev, 756 const struct ethtool_link_ksettings *cmd) 757 { 758 struct pcnet32_private *lp = netdev_priv(dev); 759 ulong ioaddr = dev->base_addr; 760 unsigned long flags; 761 int r = -EOPNOTSUPP; 762 int suspended, bcr2, bcr9, csr15; 763 764 spin_lock_irqsave(&lp->lock, flags); 765 if (lp->mii) { 766 r = mii_ethtool_set_link_ksettings(&lp->mii_if, cmd); 767 } else if (lp->chip_version == PCNET32_79C970A) { 768 suspended = pcnet32_suspend(dev, &flags, 0); 769 if (!suspended) 770 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); 771 772 lp->autoneg = cmd->base.autoneg == AUTONEG_ENABLE; 773 bcr2 = lp->a->read_bcr(ioaddr, 2); 774 if (cmd->base.autoneg == AUTONEG_ENABLE) { 775 lp->a->write_bcr(ioaddr, 2, bcr2 | 0x0002); 776 } else { 777 lp->a->write_bcr(ioaddr, 2, bcr2 & ~0x0002); 778 779 lp->port_tp = cmd->base.port == PORT_TP; 780 csr15 = lp->a->read_csr(ioaddr, CSR15) & ~0x0180; 781 if (cmd->base.port == PORT_TP) 782 csr15 |= 0x0080; 783 lp->a->write_csr(ioaddr, CSR15, csr15); 784 lp->init_block->mode = cpu_to_le16(csr15); 785 786 lp->fdx = cmd->base.duplex == DUPLEX_FULL; 787 bcr9 = lp->a->read_bcr(ioaddr, 9) & ~0x0003; 788 if (cmd->base.duplex == DUPLEX_FULL) 789 bcr9 |= 0x0003; 790 lp->a->write_bcr(ioaddr, 9, bcr9); 791 } 792 if (suspended) 793 pcnet32_clr_suspend(lp, ioaddr); 794 else if (netif_running(dev)) 795 pcnet32_restart(dev, CSR0_NORMAL); 796 r = 0; 797 } 798 spin_unlock_irqrestore(&lp->lock, flags); 799 return r; 800 } 801 802 static void pcnet32_get_drvinfo(struct net_device *dev, 803 struct ethtool_drvinfo *info) 804 { 805 struct pcnet32_private *lp = netdev_priv(dev); 806 807 strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); 808 if (lp->pci_dev) 809 strlcpy(info->bus_info, pci_name(lp->pci_dev), 810 sizeof(info->bus_info)); 811 else 812 snprintf(info->bus_info, sizeof(info->bus_info), 813 "VLB 0x%lx", dev->base_addr); 814 } 815 816 static u32 pcnet32_get_link(struct net_device *dev) 817 { 818 struct pcnet32_private *lp = netdev_priv(dev); 819 unsigned long flags; 820 int r; 821 822 spin_lock_irqsave(&lp->lock, flags); 823 if (lp->mii) { 824 r = mii_link_ok(&lp->mii_if); 825 } else if (lp->chip_version == PCNET32_79C970A) { 826 ulong ioaddr = dev->base_addr; /* card base I/O address */ 827 /* only read link if port is set to TP */ 828 if (!lp->autoneg && lp->port_tp) 829 r = (lp->a->read_bcr(ioaddr, 4) != 0xc0); 830 else /* link always up for AUI port or port auto select */ 831 r = 1; 832 } else if (lp->chip_version > PCNET32_79C970A) { 833 ulong ioaddr = dev->base_addr; /* card base I/O address */ 834 r = (lp->a->read_bcr(ioaddr, 4) != 0xc0); 835 } else { /* can not detect link on really old chips */ 836 r = 1; 837 } 838 spin_unlock_irqrestore(&lp->lock, flags); 839 840 return r; 841 } 842 843 static u32 pcnet32_get_msglevel(struct net_device *dev) 844 { 845 struct pcnet32_private *lp = netdev_priv(dev); 846 return lp->msg_enable; 847 } 848 849 static void pcnet32_set_msglevel(struct net_device *dev, u32 value) 850 { 851 struct pcnet32_private *lp = netdev_priv(dev); 852 lp->msg_enable = value; 853 } 854 855 static int pcnet32_nway_reset(struct net_device *dev) 856 { 857 struct pcnet32_private *lp = netdev_priv(dev); 858 unsigned long flags; 859 int r = -EOPNOTSUPP; 860 861 if (lp->mii) { 862 spin_lock_irqsave(&lp->lock, flags); 863 r = mii_nway_restart(&lp->mii_if); 864 spin_unlock_irqrestore(&lp->lock, flags); 865 } 866 return r; 867 } 868 869 static void pcnet32_get_ringparam(struct net_device *dev, 870 struct ethtool_ringparam *ering) 871 { 872 struct pcnet32_private *lp = netdev_priv(dev); 873 874 ering->tx_max_pending = TX_MAX_RING_SIZE; 875 ering->tx_pending = lp->tx_ring_size; 876 ering->rx_max_pending = RX_MAX_RING_SIZE; 877 ering->rx_pending = lp->rx_ring_size; 878 } 879 880 static int pcnet32_set_ringparam(struct net_device *dev, 881 struct ethtool_ringparam *ering) 882 { 883 struct pcnet32_private *lp = netdev_priv(dev); 884 unsigned long flags; 885 unsigned int size; 886 ulong ioaddr = dev->base_addr; 887 int i; 888 889 if (ering->rx_mini_pending || ering->rx_jumbo_pending) 890 return -EINVAL; 891 892 if (netif_running(dev)) 893 pcnet32_netif_stop(dev); 894 895 spin_lock_irqsave(&lp->lock, flags); 896 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */ 897 898 size = min(ering->tx_pending, (unsigned int)TX_MAX_RING_SIZE); 899 900 /* set the minimum ring size to 4, to allow the loopback test to work 901 * unchanged. 902 */ 903 for (i = 2; i <= PCNET32_LOG_MAX_TX_BUFFERS; i++) { 904 if (size <= (1 << i)) 905 break; 906 } 907 if ((1 << i) != lp->tx_ring_size) 908 pcnet32_realloc_tx_ring(dev, lp, i); 909 910 size = min(ering->rx_pending, (unsigned int)RX_MAX_RING_SIZE); 911 for (i = 2; i <= PCNET32_LOG_MAX_RX_BUFFERS; i++) { 912 if (size <= (1 << i)) 913 break; 914 } 915 if ((1 << i) != lp->rx_ring_size) 916 pcnet32_realloc_rx_ring(dev, lp, i); 917 918 lp->napi.weight = lp->rx_ring_size / 2; 919 920 if (netif_running(dev)) { 921 pcnet32_netif_start(dev); 922 pcnet32_restart(dev, CSR0_NORMAL); 923 } 924 925 spin_unlock_irqrestore(&lp->lock, flags); 926 927 netif_info(lp, drv, dev, "Ring Param Settings: RX: %d, TX: %d\n", 928 lp->rx_ring_size, lp->tx_ring_size); 929 930 return 0; 931 } 932 933 static void pcnet32_get_strings(struct net_device *dev, u32 stringset, 934 u8 *data) 935 { 936 memcpy(data, pcnet32_gstrings_test, sizeof(pcnet32_gstrings_test)); 937 } 938 939 static int pcnet32_get_sset_count(struct net_device *dev, int sset) 940 { 941 switch (sset) { 942 case ETH_SS_TEST: 943 return PCNET32_TEST_LEN; 944 default: 945 return -EOPNOTSUPP; 946 } 947 } 948 949 static void pcnet32_ethtool_test(struct net_device *dev, 950 struct ethtool_test *test, u64 * data) 951 { 952 struct pcnet32_private *lp = netdev_priv(dev); 953 int rc; 954 955 if (test->flags == ETH_TEST_FL_OFFLINE) { 956 rc = pcnet32_loopback_test(dev, data); 957 if (rc) { 958 netif_printk(lp, hw, KERN_DEBUG, dev, 959 "Loopback test failed\n"); 960 test->flags |= ETH_TEST_FL_FAILED; 961 } else 962 netif_printk(lp, hw, KERN_DEBUG, dev, 963 "Loopback test passed\n"); 964 } else 965 netif_printk(lp, hw, KERN_DEBUG, dev, 966 "No tests to run (specify 'Offline' on ethtool)\n"); 967 } /* end pcnet32_ethtool_test */ 968 969 static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1) 970 { 971 struct pcnet32_private *lp = netdev_priv(dev); 972 const struct pcnet32_access *a = lp->a; /* access to registers */ 973 ulong ioaddr = dev->base_addr; /* card base I/O address */ 974 struct sk_buff *skb; /* sk buff */ 975 int x, i; /* counters */ 976 int numbuffs = 4; /* number of TX/RX buffers and descs */ 977 u16 status = 0x8300; /* TX ring status */ 978 __le16 teststatus; /* test of ring status */ 979 int rc; /* return code */ 980 int size; /* size of packets */ 981 unsigned char *packet; /* source packet data */ 982 static const int data_len = 60; /* length of source packets */ 983 unsigned long flags; 984 unsigned long ticks; 985 986 rc = 1; /* default to fail */ 987 988 if (netif_running(dev)) 989 pcnet32_netif_stop(dev); 990 991 spin_lock_irqsave(&lp->lock, flags); 992 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */ 993 994 numbuffs = min(numbuffs, (int)min(lp->rx_ring_size, lp->tx_ring_size)); 995 996 /* Reset the PCNET32 */ 997 lp->a->reset(ioaddr); 998 lp->a->write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */ 999 1000 /* switch pcnet32 to 32bit mode */ 1001 lp->a->write_bcr(ioaddr, 20, 2); 1002 1003 /* purge & init rings but don't actually restart */ 1004 pcnet32_restart(dev, 0x0000); 1005 1006 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */ 1007 1008 /* Initialize Transmit buffers. */ 1009 size = data_len + 15; 1010 for (x = 0; x < numbuffs; x++) { 1011 skb = netdev_alloc_skb(dev, size); 1012 if (!skb) { 1013 netif_printk(lp, hw, KERN_DEBUG, dev, 1014 "Cannot allocate skb at line: %d!\n", 1015 __LINE__); 1016 goto clean_up; 1017 } 1018 packet = skb->data; 1019 skb_put(skb, size); /* create space for data */ 1020 lp->tx_skbuff[x] = skb; 1021 lp->tx_ring[x].length = cpu_to_le16(-skb->len); 1022 lp->tx_ring[x].misc = 0; 1023 1024 /* put DA and SA into the skb */ 1025 for (i = 0; i < 6; i++) 1026 *packet++ = dev->dev_addr[i]; 1027 for (i = 0; i < 6; i++) 1028 *packet++ = dev->dev_addr[i]; 1029 /* type */ 1030 *packet++ = 0x08; 1031 *packet++ = 0x06; 1032 /* packet number */ 1033 *packet++ = x; 1034 /* fill packet with data */ 1035 for (i = 0; i < data_len; i++) 1036 *packet++ = i; 1037 1038 lp->tx_dma_addr[x] = 1039 pci_map_single(lp->pci_dev, skb->data, skb->len, 1040 PCI_DMA_TODEVICE); 1041 if (pci_dma_mapping_error(lp->pci_dev, lp->tx_dma_addr[x])) { 1042 netif_printk(lp, hw, KERN_DEBUG, dev, 1043 "DMA mapping error at line: %d!\n", 1044 __LINE__); 1045 goto clean_up; 1046 } 1047 lp->tx_ring[x].base = cpu_to_le32(lp->tx_dma_addr[x]); 1048 wmb(); /* Make sure owner changes after all others are visible */ 1049 lp->tx_ring[x].status = cpu_to_le16(status); 1050 } 1051 1052 x = a->read_bcr(ioaddr, 32); /* set internal loopback in BCR32 */ 1053 a->write_bcr(ioaddr, 32, x | 0x0002); 1054 1055 /* set int loopback in CSR15 */ 1056 x = a->read_csr(ioaddr, CSR15) & 0xfffc; 1057 lp->a->write_csr(ioaddr, CSR15, x | 0x0044); 1058 1059 teststatus = cpu_to_le16(0x8000); 1060 lp->a->write_csr(ioaddr, CSR0, CSR0_START); /* Set STRT bit */ 1061 1062 /* Check status of descriptors */ 1063 for (x = 0; x < numbuffs; x++) { 1064 ticks = 0; 1065 rmb(); 1066 while ((lp->rx_ring[x].status & teststatus) && (ticks < 200)) { 1067 spin_unlock_irqrestore(&lp->lock, flags); 1068 msleep(1); 1069 spin_lock_irqsave(&lp->lock, flags); 1070 rmb(); 1071 ticks++; 1072 } 1073 if (ticks == 200) { 1074 netif_err(lp, hw, dev, "Desc %d failed to reset!\n", x); 1075 break; 1076 } 1077 } 1078 1079 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */ 1080 wmb(); 1081 if (netif_msg_hw(lp) && netif_msg_pktdata(lp)) { 1082 netdev_printk(KERN_DEBUG, dev, "RX loopback packets:\n"); 1083 1084 for (x = 0; x < numbuffs; x++) { 1085 netdev_printk(KERN_DEBUG, dev, "Packet %d: ", x); 1086 skb = lp->rx_skbuff[x]; 1087 for (i = 0; i < size; i++) 1088 pr_cont(" %02x", *(skb->data + i)); 1089 pr_cont("\n"); 1090 } 1091 } 1092 1093 x = 0; 1094 rc = 0; 1095 while (x < numbuffs && !rc) { 1096 skb = lp->rx_skbuff[x]; 1097 packet = lp->tx_skbuff[x]->data; 1098 for (i = 0; i < size; i++) { 1099 if (*(skb->data + i) != packet[i]) { 1100 netif_printk(lp, hw, KERN_DEBUG, dev, 1101 "Error in compare! %2x - %02x %02x\n", 1102 i, *(skb->data + i), packet[i]); 1103 rc = 1; 1104 break; 1105 } 1106 } 1107 x++; 1108 } 1109 1110 clean_up: 1111 *data1 = rc; 1112 pcnet32_purge_tx_ring(dev); 1113 1114 x = a->read_csr(ioaddr, CSR15); 1115 a->write_csr(ioaddr, CSR15, (x & ~0x0044)); /* reset bits 6 and 2 */ 1116 1117 x = a->read_bcr(ioaddr, 32); /* reset internal loopback */ 1118 a->write_bcr(ioaddr, 32, (x & ~0x0002)); 1119 1120 if (netif_running(dev)) { 1121 pcnet32_netif_start(dev); 1122 pcnet32_restart(dev, CSR0_NORMAL); 1123 } else { 1124 pcnet32_purge_rx_ring(dev); 1125 lp->a->write_bcr(ioaddr, 20, 4); /* return to 16bit mode */ 1126 } 1127 spin_unlock_irqrestore(&lp->lock, flags); 1128 1129 return rc; 1130 } /* end pcnet32_loopback_test */ 1131 1132 static int pcnet32_set_phys_id(struct net_device *dev, 1133 enum ethtool_phys_id_state state) 1134 { 1135 struct pcnet32_private *lp = netdev_priv(dev); 1136 const struct pcnet32_access *a = lp->a; 1137 ulong ioaddr = dev->base_addr; 1138 unsigned long flags; 1139 int i; 1140 1141 switch (state) { 1142 case ETHTOOL_ID_ACTIVE: 1143 /* Save the current value of the bcrs */ 1144 spin_lock_irqsave(&lp->lock, flags); 1145 for (i = 4; i < 8; i++) 1146 lp->save_regs[i - 4] = a->read_bcr(ioaddr, i); 1147 spin_unlock_irqrestore(&lp->lock, flags); 1148 return 2; /* cycle on/off twice per second */ 1149 1150 case ETHTOOL_ID_ON: 1151 case ETHTOOL_ID_OFF: 1152 /* Blink the led */ 1153 spin_lock_irqsave(&lp->lock, flags); 1154 for (i = 4; i < 8; i++) 1155 a->write_bcr(ioaddr, i, a->read_bcr(ioaddr, i) ^ 0x4000); 1156 spin_unlock_irqrestore(&lp->lock, flags); 1157 break; 1158 1159 case ETHTOOL_ID_INACTIVE: 1160 /* Restore the original value of the bcrs */ 1161 spin_lock_irqsave(&lp->lock, flags); 1162 for (i = 4; i < 8; i++) 1163 a->write_bcr(ioaddr, i, lp->save_regs[i - 4]); 1164 spin_unlock_irqrestore(&lp->lock, flags); 1165 } 1166 return 0; 1167 } 1168 1169 /* 1170 * process one receive descriptor entry 1171 */ 1172 1173 static void pcnet32_rx_entry(struct net_device *dev, 1174 struct pcnet32_private *lp, 1175 struct pcnet32_rx_head *rxp, 1176 int entry) 1177 { 1178 int status = (short)le16_to_cpu(rxp->status) >> 8; 1179 int rx_in_place = 0; 1180 struct sk_buff *skb; 1181 short pkt_len; 1182 1183 if (status != 0x03) { /* There was an error. */ 1184 /* 1185 * There is a tricky error noted by John Murphy, 1186 * <murf@perftech.com> to Russ Nelson: Even with full-sized 1187 * buffers it's possible for a jabber packet to use two 1188 * buffers, with only the last correctly noting the error. 1189 */ 1190 if (status & 0x01) /* Only count a general error at the */ 1191 dev->stats.rx_errors++; /* end of a packet. */ 1192 if (status & 0x20) 1193 dev->stats.rx_frame_errors++; 1194 if (status & 0x10) 1195 dev->stats.rx_over_errors++; 1196 if (status & 0x08) 1197 dev->stats.rx_crc_errors++; 1198 if (status & 0x04) 1199 dev->stats.rx_fifo_errors++; 1200 return; 1201 } 1202 1203 pkt_len = (le32_to_cpu(rxp->msg_length) & 0xfff) - 4; 1204 1205 /* Discard oversize frames. */ 1206 if (unlikely(pkt_len > PKT_BUF_SIZE)) { 1207 netif_err(lp, drv, dev, "Impossible packet size %d!\n", 1208 pkt_len); 1209 dev->stats.rx_errors++; 1210 return; 1211 } 1212 if (pkt_len < 60) { 1213 netif_err(lp, rx_err, dev, "Runt packet!\n"); 1214 dev->stats.rx_errors++; 1215 return; 1216 } 1217 1218 if (pkt_len > rx_copybreak) { 1219 struct sk_buff *newskb; 1220 dma_addr_t new_dma_addr; 1221 1222 newskb = netdev_alloc_skb(dev, PKT_BUF_SKB); 1223 /* 1224 * map the new buffer, if mapping fails, drop the packet and 1225 * reuse the old buffer 1226 */ 1227 if (newskb) { 1228 skb_reserve(newskb, NET_IP_ALIGN); 1229 new_dma_addr = pci_map_single(lp->pci_dev, 1230 newskb->data, 1231 PKT_BUF_SIZE, 1232 PCI_DMA_FROMDEVICE); 1233 if (pci_dma_mapping_error(lp->pci_dev, new_dma_addr)) { 1234 netif_err(lp, rx_err, dev, 1235 "DMA mapping error.\n"); 1236 dev_kfree_skb(newskb); 1237 skb = NULL; 1238 } else { 1239 skb = lp->rx_skbuff[entry]; 1240 pci_unmap_single(lp->pci_dev, 1241 lp->rx_dma_addr[entry], 1242 PKT_BUF_SIZE, 1243 PCI_DMA_FROMDEVICE); 1244 skb_put(skb, pkt_len); 1245 lp->rx_skbuff[entry] = newskb; 1246 lp->rx_dma_addr[entry] = new_dma_addr; 1247 rxp->base = cpu_to_le32(new_dma_addr); 1248 rx_in_place = 1; 1249 } 1250 } else 1251 skb = NULL; 1252 } else 1253 skb = netdev_alloc_skb(dev, pkt_len + NET_IP_ALIGN); 1254 1255 if (skb == NULL) { 1256 dev->stats.rx_dropped++; 1257 return; 1258 } 1259 if (!rx_in_place) { 1260 skb_reserve(skb, NET_IP_ALIGN); 1261 skb_put(skb, pkt_len); /* Make room */ 1262 pci_dma_sync_single_for_cpu(lp->pci_dev, 1263 lp->rx_dma_addr[entry], 1264 pkt_len, 1265 PCI_DMA_FROMDEVICE); 1266 skb_copy_to_linear_data(skb, 1267 (unsigned char *)(lp->rx_skbuff[entry]->data), 1268 pkt_len); 1269 pci_dma_sync_single_for_device(lp->pci_dev, 1270 lp->rx_dma_addr[entry], 1271 pkt_len, 1272 PCI_DMA_FROMDEVICE); 1273 } 1274 dev->stats.rx_bytes += skb->len; 1275 skb->protocol = eth_type_trans(skb, dev); 1276 netif_receive_skb(skb); 1277 dev->stats.rx_packets++; 1278 } 1279 1280 static int pcnet32_rx(struct net_device *dev, int budget) 1281 { 1282 struct pcnet32_private *lp = netdev_priv(dev); 1283 int entry = lp->cur_rx & lp->rx_mod_mask; 1284 struct pcnet32_rx_head *rxp = &lp->rx_ring[entry]; 1285 int npackets = 0; 1286 1287 /* If we own the next entry, it's a new packet. Send it up. */ 1288 while (npackets < budget && (short)le16_to_cpu(rxp->status) >= 0) { 1289 pcnet32_rx_entry(dev, lp, rxp, entry); 1290 npackets += 1; 1291 /* 1292 * The docs say that the buffer length isn't touched, but Andrew 1293 * Boyd of QNX reports that some revs of the 79C965 clear it. 1294 */ 1295 rxp->buf_length = cpu_to_le16(NEG_BUF_SIZE); 1296 wmb(); /* Make sure owner changes after others are visible */ 1297 rxp->status = cpu_to_le16(0x8000); 1298 entry = (++lp->cur_rx) & lp->rx_mod_mask; 1299 rxp = &lp->rx_ring[entry]; 1300 } 1301 1302 return npackets; 1303 } 1304 1305 static int pcnet32_tx(struct net_device *dev) 1306 { 1307 struct pcnet32_private *lp = netdev_priv(dev); 1308 unsigned int dirty_tx = lp->dirty_tx; 1309 int delta; 1310 int must_restart = 0; 1311 1312 while (dirty_tx != lp->cur_tx) { 1313 int entry = dirty_tx & lp->tx_mod_mask; 1314 int status = (short)le16_to_cpu(lp->tx_ring[entry].status); 1315 1316 if (status < 0) 1317 break; /* It still hasn't been Txed */ 1318 1319 lp->tx_ring[entry].base = 0; 1320 1321 if (status & 0x4000) { 1322 /* There was a major error, log it. */ 1323 int err_status = le32_to_cpu(lp->tx_ring[entry].misc); 1324 dev->stats.tx_errors++; 1325 netif_err(lp, tx_err, dev, 1326 "Tx error status=%04x err_status=%08x\n", 1327 status, err_status); 1328 if (err_status & 0x04000000) 1329 dev->stats.tx_aborted_errors++; 1330 if (err_status & 0x08000000) 1331 dev->stats.tx_carrier_errors++; 1332 if (err_status & 0x10000000) 1333 dev->stats.tx_window_errors++; 1334 #ifndef DO_DXSUFLO 1335 if (err_status & 0x40000000) { 1336 dev->stats.tx_fifo_errors++; 1337 /* Ackk! On FIFO errors the Tx unit is turned off! */ 1338 /* Remove this verbosity later! */ 1339 netif_err(lp, tx_err, dev, "Tx FIFO error!\n"); 1340 must_restart = 1; 1341 } 1342 #else 1343 if (err_status & 0x40000000) { 1344 dev->stats.tx_fifo_errors++; 1345 if (!lp->dxsuflo) { /* If controller doesn't recover ... */ 1346 /* Ackk! On FIFO errors the Tx unit is turned off! */ 1347 /* Remove this verbosity later! */ 1348 netif_err(lp, tx_err, dev, "Tx FIFO error!\n"); 1349 must_restart = 1; 1350 } 1351 } 1352 #endif 1353 } else { 1354 if (status & 0x1800) 1355 dev->stats.collisions++; 1356 dev->stats.tx_packets++; 1357 } 1358 1359 /* We must free the original skb */ 1360 if (lp->tx_skbuff[entry]) { 1361 pci_unmap_single(lp->pci_dev, 1362 lp->tx_dma_addr[entry], 1363 lp->tx_skbuff[entry]-> 1364 len, PCI_DMA_TODEVICE); 1365 dev_kfree_skb_any(lp->tx_skbuff[entry]); 1366 lp->tx_skbuff[entry] = NULL; 1367 lp->tx_dma_addr[entry] = 0; 1368 } 1369 dirty_tx++; 1370 } 1371 1372 delta = (lp->cur_tx - dirty_tx) & (lp->tx_mod_mask + lp->tx_ring_size); 1373 if (delta > lp->tx_ring_size) { 1374 netif_err(lp, drv, dev, "out-of-sync dirty pointer, %d vs. %d, full=%d\n", 1375 dirty_tx, lp->cur_tx, lp->tx_full); 1376 dirty_tx += lp->tx_ring_size; 1377 delta -= lp->tx_ring_size; 1378 } 1379 1380 if (lp->tx_full && 1381 netif_queue_stopped(dev) && 1382 delta < lp->tx_ring_size - 2) { 1383 /* The ring is no longer full, clear tbusy. */ 1384 lp->tx_full = 0; 1385 netif_wake_queue(dev); 1386 } 1387 lp->dirty_tx = dirty_tx; 1388 1389 return must_restart; 1390 } 1391 1392 static int pcnet32_poll(struct napi_struct *napi, int budget) 1393 { 1394 struct pcnet32_private *lp = container_of(napi, struct pcnet32_private, napi); 1395 struct net_device *dev = lp->dev; 1396 unsigned long ioaddr = dev->base_addr; 1397 unsigned long flags; 1398 int work_done; 1399 u16 val; 1400 1401 work_done = pcnet32_rx(dev, budget); 1402 1403 spin_lock_irqsave(&lp->lock, flags); 1404 if (pcnet32_tx(dev)) { 1405 /* reset the chip to clear the error condition, then restart */ 1406 lp->a->reset(ioaddr); 1407 lp->a->write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */ 1408 pcnet32_restart(dev, CSR0_START); 1409 netif_wake_queue(dev); 1410 } 1411 1412 if (work_done < budget && napi_complete_done(napi, work_done)) { 1413 /* clear interrupt masks */ 1414 val = lp->a->read_csr(ioaddr, CSR3); 1415 val &= 0x00ff; 1416 lp->a->write_csr(ioaddr, CSR3, val); 1417 1418 /* Set interrupt enable. */ 1419 lp->a->write_csr(ioaddr, CSR0, CSR0_INTEN); 1420 } 1421 1422 spin_unlock_irqrestore(&lp->lock, flags); 1423 return work_done; 1424 } 1425 1426 #define PCNET32_REGS_PER_PHY 32 1427 #define PCNET32_MAX_PHYS 32 1428 static int pcnet32_get_regs_len(struct net_device *dev) 1429 { 1430 struct pcnet32_private *lp = netdev_priv(dev); 1431 int j = lp->phycount * PCNET32_REGS_PER_PHY; 1432 1433 return (PCNET32_NUM_REGS + j) * sizeof(u16); 1434 } 1435 1436 static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1437 void *ptr) 1438 { 1439 int i, csr0; 1440 u16 *buff = ptr; 1441 struct pcnet32_private *lp = netdev_priv(dev); 1442 const struct pcnet32_access *a = lp->a; 1443 ulong ioaddr = dev->base_addr; 1444 unsigned long flags; 1445 1446 spin_lock_irqsave(&lp->lock, flags); 1447 1448 csr0 = a->read_csr(ioaddr, CSR0); 1449 if (!(csr0 & CSR0_STOP)) /* If not stopped */ 1450 pcnet32_suspend(dev, &flags, 1); 1451 1452 /* read address PROM */ 1453 for (i = 0; i < 16; i += 2) 1454 *buff++ = inw(ioaddr + i); 1455 1456 /* read control and status registers */ 1457 for (i = 0; i < 90; i++) 1458 *buff++ = a->read_csr(ioaddr, i); 1459 1460 *buff++ = a->read_csr(ioaddr, 112); 1461 *buff++ = a->read_csr(ioaddr, 114); 1462 1463 /* read bus configuration registers */ 1464 for (i = 0; i < 30; i++) 1465 *buff++ = a->read_bcr(ioaddr, i); 1466 1467 *buff++ = 0; /* skip bcr30 so as not to hang 79C976 */ 1468 1469 for (i = 31; i < 36; i++) 1470 *buff++ = a->read_bcr(ioaddr, i); 1471 1472 /* read mii phy registers */ 1473 if (lp->mii) { 1474 int j; 1475 for (j = 0; j < PCNET32_MAX_PHYS; j++) { 1476 if (lp->phymask & (1 << j)) { 1477 for (i = 0; i < PCNET32_REGS_PER_PHY; i++) { 1478 lp->a->write_bcr(ioaddr, 33, 1479 (j << 5) | i); 1480 *buff++ = lp->a->read_bcr(ioaddr, 34); 1481 } 1482 } 1483 } 1484 } 1485 1486 if (!(csr0 & CSR0_STOP)) /* If not stopped */ 1487 pcnet32_clr_suspend(lp, ioaddr); 1488 1489 spin_unlock_irqrestore(&lp->lock, flags); 1490 } 1491 1492 static const struct ethtool_ops pcnet32_ethtool_ops = { 1493 .get_drvinfo = pcnet32_get_drvinfo, 1494 .get_msglevel = pcnet32_get_msglevel, 1495 .set_msglevel = pcnet32_set_msglevel, 1496 .nway_reset = pcnet32_nway_reset, 1497 .get_link = pcnet32_get_link, 1498 .get_ringparam = pcnet32_get_ringparam, 1499 .set_ringparam = pcnet32_set_ringparam, 1500 .get_strings = pcnet32_get_strings, 1501 .self_test = pcnet32_ethtool_test, 1502 .set_phys_id = pcnet32_set_phys_id, 1503 .get_regs_len = pcnet32_get_regs_len, 1504 .get_regs = pcnet32_get_regs, 1505 .get_sset_count = pcnet32_get_sset_count, 1506 .get_link_ksettings = pcnet32_get_link_ksettings, 1507 .set_link_ksettings = pcnet32_set_link_ksettings, 1508 }; 1509 1510 /* only probes for non-PCI devices, the rest are handled by 1511 * pci_register_driver via pcnet32_probe_pci */ 1512 1513 static void pcnet32_probe_vlbus(unsigned int *pcnet32_portlist) 1514 { 1515 unsigned int *port, ioaddr; 1516 1517 /* search for PCnet32 VLB cards at known addresses */ 1518 for (port = pcnet32_portlist; (ioaddr = *port); port++) { 1519 if (request_region 1520 (ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_vlbus")) { 1521 /* check if there is really a pcnet chip on that ioaddr */ 1522 if ((inb(ioaddr + 14) == 0x57) && 1523 (inb(ioaddr + 15) == 0x57)) { 1524 pcnet32_probe1(ioaddr, 0, NULL); 1525 } else { 1526 release_region(ioaddr, PCNET32_TOTAL_SIZE); 1527 } 1528 } 1529 } 1530 } 1531 1532 static int 1533 pcnet32_probe_pci(struct pci_dev *pdev, const struct pci_device_id *ent) 1534 { 1535 unsigned long ioaddr; 1536 int err; 1537 1538 err = pci_enable_device(pdev); 1539 if (err < 0) { 1540 if (pcnet32_debug & NETIF_MSG_PROBE) 1541 pr_err("failed to enable device -- err=%d\n", err); 1542 return err; 1543 } 1544 pci_set_master(pdev); 1545 1546 ioaddr = pci_resource_start(pdev, 0); 1547 if (!ioaddr) { 1548 if (pcnet32_debug & NETIF_MSG_PROBE) 1549 pr_err("card has no PCI IO resources, aborting\n"); 1550 err = -ENODEV; 1551 goto err_disable_dev; 1552 } 1553 1554 err = pci_set_dma_mask(pdev, PCNET32_DMA_MASK); 1555 if (err) { 1556 if (pcnet32_debug & NETIF_MSG_PROBE) 1557 pr_err("architecture does not support 32bit PCI busmaster DMA\n"); 1558 goto err_disable_dev; 1559 } 1560 if (!request_region(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_pci")) { 1561 if (pcnet32_debug & NETIF_MSG_PROBE) 1562 pr_err("io address range already allocated\n"); 1563 err = -EBUSY; 1564 goto err_disable_dev; 1565 } 1566 1567 err = pcnet32_probe1(ioaddr, 1, pdev); 1568 1569 err_disable_dev: 1570 if (err < 0) 1571 pci_disable_device(pdev); 1572 1573 return err; 1574 } 1575 1576 static const struct net_device_ops pcnet32_netdev_ops = { 1577 .ndo_open = pcnet32_open, 1578 .ndo_stop = pcnet32_close, 1579 .ndo_start_xmit = pcnet32_start_xmit, 1580 .ndo_tx_timeout = pcnet32_tx_timeout, 1581 .ndo_get_stats = pcnet32_get_stats, 1582 .ndo_set_rx_mode = pcnet32_set_multicast_list, 1583 .ndo_do_ioctl = pcnet32_ioctl, 1584 .ndo_set_mac_address = eth_mac_addr, 1585 .ndo_validate_addr = eth_validate_addr, 1586 #ifdef CONFIG_NET_POLL_CONTROLLER 1587 .ndo_poll_controller = pcnet32_poll_controller, 1588 #endif 1589 }; 1590 1591 /* pcnet32_probe1 1592 * Called from both pcnet32_probe_vlbus and pcnet_probe_pci. 1593 * pdev will be NULL when called from pcnet32_probe_vlbus. 1594 */ 1595 static int 1596 pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev) 1597 { 1598 struct pcnet32_private *lp; 1599 int i, media; 1600 int fdx, mii, fset, dxsuflo, sram; 1601 int chip_version; 1602 char *chipname; 1603 struct net_device *dev; 1604 const struct pcnet32_access *a = NULL; 1605 u8 promaddr[ETH_ALEN]; 1606 int ret = -ENODEV; 1607 1608 /* reset the chip */ 1609 pcnet32_wio_reset(ioaddr); 1610 1611 /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */ 1612 if (pcnet32_wio_read_csr(ioaddr, 0) == 4 && pcnet32_wio_check(ioaddr)) { 1613 a = &pcnet32_wio; 1614 } else { 1615 pcnet32_dwio_reset(ioaddr); 1616 if (pcnet32_dwio_read_csr(ioaddr, 0) == 4 && 1617 pcnet32_dwio_check(ioaddr)) { 1618 a = &pcnet32_dwio; 1619 } else { 1620 if (pcnet32_debug & NETIF_MSG_PROBE) 1621 pr_err("No access methods\n"); 1622 goto err_release_region; 1623 } 1624 } 1625 1626 chip_version = 1627 a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr, 89) << 16); 1628 if ((pcnet32_debug & NETIF_MSG_PROBE) && (pcnet32_debug & NETIF_MSG_HW)) 1629 pr_info(" PCnet chip version is %#x\n", chip_version); 1630 if ((chip_version & 0xfff) != 0x003) { 1631 if (pcnet32_debug & NETIF_MSG_PROBE) 1632 pr_info("Unsupported chip version\n"); 1633 goto err_release_region; 1634 } 1635 1636 /* initialize variables */ 1637 fdx = mii = fset = dxsuflo = sram = 0; 1638 chip_version = (chip_version >> 12) & 0xffff; 1639 1640 switch (chip_version) { 1641 case 0x2420: 1642 chipname = "PCnet/PCI 79C970"; /* PCI */ 1643 break; 1644 case 0x2430: 1645 if (shared) 1646 chipname = "PCnet/PCI 79C970"; /* 970 gives the wrong chip id back */ 1647 else 1648 chipname = "PCnet/32 79C965"; /* 486/VL bus */ 1649 break; 1650 case 0x2621: 1651 chipname = "PCnet/PCI II 79C970A"; /* PCI */ 1652 fdx = 1; 1653 break; 1654 case 0x2623: 1655 chipname = "PCnet/FAST 79C971"; /* PCI */ 1656 fdx = 1; 1657 mii = 1; 1658 fset = 1; 1659 break; 1660 case 0x2624: 1661 chipname = "PCnet/FAST+ 79C972"; /* PCI */ 1662 fdx = 1; 1663 mii = 1; 1664 fset = 1; 1665 break; 1666 case 0x2625: 1667 chipname = "PCnet/FAST III 79C973"; /* PCI */ 1668 fdx = 1; 1669 mii = 1; 1670 sram = 1; 1671 break; 1672 case 0x2626: 1673 chipname = "PCnet/Home 79C978"; /* PCI */ 1674 fdx = 1; 1675 /* 1676 * This is based on specs published at www.amd.com. This section 1677 * assumes that a card with a 79C978 wants to go into standard 1678 * ethernet mode. The 79C978 can also go into 1Mb HomePNA mode, 1679 * and the module option homepna=1 can select this instead. 1680 */ 1681 media = a->read_bcr(ioaddr, 49); 1682 media &= ~3; /* default to 10Mb ethernet */ 1683 if (cards_found < MAX_UNITS && homepna[cards_found]) 1684 media |= 1; /* switch to home wiring mode */ 1685 if (pcnet32_debug & NETIF_MSG_PROBE) 1686 printk(KERN_DEBUG PFX "media set to %sMbit mode\n", 1687 (media & 1) ? "1" : "10"); 1688 a->write_bcr(ioaddr, 49, media); 1689 break; 1690 case 0x2627: 1691 chipname = "PCnet/FAST III 79C975"; /* PCI */ 1692 fdx = 1; 1693 mii = 1; 1694 sram = 1; 1695 break; 1696 case 0x2628: 1697 chipname = "PCnet/PRO 79C976"; 1698 fdx = 1; 1699 mii = 1; 1700 break; 1701 default: 1702 if (pcnet32_debug & NETIF_MSG_PROBE) 1703 pr_info("PCnet version %#x, no PCnet32 chip\n", 1704 chip_version); 1705 goto err_release_region; 1706 } 1707 1708 /* 1709 * On selected chips turn on the BCR18:NOUFLO bit. This stops transmit 1710 * starting until the packet is loaded. Strike one for reliability, lose 1711 * one for latency - although on PCI this isn't a big loss. Older chips 1712 * have FIFO's smaller than a packet, so you can't do this. 1713 * Turn on BCR18:BurstRdEn and BCR18:BurstWrEn. 1714 */ 1715 1716 if (fset) { 1717 a->write_bcr(ioaddr, 18, (a->read_bcr(ioaddr, 18) | 0x0860)); 1718 a->write_csr(ioaddr, 80, 1719 (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00); 1720 dxsuflo = 1; 1721 } 1722 1723 /* 1724 * The Am79C973/Am79C975 controllers come with 12K of SRAM 1725 * which we can use for the Tx/Rx buffers but most importantly, 1726 * the use of SRAM allow us to use the BCR18:NOUFLO bit to avoid 1727 * Tx fifo underflows. 1728 */ 1729 if (sram) { 1730 /* 1731 * The SRAM is being configured in two steps. First we 1732 * set the SRAM size in the BCR25:SRAM_SIZE bits. According 1733 * to the datasheet, each bit corresponds to a 512-byte 1734 * page so we can have at most 24 pages. The SRAM_SIZE 1735 * holds the value of the upper 8 bits of the 16-bit SRAM size. 1736 * The low 8-bits start at 0x00 and end at 0xff. So the 1737 * address range is from 0x0000 up to 0x17ff. Therefore, 1738 * the SRAM_SIZE is set to 0x17. The next step is to set 1739 * the BCR26:SRAM_BND midway through so the Tx and Rx 1740 * buffers can share the SRAM equally. 1741 */ 1742 a->write_bcr(ioaddr, 25, 0x17); 1743 a->write_bcr(ioaddr, 26, 0xc); 1744 /* And finally enable the NOUFLO bit */ 1745 a->write_bcr(ioaddr, 18, a->read_bcr(ioaddr, 18) | (1 << 11)); 1746 } 1747 1748 dev = alloc_etherdev(sizeof(*lp)); 1749 if (!dev) { 1750 ret = -ENOMEM; 1751 goto err_release_region; 1752 } 1753 1754 if (pdev) 1755 SET_NETDEV_DEV(dev, &pdev->dev); 1756 1757 if (pcnet32_debug & NETIF_MSG_PROBE) 1758 pr_info("%s at %#3lx,", chipname, ioaddr); 1759 1760 /* In most chips, after a chip reset, the ethernet address is read from the 1761 * station address PROM at the base address and programmed into the 1762 * "Physical Address Registers" CSR12-14. 1763 * As a precautionary measure, we read the PROM values and complain if 1764 * they disagree with the CSRs. If they miscompare, and the PROM addr 1765 * is valid, then the PROM addr is used. 1766 */ 1767 for (i = 0; i < 3; i++) { 1768 unsigned int val; 1769 val = a->read_csr(ioaddr, i + 12) & 0x0ffff; 1770 /* There may be endianness issues here. */ 1771 dev->dev_addr[2 * i] = val & 0x0ff; 1772 dev->dev_addr[2 * i + 1] = (val >> 8) & 0x0ff; 1773 } 1774 1775 /* read PROM address and compare with CSR address */ 1776 for (i = 0; i < ETH_ALEN; i++) 1777 promaddr[i] = inb(ioaddr + i); 1778 1779 if (!ether_addr_equal(promaddr, dev->dev_addr) || 1780 !is_valid_ether_addr(dev->dev_addr)) { 1781 if (is_valid_ether_addr(promaddr)) { 1782 if (pcnet32_debug & NETIF_MSG_PROBE) { 1783 pr_cont(" warning: CSR address invalid,\n"); 1784 pr_info(" using instead PROM address of"); 1785 } 1786 memcpy(dev->dev_addr, promaddr, ETH_ALEN); 1787 } 1788 } 1789 1790 /* if the ethernet address is not valid, force to 00:00:00:00:00:00 */ 1791 if (!is_valid_ether_addr(dev->dev_addr)) 1792 eth_zero_addr(dev->dev_addr); 1793 1794 if (pcnet32_debug & NETIF_MSG_PROBE) { 1795 pr_cont(" %pM", dev->dev_addr); 1796 1797 /* Version 0x2623 and 0x2624 */ 1798 if (((chip_version + 1) & 0xfffe) == 0x2624) { 1799 i = a->read_csr(ioaddr, 80) & 0x0C00; /* Check tx_start_pt */ 1800 pr_info(" tx_start_pt(0x%04x):", i); 1801 switch (i >> 10) { 1802 case 0: 1803 pr_cont(" 20 bytes,"); 1804 break; 1805 case 1: 1806 pr_cont(" 64 bytes,"); 1807 break; 1808 case 2: 1809 pr_cont(" 128 bytes,"); 1810 break; 1811 case 3: 1812 pr_cont("~220 bytes,"); 1813 break; 1814 } 1815 i = a->read_bcr(ioaddr, 18); /* Check Burst/Bus control */ 1816 pr_cont(" BCR18(%x):", i & 0xffff); 1817 if (i & (1 << 5)) 1818 pr_cont("BurstWrEn "); 1819 if (i & (1 << 6)) 1820 pr_cont("BurstRdEn "); 1821 if (i & (1 << 7)) 1822 pr_cont("DWordIO "); 1823 if (i & (1 << 11)) 1824 pr_cont("NoUFlow "); 1825 i = a->read_bcr(ioaddr, 25); 1826 pr_info(" SRAMSIZE=0x%04x,", i << 8); 1827 i = a->read_bcr(ioaddr, 26); 1828 pr_cont(" SRAM_BND=0x%04x,", i << 8); 1829 i = a->read_bcr(ioaddr, 27); 1830 if (i & (1 << 14)) 1831 pr_cont("LowLatRx"); 1832 } 1833 } 1834 1835 dev->base_addr = ioaddr; 1836 lp = netdev_priv(dev); 1837 /* pci_alloc_consistent returns page-aligned memory, so we do not have to check the alignment */ 1838 lp->init_block = pci_alloc_consistent(pdev, sizeof(*lp->init_block), 1839 &lp->init_dma_addr); 1840 if (!lp->init_block) { 1841 if (pcnet32_debug & NETIF_MSG_PROBE) 1842 pr_err("Consistent memory allocation failed\n"); 1843 ret = -ENOMEM; 1844 goto err_free_netdev; 1845 } 1846 lp->pci_dev = pdev; 1847 1848 lp->dev = dev; 1849 1850 spin_lock_init(&lp->lock); 1851 1852 lp->name = chipname; 1853 lp->shared_irq = shared; 1854 lp->tx_ring_size = TX_RING_SIZE; /* default tx ring size */ 1855 lp->rx_ring_size = RX_RING_SIZE; /* default rx ring size */ 1856 lp->tx_mod_mask = lp->tx_ring_size - 1; 1857 lp->rx_mod_mask = lp->rx_ring_size - 1; 1858 lp->tx_len_bits = (PCNET32_LOG_TX_BUFFERS << 12); 1859 lp->rx_len_bits = (PCNET32_LOG_RX_BUFFERS << 4); 1860 lp->mii_if.full_duplex = fdx; 1861 lp->mii_if.phy_id_mask = 0x1f; 1862 lp->mii_if.reg_num_mask = 0x1f; 1863 lp->dxsuflo = dxsuflo; 1864 lp->mii = mii; 1865 lp->chip_version = chip_version; 1866 lp->msg_enable = pcnet32_debug; 1867 if ((cards_found >= MAX_UNITS) || 1868 (options[cards_found] >= sizeof(options_mapping))) 1869 lp->options = PCNET32_PORT_ASEL; 1870 else 1871 lp->options = options_mapping[options[cards_found]]; 1872 /* force default port to TP on 79C970A so link detection can work */ 1873 if (lp->chip_version == PCNET32_79C970A) 1874 lp->options = PCNET32_PORT_10BT; 1875 lp->mii_if.dev = dev; 1876 lp->mii_if.mdio_read = mdio_read; 1877 lp->mii_if.mdio_write = mdio_write; 1878 1879 /* napi.weight is used in both the napi and non-napi cases */ 1880 lp->napi.weight = lp->rx_ring_size / 2; 1881 1882 netif_napi_add(dev, &lp->napi, pcnet32_poll, lp->rx_ring_size / 2); 1883 1884 if (fdx && !(lp->options & PCNET32_PORT_ASEL) && 1885 ((cards_found >= MAX_UNITS) || full_duplex[cards_found])) 1886 lp->options |= PCNET32_PORT_FD; 1887 1888 lp->a = a; 1889 1890 /* prior to register_netdev, dev->name is not yet correct */ 1891 if (pcnet32_alloc_ring(dev, pci_name(lp->pci_dev))) { 1892 ret = -ENOMEM; 1893 goto err_free_ring; 1894 } 1895 /* detect special T1/E1 WAN card by checking for MAC address */ 1896 if (dev->dev_addr[0] == 0x00 && dev->dev_addr[1] == 0xe0 && 1897 dev->dev_addr[2] == 0x75) 1898 lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI; 1899 1900 lp->init_block->mode = cpu_to_le16(0x0003); /* Disable Rx and Tx. */ 1901 lp->init_block->tlen_rlen = 1902 cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits); 1903 for (i = 0; i < 6; i++) 1904 lp->init_block->phys_addr[i] = dev->dev_addr[i]; 1905 lp->init_block->filter[0] = 0x00000000; 1906 lp->init_block->filter[1] = 0x00000000; 1907 lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr); 1908 lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr); 1909 1910 /* switch pcnet32 to 32bit mode */ 1911 a->write_bcr(ioaddr, 20, 2); 1912 1913 a->write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff)); 1914 a->write_csr(ioaddr, 2, (lp->init_dma_addr >> 16)); 1915 1916 if (pdev) { /* use the IRQ provided by PCI */ 1917 dev->irq = pdev->irq; 1918 if (pcnet32_debug & NETIF_MSG_PROBE) 1919 pr_cont(" assigned IRQ %d\n", dev->irq); 1920 } else { 1921 unsigned long irq_mask = probe_irq_on(); 1922 1923 /* 1924 * To auto-IRQ we enable the initialization-done and DMA error 1925 * interrupts. For ISA boards we get a DMA error, but VLB and PCI 1926 * boards will work. 1927 */ 1928 /* Trigger an initialization just for the interrupt. */ 1929 a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_INIT); 1930 mdelay(1); 1931 1932 dev->irq = probe_irq_off(irq_mask); 1933 if (!dev->irq) { 1934 if (pcnet32_debug & NETIF_MSG_PROBE) 1935 pr_cont(", failed to detect IRQ line\n"); 1936 ret = -ENODEV; 1937 goto err_free_ring; 1938 } 1939 if (pcnet32_debug & NETIF_MSG_PROBE) 1940 pr_cont(", probed IRQ %d\n", dev->irq); 1941 } 1942 1943 /* Set the mii phy_id so that we can query the link state */ 1944 if (lp->mii) { 1945 /* lp->phycount and lp->phymask are set to 0 by memset above */ 1946 1947 lp->mii_if.phy_id = ((lp->a->read_bcr(ioaddr, 33)) >> 5) & 0x1f; 1948 /* scan for PHYs */ 1949 for (i = 0; i < PCNET32_MAX_PHYS; i++) { 1950 unsigned short id1, id2; 1951 1952 id1 = mdio_read(dev, i, MII_PHYSID1); 1953 if (id1 == 0xffff) 1954 continue; 1955 id2 = mdio_read(dev, i, MII_PHYSID2); 1956 if (id2 == 0xffff) 1957 continue; 1958 if (i == 31 && ((chip_version + 1) & 0xfffe) == 0x2624) 1959 continue; /* 79C971 & 79C972 have phantom phy at id 31 */ 1960 lp->phycount++; 1961 lp->phymask |= (1 << i); 1962 lp->mii_if.phy_id = i; 1963 if (pcnet32_debug & NETIF_MSG_PROBE) 1964 pr_info("Found PHY %04x:%04x at address %d\n", 1965 id1, id2, i); 1966 } 1967 lp->a->write_bcr(ioaddr, 33, (lp->mii_if.phy_id) << 5); 1968 if (lp->phycount > 1) 1969 lp->options |= PCNET32_PORT_MII; 1970 } 1971 1972 timer_setup(&lp->watchdog_timer, pcnet32_watchdog, 0); 1973 1974 /* The PCNET32-specific entries in the device structure. */ 1975 dev->netdev_ops = &pcnet32_netdev_ops; 1976 dev->ethtool_ops = &pcnet32_ethtool_ops; 1977 dev->watchdog_timeo = (5 * HZ); 1978 1979 /* Fill in the generic fields of the device structure. */ 1980 if (register_netdev(dev)) 1981 goto err_free_ring; 1982 1983 if (pdev) { 1984 pci_set_drvdata(pdev, dev); 1985 } else { 1986 lp->next = pcnet32_dev; 1987 pcnet32_dev = dev; 1988 } 1989 1990 if (pcnet32_debug & NETIF_MSG_PROBE) 1991 pr_info("%s: registered as %s\n", dev->name, lp->name); 1992 cards_found++; 1993 1994 /* enable LED writes */ 1995 a->write_bcr(ioaddr, 2, a->read_bcr(ioaddr, 2) | 0x1000); 1996 1997 return 0; 1998 1999 err_free_ring: 2000 pcnet32_free_ring(dev); 2001 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block), 2002 lp->init_block, lp->init_dma_addr); 2003 err_free_netdev: 2004 free_netdev(dev); 2005 err_release_region: 2006 release_region(ioaddr, PCNET32_TOTAL_SIZE); 2007 return ret; 2008 } 2009 2010 /* if any allocation fails, caller must also call pcnet32_free_ring */ 2011 static int pcnet32_alloc_ring(struct net_device *dev, const char *name) 2012 { 2013 struct pcnet32_private *lp = netdev_priv(dev); 2014 2015 lp->tx_ring = pci_alloc_consistent(lp->pci_dev, 2016 sizeof(struct pcnet32_tx_head) * 2017 lp->tx_ring_size, 2018 &lp->tx_ring_dma_addr); 2019 if (lp->tx_ring == NULL) { 2020 netif_err(lp, drv, dev, "Consistent memory allocation failed\n"); 2021 return -ENOMEM; 2022 } 2023 2024 lp->rx_ring = pci_alloc_consistent(lp->pci_dev, 2025 sizeof(struct pcnet32_rx_head) * 2026 lp->rx_ring_size, 2027 &lp->rx_ring_dma_addr); 2028 if (lp->rx_ring == NULL) { 2029 netif_err(lp, drv, dev, "Consistent memory allocation failed\n"); 2030 return -ENOMEM; 2031 } 2032 2033 lp->tx_dma_addr = kcalloc(lp->tx_ring_size, sizeof(dma_addr_t), 2034 GFP_KERNEL); 2035 if (!lp->tx_dma_addr) 2036 return -ENOMEM; 2037 2038 lp->rx_dma_addr = kcalloc(lp->rx_ring_size, sizeof(dma_addr_t), 2039 GFP_KERNEL); 2040 if (!lp->rx_dma_addr) 2041 return -ENOMEM; 2042 2043 lp->tx_skbuff = kcalloc(lp->tx_ring_size, sizeof(struct sk_buff *), 2044 GFP_KERNEL); 2045 if (!lp->tx_skbuff) 2046 return -ENOMEM; 2047 2048 lp->rx_skbuff = kcalloc(lp->rx_ring_size, sizeof(struct sk_buff *), 2049 GFP_KERNEL); 2050 if (!lp->rx_skbuff) 2051 return -ENOMEM; 2052 2053 return 0; 2054 } 2055 2056 static void pcnet32_free_ring(struct net_device *dev) 2057 { 2058 struct pcnet32_private *lp = netdev_priv(dev); 2059 2060 kfree(lp->tx_skbuff); 2061 lp->tx_skbuff = NULL; 2062 2063 kfree(lp->rx_skbuff); 2064 lp->rx_skbuff = NULL; 2065 2066 kfree(lp->tx_dma_addr); 2067 lp->tx_dma_addr = NULL; 2068 2069 kfree(lp->rx_dma_addr); 2070 lp->rx_dma_addr = NULL; 2071 2072 if (lp->tx_ring) { 2073 pci_free_consistent(lp->pci_dev, 2074 sizeof(struct pcnet32_tx_head) * 2075 lp->tx_ring_size, lp->tx_ring, 2076 lp->tx_ring_dma_addr); 2077 lp->tx_ring = NULL; 2078 } 2079 2080 if (lp->rx_ring) { 2081 pci_free_consistent(lp->pci_dev, 2082 sizeof(struct pcnet32_rx_head) * 2083 lp->rx_ring_size, lp->rx_ring, 2084 lp->rx_ring_dma_addr); 2085 lp->rx_ring = NULL; 2086 } 2087 } 2088 2089 static int pcnet32_open(struct net_device *dev) 2090 { 2091 struct pcnet32_private *lp = netdev_priv(dev); 2092 struct pci_dev *pdev = lp->pci_dev; 2093 unsigned long ioaddr = dev->base_addr; 2094 u16 val; 2095 int i; 2096 int rc; 2097 unsigned long flags; 2098 2099 if (request_irq(dev->irq, pcnet32_interrupt, 2100 lp->shared_irq ? IRQF_SHARED : 0, dev->name, 2101 (void *)dev)) { 2102 return -EAGAIN; 2103 } 2104 2105 spin_lock_irqsave(&lp->lock, flags); 2106 /* Check for a valid station address */ 2107 if (!is_valid_ether_addr(dev->dev_addr)) { 2108 rc = -EINVAL; 2109 goto err_free_irq; 2110 } 2111 2112 /* Reset the PCNET32 */ 2113 lp->a->reset(ioaddr); 2114 2115 /* switch pcnet32 to 32bit mode */ 2116 lp->a->write_bcr(ioaddr, 20, 2); 2117 2118 netif_printk(lp, ifup, KERN_DEBUG, dev, 2119 "%s() irq %d tx/rx rings %#x/%#x init %#x\n", 2120 __func__, dev->irq, (u32) (lp->tx_ring_dma_addr), 2121 (u32) (lp->rx_ring_dma_addr), 2122 (u32) (lp->init_dma_addr)); 2123 2124 lp->autoneg = !!(lp->options & PCNET32_PORT_ASEL); 2125 lp->port_tp = !!(lp->options & PCNET32_PORT_10BT); 2126 lp->fdx = !!(lp->options & PCNET32_PORT_FD); 2127 2128 /* set/reset autoselect bit */ 2129 val = lp->a->read_bcr(ioaddr, 2) & ~2; 2130 if (lp->options & PCNET32_PORT_ASEL) 2131 val |= 2; 2132 lp->a->write_bcr(ioaddr, 2, val); 2133 2134 /* handle full duplex setting */ 2135 if (lp->mii_if.full_duplex) { 2136 val = lp->a->read_bcr(ioaddr, 9) & ~3; 2137 if (lp->options & PCNET32_PORT_FD) { 2138 val |= 1; 2139 if (lp->options == (PCNET32_PORT_FD | PCNET32_PORT_AUI)) 2140 val |= 2; 2141 } else if (lp->options & PCNET32_PORT_ASEL) { 2142 /* workaround of xSeries250, turn on for 79C975 only */ 2143 if (lp->chip_version == 0x2627) 2144 val |= 3; 2145 } 2146 lp->a->write_bcr(ioaddr, 9, val); 2147 } 2148 2149 /* set/reset GPSI bit in test register */ 2150 val = lp->a->read_csr(ioaddr, 124) & ~0x10; 2151 if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI) 2152 val |= 0x10; 2153 lp->a->write_csr(ioaddr, 124, val); 2154 2155 /* Allied Telesyn AT 2700/2701 FX are 100Mbit only and do not negotiate */ 2156 if (pdev && pdev->subsystem_vendor == PCI_VENDOR_ID_AT && 2157 (pdev->subsystem_device == PCI_SUBDEVICE_ID_AT_2700FX || 2158 pdev->subsystem_device == PCI_SUBDEVICE_ID_AT_2701FX)) { 2159 if (lp->options & PCNET32_PORT_ASEL) { 2160 lp->options = PCNET32_PORT_FD | PCNET32_PORT_100; 2161 netif_printk(lp, link, KERN_DEBUG, dev, 2162 "Setting 100Mb-Full Duplex\n"); 2163 } 2164 } 2165 if (lp->phycount < 2) { 2166 /* 2167 * 24 Jun 2004 according AMD, in order to change the PHY, 2168 * DANAS (or DISPM for 79C976) must be set; then select the speed, 2169 * duplex, and/or enable auto negotiation, and clear DANAS 2170 */ 2171 if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) { 2172 lp->a->write_bcr(ioaddr, 32, 2173 lp->a->read_bcr(ioaddr, 32) | 0x0080); 2174 /* disable Auto Negotiation, set 10Mpbs, HD */ 2175 val = lp->a->read_bcr(ioaddr, 32) & ~0xb8; 2176 if (lp->options & PCNET32_PORT_FD) 2177 val |= 0x10; 2178 if (lp->options & PCNET32_PORT_100) 2179 val |= 0x08; 2180 lp->a->write_bcr(ioaddr, 32, val); 2181 } else { 2182 if (lp->options & PCNET32_PORT_ASEL) { 2183 lp->a->write_bcr(ioaddr, 32, 2184 lp->a->read_bcr(ioaddr, 2185 32) | 0x0080); 2186 /* enable auto negotiate, setup, disable fd */ 2187 val = lp->a->read_bcr(ioaddr, 32) & ~0x98; 2188 val |= 0x20; 2189 lp->a->write_bcr(ioaddr, 32, val); 2190 } 2191 } 2192 } else { 2193 int first_phy = -1; 2194 u16 bmcr; 2195 u32 bcr9; 2196 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET }; 2197 2198 /* 2199 * There is really no good other way to handle multiple PHYs 2200 * other than turning off all automatics 2201 */ 2202 val = lp->a->read_bcr(ioaddr, 2); 2203 lp->a->write_bcr(ioaddr, 2, val & ~2); 2204 val = lp->a->read_bcr(ioaddr, 32); 2205 lp->a->write_bcr(ioaddr, 32, val & ~(1 << 7)); /* stop MII manager */ 2206 2207 if (!(lp->options & PCNET32_PORT_ASEL)) { 2208 /* setup ecmd */ 2209 ecmd.port = PORT_MII; 2210 ecmd.transceiver = XCVR_INTERNAL; 2211 ecmd.autoneg = AUTONEG_DISABLE; 2212 ethtool_cmd_speed_set(&ecmd, 2213 (lp->options & PCNET32_PORT_100) ? 2214 SPEED_100 : SPEED_10); 2215 bcr9 = lp->a->read_bcr(ioaddr, 9); 2216 2217 if (lp->options & PCNET32_PORT_FD) { 2218 ecmd.duplex = DUPLEX_FULL; 2219 bcr9 |= (1 << 0); 2220 } else { 2221 ecmd.duplex = DUPLEX_HALF; 2222 bcr9 |= ~(1 << 0); 2223 } 2224 lp->a->write_bcr(ioaddr, 9, bcr9); 2225 } 2226 2227 for (i = 0; i < PCNET32_MAX_PHYS; i++) { 2228 if (lp->phymask & (1 << i)) { 2229 /* isolate all but the first PHY */ 2230 bmcr = mdio_read(dev, i, MII_BMCR); 2231 if (first_phy == -1) { 2232 first_phy = i; 2233 mdio_write(dev, i, MII_BMCR, 2234 bmcr & ~BMCR_ISOLATE); 2235 } else { 2236 mdio_write(dev, i, MII_BMCR, 2237 bmcr | BMCR_ISOLATE); 2238 } 2239 /* use mii_ethtool_sset to setup PHY */ 2240 lp->mii_if.phy_id = i; 2241 ecmd.phy_address = i; 2242 if (lp->options & PCNET32_PORT_ASEL) { 2243 mii_ethtool_gset(&lp->mii_if, &ecmd); 2244 ecmd.autoneg = AUTONEG_ENABLE; 2245 } 2246 mii_ethtool_sset(&lp->mii_if, &ecmd); 2247 } 2248 } 2249 lp->mii_if.phy_id = first_phy; 2250 netif_info(lp, link, dev, "Using PHY number %d\n", first_phy); 2251 } 2252 2253 #ifdef DO_DXSUFLO 2254 if (lp->dxsuflo) { /* Disable transmit stop on underflow */ 2255 val = lp->a->read_csr(ioaddr, CSR3); 2256 val |= 0x40; 2257 lp->a->write_csr(ioaddr, CSR3, val); 2258 } 2259 #endif 2260 2261 lp->init_block->mode = 2262 cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7); 2263 pcnet32_load_multicast(dev); 2264 2265 if (pcnet32_init_ring(dev)) { 2266 rc = -ENOMEM; 2267 goto err_free_ring; 2268 } 2269 2270 napi_enable(&lp->napi); 2271 2272 /* Re-initialize the PCNET32, and start it when done. */ 2273 lp->a->write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff)); 2274 lp->a->write_csr(ioaddr, 2, (lp->init_dma_addr >> 16)); 2275 2276 lp->a->write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */ 2277 lp->a->write_csr(ioaddr, CSR0, CSR0_INIT); 2278 2279 netif_start_queue(dev); 2280 2281 if (lp->chip_version >= PCNET32_79C970A) { 2282 /* Print the link status and start the watchdog */ 2283 pcnet32_check_media(dev, 1); 2284 mod_timer(&lp->watchdog_timer, PCNET32_WATCHDOG_TIMEOUT); 2285 } 2286 2287 i = 0; 2288 while (i++ < 100) 2289 if (lp->a->read_csr(ioaddr, CSR0) & CSR0_IDON) 2290 break; 2291 /* 2292 * We used to clear the InitDone bit, 0x0100, here but Mark Stockton 2293 * reports that doing so triggers a bug in the '974. 2294 */ 2295 lp->a->write_csr(ioaddr, CSR0, CSR0_NORMAL); 2296 2297 netif_printk(lp, ifup, KERN_DEBUG, dev, 2298 "pcnet32 open after %d ticks, init block %#x csr0 %4.4x\n", 2299 i, 2300 (u32) (lp->init_dma_addr), 2301 lp->a->read_csr(ioaddr, CSR0)); 2302 2303 spin_unlock_irqrestore(&lp->lock, flags); 2304 2305 return 0; /* Always succeed */ 2306 2307 err_free_ring: 2308 /* free any allocated skbuffs */ 2309 pcnet32_purge_rx_ring(dev); 2310 2311 /* 2312 * Switch back to 16bit mode to avoid problems with dumb 2313 * DOS packet driver after a warm reboot 2314 */ 2315 lp->a->write_bcr(ioaddr, 20, 4); 2316 2317 err_free_irq: 2318 spin_unlock_irqrestore(&lp->lock, flags); 2319 free_irq(dev->irq, dev); 2320 return rc; 2321 } 2322 2323 /* 2324 * The LANCE has been halted for one reason or another (busmaster memory 2325 * arbitration error, Tx FIFO underflow, driver stopped it to reconfigure, 2326 * etc.). Modern LANCE variants always reload their ring-buffer 2327 * configuration when restarted, so we must reinitialize our ring 2328 * context before restarting. As part of this reinitialization, 2329 * find all packets still on the Tx ring and pretend that they had been 2330 * sent (in effect, drop the packets on the floor) - the higher-level 2331 * protocols will time out and retransmit. It'd be better to shuffle 2332 * these skbs to a temp list and then actually re-Tx them after 2333 * restarting the chip, but I'm too lazy to do so right now. dplatt@3do.com 2334 */ 2335 2336 static void pcnet32_purge_tx_ring(struct net_device *dev) 2337 { 2338 struct pcnet32_private *lp = netdev_priv(dev); 2339 int i; 2340 2341 for (i = 0; i < lp->tx_ring_size; i++) { 2342 lp->tx_ring[i].status = 0; /* CPU owns buffer */ 2343 wmb(); /* Make sure adapter sees owner change */ 2344 if (lp->tx_skbuff[i]) { 2345 if (!pci_dma_mapping_error(lp->pci_dev, 2346 lp->tx_dma_addr[i])) 2347 pci_unmap_single(lp->pci_dev, 2348 lp->tx_dma_addr[i], 2349 lp->tx_skbuff[i]->len, 2350 PCI_DMA_TODEVICE); 2351 dev_kfree_skb_any(lp->tx_skbuff[i]); 2352 } 2353 lp->tx_skbuff[i] = NULL; 2354 lp->tx_dma_addr[i] = 0; 2355 } 2356 } 2357 2358 /* Initialize the PCNET32 Rx and Tx rings. */ 2359 static int pcnet32_init_ring(struct net_device *dev) 2360 { 2361 struct pcnet32_private *lp = netdev_priv(dev); 2362 int i; 2363 2364 lp->tx_full = 0; 2365 lp->cur_rx = lp->cur_tx = 0; 2366 lp->dirty_rx = lp->dirty_tx = 0; 2367 2368 for (i = 0; i < lp->rx_ring_size; i++) { 2369 struct sk_buff *rx_skbuff = lp->rx_skbuff[i]; 2370 if (rx_skbuff == NULL) { 2371 lp->rx_skbuff[i] = netdev_alloc_skb(dev, PKT_BUF_SKB); 2372 rx_skbuff = lp->rx_skbuff[i]; 2373 if (!rx_skbuff) { 2374 /* there is not much we can do at this point */ 2375 netif_err(lp, drv, dev, "%s netdev_alloc_skb failed\n", 2376 __func__); 2377 return -1; 2378 } 2379 skb_reserve(rx_skbuff, NET_IP_ALIGN); 2380 } 2381 2382 rmb(); 2383 if (lp->rx_dma_addr[i] == 0) { 2384 lp->rx_dma_addr[i] = 2385 pci_map_single(lp->pci_dev, rx_skbuff->data, 2386 PKT_BUF_SIZE, PCI_DMA_FROMDEVICE); 2387 if (pci_dma_mapping_error(lp->pci_dev, 2388 lp->rx_dma_addr[i])) { 2389 /* there is not much we can do at this point */ 2390 netif_err(lp, drv, dev, 2391 "%s pci dma mapping error\n", 2392 __func__); 2393 return -1; 2394 } 2395 } 2396 lp->rx_ring[i].base = cpu_to_le32(lp->rx_dma_addr[i]); 2397 lp->rx_ring[i].buf_length = cpu_to_le16(NEG_BUF_SIZE); 2398 wmb(); /* Make sure owner changes after all others are visible */ 2399 lp->rx_ring[i].status = cpu_to_le16(0x8000); 2400 } 2401 /* The Tx buffer address is filled in as needed, but we do need to clear 2402 * the upper ownership bit. */ 2403 for (i = 0; i < lp->tx_ring_size; i++) { 2404 lp->tx_ring[i].status = 0; /* CPU owns buffer */ 2405 wmb(); /* Make sure adapter sees owner change */ 2406 lp->tx_ring[i].base = 0; 2407 lp->tx_dma_addr[i] = 0; 2408 } 2409 2410 lp->init_block->tlen_rlen = 2411 cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits); 2412 for (i = 0; i < 6; i++) 2413 lp->init_block->phys_addr[i] = dev->dev_addr[i]; 2414 lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr); 2415 lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr); 2416 wmb(); /* Make sure all changes are visible */ 2417 return 0; 2418 } 2419 2420 /* the pcnet32 has been issued a stop or reset. Wait for the stop bit 2421 * then flush the pending transmit operations, re-initialize the ring, 2422 * and tell the chip to initialize. 2423 */ 2424 static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits) 2425 { 2426 struct pcnet32_private *lp = netdev_priv(dev); 2427 unsigned long ioaddr = dev->base_addr; 2428 int i; 2429 2430 /* wait for stop */ 2431 for (i = 0; i < 100; i++) 2432 if (lp->a->read_csr(ioaddr, CSR0) & CSR0_STOP) 2433 break; 2434 2435 if (i >= 100) 2436 netif_err(lp, drv, dev, "%s timed out waiting for stop\n", 2437 __func__); 2438 2439 pcnet32_purge_tx_ring(dev); 2440 if (pcnet32_init_ring(dev)) 2441 return; 2442 2443 /* ReInit Ring */ 2444 lp->a->write_csr(ioaddr, CSR0, CSR0_INIT); 2445 i = 0; 2446 while (i++ < 1000) 2447 if (lp->a->read_csr(ioaddr, CSR0) & CSR0_IDON) 2448 break; 2449 2450 lp->a->write_csr(ioaddr, CSR0, csr0_bits); 2451 } 2452 2453 static void pcnet32_tx_timeout(struct net_device *dev, unsigned int txqueue) 2454 { 2455 struct pcnet32_private *lp = netdev_priv(dev); 2456 unsigned long ioaddr = dev->base_addr, flags; 2457 2458 spin_lock_irqsave(&lp->lock, flags); 2459 /* Transmitter timeout, serious problems. */ 2460 if (pcnet32_debug & NETIF_MSG_DRV) 2461 pr_err("%s: transmit timed out, status %4.4x, resetting\n", 2462 dev->name, lp->a->read_csr(ioaddr, CSR0)); 2463 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); 2464 dev->stats.tx_errors++; 2465 if (netif_msg_tx_err(lp)) { 2466 int i; 2467 printk(KERN_DEBUG 2468 " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.", 2469 lp->dirty_tx, lp->cur_tx, lp->tx_full ? " (full)" : "", 2470 lp->cur_rx); 2471 for (i = 0; i < lp->rx_ring_size; i++) 2472 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ", 2473 le32_to_cpu(lp->rx_ring[i].base), 2474 (-le16_to_cpu(lp->rx_ring[i].buf_length)) & 2475 0xffff, le32_to_cpu(lp->rx_ring[i].msg_length), 2476 le16_to_cpu(lp->rx_ring[i].status)); 2477 for (i = 0; i < lp->tx_ring_size; i++) 2478 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ", 2479 le32_to_cpu(lp->tx_ring[i].base), 2480 (-le16_to_cpu(lp->tx_ring[i].length)) & 0xffff, 2481 le32_to_cpu(lp->tx_ring[i].misc), 2482 le16_to_cpu(lp->tx_ring[i].status)); 2483 printk("\n"); 2484 } 2485 pcnet32_restart(dev, CSR0_NORMAL); 2486 2487 netif_trans_update(dev); /* prevent tx timeout */ 2488 netif_wake_queue(dev); 2489 2490 spin_unlock_irqrestore(&lp->lock, flags); 2491 } 2492 2493 static netdev_tx_t pcnet32_start_xmit(struct sk_buff *skb, 2494 struct net_device *dev) 2495 { 2496 struct pcnet32_private *lp = netdev_priv(dev); 2497 unsigned long ioaddr = dev->base_addr; 2498 u16 status; 2499 int entry; 2500 unsigned long flags; 2501 2502 spin_lock_irqsave(&lp->lock, flags); 2503 2504 netif_printk(lp, tx_queued, KERN_DEBUG, dev, 2505 "%s() called, csr0 %4.4x\n", 2506 __func__, lp->a->read_csr(ioaddr, CSR0)); 2507 2508 /* Default status -- will not enable Successful-TxDone 2509 * interrupt when that option is available to us. 2510 */ 2511 status = 0x8300; 2512 2513 /* Fill in a Tx ring entry */ 2514 2515 /* Mask to ring buffer boundary. */ 2516 entry = lp->cur_tx & lp->tx_mod_mask; 2517 2518 /* Caution: the write order is important here, set the status 2519 * with the "ownership" bits last. */ 2520 2521 lp->tx_ring[entry].length = cpu_to_le16(-skb->len); 2522 2523 lp->tx_ring[entry].misc = 0x00000000; 2524 2525 lp->tx_dma_addr[entry] = 2526 pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE); 2527 if (pci_dma_mapping_error(lp->pci_dev, lp->tx_dma_addr[entry])) { 2528 dev_kfree_skb_any(skb); 2529 dev->stats.tx_dropped++; 2530 goto drop_packet; 2531 } 2532 lp->tx_skbuff[entry] = skb; 2533 lp->tx_ring[entry].base = cpu_to_le32(lp->tx_dma_addr[entry]); 2534 wmb(); /* Make sure owner changes after all others are visible */ 2535 lp->tx_ring[entry].status = cpu_to_le16(status); 2536 2537 lp->cur_tx++; 2538 dev->stats.tx_bytes += skb->len; 2539 2540 /* Trigger an immediate send poll. */ 2541 lp->a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_TXPOLL); 2542 2543 if (lp->tx_ring[(entry + 1) & lp->tx_mod_mask].base != 0) { 2544 lp->tx_full = 1; 2545 netif_stop_queue(dev); 2546 } 2547 drop_packet: 2548 spin_unlock_irqrestore(&lp->lock, flags); 2549 return NETDEV_TX_OK; 2550 } 2551 2552 /* The PCNET32 interrupt handler. */ 2553 static irqreturn_t 2554 pcnet32_interrupt(int irq, void *dev_id) 2555 { 2556 struct net_device *dev = dev_id; 2557 struct pcnet32_private *lp; 2558 unsigned long ioaddr; 2559 u16 csr0; 2560 int boguscnt = max_interrupt_work; 2561 2562 ioaddr = dev->base_addr; 2563 lp = netdev_priv(dev); 2564 2565 spin_lock(&lp->lock); 2566 2567 csr0 = lp->a->read_csr(ioaddr, CSR0); 2568 while ((csr0 & 0x8f00) && --boguscnt >= 0) { 2569 if (csr0 == 0xffff) 2570 break; /* PCMCIA remove happened */ 2571 /* Acknowledge all of the current interrupt sources ASAP. */ 2572 lp->a->write_csr(ioaddr, CSR0, csr0 & ~0x004f); 2573 2574 netif_printk(lp, intr, KERN_DEBUG, dev, 2575 "interrupt csr0=%#2.2x new csr=%#2.2x\n", 2576 csr0, lp->a->read_csr(ioaddr, CSR0)); 2577 2578 /* Log misc errors. */ 2579 if (csr0 & 0x4000) 2580 dev->stats.tx_errors++; /* Tx babble. */ 2581 if (csr0 & 0x1000) { 2582 /* 2583 * This happens when our receive ring is full. This 2584 * shouldn't be a problem as we will see normal rx 2585 * interrupts for the frames in the receive ring. But 2586 * there are some PCI chipsets (I can reproduce this 2587 * on SP3G with Intel saturn chipset) which have 2588 * sometimes problems and will fill up the receive 2589 * ring with error descriptors. In this situation we 2590 * don't get a rx interrupt, but a missed frame 2591 * interrupt sooner or later. 2592 */ 2593 dev->stats.rx_errors++; /* Missed a Rx frame. */ 2594 } 2595 if (csr0 & 0x0800) { 2596 netif_err(lp, drv, dev, "Bus master arbitration failure, status %4.4x\n", 2597 csr0); 2598 /* unlike for the lance, there is no restart needed */ 2599 } 2600 if (napi_schedule_prep(&lp->napi)) { 2601 u16 val; 2602 /* set interrupt masks */ 2603 val = lp->a->read_csr(ioaddr, CSR3); 2604 val |= 0x5f00; 2605 lp->a->write_csr(ioaddr, CSR3, val); 2606 2607 __napi_schedule(&lp->napi); 2608 break; 2609 } 2610 csr0 = lp->a->read_csr(ioaddr, CSR0); 2611 } 2612 2613 netif_printk(lp, intr, KERN_DEBUG, dev, 2614 "exiting interrupt, csr0=%#4.4x\n", 2615 lp->a->read_csr(ioaddr, CSR0)); 2616 2617 spin_unlock(&lp->lock); 2618 2619 return IRQ_HANDLED; 2620 } 2621 2622 static int pcnet32_close(struct net_device *dev) 2623 { 2624 unsigned long ioaddr = dev->base_addr; 2625 struct pcnet32_private *lp = netdev_priv(dev); 2626 unsigned long flags; 2627 2628 del_timer_sync(&lp->watchdog_timer); 2629 2630 netif_stop_queue(dev); 2631 napi_disable(&lp->napi); 2632 2633 spin_lock_irqsave(&lp->lock, flags); 2634 2635 dev->stats.rx_missed_errors = lp->a->read_csr(ioaddr, 112); 2636 2637 netif_printk(lp, ifdown, KERN_DEBUG, dev, 2638 "Shutting down ethercard, status was %2.2x\n", 2639 lp->a->read_csr(ioaddr, CSR0)); 2640 2641 /* We stop the PCNET32 here -- it occasionally polls memory if we don't. */ 2642 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); 2643 2644 /* 2645 * Switch back to 16bit mode to avoid problems with dumb 2646 * DOS packet driver after a warm reboot 2647 */ 2648 lp->a->write_bcr(ioaddr, 20, 4); 2649 2650 spin_unlock_irqrestore(&lp->lock, flags); 2651 2652 free_irq(dev->irq, dev); 2653 2654 spin_lock_irqsave(&lp->lock, flags); 2655 2656 pcnet32_purge_rx_ring(dev); 2657 pcnet32_purge_tx_ring(dev); 2658 2659 spin_unlock_irqrestore(&lp->lock, flags); 2660 2661 return 0; 2662 } 2663 2664 static struct net_device_stats *pcnet32_get_stats(struct net_device *dev) 2665 { 2666 struct pcnet32_private *lp = netdev_priv(dev); 2667 unsigned long ioaddr = dev->base_addr; 2668 unsigned long flags; 2669 2670 spin_lock_irqsave(&lp->lock, flags); 2671 dev->stats.rx_missed_errors = lp->a->read_csr(ioaddr, 112); 2672 spin_unlock_irqrestore(&lp->lock, flags); 2673 2674 return &dev->stats; 2675 } 2676 2677 /* taken from the sunlance driver, which it took from the depca driver */ 2678 static void pcnet32_load_multicast(struct net_device *dev) 2679 { 2680 struct pcnet32_private *lp = netdev_priv(dev); 2681 volatile struct pcnet32_init_block *ib = lp->init_block; 2682 volatile __le16 *mcast_table = (__le16 *)ib->filter; 2683 struct netdev_hw_addr *ha; 2684 unsigned long ioaddr = dev->base_addr; 2685 int i; 2686 u32 crc; 2687 2688 /* set all multicast bits */ 2689 if (dev->flags & IFF_ALLMULTI) { 2690 ib->filter[0] = cpu_to_le32(~0U); 2691 ib->filter[1] = cpu_to_le32(~0U); 2692 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER, 0xffff); 2693 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER+1, 0xffff); 2694 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER+2, 0xffff); 2695 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER+3, 0xffff); 2696 return; 2697 } 2698 /* clear the multicast filter */ 2699 ib->filter[0] = 0; 2700 ib->filter[1] = 0; 2701 2702 /* Add addresses */ 2703 netdev_for_each_mc_addr(ha, dev) { 2704 crc = ether_crc_le(6, ha->addr); 2705 crc = crc >> 26; 2706 mcast_table[crc >> 4] |= cpu_to_le16(1 << (crc & 0xf)); 2707 } 2708 for (i = 0; i < 4; i++) 2709 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER + i, 2710 le16_to_cpu(mcast_table[i])); 2711 } 2712 2713 /* 2714 * Set or clear the multicast filter for this adaptor. 2715 */ 2716 static void pcnet32_set_multicast_list(struct net_device *dev) 2717 { 2718 unsigned long ioaddr = dev->base_addr, flags; 2719 struct pcnet32_private *lp = netdev_priv(dev); 2720 int csr15, suspended; 2721 2722 spin_lock_irqsave(&lp->lock, flags); 2723 suspended = pcnet32_suspend(dev, &flags, 0); 2724 csr15 = lp->a->read_csr(ioaddr, CSR15); 2725 if (dev->flags & IFF_PROMISC) { 2726 /* Log any net taps. */ 2727 netif_info(lp, hw, dev, "Promiscuous mode enabled\n"); 2728 lp->init_block->mode = 2729 cpu_to_le16(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) << 2730 7); 2731 lp->a->write_csr(ioaddr, CSR15, csr15 | 0x8000); 2732 } else { 2733 lp->init_block->mode = 2734 cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7); 2735 lp->a->write_csr(ioaddr, CSR15, csr15 & 0x7fff); 2736 pcnet32_load_multicast(dev); 2737 } 2738 2739 if (suspended) { 2740 pcnet32_clr_suspend(lp, ioaddr); 2741 } else { 2742 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); 2743 pcnet32_restart(dev, CSR0_NORMAL); 2744 netif_wake_queue(dev); 2745 } 2746 2747 spin_unlock_irqrestore(&lp->lock, flags); 2748 } 2749 2750 /* This routine assumes that the lp->lock is held */ 2751 static int mdio_read(struct net_device *dev, int phy_id, int reg_num) 2752 { 2753 struct pcnet32_private *lp = netdev_priv(dev); 2754 unsigned long ioaddr = dev->base_addr; 2755 u16 val_out; 2756 2757 if (!lp->mii) 2758 return 0; 2759 2760 lp->a->write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f)); 2761 val_out = lp->a->read_bcr(ioaddr, 34); 2762 2763 return val_out; 2764 } 2765 2766 /* This routine assumes that the lp->lock is held */ 2767 static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val) 2768 { 2769 struct pcnet32_private *lp = netdev_priv(dev); 2770 unsigned long ioaddr = dev->base_addr; 2771 2772 if (!lp->mii) 2773 return; 2774 2775 lp->a->write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f)); 2776 lp->a->write_bcr(ioaddr, 34, val); 2777 } 2778 2779 static int pcnet32_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 2780 { 2781 struct pcnet32_private *lp = netdev_priv(dev); 2782 int rc; 2783 unsigned long flags; 2784 2785 /* SIOC[GS]MIIxxx ioctls */ 2786 if (lp->mii) { 2787 spin_lock_irqsave(&lp->lock, flags); 2788 rc = generic_mii_ioctl(&lp->mii_if, if_mii(rq), cmd, NULL); 2789 spin_unlock_irqrestore(&lp->lock, flags); 2790 } else { 2791 rc = -EOPNOTSUPP; 2792 } 2793 2794 return rc; 2795 } 2796 2797 static int pcnet32_check_otherphy(struct net_device *dev) 2798 { 2799 struct pcnet32_private *lp = netdev_priv(dev); 2800 struct mii_if_info mii = lp->mii_if; 2801 u16 bmcr; 2802 int i; 2803 2804 for (i = 0; i < PCNET32_MAX_PHYS; i++) { 2805 if (i == lp->mii_if.phy_id) 2806 continue; /* skip active phy */ 2807 if (lp->phymask & (1 << i)) { 2808 mii.phy_id = i; 2809 if (mii_link_ok(&mii)) { 2810 /* found PHY with active link */ 2811 netif_info(lp, link, dev, "Using PHY number %d\n", 2812 i); 2813 2814 /* isolate inactive phy */ 2815 bmcr = 2816 mdio_read(dev, lp->mii_if.phy_id, MII_BMCR); 2817 mdio_write(dev, lp->mii_if.phy_id, MII_BMCR, 2818 bmcr | BMCR_ISOLATE); 2819 2820 /* de-isolate new phy */ 2821 bmcr = mdio_read(dev, i, MII_BMCR); 2822 mdio_write(dev, i, MII_BMCR, 2823 bmcr & ~BMCR_ISOLATE); 2824 2825 /* set new phy address */ 2826 lp->mii_if.phy_id = i; 2827 return 1; 2828 } 2829 } 2830 } 2831 return 0; 2832 } 2833 2834 /* 2835 * Show the status of the media. Similar to mii_check_media however it 2836 * correctly shows the link speed for all (tested) pcnet32 variants. 2837 * Devices with no mii just report link state without speed. 2838 * 2839 * Caller is assumed to hold and release the lp->lock. 2840 */ 2841 2842 static void pcnet32_check_media(struct net_device *dev, int verbose) 2843 { 2844 struct pcnet32_private *lp = netdev_priv(dev); 2845 int curr_link; 2846 int prev_link = netif_carrier_ok(dev) ? 1 : 0; 2847 u32 bcr9; 2848 2849 if (lp->mii) { 2850 curr_link = mii_link_ok(&lp->mii_if); 2851 } else if (lp->chip_version == PCNET32_79C970A) { 2852 ulong ioaddr = dev->base_addr; /* card base I/O address */ 2853 /* only read link if port is set to TP */ 2854 if (!lp->autoneg && lp->port_tp) 2855 curr_link = (lp->a->read_bcr(ioaddr, 4) != 0xc0); 2856 else /* link always up for AUI port or port auto select */ 2857 curr_link = 1; 2858 } else { 2859 ulong ioaddr = dev->base_addr; /* card base I/O address */ 2860 curr_link = (lp->a->read_bcr(ioaddr, 4) != 0xc0); 2861 } 2862 if (!curr_link) { 2863 if (prev_link || verbose) { 2864 netif_carrier_off(dev); 2865 netif_info(lp, link, dev, "link down\n"); 2866 } 2867 if (lp->phycount > 1) { 2868 curr_link = pcnet32_check_otherphy(dev); 2869 prev_link = 0; 2870 } 2871 } else if (verbose || !prev_link) { 2872 netif_carrier_on(dev); 2873 if (lp->mii) { 2874 if (netif_msg_link(lp)) { 2875 struct ethtool_cmd ecmd = { 2876 .cmd = ETHTOOL_GSET }; 2877 mii_ethtool_gset(&lp->mii_if, &ecmd); 2878 netdev_info(dev, "link up, %uMbps, %s-duplex\n", 2879 ethtool_cmd_speed(&ecmd), 2880 (ecmd.duplex == DUPLEX_FULL) 2881 ? "full" : "half"); 2882 } 2883 bcr9 = lp->a->read_bcr(dev->base_addr, 9); 2884 if ((bcr9 & (1 << 0)) != lp->mii_if.full_duplex) { 2885 if (lp->mii_if.full_duplex) 2886 bcr9 |= (1 << 0); 2887 else 2888 bcr9 &= ~(1 << 0); 2889 lp->a->write_bcr(dev->base_addr, 9, bcr9); 2890 } 2891 } else { 2892 netif_info(lp, link, dev, "link up\n"); 2893 } 2894 } 2895 } 2896 2897 /* 2898 * Check for loss of link and link establishment. 2899 * Could possibly be changed to use mii_check_media instead. 2900 */ 2901 2902 static void pcnet32_watchdog(struct timer_list *t) 2903 { 2904 struct pcnet32_private *lp = from_timer(lp, t, watchdog_timer); 2905 struct net_device *dev = lp->dev; 2906 unsigned long flags; 2907 2908 /* Print the link status if it has changed */ 2909 spin_lock_irqsave(&lp->lock, flags); 2910 pcnet32_check_media(dev, 0); 2911 spin_unlock_irqrestore(&lp->lock, flags); 2912 2913 mod_timer(&lp->watchdog_timer, round_jiffies(PCNET32_WATCHDOG_TIMEOUT)); 2914 } 2915 2916 static int pcnet32_pm_suspend(struct pci_dev *pdev, pm_message_t state) 2917 { 2918 struct net_device *dev = pci_get_drvdata(pdev); 2919 2920 if (netif_running(dev)) { 2921 netif_device_detach(dev); 2922 pcnet32_close(dev); 2923 } 2924 pci_save_state(pdev); 2925 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 2926 return 0; 2927 } 2928 2929 static int pcnet32_pm_resume(struct pci_dev *pdev) 2930 { 2931 struct net_device *dev = pci_get_drvdata(pdev); 2932 2933 pci_set_power_state(pdev, PCI_D0); 2934 pci_restore_state(pdev); 2935 2936 if (netif_running(dev)) { 2937 pcnet32_open(dev); 2938 netif_device_attach(dev); 2939 } 2940 return 0; 2941 } 2942 2943 static void pcnet32_remove_one(struct pci_dev *pdev) 2944 { 2945 struct net_device *dev = pci_get_drvdata(pdev); 2946 2947 if (dev) { 2948 struct pcnet32_private *lp = netdev_priv(dev); 2949 2950 unregister_netdev(dev); 2951 pcnet32_free_ring(dev); 2952 release_region(dev->base_addr, PCNET32_TOTAL_SIZE); 2953 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block), 2954 lp->init_block, lp->init_dma_addr); 2955 free_netdev(dev); 2956 pci_disable_device(pdev); 2957 } 2958 } 2959 2960 static struct pci_driver pcnet32_driver = { 2961 .name = DRV_NAME, 2962 .probe = pcnet32_probe_pci, 2963 .remove = pcnet32_remove_one, 2964 .id_table = pcnet32_pci_tbl, 2965 .suspend = pcnet32_pm_suspend, 2966 .resume = pcnet32_pm_resume, 2967 }; 2968 2969 /* An additional parameter that may be passed in... */ 2970 static int debug = -1; 2971 static int tx_start_pt = -1; 2972 static int pcnet32_have_pci; 2973 2974 module_param(debug, int, 0); 2975 MODULE_PARM_DESC(debug, DRV_NAME " debug level"); 2976 module_param(max_interrupt_work, int, 0); 2977 MODULE_PARM_DESC(max_interrupt_work, 2978 DRV_NAME " maximum events handled per interrupt"); 2979 module_param(rx_copybreak, int, 0); 2980 MODULE_PARM_DESC(rx_copybreak, 2981 DRV_NAME " copy breakpoint for copy-only-tiny-frames"); 2982 module_param(tx_start_pt, int, 0); 2983 MODULE_PARM_DESC(tx_start_pt, DRV_NAME " transmit start point (0-3)"); 2984 module_param(pcnet32vlb, int, 0); 2985 MODULE_PARM_DESC(pcnet32vlb, DRV_NAME " Vesa local bus (VLB) support (0/1)"); 2986 module_param_array(options, int, NULL, 0); 2987 MODULE_PARM_DESC(options, DRV_NAME " initial option setting(s) (0-15)"); 2988 module_param_array(full_duplex, int, NULL, 0); 2989 MODULE_PARM_DESC(full_duplex, DRV_NAME " full duplex setting(s) (1)"); 2990 /* Module Parameter for HomePNA cards added by Patrick Simmons, 2004 */ 2991 module_param_array(homepna, int, NULL, 0); 2992 MODULE_PARM_DESC(homepna, 2993 DRV_NAME 2994 " mode for 79C978 cards (1 for HomePNA, 0 for Ethernet, default Ethernet"); 2995 2996 MODULE_AUTHOR("Thomas Bogendoerfer"); 2997 MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards"); 2998 MODULE_LICENSE("GPL"); 2999 3000 #define PCNET32_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK) 3001 3002 static int __init pcnet32_init_module(void) 3003 { 3004 pcnet32_debug = netif_msg_init(debug, PCNET32_MSG_DEFAULT); 3005 3006 if ((tx_start_pt >= 0) && (tx_start_pt <= 3)) 3007 tx_start = tx_start_pt; 3008 3009 /* find the PCI devices */ 3010 if (!pci_register_driver(&pcnet32_driver)) 3011 pcnet32_have_pci = 1; 3012 3013 /* should we find any remaining VLbus devices ? */ 3014 if (pcnet32vlb) 3015 pcnet32_probe_vlbus(pcnet32_portlist); 3016 3017 if (cards_found && (pcnet32_debug & NETIF_MSG_PROBE)) 3018 pr_info("%d cards_found\n", cards_found); 3019 3020 return (pcnet32_have_pci + cards_found) ? 0 : -ENODEV; 3021 } 3022 3023 static void __exit pcnet32_cleanup_module(void) 3024 { 3025 struct net_device *next_dev; 3026 3027 while (pcnet32_dev) { 3028 struct pcnet32_private *lp = netdev_priv(pcnet32_dev); 3029 next_dev = lp->next; 3030 unregister_netdev(pcnet32_dev); 3031 pcnet32_free_ring(pcnet32_dev); 3032 release_region(pcnet32_dev->base_addr, PCNET32_TOTAL_SIZE); 3033 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block), 3034 lp->init_block, lp->init_dma_addr); 3035 free_netdev(pcnet32_dev); 3036 pcnet32_dev = next_dev; 3037 } 3038 3039 if (pcnet32_have_pci) 3040 pci_unregister_driver(&pcnet32_driver); 3041 } 3042 3043 module_init(pcnet32_init_module); 3044 module_exit(pcnet32_cleanup_module); 3045 3046 /* 3047 * Local variables: 3048 * c-indent-level: 4 3049 * tab-width: 8 3050 * End: 3051 */ 3052